MSM9225BGA-2K [OKI]
CAN (Controller Area Network) Controller; CAN （控制器局域网）控制器
| 型号： | MSM9225BGA-2K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | CAN (Controller Area Network) Controller |
| 文件： | 总16页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL9225B-03
This version:
Previous version: Feb. 2001
Aug. 2001
1
Semiconductor
MSM9225B
CAN (Controller Area Network) Controller
GENERAL DESCRIPTION
The MSM9225B is a microcontroller peripheral LSI which conforms to the CAN protocol for high-speed LANs
in automobiles.
FEATURES
•
•
•
Conforms to CAN protocol specification (Bosch, V2.0 part B/Active)
Maximum of 1 Mbps bit rate
Communication method:
• Transmission line is bi-directional, two-wire serial communication
• NRZ (Non-Return to Zero) system using bit stuff function
• Multi-master system
• Broadcast system
•
Message boxes:
• Up to 16 message boxes can be used, and messages up to 8 bytes long can be transmitted or received for
each message box.
• Number of received messages can be extended by group message function (up to 2 groups can be set)
• Overwrite flag is provided
•
•
Priority control by identifier
• 2032 types in standard format, 2032 × 218 types in extended format
Microcontroller interface
• Corresponding to both parallel and serial interface
Parallel interface: Separate address/data bus type (with address latch signal/no address latch signal)
and multiplexed address/data bus type
Serial interface: Synchronous communication type
• Three interrupt sources: Transmission/receive/error
Error control:
•
• Bit error/stuff error/CRC error/form error/acknowledgment error detection functions
• Retransmission/error status monitoring function when error occurs
• Bit error flag/stuff error flag/CRC error flag/form error flag/acknowledge error flag are provided
Communication control by remote data request function
Sleep/Stop mode function
Supply voltage: 5 V±10%
Operating temperature: –40 to +125°C
Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSM9225BGA-2K)
•
•
•
•
•
1/16
FEDL9225B-03
1Semiconductor
MSM9225B
BLOCK DIAGRAM
CS
8
Bit stream
logic
(BSL)
A7-0
Bit timing logic (BTL)
8
AD7-0/D7-0
PALE
PWR
RD
RDY
PRD/SR
W
Transmission
control logic
(TCL)
Tx0
Tx1
PRDY/SWAIT
R
W
WAIT
Message
memory
Data
manage-
ment
SCLK
SDI
Error
management
logic (EML)
Control
register
logic
SDO
INT
Mode1, 0
Receive
control logic
(RCL)
Rx0
Rx1
XT
XT
Timing
generator
RESET
V
DD
GND
CONFIGURATION EXAMPLE
ABS
CAN
Power steering
Suspension
CAN
CAN
Engine
controller
Seat-position controller
CAN
CAN
CAN Bus
CAN
Transmission
CAN
Automatic
air conditioner
CAN
Power window
CAN
Outside mirror controller
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FEDL9225B-03
1Semiconductor
MSM9225B
PIN CONFIGURATION
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
T 0
X
AD3/D3
AD4/D4
AD5/D5
AD6/D6
AD7/D7
GND
VDD
R
X
1
0
RX
GND
VDD
GND
PRDY
GND
/SWAIT
A0
A1
XT
XT
A2
A3
VDD
44-Pin Plastic QFP (Top View)
3/16
FEDL9225B-03
1Semiconductor
MSM9225B
PIN DESCRIPTIONS
Symbol
Pin
10
Type
I
Description
Chip select pin. When “L”, PALE, PWR, PRD/SRW, SCLK and SDO
pins (microcontroller interface pins) are valid.
CS
When “H”, these pins are invalid.
Address bus pins (when using separate buses). If used with a
multiplexed bus or if used in the serial mode, fix these pins at “H” or “L”
levels.
A7-0
41-44, 1-4
31-38
26
I
Multiplexed bus: Address/data pins (AD7-0)
I/O Separate buses: Data pins (D7-0)
AD7-0/
D7-0
If used in the serial mode, fix these pins at a “L” levels.
Write input pin if used in the parallel mode. Data is captured when this
pin is at a “L” level.
If used in the serial mode, fix this pin at a “L” level.
PWR
I
I
Parallel mode: Read signal pin (PRD)
When at a “L” level, data is output from the data pins.
Serial mode: Read/write signal pin (SRW)
When at a “H” level, data is output from the SDO pin.
When at a “L” level, the SDO pin is at high impedance, and data is
captured beginning with the second byte of data input from the SDI pin.
PRD/
SRW
9
Address latch signal pin
When at a “H” level, addresses are captured.
If used in the parallel mode and the address latch signal is unnecessary
or in the serial mode, fix this pin at a “H” or “L” level.
PALE
SDI
27
7
I
I
Serial data input pin
Addresses (1st byte) and data (beginning from the 2nd byte) are input to
this pin, LSB first. If used in the parallel mode, fix this pin at a “H” or “L”
level.
Serial data output pin
When the CS pin is at a “H” level, this pin is at high impedance. When
CS is at a “L” level, data is output from this pin, LSB first.
If used in the parallel mode, fix this pin at a “H” or “L” level.
SDO
5
8
O
I
Shift clock input pin for serial data
At the rising edge of the shift clock, SDI pin data is captured. At the
falling edge, data is output from the SDO pin.
SCLK
Ready output pin
When required by the MSM9225B, a signal may be output to extend the
bus cycle until the internal access is completed.
Internal access in
progress
After completion of
access
High impedance
output
PRDY/
SWAIT
16
O
Parallel mode
“L” level output
“H” level output
(PRDY)
Serial mode
(SWAIT)
“L” level output
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FEDL9225B-03
1Semiconductor
MSM9225B
Symbol
Pin
Type
Description
Microcontroller interface select pins
Mode1 Mode0
Interface
Separate No address latch signal
buses
Multiplexed buses
Serial mode
0
0
1
1
0
1
0
1
Parallel
mode
With address latch signal
Mode1, 0
29, 30
I
Interrupt request output pin
When an interrupt request occurs, a “L” level is output. This pin
automatically outputs a “H” level after 32 Ts (T = 1/fosc).
INT
11
O
Three types of interrupts share this pin: transmission complete, reception
complete, and error.
Reset pin
RESET
25
13
I
I
System is reset when this pin is at a “L” level.
XT
Clock pins. If internal oscillator is used, connect a crystal (ceramic
resonator).
If external clock is used, input clock via XT pin. The XT pin should be left
open.
XT
14
O
Rx0, Rx1
Tx0, Tx1
VDD
18, 19
22, 23
I
Receive input pin. Differential amplifier included.
Transmission output pin
O
—
12, 20, 24, 40
Power supply pin
6, 15, 17, 21,
28, 39
GND
—
GND pin
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FEDL9225B-03
1Semiconductor
MSM9225B
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Input Voltage
Symbol
VDD
VI
Condition
Rating
–0.3 to +7.0
–0.3 to VDD +3.0
–0.3 to VDD +3.0
615
Unit
V
Ta = 25°C
—
V
Output Voltage
VO
—
Ta ≤ 25°C
—
V
Power Dissipation
Operating Temperature
Storage Temperature
PD
mW
°C
°C
TOP
TSTG
–40 to +125
–65 to +150
—
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VDD
Condition
VDD = AVDD
—
Min.
4.5
Typ.
5.0
Max.
Unit
V
Power Supply Voltage
Operating Temperature
5.5
TOP
–40
+25
+125
°C
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FEDL9225B-03
1Semiconductor
MSM9225B
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 4.5 to 5.5 V, Ta = –40 to +125°C)
Parameter
“H” Input Voltage
“L” Input Voltage
Symbol
VIH
VIL
IIH1
IIH2
IIL1
Applicable pin
Condition
Min.
Max.
Unit
V
V
µA
µA
µA
µA
V
Applies to all inputs
Applies to all inputs
XT
Other inputs
XT
—
—
0.8VDD
–0.3
3
–1.0
–25
–1.0
VDD –1.0
VDD –1.0
—
VDD +0.3
+0.2 VDD
25
+1.0
–3
+1.0
—
—
“H” Input Current
“L” Input Current
“H” Output Voltage
VI = VDD
VI = 0V
IIL2
VOH1
Other input
IOH1 = –80 µA
OH2 = –400 µA
IOL1 = 1.6 mA
IOL2 = 3.2 mA
INT, PRDY/SWAIT
VOH2
VOL1
VOL2
AD7-0/D7-0
V
V
V
I
0.4
0.4
INT, PRDY/SWAIT
“L” Output Voltage
AD7-0/D7-0
—
PRDY/SWAIT
Output Leakage Current
Dynamic Supply Current
Static Supply Current
IIH1
IDD
VI = VDD/0 V
–1.0
—
+1.0
9
µA
AD7-0/D7-0
fOSC = 16 MHz,
No Load
SLEEP Mode
STOP Mode
—
mA
—
—
—
—
400
100
µA
µA
IDDS
Rx0, Rx1 Characteristics
Differencial input mode
(VDD = 4.5 to 5.5 V, Ta = –40 to +125°C)
Parameter
Symbol
VRx0 (d)
VRx0 (r)
ILK
Applicable pin
Rx0
Condition
Min.
–0.3
Max.
VRx1 –0.4
VDD +3
+1
Unit
V
‘dominant’ Input Voltage
‘recessive Input Voltage
Input Leakage Current
VRx1 = 0.4 VDD
to 0.6 VDD
Rx0
VRx1 +0.4
–1
V
Rx0, Rx1
VRX1 = VDD/0 V
µA
Tx0, Tx1 Characteristics
(VDD = 4.5 to 5.5 V, Ta = –40 to +125°C)
Parameter
Symbol
Condition
Min.
Max.
Unit
“H” Output Voltage
“L” Output Voltage
VOH
VOL
IOH = –3.0 mA
IOL = 10.0 mA
VDD –0.4
—
—
0.4
V
V
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FEDL9225B-03
1Semiconductor
MSM9225B
AC Characteristics
Parallel mode
(VDD = 4.5 to 5.5 V, Ta = –40 to +125°C, fOSC = 16 MHz)
Parameter
Symbol
Condition
Min.
Max.
Unit
ALE Address Setup Time
ALE Address Hold Time
tAS
tAH
—
—
10
10
—
—
ns
ns
1
tRDLY
—
—
ns
PRD Output Data Delay Time
60*
—
—
tRDH
tWALEH
—
—
5
16.5
ns
ns
PRD Output Data Hold Time
ALE “H” Level Width
When PRDY is not
4T
7T
—
—
ns
ns
generated
Access Cycle
tcyc
—
When PRDY is
generated
tRAH
tHRA
—
—
—
—
—
—
0
—
—
ns
ns
ns
ns
ns
ns
Address Hold Time from PRD
ALE Delay Time from PRD
PRD “H” Level Width
27
27
—
0
tWRDH
tARLDLY
tWRDYL
tARDDLY
—
35
PRDY “L” Delay Time
2.5T
35
PRDY “L” Level Width
Data Output Delay Time from PRDY
—
tARWDLY
tWDS
tWDH
tRS
—
—
—
—
10
30
4
—
—
—
—
ns
ns
ns
ns
PWR Hold Time from PRDY
Input Data Setup Time
Input Data Hold Time
PRD Delay Time
10
tWS
—
—
—
—
—
—
—
10
10
27
40
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
PWR Delay Time
tWAH
tHWA
tWRH
tWRL
tHRC
tHWC
Address Hold Time from PWR
ALE Delay Time from PWR
PWR “H” Level Width
1
PWR “L” Level Width
20*
0
0
ns
ns
T = 1/fOSC
CS Delay Time from PRD
CS Delay Time from PWR
The values with *1 indicate those when PRDY is not generated.
The values with *1 when PRDY is generated are defined by “Data Output Delay Time from PRDY”
tARDDLY and “PWR Hold Time from PRDY” tARWDLY
.
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FEDL9225B-03
1Semiconductor
MSM9225B
Serial mode
(VDD = 4.5 to 5.5 V, Ta = –40 to +125°C, fOSC = 16 MHz)
Parameter
CS Setup Time
CS Hold Time
Symbol
tCS
Condition
Min.
10
8T
167
83
30
5
Max.
—
Unit
ns
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tCH
—
ns
SCLK Cycle
tCP
—
ns
SCLK Pulse Width
SDI Setup Time
tCW
—
ns
tDS
—
ns
SDI Hold Time
tDH
—
ns
SDO Output Enable Time
SDO Output Disable Time
SDO Output Delay Time
SRW Setup Time
SRW Hold Time
SWAIT Output Delay Time
SWAIT “H” Level Width
Byte Delay
tCSODLY
tCSZDLY
tPD
—
—
—
10
0
30
30
30
—
ns
ns
ns
tRS
ns
tRH
—
ns
tSRDLY
tWRDY
tWAIT
—
—
8T
2T
6T
—
ns
ns
ns
T = 1/fOSC
Other timing characteristics
(VDD = 4.5 to 5.5 V, Ta = –40 to +125°C)
Parameter
Symbol
tclkcy
Condition
Min.
62
5
Max.
—
Unit
ns
System Clock Cycle
—
—
—
—
RESET “H” Level Input Width
RESET “L” Level Input Width
INT “L” Level Output Width
tWRSTH
tWRSTL
tWINTL
—
µs
5
—
µs
32T
—
ns
T = 1/fOSC
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FEDL9225B-03
1Semiconductor
MSM9225B
TIMING DIAGRAMS
Separate Bus Mode
Read access timing
tHRC
CS
tcyc
A7-0
tRAH
AD7-0/
D7-0
tRS
tRDH
tWRDH
tRDLY
tARDDLY
SR
PRD/
W
tWRDYL
PRDY/SWAIT
tARLDLY
Note: The PRDY signal may be output depending on the internal state of the MSM9225B.
Write access timing
tHWC
CS
tcyc
A7-0
tWAH
AD7-0/
D7-0
tWDS
tWS
tWDH
tWRH
tWRL
PWR
tARWDLY
tWRDYL
PRDY/SWAIT
tARLDLY
Note: The PRDY signal may be output depending on the internal state of the MSM9225B.
10/16
FEDL9225B-03
1Semiconductor
MSM9225B
Separate Bus/Address Latch Mode
Read access timing
tHRC
CS
tWALEH
tHRA
PALE
tAS
tcyc
tAH
A7-0
don’t care
AD7-0/
D7-0
tRS
tRDH
tRDLY
tWRDH
tARDDLY
PRD/SRW
tWRDYL
PRDY/SWAIT
tARLDLY
Note: The PRDY signal may be output depending on the internal state of the MSM9225B.
Write access timing
tHWC
CS
tWALEH
tHWA
PALE
tAS
tcyc
tAH
A7-0
don’t care
AD7-0/
D7-0
tWDS
tWDH
tWS
tWRH
tWRL
PWR
tARWDLY
tWRDYL
PRDY/SWAIT
tARLDLY
Note: The PRDY signal may be output depending on the internal state of the MSM9225B.
11/16
FEDL9225B-03
1Semiconductor
MSM9225B
Multiplexed Bus Mode
Read access timing
tHRC
CS
tWALEH
tHRA
PALE
tAS
tcyc
tAH
AD7-0/
D7-0
tRDH
tRS
tRDLY
tWRDH
tARDDLY
PRD/SRW
tWRDYL
PRDY/SWAIT
tARLDLY
Note: The PRDY signal may be output depending on the internal state of the MSM9225B.
Write access timing
tHWC
CS
tWALEH
tHWA
PALE
tAS
tcyc
tAH
AD7-0/
D7-0
tWDS
tWDH
tWS
tWRH
tWRL
PWR
tARWDLY
tWRDYL
PRDY/SWAIT
tARLDLY
Note: The PRDY signal may be output depending on the internal state of the MSM9225B.
12/16
FEDL9225B-03
1Semiconductor
MSM9225B
Serial Mode
Read access timing
CS
tCS
tCH
tWAIT
tCP
tCW
SCLK
tCW
tDH
tDS
A0
A1
A6
A7
Don't Care
SDI
tPD
tCSZDLY
tCSODLY
DMY0
DMY1
DMY6
DMY7
D0
SDO
tRS
tRH
PRD/SR
W
tWRDY
tSRDLY
PRDY/SWAIT
Note: The SWAIT signal will be output during the interval between address and data transfers.
Write access timing
CS
tCS
tCH
tWAIT
tCP
tCW
SCLK
tCW
tDH
tDS
A0
A1
A6
A7
D0
SDI
tCSZDLY
tCSODLY
*
*
*
*
*
SDO
tRS
tRH
PRD/SR
W
tWRDY
tSRDLY
PRDY/SWAIT
Note:
The SWAIT signal will be output during the interval between address and data transfers.
* : don’t care
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FEDL9225B-03
1Semiconductor
MSM9225B
Other Timing
tWRSTL
tWRSTH
RESET
tWINTL
INT
tclkcy
CLK
(XT)
tclkcy
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FEDL9225B-03
1Semiconductor
MSM9225B
PACKAGE DIMENSIONS
(Unit: mm)
QFP44-P-910-0.80-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.41 TYP.
4/Nov. 28, 1996
5
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales
person on the product name, package name, pin number, package code and desired mounting
conditions (reflow method, temperature and times).
15/16
FEDL9225B-03
1Semiconductor
MSM9225B
NOTICE
1. The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is up-to-
date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party’s right which may result
from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires
special or enhanced quality and reliability characteristics nor in any system or application where the failure
of such system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
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