PHN1011 [NXP]
TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管
| 型号： | PHN1011 |
| 厂家： | 
NXP |
| 描述： | TrenchMOS transistor Logic level FET |
| 文件： | 总7页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• High thermal cycling performance
• Low-profile surface mount
package
VDSS = 25 V
ID = 11 A
R
DS(ON) ≤ 11 mΩ (VGS = 10 V)
g
• Logic level compatible
RDS(ON) ≤ 13.5 mΩ (VGS = 5 V)
s
GENERAL DESCRIPTION
PINNING
SOT96-1 (SO8)
N-channel enhancement mode
logic level field-effect power
transistor in a surface mounting
plastic package using ’trench’
technology. The combination of
very low on-state resistance and
low switching losses make this
device the optimum choice in high
speed computer motherboard d.c.
to d.c. converters.
PIN
DESCRIPTION
8
7
6
5
1-3
4
source
gate
5-8
drain
pin 1 index
1
2
3
4
The PHN1011 is supplied in the
SOT96-1 (SO8) surface mounting
package
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
Drain-source voltage
Drain-gate voltage
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C;
RGS = 20 kΩ
-
-
-
25
25
V
V
VGS
VGSM
Gate-source voltage (DC)
Gate-source voltage (pulse peak
value)
-
-
± 15
± 20
V
V
ID
Drain current (tp ≤ 10 s)
Ta = 25 ˚C
Ta = 70 ˚C
Ta = 25 ˚C
Ta = 25 ˚C
Ta = 70 ˚C
-
-
-
-
-
-
11
9
44
2.5
1.6
150
A
A
A
W
W
˚C
IDM
Ptot
Drain current (pulse peak value)
Total power dissipation
Tj, Tstg
Operating junction and storage
temperature
- 55
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-a
Thermal resistance junction Surface mounted, FR4 board, t ≤ 10 sec
to ambient
-
50
K/W
Rth j-a
Thermal resistance junction Surface mounted, FR4 board
to ambient
150
-
K/W
June 1999
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS Drain-source breakdown
CONDITIONS
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 0.25 mA;
VDS = VGS; ID = 1 mA
25
22
1
0.6
-
-
-
-
-
2
V
V
V
V
V
voltage
Gate threshold voltage
Tj = -55˚C
VGS(TO)
1.5
-
-
Tj = 150˚C
Tj = -55˚C
-
2.3
11
RDS(ON)
Drain-source on-state
resistance
VGS = 10 V; ID = 10 A
-
9
mΩ
VGS = 5 V; ID = 5 A
-
-
11
-
13.5 mΩ
VGS = 5 V; ID = 5 A; Tj = 150˚C
23
mΩ
gfs
IGSS
IDSS
Forward transconductance
Gate source leakage current VGS = ±5 V; VDS = 0 V
Zero gate voltage drain
current
VDS = 25 V; ID = 10 A
12
-
-
36
10
0.05
-
-
S
100
10
500
nA
µA
µA
VDS = 25 V; VGS = 0 V;
Tj = 150˚C
-
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 25 A; VDD = 15 V; VGS = 5 V
-
-
-
26
6
9.4
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; ID = 25 A;
VGS = 10 V; RG = 5 Ω
Resistive load
-
-
-
-
7
15
75
120
ns
ns
ns
ns
50
82
59
75
Ld
Ls
Internal drain inductance
Internal source inductance
Drain leads to centre of die
Source leads to source bond pad
-
-
1
3
-
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
-
-
-
1700
475
300
-
-
-
pF
pF
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Ta = 25 ˚C, tp ≤ 10 s
-
-
-
-
11
A
A
V
ISM
-
44
VSD
IF = 10 A; VGS = 0 V
0.95
1.2
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 10 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
-
-
83
0.1
-
-
ns
µC
June 1999
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
Transient thermal impedance, Zth j-mb (K/W)
Normalised Power Derating, Ptot (%)
100
100
10
D = 0.5
0.2
90
80
70
60
50
40
30
20
10
0
0.1
0.05
0.02
1
P
D = tp/T
D
tp
single pulse
0.1
T
0.01
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
0
20
40
60
80
100
120
140
160
Pulse width, tp (s)
Ambient temperature, Ta (C)
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Ta)
Fig.4. Transient thermal impedance.
Zth j-a = f(t); parameter D = tp/T
Drain Current, ID (A)
50
45
40
35
30
25
20
15
10
5
Normalised Current Derating, ID (%)
5 V
Tj = 25 C
120
100
80
60
40
20
0
VGS = 10 V
4.5 V
3 V
2.8 V
2.6 V
2.4 V
2.2 V
2 V
0
0
20
40
60
80
100
120
140
160
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Ambient temperature, Ta (C)
Drain-Source Voltage, VDS (V)
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Ta); conditions: VGS ≥ 5 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Peak Pulsed Drain Current, IDM (A)
100
Drain-Source On Resistance, RDS(on) (Ohms)
0.1
tp = 10 us
100 us
RDS(on) = VDS/ ID
2.6 V
2.2 V
2.4 V
Tj = 25 C
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
1 ms
10
1
10 ms
2.8V
100 ms
3 V
D.C.
0.1
0.01
VGS =4.5 V
10V
5 V
0.1
1
10
100
0
5
10
15
20
25
30
35
40
45
50
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
Fig.3. Safe operating area. Ta = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
June 1999
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
Threshold Voltage, VGS(TO) (V)
Drain current, ID (A)
50
2.25
2
VDS > ID X RDS(ON)
45
maximum
1.75
1.5
1.25
1
40
35
30
25
20
15
typical
minimum
0.75
0.5
0.25
0
10
5
150 C
Tj = 25 C
2.5
0
0
0.5
1
1.5
2
3
3.5
4
4.5
5
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Gate-source voltage, VGS (V)
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
GS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
V
Transconductance, gfs (S)
50
Drain current, ID (A)
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
VDS > ID X RDS(ON)
VDS = 5 V
45
Tj = 25 C
40
35
150 C
30
25
20
15
10
5
minimum
typical
maximum
0
0
0.5
1
1.5
2
2.5
3
0
5
10
15
20
25
30
35
40
Gate-source voltage, VGS (V)
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised On-state Resistance
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
Capacitances, Ciss, Coss, Crss (pF)
10000
Ciss
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1000
Coss
Crss
100
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
0.1
1
10
100
Junction temperature, Tj (C)
Drain-Source Voltage, VDS (V)
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
June 1999
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
Source-Drain Diode Current, IF (A)
VGS = 0 V
50
45
40
35
30
25
20
15
10
5
Gate-source voltage, VGS (V)
15
ID = 25A
14
13
12
11
10
9
Tj = 25 C
VDD = 15 V
150 C
8
7
6
5
4
3
2
1
Tj = 25 C
0
0
0
5
10
15
20
25
30
35
40
45
50
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5
Gate charge, QG (nC)
Source-Drain Voltage, VSDS (V)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
June 1999
5
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
MECHANICAL DATA
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A
)
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
0.25
0.01
0.25
0.1
1.75
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-05-22
SOT96-1
076E03S
MS-012AA
Fig.15. SOT96 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Integrated Circuit Packages, Data Handbook IC26.
3. Epoxy meets UL94 V0 at 1/8".
June 1999
6
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
June 1999
7
Rev 1.100
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