PHN1018 [NXP]

N-channel TrenchMOS transistor Logic level FET; N沟道晶体管的TrenchMOS逻辑电平FET


型号：	PHN1018
厂家：	NXP
描述：	N-channel TrenchMOS transistor Logic level FET N沟道晶体管的TrenchMOS逻辑电平FET 晶体晶体管
文件：	总7页 (文件大小：91K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

Logic level FET

PHN1018

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Low on-state resistance

• Fast switching

• Low-profile surface mount

package

V_DSS= 25 V

I_D= 9.6 A

_DS(ON)≤ 18 mΩ (V_GS= 10 V)

• Logic level compatible

R_DS(ON)≤ 21 mΩ (V_GS= 5 V)

GENERAL DESCRIPTION

PINNING

SOT96-1 (SO8)

N-channel enhancement mode

logic level field-effect power

transistor in a surface mounting

plastic package using ’trench’

technology.

DESCRIPTION

1-3

source

gate

Application:-

5-8

drain

•

High frequency computer

pin 1 index

motherboard d.c. to d.c. converters

The PHN1018 is supplied in the

SOT96-1 (SO8) surface mounting

package.

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

Drain-source voltage

Drain-gate voltage

T_j= 25 ˚C to 150˚C

T_j= 25 ˚C to 150˚C;

R_GS= 20 kΩ

V_GS

V_GSM

Gate-source voltage (DC)

Gate-source voltage (pulse peak

value)

± 15

± 20

I_D

Drain current (t_p≤ 10 s)

T_a= 25 ˚C

T_a= 70 ˚C

T_a= 25 ˚C

T_a= 70 ˚C

9.6

7.7

2.5

1.6

150

˚C

I_DM

P_tot

Drain current (pulse peak value)

Total power dissipation

T_j, T_stg

Operating junction and storage

temperature

- 55

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R_{th j-a}

Thermal resistance junction Surface mounted, FR4 board, t ≤ 10 sec

to ambient

K/W

R_{th j-a}

Thermal resistance junction Surface mounted, FR4 board

to ambient

150

K/W

October 1999

Rev 1.200

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

Logic level FET

PHN1018

ELECTRICAL CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

V_(BR)DSSDrain-source breakdown

CONDITIONS

MIN. TYP. MAX. UNIT

V_GS= 0 V; I_D= 0.25 mA;

V_DS= V_GS; I_D= 1 mA

0.6

mΩ

voltage

Gate threshold voltage

T_j= -55˚C

V_GS(TO)

1.5

0.05

T_j= 150˚C

T_j= -55˚C

2.3

R_DS(ON)

Drain-source on-state

resistance

V_GS= 10 V; I_D= 10 A

V_GS= 5 V; I_D= 10 A

V_GS= 5 V; I_D= 10 A; T_j= 150˚C

V_DS= 25 V; I_D= 10 A

g_fs

I_GSS

I_DSS

Forward transconductance

Gate source leakage current V_GS= ±5 V; V_DS= 0 V

Zero gate voltage drain

current

100

500

µA

V_DS= 25 V; V_GS= 0 V;

T_j= 150˚C

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 10 A; V_DD= 15 V; V_GS= 5 V

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 15 V; I_D= 25 A;

V_GS= 10 V; R_G= 5 Ω

Resistive load

6.4

L_d

L_s

Internal drain inductance

Internal source inductance

Drain leads to centre of die

Source leads to source bond pad

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 20 V; f = 1 MHz

1050

330

220

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_DR

Continuous source current

(body diode)

Pulsed source current (body

diode)

Diode forward voltage

T_a= 25 ˚C, t_p≤ 10 s

9.6

I_DRM

V_SD

I_F= 10 A; V_GS= 0 V

0.83

1.2

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_F= 10 A; -dI_F/dt = 100 A/µs;

V_GS= 0 V; V_R= 25 V

100

0.13

µC

October 1999

Rev 1.200

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

Logic level FET

PHN1018

Transient thermal impedance, Zth j-mb (K/W)

Normalised Power Derating, Ptot (%)

100

D = 0.5

0.2

0.1

0.05

0.02

D = tp/T

single pulse

0.1

0.01

1E-06

1E-05

1E-04

1E-03

1E-02

1E-01

1E+00

1E+01

100

120

140

160

Pulse width, tp (s)

Ambient temperature, Ta (C)

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_a)

Fig.4. Transient thermal impedance.

Z_{th j-a}= f(t); parameter D = t_p/T

Drain Current, ID (A)

VGS = 10 V

Normalised Current Derating, ID (%)

5 V

Tj = 25 C

120

100

4.5 V

3.2 V

3 V

2.8 V

2.6 V

2.4 V

2.2 V

100

120

140

160

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

Ambient temperature, Ta (C)

Drain-Source Voltage, VDS (V)

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_a); conditions: V_GS≥ 5 V

Fig.5. Typical output characteristics, T_j= 25 ˚C.

I_D= f(V_DS); parameter V_GS

Peak Pulsed Drain Current, IDM (A)

100

Drain-Source On Resistance, RDS(on) (Ohms)

0.1

tp = 10 us

100 us

RDS(on) = VDS/ ID

2.6 V

2.2 V

Tj = 25 C

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

2.4 V

2.8V

3 V

1 ms

10 ms

3.2 V

100 ms

D.C.

0.1

0.01

5 V

VGS =4.5 V

10V

0.1

100

Drain-Source Voltage, VDS (V)

Drain Current, ID (A)

Fig.3. Safe operating area. T_a= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.6. Typical on-state resistance, T_j= 25 ˚C.

R_DS(ON)= f(I_D); parameter V_GS

October 1999

Rev 1.200

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

Logic level FET

PHN1018

Threshold Voltage, VGS(TO) (V)

Drain current, ID (A)

2.25

VDS > ID X RDS(ON)

maximum

1.75

1.5

1.25

typical

minimum

0.75

0.5

0.25

150 C

Tj = 25 C

0.5

1.5

2.5

3.5

4.5

-60

-40

-20

100 120 140 160 180

Gate-source voltage, VGS (V)

Junction Temperature, Tj (C)

Fig.7. Typical transfer characteristics.

I_D= f(V_GS)

Fig.10. Gate threshold voltage.

_GS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= V_GS

Transconductance, gfs (S)

VDS > ID X RDS(ON)

Drain current, ID (A)

1.0E-01

1.0E-02

1.0E-03

1.0E-04

1.0E-05

1.0E-06

VDS = 5 V

Tj = 25 C

150 C

minimum

typical

maximum

0.5

1.5

2.5

Gate-source voltage, VGS (V)

Drain current, ID (A)

Fig.8. Typical transconductance, T_j= 25 ˚C.

g_fs= f(I_D)

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C; V_DS= V_GS

Normalised On-state Resistance

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

Capacitances, Ciss, Coss, Crss (pF)

10000

Ciss

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1000

Coss

Crss

100

-60

-40

-20

100 120 140 160 180

0.1

100

Junction temperature, Tj (C)

Drain-Source Voltage, VDS (V)

Fig.9. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j)

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); V_GS= 0 V; f = 1 MHz

October 1999

Rev 1.200

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

Logic level FET

PHN1018

Source-Drain Diode Current, IF (A)

VGS = 0 V

Gate-source voltage, VGS (V)

ID = 10A

Tj = 25 C

VDD = 15 V

150 C

Tj = 25 C

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1.1 1.2 1.3 1.4 1.5

Gate charge, QG (nC)

Source-Drain Voltage, VSDS (V)

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G)

Fig.14. Typical reverse diode current.

I_F= f(V_SDS); conditions: V_GS= 0 V; parameter T_j

October 1999

Rev 1.200

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

Logic level FET

PHN1018

MECHANICAL DATA

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

)

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

(2)

UNIT

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

1.27

0.050

1.05

0.041

0.25

0.01

0.25

0.1

1.75

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-02-04

97-05-22

SOT96-1

076E03S

MS-012AA

Fig.15. SOT96 surface mounting package.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static

discharge during transport or handling.

2. Refer to Integrated Circuit Packages, Data Handbook IC26.

3. Epoxy meets UL94 V0 at 1/8".

October 1999

Rev 1.200

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

Logic level FET

PHN1018

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

October 1999

Rev 1.200

PHN1018 [NXP]

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