PHN1013 [NXP]

N-channel enhancement mode MOS transistor; N沟道增强型MOS晶体管
PHN1013
型号: PHN1013
厂家: NXP    NXP
描述:

N-channel enhancement mode MOS transistor
N沟道增强型MOS晶体管

晶体 晶体管
文件: 总8页 (文件大小:64K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
DISCRETE SEMICONDUCTORS  
DATA SHEET  
PHN1013  
N-channel enhancement mode  
MOS transistor  
1997 Jun 20  
Objective specification  
File under Discrete Semiconductors, SC13b  
Philips Semiconductors  
Objective specification  
N-channel enhancement mode  
MOS transistor  
PHN1013  
FEATURES  
DESCRIPTION  
Very low on-state resistance.  
N-channel enhancement mode logic level field-effect  
power transistor using ‘trench’ technology, in an 8-pin  
plastic SOT96-1 (SO8) package.  
APPLICATIONS  
DC to DC converters  
General purpose switching applications.  
PINNING - SOT96-1 (SO8)  
d
handbook, halfpage  
5
4
8
PIN  
SYMBOL  
DESCRIPTION  
source  
1
2
3
4
5
6
7
8
s
s
s
g
d
d
d
d
g
source  
source  
gate  
1
s
MAM358  
Top view  
drain  
drain  
drain  
drain  
Fig.1 Simplified outline and symbol.  
QUICK REFERENCE DATA  
SYMBOL  
PARAMETER  
CONDITIONS  
MAX.  
UNIT  
VDS  
ID  
drain-source voltage  
drain current (DC)  
30  
10  
V
A
Ptot  
RDSon  
Tj  
total power dissipation  
2.5  
W
drain-source on-state resistance  
junction temperature  
VGS = 10 V  
13.5  
150  
mΩ  
°C  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL PARAMETER CONDITIONS  
VDS drain-source voltage  
MIN.  
MAX.  
30  
UNIT  
V
VDG  
VGS  
ID  
drain-gate voltage  
gate-source voltage  
drain current (DC)  
RGS = 20 kΩ  
30  
V
V
A
A
A
±20  
10  
Tamb = 25 °C; tp 10 s  
amb = 70 °C; tp 10 s  
T
8
IDM  
Ptot  
peak drain current  
Tamb = 25 °C  
Tamb = 25 °C  
Tamb = 70 °C  
50  
total power dissipation  
2.5  
1.6  
+150  
+150  
W
W
°C  
°C  
Tstg  
Tj  
storage temperature  
55  
55  
operating junction temperature  
1997 Jun 20  
2
Philips Semiconductors  
Objective specification  
N-channel enhancement mode  
MOS transistor  
PHN1013  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
MAX.  
UNIT  
Rth j-a  
thermal resistance from junction to ambient minimum footprint; tp 10 s; note 1  
50  
K/W  
Note  
1. Device mounted on an FR4 printed-circuit board.  
STATIC CHARACTERISTICS  
Tj = 25 °C unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
V(BR)DSS  
drain-source breakdown voltage VGS = 0; ID = 250 µA  
30  
27  
2.1  
1.4  
3
V
V
GS = 0; ID = 250 µA; Tj = 55 °C  
V
VGSth  
gate-source threshold voltage  
VDS = VGS; ID = 250 µA  
4
V
VDS = VGS; ID = 250 µA; Tj = 150 °C  
V
V
DS = VGS; ID = 250 µA; Tj = 55 °C  
VDS = 30 V; VGS = 0  
DS = 30 V; VGS = 0; Tj = 150 °C  
VGS = ±10 V; VDS = 0  
4.4  
V
IDSS  
drain-source leakage current  
gate leakage current  
0.05 10  
µA  
µA  
nA  
V
500  
100  
IGSS  
10  
11  
RDSon  
drain-source on-state resistance VGS = 10 V; ID = 10 A  
GS = 10 V; ID = 10 A; Tj = 150 °C  
13.5 mΩ  
26 mΩ  
V
DYNAMIC CHARACTERISTICS  
Tj = 25 °C unless otherwise specified.  
SYMBOL  
gfs  
PARAMETER  
forward transconductance  
input capacitance  
CONDITIONS  
MIN. TYP. MAX. UNIT  
VDS = 25 V; ID = 10 A  
4
8
S
Ciss  
Coss  
Crss  
QG  
VGS = 0; VDS = 25 V; f = 1 MHz  
VGS = 0; VDS = 25 V; f = 1 MHz  
VGS = 0; VDS = 25 V; f = 1 MHz  
VGS = 5 V; VDD = 24 V; ID = 10 A  
VGS = 5 V; VDD = 24 V; ID = 10 A  
VGS = 5 V; VDD = 24 V; ID = 10 A  
1700 2200 pF  
output capacitance  
325  
214  
27  
450  
260  
pF  
pF  
nC  
nC  
nC  
reverse transfer capacitance  
total gate charge  
QGS  
QGD  
gate-source charge  
gate-drain charge  
3.5  
15  
Switching times  
td(on)  
td(off)  
tr  
turn-on delay time  
VGS = 5 V; VDD = 25 V; ID = 10 A;  
Rgen = 10 resistive load  
25  
90  
75  
35  
40  
ns  
ns  
ns  
ns  
turn-off delay time  
rise time  
VGS = 5 V; VDD = 25 V; ID = 10 A;  
Rgen = 10 resistive load  
130  
125  
50  
VGS = 5 V; VDD = 25 V; ID = 10 A;  
Rgen = 10 resistive load  
tf  
fall time  
VGS = 5 V; VDD = 25 V; ID = 10 A;  
Rgen = 10 resistive load  
1997 Jun 20  
3
Philips Semiconductors  
Objective specification  
N-channel enhancement mode  
MOS transistor  
PHN1013  
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS  
Tj = 25 °C unless otherwise specified.  
SYMBOL  
IDR  
IDRM  
VSD  
PARAMETER  
CONDITIONS  
Tamb = 25 °C; tp 10 s  
TYP. MAX. UNIT  
continuous reverse drain current  
pulsed reverse drain current  
10  
50  
1.2  
A
A
source-drain diode forward voltage  
IF = 10 A; VGS = 0  
0.95  
1
V
IF = 50 A; VGS = 0  
V
trr  
reverse recovery time  
IF = 10 A; di/dt = 100 A/µs;  
50  
ns  
V
GS = 10 V; VR = 25 V  
Qrr  
reverse recovery charge  
IF = 10 A; di/dt = 100 A/µs;  
VGS = 10 V; VR = 25 V  
0.1  
µC  
1997 Jun 20  
4
Philips Semiconductors  
Objective specification  
N-channel enhancement mode  
MOS transistor  
PHN1013  
PACKAGE OUTLINE  
SO8: plastic small outline package; 8 leads; body width 3.9 mm  
SOT96-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
4
e
w
M
detail X  
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
5.0  
4.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.050  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.20  
0.014 0.0075 0.19  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.024  
0.028  
0.012  
inches 0.069  
0.01 0.004  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
95-02-04  
97-05-22  
SOT96-1  
076E03S  
MS-012AA  
1997 Jun 20  
5
Philips Semiconductors  
Objective specification  
N-channel enhancement mode  
MOS transistor  
PHN1013  
DEFINITIONS  
Data Sheet Status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
1997 Jun 20  
6
Philips Semiconductors  
Objective specification  
N-channel enhancement mode  
MOS transistor  
PHN1013  
NOTES  
1997 Jun 20  
7
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Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825  
© Philips Electronics N.V. 1997  
SCA54  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
137107/00/01/pp8  
Date of release: 1997 Jun 20  
Document order number: 9397 750 02452  

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