PC33897AEF [NXP]
DATACOM, INTERFACE CIRCUIT, PDSO14, LEAD FREE, SOIC-14;
| 型号： | PC33897AEF |
| 厂家： | 
NXP |
| 描述： | DATACOM, INTERFACE CIRCUIT, PDSO14, LEAD FREE, SOIC-14 电信 光电二极管 电信集成电路 |
| 文件： | 总16页 (文件大小：325K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33897/D
Rev 6.0, 09/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
33897
33897A
Single-Wire CAN Transceiver
The 33897 provides a physical layer for digital communications purposes
using a Carrier Sense Multiple Access/Collision Resolution (CSMA/CR) data
link operating over a single-wire medium. This is more commonly referred to
as single-wire Controller Area Network (CAN).
SINGLE-WIRE CAN
TRANSCEIVER
The 33897 operates directly from a vehicle's 12 V battery system or a broad
range of DC-power sources. It can operate at either low or high (33.33 kbps
and 83.33 kbps) data rates. A high-voltage wake-up feature allows the 33897
to control the regulator used in support of the MCU and other logic. The 33897
includes a control terminal that can be used to put the module regulator into
Sleep mode. The presence of a defined wake-up voltage level on the bus will
reactivate the control line to turn the regulator and the system back on.
The 33897 complies with the GM3089v2.0 General Motors Corporation
specification.
Features
D SUFFIX
• Waveshaping for Low EMI
EF (Pb-FREE) SUFFIX
CASE 751A-03
14-LEAD NARROW SOIC
• Detects and Automatically Handles Loss of Ground
• Worst-Case Sleep Mode Current of Only 80 µA
• Current Limit Prevents Damage Due to Bus Shorts
• Built-In Thermal Shutdown on Bus Output
• Protected Against Vehicular Electrical Transients
• Undervoltage Lockout Prevents False Data with Low Battery
• Pb-Free Packaging Designated by Suffix Code EF
ORDERING INFORMATION
Temperature
Package
Device
Range (T )
A
MC33897D/R2
MC33897EF/R2
PC33897AD/R2
PC33897AEF/R2
-40°C to 125°C
14 SOICN
33897 Simplified Application Diagram
Power
Source
VCC
Voltage
Regulator
EN
33897
VCC
GND
TXD
GND
NC
SWCAN Bus
MODE0
MODE1
RXD
BUS
Battery
MCU
LOAD
VBATT
CNTL
GND
NC
GND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
For More Information On This Product,
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© Motorola, Inc. 2004
Freescale Semiconductor, Inc.
Table 1. Significant Device Differences
Load Voltage Sleep Mode
Motorola Part No.
Significant Device Differences
See Page
(VLDRISE
)
33897
–
6
6
1.0 V Maximum
0.1 V Maximum
33897A
Removes diode drop during Sleep
Mode.
TXD BUS DRVR
MODE0
MODE1
HVWU Enable
BUS
Waveshaping Enable
Mode
Control
TXD Data
Disable
BUS RCVR
HVWUDetect
RX Data
Disable
TXD
RXD
Undervoltage
Detect
VBATT
Timer
OSC
Timers
Load Switch
LOAD
GND
CNTL
Figure 1. 33897 Simplified Internal Block Diagram
33897
2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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1
2
3
4
5
6
7
14
13
12
11
10
9
GND
TXD
GND
NC
MODE0
MODE1
RXD
BUS
LOAD
VBATT
CNTL
GND
NC
8
GND
TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section beginning on page 11.
Terminal
Name
Terminal
Formal Name
Definition
1, 7, 8, 14
GND
Ground
Electrical Common Ground and Heat removal. A good thermal path will also reduce the
die temperature.
2
3, 4
5
TXD
MODEn
RXD
Transmit Data
Mode Control
Receive Data
Data input here will appear on the BUS terminal. A logic “0” will assert the bus, a “1” will
go to the recessive state.
These terminals control Sleep Mode, Transmit Level, and Speed. They have weak
pulldowns.
Open drain output of the data on BUS. A recessive bus = “1”, dominant = “0”. An
external pullup is required.
6, 13
9
NC
No connect
Control
Battery
Load
No internal connection to this terminal.
CNTL
VBATT
LOAD
Provides a battery-level logic signal.
10
Power input. An external diode is needed for reverse battery protection.
11
The external bus load resistor connects here to prevent bus pullup in the case of loss of
module ground.
12
BUS
Bus
This terminal connects to the bus through external components.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33897
3
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Supply Voltage
VBATT
VIN
VRXD
VCNTL
-0.3 to 40
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 40
V
V
V
V
V
Input Logic Voltage
RXD
CNTL
ESD Voltage
V
±2000
±200
Human Body Model (Note 1)
Machine Model (Note 2)
ESD1
V
ESD2
THERMAL RATINGS
°C
Operating Temperature
Ambient
T
-40 to 125
-40 to 150
A
T
Junction
J
Storage Temperature
TSTG
RθJA
-55 to 150
150
°C
°C/W
°C
Junction-to-Ambient Thermal Resistance
T
Peak Package Reflow Temperature During Solder Mounting (Note 3)
SOLDER
245
260
D Suffix
EF (Pb-Free) Suffix
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (C
=100 pF, R
=1500 Ω).
ZAP
ZAP
2. ESD2 testing is performed in accordance with the Machine Model (C
=200 pF, R
=0 Ω).
ZAP
ZAP
3. Terminal soldering temperature limit is for 10 second maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
33897
4
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C unless otherwise noted. Voltages are relative to GND unless otherwise
noted. All positive currents are into the terminal. All negative currents are out of the terminal.
Characteristic
Symbol
Min
Typ
Max
Unit
LOGIC I/O
Logic Input Low Level (MODE0, MODE1, and TXD)
VIL
V
V
5.0 V ≤ VBATT ≤ 26.5 V
0
–
–
–
–
–
–
0.8
–
Logic Input High Level (MODE0, MODE1, and TXD)
VIH
5.0 V ≤ VBATT ≤ 26.5 V
2.0
Mode Terminal Pulldown Current (MODE0 and MODE1)
IPD
µA
V
Terminal Voltage = 0.8 V, 5.0 V ≤ VBATT ≤ 26.5 V
10
50
Receiver Output Low
VOL
IIN = 2.0 mA, 5.0 V ≤ VBATT ≤ 26.5 V
0
0.45
0.8
CNTL Output Low
VOLCNTL
V
IIN = 5.0 µA, 5.0 V ≤ VBATT ≤ 26.5 V
0
CNTL Output High
VOHCNTL
V
IOUT = 180 µA, 5.0 V ≤ VBATT ≤ 26.5 V
VBATT - 0.8
VBATT
GENERAL
Passive Out BUS Leakage
Passive In
µA
ILEAK
10
10
10
–
–
–
-10
-10
-10
0 V ≤ VBATT ≤ 26.5 V, -1.5 V ≤ VBUS < 0 V
Active In
0 V ≤ VBATT ≤ 26.5 V, 0 V < VBUS ≤ 12.5 V
ILKAI
BUS Leakage During Loss of Module Ground (Note 4)
0 V ≤ VBATT ≤ 18 V
IBLKLOG
Quiescent Current
Sleep
IQSLP
IQATDIS
IQATEN
5.0 V ≤ VBATT ≤ 13 V (Note 5)
0
0
45
–
80
µA
Awake with Transmitter Disabled
5.0 V ≤ VBATT ≤ 26.5 V
4.0
mA
Awake with Transmitter Enabled
5.0 V ≤ VBATT ≤ 26.5 V
0
2.5
0
–
4.8
–
9.0
5.0
0.5
mA
V
Undervoltage Shutdown
Undervoltage Hysteresis
VBATTUV
VUVHYS
V
Notes
4. BUS terminal is at system ground voltage.
5. After t
.
CNTLFDLY
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33897
5
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C unless otherwise noted. Voltages are relative to GND unless otherwise
noted. All positive currents are into the terminal. All negative currents are out of the terminal.
Characteristic
Symbol
Min
Typ
Max
Unit
GENERAL (continued)
LOAD Voltage Rise (Note 6)
VLDRISE
V
Normal Speed and Voltage Mode, Transmit High-Voltage Mode, Transmit
High-Speed Mode
I
IN = 1.0 mA, 5.0 V ≤ VBATT ≤ 26.5 V
0
–
0.1
Sleep Mode
0
0
–
–
1.0
0.1
33897 IIN = 7.0 mA
33897A IIN = 7.0 mA (Note 7)
Loss of Battery
IIN = 7.0 mA
0
0
–
–
1.0
-90
ILDLEAK
µA
LOAD Leakage During Loss of Module Ground (Note 8)
0 V ≤ VBATT ≤ 18 V
TRANSMITTER
High-Voltage Wake-up Mode Output High Voltage
12 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω
5.0 V ≤ VBATT < 12 V, 200 Ω ≤ RL ≤ 3332 Ω
V
VHVWUOHF
VHVWUOHO
9.7
–
–
12.5
Lesser of
BATT - 1.5
VBATT
V
or 9.7
High-Speed Mode Output High Voltage
VOHHS
V
V
8.0 V ≤ VBATT ≤ 16 V, 75 Ω ≤ RL ≤ 135 Ω
4.2
–
5.1
5.1
Normal Mode Output High Voltage
6.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω
5.0 V ≤ VBATT < 6.0 V, 200 Ω ≤ RL ≤ 3332 Ω
VNOHF
VNOHO
4.4
–
–
Lesser of
BATT - 1.6
Lesser of
VBATT
V
or 4.4
or 5.1
BUS Low Voltage
VOL
V
5.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω
-0.2
-150
150
10
–
–
–
–
0.2
Short Circuit BUS Output Current
IBSC
mA
°C
°C
Dominant State, 5.0 V ≤ VBATT ≤ 26.5 V
-350
190
20
Thermal Shutdown (Note 7), (Note 9)
TSD
5.0 V ≤ VBATT ≤ 26.5 V
Thermal Shutdown Hysteresis (Note 7)
TSDHYS
5.0 V ≤ VBATT ≤ 26.5 V
Notes
6. GMW3089V2.3 specifies the maximum load voltage rise to be 0.1 V whenever module battery is intact, including when in Sleep mode. The
maximum load voltage rise of 1.0 V in Sleep mode is a GM-approved exception to GMW3089V2.3.
7. ”A” removes diode drop during Sleep state.
8. LOAD terminal is at system ground voltage.
9. Thermal shutdown causes the BUS output driver to be disabled.
33897
6
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C unless otherwise noted. Voltages are relative to GND unless otherwise
noted. All positive currents are into the terminal. All negative currents are out of the terminal.
Characteristic
Symbol
Min
Typ
Max
Unit
RECEIVER
Input Threshold
Awake
V
5.0 V ≤ VBATT ≤ 26.5 V
Sleep
12 V ≤ VBATT ≤ 26.5 V
Sleep
5.0 V ≤ VBATT < 12 V
VBIA
VBISF
VBISO
2.0
6.6
–
2.2
7.9
–
–
Lesser of
6.6 V or
Lesser of
7.9 V or
V
-4.3
V
-3.25
BATT
BATT
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33897
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C unless otherwise noted. Voltages are relative to GND unless otherwise
noted. All positive currents are into the terminal. All negative currents are out of the terminal.
Characteristic
Symbol
Min
Typ
Max
Unit
TRANSMITTER
Normal Speed Rising Output Delay
µs
tDLYNORMRO
200 Ω ≤ RL ≤ 3332 Ω, 1.0 µs ≤ Load Time Constance ≤ 4.0 µs
Measured from TXD = VIL to VBUS as follows:
2.0
–
6.3
Max Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (Note 10)
Min Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (Note 10)
Max Time to VBUSMOD = 2.7 V, VBATT = 5.0 V (Note 10)
Min Time to VBUSMOD = 1.0 V, VBATT = 5.0 V (Note 10)
Normal Speed Falling Output Delay
µs
tDLYNORMFO
200 Ω ≤ RL ≤ 3332 Ω, 1.0 µs ≤ Load Time Constance ≤ 4.0 µs
Measured from TXD = VIH to VBUS as follows:
1.8
–
8.5
Max Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (Note 10)
Min Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (Note 10)
Max Time to VBUSMOD = 1.0 V, VBATT = 5.0 V (Note 10)
Min Time to VBUSMOD = 2.7 V, VBATT = 5.0 V (Note 10)
High-Speed Rising Output Delay
µs
tDLYHSRO
75 Ω ≤ RL ≤ 135 Ω, 0 µs ≤ Load Time Constant ≤ 1.5 µs,
0.1
–
2.0
8.0 V ≤ V
≤ 16 V
BATT
Measured from TXD = VIL to VBUS as follows:
Max Time to VBUS = 3.7 V (Note 11)
Min Time to VBUS = 1.0 V (Note 11)
High-Speed Falling Output Delay
µs
tDLYHSFO
75 Ω ≤ RL ≤ 135 Ω, 0 µs ≤ Load Time Constant ≤ 1.5 µs,
0.04
–
3.0
8.0 V ≤ V
≤ 16 V
BATT
Measured from TXD = VIH to VBUS as follows:
Max Time to VBUS = 1.0 V (Note 11)
Min Time to VBUS = 3.7 V (Note 11)
Notes
10.
11.
V
V
is the voltage at the BUSMOD node in Figure 2, page 10.
BUSMOD
is the voltage at the BUS terminal in Figure 3, page 10.
BUS
33897
8
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C unless otherwise noted. Voltages are relative to GND unless otherwise
noted. All positive currents are into the terminal. All negative currents are out of the terminal.
Characteristic
Symbol
Min
Typ
Max
Unit
TRANSMITTER (continued)
High-Voltage Rising Output Delay
µs
tDLYHVRO
200 Ω ≤ RL ≤ 3332 Ω, 1.0 µs ≤ Load Time Constance ≤ 4.0 µs
Measured from VIL to VBUS as follows:
2.0
2.0
2.0
–
–
–
6.3
6.3
18
Max Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (Note 12)
Min Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (Note 12)
Max Time to VBUSMOD = 9.4 V, 12.0 V ≤ VBATT ≤ 26.5 V (Note 12)
High-Voltage Falling Output Delay
µs
tDLYHVFO
200 Ω ≤ RL ≤ 3332 Ω, 1.0 µs ≤ Load Time Constance ≤ 4.0 µs,
12.0 V ≤ VBATT ≤ 26.5 V
Measured from VIH to VBUS as follows:
Max Time to VBUSMOD = 1.0 V (Note 12)
Min Time to VBUSMOD = 3.7 V (Note 12)
1.8
1.8
–
–
13.7
13.7
RECEIVER
µs
µs
t
Receive Delay Time (5.0 V ≤ VBATT ≤ 26.5 V)
RDLY
0.2
10
–
–
1.0
70
Awake
t
Receive Delay Time (BUS Rising to RXD Falling, 5.0 V ≤ VBATT ≤ 26.5 V)
RDLYSL
Sleep
LOGIC I/O
300
–
1000
ms
t
CNTL Falling Delay Time (5.0 V ≤ VBATT ≤ 26.5 V)
CNTLFDLY
Notes
12.
V
is the voltage at the BUSMOD node in Figure 2, page 10.
BUSMOD
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33897
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VBATT
100 pF
1.0 kΩ
47 µH
33897
BUSMOD
BUS
6.49 kΩ
(n -1)
6.49 kΩ
C
= 100 pF + (n -1) 220 pF
R=
NOM
LOAD
GND
Figure 2. Transmitter Delays in Normal and High-Voltage Wake-up Modes
33897
BUS
6.49 kΩ
(n -1)
6.49 kΩ
130 Ω
C
= (n) 220 pF
R=
NOM
LOAD
GND
Figure 3. Transmitter Delays in High-Speed Mode
33897
10
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33897 is intended for use as a physical layer device in a
communications where the radiated EMI of the higher rate
single-wire CAN communications bus. The communications
takes place from a single terminal over a single wire using a
common ground for a current return path. Two data rates are
available, with the high rate used for factory or assembly line
communications and the lower for actual system
could be an issue.
Two terminals control of the mode of operation (sleep, low-
speed, high-speed, and high-voltage wake-up).
BLOCK DIAGRAM COMPONENTS
Timer OSC
TXD BUS DRVR
This circuit generates a 500 kHz signal to be used for internal
logic. It is the reference for some of the required delays.
This circuit drives the BUS. It can drive it with the higher
voltage wake-up signals when enabled by the Mode Control
circuit. It can also provide waveshaping for reduced EMI or not
provide it for the higher data rate mode. The actual data is
received on TXD at CMOS logic levels, then translated by this
circuit to the necessary operating voltages.
Timers
This circuit contains the timing logic used to hold the CNTL
active for the required time after the conditions for sleep mode
have been met. It is also used to keep the TXD driver active for
a period of time after it has generated a passive level on the
bus.
Undervoltage Detect
This circuit monitors internal operating voltage to assure
proper operation of the part. If a low-voltage condition is
detected, it sends a signal to disable the BUS RCVR and TXD
BUS DRVR circuits. This prevents incorrect data from being put
on the bus or sent to the MCU.
Mode Control
This circuit contains the control logic for the various
operating modes and conditions required for the IC.
Load Switch
BUS RCVR
The LOAD switch provides a path for an external resistor
connected to the BUS to be connected to ground. When a loss
of ground is detected, this switch is opened to prevent the
current that would normally be flowing to the ground from the
module from going back through the load resistor and raising
the bus level. The circuit is opened when the voltage between
GND and VBATT becomes too low as would be the case if
module ground were lost.
This circuit translates the levels on the BUS terminal to a
CMOS level indicating the presence of a data 0 or 1. It also
determines the presence of a high-voltage wake-up (HVWU)
signal that is passed to Mode Control and Timers circuits. An
analog filter is used to “de-glitch” the high-voltage wake-up
signal and prevent false exits from the sleep mode.
OPERATION
The 33897 is intended to be used with an MCU to control its
operation and to process and generate the data for the bus.
(recessive) state (bus at near zero volts). When the TXD
terminal is low, the output goes to a driven state. The voltage
and waveshaping in the driven state is determined by the levels
on the MODE0 and MODE1 terminals (refer to Table 2).
Ground Terminals
The four ground terminals are not only for electrical
conduction, their number and locations at each of the four
corners serve also to remove heat from the IC. The biggest
benefit of this is obtained by putting a lot of copper on the PCB
in this area and, if ground is an internal layer, by adding
numerous plated- through connections to it with the largest
diameter holes the layout can use.
Table 2. Mode Control
MODE0
MODE1
Operation
Sleep Mode
0
0
0
1
Transmit High Voltage
(Wake-up)
1
1
0
1
Transmit High Speed
TXD Data
Normal Speed and Voltage
The data driven onto the SWCAN bus is inverted from the
TXD terminal. A “1” driven on TXD will result in an undriven
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Mode Control
CNTL Output
The MODE terminals control the transmitter filtering and
BUS voltage and the IC sleep mode operation. Table 2 shows
the mode versus the logic levels on MODE0 and MODE1.
This logic level signal is used to control a VCC regulator.
When the output is low, the VCC regulator is expected to
shutdown. This is normally used to shut down the MCU and all
the devices powered by VCC when the IC is in sleep mode. This
is done to save power. When the part is taken out of the sleep
mode by the higher-than-normal bus voltage, this terminal is
asserted high and the VCC regulator brings its output up to the
The MODE0 and MODE1 terminals have a weak pulldown in
the IC so that in case the terminals are not driven, the device
will enter the sleep mode. This is usually the situation as the
MCU comes out of reset, before the driving signals have been
configured as outputs.
regulated level. This starts the MCU, which controls the mode
of the IC. The MCU must change the mode signals to non-sleep
mode levels in order to keep this terminal from going low. There
is a delay to allow the MCU to fully wake up and take control
after the high-voltage signaling is removed before the level on
this output returns low. After a delay time, even if the bus is at
high voltage, the IC will return to sleep mode if both MODE
terminals are low.
RX Data
The data received on the bus is translated to logic levels on
this terminal. This terminal is a logic high when the bus is in the
recessive state (near zero volts) and is low when the bus is in
either the normal or high-voltage dominant state.
This is an open-drain type of output that requires an external
resistor to pull it up. When the device is in sleep mode, the
output will be off unless a high-voltage wake-up level is
detected on the bus. If the wake-up level is detected, the output
will be driven by the data on the bus. If the level of the data
returns to normal level, the output will return to off after a short
delay unless a non-sleep mode condition is set by the MCU.
VBATT Input
This power input is not reverse battery protected and should
use an external diode to protect it from damage owing to
reverse battery if this protection is desired. The voltage drop of
the diode must be taken into consideration when the operating
range of the system is being determined. This diode is generally
used to protect the entire module from reverse battery and
should be selected accordingly.
LOAD Switch
This switch is on in all operating modes unless a loss of
ground is detected. If this happens, the switch is opened and
the resistor normally attached to its terminal will be no longer
pass current to or from the bus.
BUS I/O
This input/output may require ESD and/or EMI external
circuitry. A set of components is shown in the Simplified
Application Diagram on the front of this datasheet. The value of
the capacitor should be adjusted downward in direct proportion
to the added capacitance of the ESD or EMI circuits. The series
resistance of the inductor should be kept below 3.5 Ω to prevent
its voltage drop from significantly degrading system noise
margins.
33897
12
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APPLICATIONS
Figure 4 shows a typical application schematic for the 33897.
Power
Source
V
CC
Voltage
Regulator
EN
33897
1.0 kΩ
2.7 kΩ
10 kΩ
GND
TXD
V
GND
CC
47
µ
H
SWCAN Bus
NC
BUS
100 pF
Battery
MODE0
MODE1
RXD
6.49 k
100 pF
100 nF
Ω
LOAD
VBATT
CNTL
GND
MCU
4.7 µF
NC
GND
Figure 4. 33897 Typical Application Schematic
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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PACKAGE DIMENSIONS
D SUFFIX
EF (Pb-FREE) SUFFIX
14-LEAD SOICN
PLASTIC PACKAGE
CASE 751A-03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-A-
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
14
1
8
7
-B-
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM MIN
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
°
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
0.337
0.150
0.054
0.014
0.016
-T-
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
5.80
0.25
0.25
0.25
7
6.20
0.50
0.008
0.004
0
0.228
0.010
0.009
0.009
7
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
°
°
°
°
33897
14
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33897
15
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