PC33897EF [NXP]
DATACOM, INTERFACE CIRCUIT, PDSO14, LEAD FREE, PLASTIC, SOIC-14;
| 型号： | PC33897EF |
| 厂家： | 
NXP |
| 描述： | DATACOM, INTERFACE CIRCUIT, PDSO14, LEAD FREE, PLASTIC, SOIC-14 电信 光电二极管 电信集成电路 |
| 文件： | 总16页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33897/D
Rev 5.0, 05/2004
Advance Information
33897
Single-Wire CAN Transceiver
The 33897 is intended to be used as the physical interface in an SWCAN
(Single-Wire Controller Area Network) application. It supports both the
standard 33.333 kbps communications rate and the high-speed service rate of
83.333 kbps. The modes (speed, high-voltage wake-up [HVWU], and sleep)
are controlled by the state of two input pins for easy MCU interfacing.
SINGLE-WIRE CAN
TRANSCEIVER
Features
• 33.33 kbps Data Rate with Loading per J2411
• Waveshaping for Low EMI
• High-Speed Mode up to 83.33 kbps
• Responds to High-Voltage Wake-up
• CNTL Output to External Regulator for Bus-Controlled Module Wake-up
• Built-In Delay Timers to Allow MCU-Required Wake-up Timing
• Detects and Automatically Handles Loss of Ground
• Extended Frame Tolerance
D SUFFIX
• Worst-Case Sleep Mode Current of Only 80 µA
• Current Limit Prevents Damage Due to Bus Shorts
• Built-In Thermal Shutdown on Bus Output
• Protected Against Vehicular Electrical Transients
• Undervoltage Lockout Prevents False Data with Low Battery
• Designed to Meet GMW3089V2.3 Requirements
• Pb-Free Packaging Designated by Suffix Code EF
EF (Pb-FREE) SUFFIX
CASE 751A-03
14-LEAD NARROW SOIC
ORDERING INFORMATION
Temperature
Package
Device
Range (T )
A
PC33897D/R2
PC33897EF/R2
-40°C to 125°C
14 SOICN
33897 Simplified Application Diagram
Power
Source
VCC
Voltage
Regulator
EN
33897
VCC
GND
TXD
GND
NC
SWCAN Bus
MODE0
MODE1
RXD
BUS
Battery
MCU
LOAD
VBATT
CNTL
GND
NC
GND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
For More Information On This Product,
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© Motorola, Inc. 2004
Freescale Semiconductor, Inc.
TX BUS DRVR
MODE0
MODE1
HVWU Enable
BUS
Waveshaping Enable
Mode
Control
TX Data
Disable
BUS RCVR
HVWU D
etect
RX Data
Disable
TXD
RXD
Undervoltage
Detect
VBATT
Timer
OSC
Timers
Load Switch
LOAD
GND
CNTL
Figure 1. 33897 Simplified Internal Block Diagram
33897
2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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1
2
3
4
5
6
7
14
13
GND
TXD
GND
NC
12
11
10
9
MODE0
MODE1
RXD
BUS
LOAD
VBATT
CNTL
GND
NC
8
GND
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Formal Name
Definition
1, 7, 8, 14
GND
Ground
Electrical Common Ground and Heat removal. A good thermal path will also reduce the
die temperature.
2
3, 4
5
TXD
MODEn
RXD
Transmit Data
Mode Control
Receive Data
Data input here will appear on the BUS pin. A logic “0” will assert the bus, a “1” will go
to the recessive state.
These pins control Sleep Mode, Transmit Level, and Speed. They have weak pull-
downs.
Open drain output of the data on BUS. A recessive bus = “1”, dominant = “0”. An
external pull-up is required.
6, 13
9
NC
No connect
Control
Battery
Load
No internal connection to this pin.
CNTL
VBATT
LOAD
Provides a battery-level logic signal.
10
Power input. An external diode is needed for reverse battery protection.
11
The external bus load resistor connects here to prevent bus pull-up in the case of loss
of module ground.
12
BUS
Bus
This pin connects to the bus through external components.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33897
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Supply Voltage
V
-0.3 to 40
V
BATT
Input Logic Voltage
V
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 40
V
V
V
V
IN
RXD
V
RXD
CNTL
V
CNTL
ESD Voltage
V
2000
200
Human Body Model (Note 1)
Machine Model (Note 2)
ESD1
ESD2
V
Storage Temperature
T
-55 to 150
-40 to 125
-40 to 150
150
°C
°C
STG
Operating Ambient Temperature
Operating Junction Temperature
Junction-to-Ambient Thermal Resistance
T
A
T
°C
J
R
°C/W
°C
θJA
SOLDER
T
Terminal Soldering Temperature (Note 3)
D Suffix
245
260
EF (Pb-Free) Suffix
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (C
=100 pF, R
=1500 Ω).
ZAP
ZAP
2. ESD2 testing is performed in accordance with the Machine Model (C
=200 pF, R
=0 Ω).
ZAP
ZAP
3. Terminal soldering temperature limit is for 10 second maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
33897
4
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C unless otherwise noted. Voltages are relative to GND unless otherwise
noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
LOGIC I/O
Logic Input Low Level (MODE0, MODE1, and TXD)
5.0 V ≤ V ≤ 26.5 V
V
V
V
IL
0
2.0
10
0
–
–
–
–
–
–
0.8
–
BATT
Logic Input High Level (MODE0, MODE1, and TXD)
5.0 V ≤ V ≤ 26.5 V
V
IH
BATT
Mode Pin Pull-Down Current (MODE0 and MODE1)
I
µA
V
PD
Pin Voltage = 0.8 V, 5.0 V ≤ V
≤ 26.5 V
50
BATT
Receiver Output Low
V
OL
I
= 2.0 mA, 5.0 V ≤ V
≤ 26.5 V
0.45
0.8
IN
BATT
CNTL Output Low
= 5.0 µA, 5.0 V ≤ V
V
V
OLCNTL
OHCNTL
I
≤ 26.5 V
0
IN
BATT
CNTL Output High
= 180 µA, 5.0 V ≤ V
V
V
I
≤ 26.5 V
V
- 0.8
V
BATT
OUT
BATT
BATT
GENERAL
Passive Out BUS Leakage
Passive In
µA
I
10
10
10
–
–
–
-10
-10
-10
0 V ≤ V
≤ 26.5 V, -1.5 V ≤ V
< 0 V
BUS
LEAK
BATT
Active In
0 V ≤ V
≤ 26.5 V, 0 V < V
≤ 12.5 V
I
BATT
BUS
LKAI
BUS Leakage During Loss of Module Ground (Note 4)
0 V ≤ V ≤ 18 V
I
BATT
BLKLOG
Quiescent Current
Sleep
I
QSLP
5.0 V ≤ V
≤ 13 V (Note 5)
BATT
0
0
45
–
80
µA
Awake with Transmitter Disabled
5.0 V ≤ V ≤ 26.5 V
I
QATDIS
BATT
4.0
mA
Awake with Transmitter Enabled
5.0 V ≤ V ≤ 26.5 V
I
QATEN
0
2.5
0
–
4.8
–
9.0
5.0
0.5
mA
V
BATT
Undervoltage Shutdown
Undervoltage Hysteresis
V
BATTUV
V
V
UVHYS
Notes
4. BUS pin is at system ground voltage.
5. After t
.
CNTLFDLY
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33897
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C unless otherwise noted. Voltages are relative to GND unless otherwise
noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
GENERAL (continued)
LOAD Voltage Rise (Note 6)
V
V
LDRISE
Normal Speed and Voltage Mode, Transmit High-Voltage Mode, Transmit
High-Speed Mode
I
= 1.0 mA, 5.0 V ≤ V
≤ 26.5 V
0
0
0
–
–
–
0.1
1.0
1.0
IN
BATT
Sleep Mode (Note 8)
= 7.0 mA
I
IN
Loss of Battery
= 7.0 mA
I
IN
I
µA
LOAD Leakage During Loss of Module Ground (Note 7)
0 V ≤ V ≤ 18 V
LDLEAK
0
–
-90
BATT
TRANSMITTER
High-Voltage Wake-up Mode Output High Voltage
V
12 V ≤ V
≤ 26.5 V, 200 Ω ≤ R ≤ 3332 Ω
V
V
9.7
–
–
12.5
BATT
L
HVWUOHF
Lesser of
V
BATT
5.0 V ≤ V
< 12 V, 200 Ω ≤ R ≤ 3332 Ω
BATT
L
HVWUOHO
V
- 1.5
BATT
or 9.7
High-Speed Mode Output High Voltage
8.0 V ≤ V ≤ 16 V, 75 Ω ≤ R ≤ 135 Ω
V
V
V
OHHS
4.2
–
5.1
BATT
L
Normal Mode Output High Voltage
6.0 V ≤ V
5.0 V ≤ V
≤ 26.5 V, 200 Ω ≤ R ≤ 3332 Ω
V
V
4.4
–
–
5.1
BATT
BATT
L
NOHF
Lesser of
- 1.6
Lesser of
< 6.0 V, 200 Ω ≤ R ≤ 3332 Ω
L
NOHO
V
V
BATT
BATT
or 4.4
or 5.1
0.2
BUS Low Voltage
V
V
OL
5.0 V ≤ V
≤ 26.5 V, 200 Ω ≤ R ≤ 3332 Ω
-0.2
-150
150
10
–
–
–
–
BATT
L
Short Circuit BUS Output Current
I
mA
°C
°C
BSC
Dominant State, 5.0 V ≤ V
≤ 26.5 V
-350
190
20
BATT
Thermal Shutdown (Note 8), (Note 9)
5.0 V ≤ V ≤ 26.5 V
T
SD
BATT
Thermal Shutdown Hysteresis (Note 8)
5.0 V ≤ V ≤ 26.5 V
T
SDHYS
BATT
Notes
6. GMW3089V2.3 specifies the maximum load voltage rise to be 0.1 V whenever module battery is intact, including when in Sleep mode. The
maximum load voltage rise of 1.0 V in Sleep mode is a GM-approved exception to GMW3089V2.3.
7. LOAD pin is at system ground voltage.
8. Guaranteed by design but not production tested.
9. Thermal shutdown causes the BUS output driver to be disabled.
33897
6
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C unless otherwise noted. Voltages are relative to GND unless otherwise
noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
RECEIVER
Input Threshold
Awake
V
5.0 V ≤ V
≤ 26.5 V
≤ 26.5 V
< 12 V
V
2.0
6.6
–
2.2
7.9
BATT
BIA
Sleep
12 V ≤ V
V
BISF
BATT
BATT
–
–
Sleep
5.0 V ≤ V
Lesser of
6.6 V or
Lesser of
7.9 V or
V
BISO
V
-4.3
V
-3.25
BATT
BATT
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C unless otherwise noted. Voltages are relative to GND unless otherwise
noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
TRANSMITTER
Normal Speed Rising Output Delay
µs
tDLYNORMRO
200 Ω ≤ R ≤ 3332 Ω, 1.0 µs ≤ Load Time Constance ≤ 4.0 µs
2.0
–
6.3
L
Measured from TXD = V to V
as follows:
IL
BUS
Max Time to V
Min Time to V
= 3.7 V, 6.0 V ≤ V
= 1.0 V, 6.0 V ≤ V
≤ 26.5 V (Note 10)
≤ 26.5 V (Note 10)
BUSMOD
BATT
BUSMOD
BATT
Max Time to V
= 2.7 V, V
= 5.0 V (Note 10)
= 5.0 V (Note 10)
BUSMOD
BUSMOD
BATT
Min Time to V
= 1.0 V, V
BATT
Normal Speed Falling Output Delay
200 Ω ≤ R ≤ 3332 Ω, 1.0 µs ≤ Load Time Constance ≤ 4.0 µs
µs
tDLYNORMFO
1.8
–
8.5
L
Measured from TXD = V to V
as follows:
IH
BUS
Max Time to V
Min Time to V
= 1.0 V, 6.0 V ≤ V
= 3.7 V, 6.0 V ≤ V
≤ 26.5 V (Note 10)
≤ 26.5 V (Note 10)
BUSMOD
BUSMOD
BATT
BATT
Max Time to V
= 1.0 V, V
= 5.0 V (Note 10)
= 5.0 V (Note 10)
BUSMOD
BUSMOD
BATT
Min Time to V
= 2.7 V, V
BATT
High-Speed Rising Output Delay
75 Ω ≤ R ≤ 135 Ω, 0 µs ≤ Load Time Constant ≤ 1.5 µs,
µs
µs
tDLYHSRO
0.1
–
2.0
L
8.0 V ≤ V
≤ 16 V
BATT
Measured from TXD = V to V
as follows:
BUS
IL
Max Time to V
= 3.7 V (Note 11)
= 1.0 V (Note 11)
BUS
BUS
Min Time to V
High-Speed Falling Output Delay
tDLYHSFO
75 Ω ≤ R ≤ 135 Ω, 0 µs ≤ Load Time Constant ≤ 1.5 µs,
0.04
–
3.0
L
8.0 V ≤ V
≤ 16 V
BATT
Measured from TXD = V to V
as follows:
IH
BUS
Max Time to V
= 1.0 V (Note 11)
= 3.7 V (Note 11)
BUS
BUS
Min Time to V
Notes
10.
V
V
is the voltage at the BUSMOD node in Figure 2, page 10.
BUSMOD
11.
is the voltage at the BUS pin in Figure 3, page 10.
BUS
33897
8
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C unless otherwise noted. Voltages are relative to GND unless otherwise
noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
TRANSMITTER (continued)
High-Voltage Rising Output Delay
µs
tDLYHVRO
200 Ω ≤ R ≤ 3332 Ω, 1.0 µs ≤ Load Time Constance ≤ 4.0 µs
L
Measured from V to V
as follows:
IL
BUS
2.0
2.0
2.0
–
–
–
6.3
6.3
18
Max Time to V
= 3.7 V, 6.0 V ≤ V
= 1.0 V, 6.0 V ≤ V
≤ 26.5 V (Note 12)
≤ 26.5 V (Note 12)
≤ 26.5 V (Note 12)
BUSMOD
BATT
Min Time to V
BUSMOD
BATT
Max Time to V
= 9.4 V, 12.0 V ≤ V
BATT
BUSMOD
High-Voltage Falling Output Delay
200 Ω ≤ R ≤ 3332 Ω, 1.0 µs ≤ Load Time Constance ≤ 4.0 µs,
µs
tDLYHVFO
L
12.0 V ≤ V
≤ 26.5 V
BATT
Measured from V to V
as follows:
IH
BUS
1.8
1.8
–
–
13.7
13.7
Max Time to V
= 1.0 V (Note 12)
= 3.7 V (Note 12)
BUSMOD
BUSMOD
Min Time to V
RECEIVER
µs
µs
t
Receive Delay Time (5.0 V ≤ V
≤ 26.5 V)
RDLY
BATT
0.2
10
–
–
1.0
70
Awake
t
Receive Delay Time (BUS Rising to RXD Falling, 5.0 V ≤ V
≤ 26.5 V)
RDLYSL
BATT
Sleep
LOGIC I/O
300
–
1000
ms
t
CNTL Falling Delay Time (5.0 V ≤ V
≤ 26.5 V)
CNTLFDLY
BATT
Notes
12.
V
is the voltage at the BUSMOD node in Figure 2, page 10.
BUSMOD
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33897
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V
BATT
1.0 kΩ
47 µH
100 pF
33897
BUSMOD
BUS
6.49 kΩ
(n -1)
6.49 kΩ
C
= 100 pF + (n -1) 220 pF
R=
NOM
LOAD
GND
Figure 2. Transmitter Delays in Normal and High-Voltage Wake-up Modes
33897
BUS
6.49 kΩ
(n -1)
6.49 kΩ
130 Ω
C
= (n) 220 pF
R=
NOM
LOAD
GND
Figure 3. Transmitter Delays in High-Speed Mode
33897
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33897 is intended for use as a physical layer device in a
communications where the radiated EMI of the higher rate
single-wire CAN communications bus. The communications
takes place from a single pin over a single wire using a common
ground for a current return path. Two data rates are available,
with the high rate used for factory or assembly line
could be an issue.
Two pins control of the mode of operation (sleep, low-speed,
high-speed, and high-voltage wake-up).
communications and the lower for actual system
BLOCK DIAGRAM COMPONENTS
Timer OSC
TX BUS DRVR
This circuit generates a 500 kHz signal to be used for internal
logic. It is the reference for some of the required delays.
This circuit drives the BUS. It can drive it with the higher
voltage wake-up signals when enabled by the Mode Control
circuit. It can also provide waveshaping for reduced EMI or not
provide it for the higher data rate mode. The actual data is
received on TXD at CMOS logic levels, then translated by this
circuit to the necessary operating voltages.
Timers
This circuit contains the timing logic used to hold the CNTL
active for the required time after the conditions for sleep mode
have been met. It is also used to keep the TXD driver active for
a period of time after it has generated a passive level on the
bus.
Undervoltage Detect
This circuit monitors internal operating voltage to assure
proper operation of the part. If a low-voltage condition is
detected, it sends a signal to disable the BUS RCVR and Tx
BUS DRVR circuits. This prevents incorrect data from being put
on the bus or sent to the MCU.
Mode Control
This circuit contains the control logic for the various
operating modes and conditions required for the IC.
Load Switch
BUS RCVR
The LOAD switch provides a path for an external resistor
connected to the BUS to be connected to ground. When a loss
of ground is detected, this switch is opened to prevent the
current that would normally be flowing to the ground from the
module from going back through the load resistor and raising
the bus level. The circuit is opened when the voltage between
GND and VBATT becomes too low as would be the case if
module ground were lost.
This circuit translates the levels on the BUS pin to a CMOS
level indicating the presence of a data 0 or 1. It also determines
the presence of a high-voltage wake-up (HVWU) signal that is
passed to Mode Control and Timers circuits. An analog filter is
used to “de-glitch” the high-voltage wake-up signal and prevent
false exits from the sleep mode.
OPERATION
The 33897 is intended to be used with an MCU to control its
operation and to process and generate the data for the bus.
(recessive) state (bus at near zero volts). When the TXD pin is
low, the output goes to a driven state. The voltage and
waveshaping in the driven state is determined by the levels on
the MODE0 and MODE1 pins (refer to Table 1).
Ground Pins
The four ground pins are not only for electrical conduction,
their number and locations at each of the four corners serve
also to remove heat from the IC. The biggest benefit of this is
obtained by putting a lot of copper on the PCB in this area and,
if ground is an internal layer, by adding numerous plated-
through connections to it with the largest diameter holes the
layout can use.
Table 1. Mode Control
MODE0
MODE1
Operation
Sleep Mode
0
0
0
1
Transmit High Voltage
(Wake-up)
1
1
0
1
Transmit High Speed
TX Data
Normal Speed and Voltage
The data driven onto the SWCAN bus is inverted from the
TXD pin. A “1” driven on TXD will result in an undriven
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Mode Control
CNTL Output
The MODE pins control the transmitter filtering and BUS
voltage and the IC sleep mode operation. Table 1 shows the
mode versus the logic levels on MODE0 and MODE1.
This logic level signal is used to control a VCC regulator.
When the output is low, the VCC regulator is expected to
shutdown. This is normally used to shut down the MCU and all
the devices powered by VCC when the IC is in sleep mode. This
is done to save power. When the part is taken out of the sleep
mode by the higher-than-normal bus voltage, this pin is
asserted high and the VCC regulator brings its output up to the
regulated level. This starts the MCU, which controls the mode
of the IC. The MCU must change the mode signals to non-sleep
mode levels in order to keep this pin from going low. There is a
delay to allow the MCU to fully wake up and take control after
the high-voltage signaling is removed before the level on this
output returns low. After a delay time, even if the bus is at high
voltage, the IC will return to sleep mode if both MODE pins are
low.
The MODE0 and MODE1 pins have a weak pull-down in the
IC so that in case the pins are not driven, the device will enter
the sleep mode. This is usually the situation as the MCU comes
out of reset, before the driving signals have been configured as
outputs.
RX Data
The data received on the bus is translated to logic levels on
this pin. This pin is a logic high when the bus is in the recessive
state (near zero volts) and is low when the bus is in either the
normal or high-voltage dominant state.
This is an open-drain type of output that requires an external
resistor to pull it up. When the device is in sleep mode, the
output will be off unless a high-voltage wake-up level is
detected on the bus. If the wake-up level is detected, the output
will be driven by the data on the bus. If the level of the data
returns to normal level, the output will return to off after a short
delay unless a non-sleep mode condition is set by the MCU.
VBATT Input
This power input is not reverse battery protected and should
use an external diode to protect it from damage owing to
reverse battery if this protection is desired. The voltage drop of
the diode must be taken into consideration when the operating
range of the system is being determined. This diode is generally
used to protect the entire module from reverse battery and
should be selected accordingly.
LOAD Switch
This switch is on in all operating modes unless a loss of
ground is detected. If this happens, the switch is opened and
the resistor normally attached to its pin will be no longer pass
current to or from the bus.
BUS I/O
This input/output may require ESD and/or EMI external
circuitry. A set of components is shown in the Simplified
Application Diagram on the front of this datasheet. The value of
the capacitor should be adjusted downward in direct proportion
to the added capacitance of the ESD or EMI circuits. The series
resistance of the inductor should be kept below 3.5 Ω to prevent
its voltage drop from significantly degrading system noise
margins.
33897
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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APPLICATIONS
Figure 4 shows a typical application schematic for the 33897.
Power
Source
V
CC
Voltage
Regulator
EN
33897
1.0 kΩ
2.7 kΩ
10 kΩ
V
GND
TXD
GND
CC
47
µ
H
SWCAN Bus
NC
BUS
100 pF
Battery
MODE0
MODE1
RXD
6.49 k
100 pF
100 nF
Ω
LOAD
VBATT
CNTL
GND
MCU
4.7 µF
NC
GND
Figure 4. 33897 Typical Application Schematic
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33897
13
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PACKAGE DIMENSIONS
D SUFFIX
EF (Pb-FREE) SUFFIX
14-LEAD SOICN
PLASTIC PACKAGE
CASE 751A-03
ISSUE F
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-A-
2.
3.
CONTROLLING DIMENSION: MILLIMETER.
DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4.
5.
MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
14
1
8
7
-B-
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
°
C
0.337
0.150
0.054
0.014
0.016
-T-
J
M
1.27 BSC
0.050 BSC
K
SEATING
D 14 PL
PLANE
0.19
0.10
0
5.80
0.25
0.25
0.25
7
6.20
0.50
0.008
0.004
0
0.228
0.010
0.009
0.009
M
S
S
0.25 (0.010)
T
B
A
7
°
°
°
°
0.244
0.019
R
33897
14
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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