PC33922PNBR2 [NXP]
IC,MOTOR CONTROLLER,BIPOLAR,LLCC,29PIN;
| 型号： | PC33922PNBR2 |
| 厂家： | 
NXP |
| 描述： | IC,MOTOR CONTROLLER,BIPOLAR,LLCC,29PIN 电动机控制 |
| 文件： | 总20页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33922/D
Rev 3.0, 12/2003
SEMICONDUCTOR TECHNICAL DATA
Product Preview
33922
34922
Dual 4.0 A Power H-Bridge
The 33922/34922 is a dual H-Bridge Power IC with a load current feedback
feature making it ideal for closed-loop DC motor control and bipolar stepper
motor control. The IC incorporates internal input control logic, charge pumps,
gate drivers, and low RDS(ON) output MOSFETs. The 33922/34922 is able to
DUAL 4.0 A POWER H-BRIDGE
control two inductive loads with continuous DC load currents up to 4.0 A.
Output loads can be efficiently pulse width modulated (PWM-ed) at
frequencies up to 20 kHz. The load current feedback feature provides a
proportional (1/375th of the load current) constant-current source output
suitable for monitoring by a microcontroller’s A/D input. This feedback feature
facilitates the design of closed-loop torque/speed control.
Two fault status terminals (SFA, SFB) report undervoltage, short circuit, and
overtemperature conditions separately for each H-Bridge. Each H-Bridge has
two independent inputs providing polarity control of the outputs. Two disable
inputs on each H-Bridge provide a choice of high=true or low=true shutdown
of the H-Bridge outputs.
PNB SUFFIX
29-TERMINAL PQFN
CASE 1469-02
Normal operating voltage covers the range of 5.0 V ≤ V+ ≤ 36 V. The IC can
also be operated up to 40 V with derating of the specifications.
Features
• 5.0 V to 40 V Continuous Operation
• 120 mΩ RDS(ON) H-Bridge MOSFETs
ORDERING INFORMATION
Temperature
• TTL/CMOS Compatible Inputs (5.0 V Logic Levels)
• PWM Frequencies up to 20 kHz
• Active Current Limiting via Internal Constant OFF-Time PWM (with
Temperature-Dependent Threshold Reduction)
• Output Short Circuit Protection with Shutdown
Device
Package
Range (T )
A
PC33922PNB/R2
PC34922PNB/R2
-40°C to 125°C
0°C to 85°C
29 PQFN
29 PQFN
33922/34922 Simplified Appliction Diagram
V+A
V+B
33922
34922
V+A
V+B
IN1
IN2
IN3
IN4
M1
M2
M4
Bipolar
MCU
Step
N
Motor
S
M3
A/D
A/D
FBA
CA
CB
FBB PGND AGND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
For More Information On This Product,
Go to: www.freescale.com
© Motorola, Inc. 2003
Freescale Semiconductor, Inc.
CA
V+A
Charge Pump
EA
Currnt Limi,
Current Limit,
5.0 V
Short Circuit
80 A
µ
Regulator
Detection,and
(each)
Feedback
Circuit
M1
IN1
IN2
D1
D2
Gate Drive
M2
Over-
Control
Logic
temperature
25 µA
25 uA
Undervoltage
SFA
FBA
AGND
H-Bridge A
H-Bridge B
CB
EB
V+B
Charge Pump
Current Limit,
5.0 V
Short Circuit
80 µA
Regulator
Detection,and
Feedback
(each)
Circuit
Cirut
M3
IN
3
Gate Drive
IN4
M4
D3
Over-
D4
Control
Logic
temperature
25 µA
25 uA
Undervoltage
SFB
FBB
AGND
AGND
PGND
Figure 1. 33922/34922 Simplified Internal Block Diagram
33922/34922
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Transparent Top View of
Dual H-Bridge Package
24
23
CA
IN2
1
2
3
4
5
NC
SFA
V+A
M1
FBA
D4
22 V+A
21
H-Bridge A
H-Bridge B
M2
D2
20
19 FBB
18
6
7
8
9
M3
M4
17 V+B
16
V+B
IN4
CB
SFB
NC
15
10
TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal Name
Formal Name
Definition
1, 15
NC
No Connect
These terminals have no internal connections.
2
16
Fault Status for
H-Bridge A and H-Bridge B
SFA
SFB
Open drain active LOW fault status output requiring a pull-up resistor to 5.0 V.
One required for each H-Bridge.
3, 22
8, 17
Positive Power Supply
V+A
V+B
Positive supply connections of H-Bridge A and H-Bridge B, respectively.
4
21
M1
M2
H-Bridge A Output
Output of H-Bridge A.
5
19
FBA
FBB
Feedback for
H-Bridge A and H-Bridge B
Load current feedback outputs providing constant 1/375th of H-Bridge A or B
high-side current.
6
20
Disable
D4
D2
Active LOW inputs used to tri-state for H-Bridge B and H-Bridge A outputs,
respectively. When terminals are logic LOW, outputs are tri-stated.
7
M4
M3
H-Bridge B Output
Logic Input Control
Output of H-Bridge B.
18
9
IN4
IN3
IN2
IN1
Logic input control of their respective M4 through M1 terminals; e.g., IN1 logic
HIGH = M1 HIGH.
14
23
28
10
24
CB
CA
Charge Pump B and
Charge Pump A
External reservoir capacitor connection for internal charge pump capacitor for
H-Bridge B and H-Bridge A, respectively.
11
25
D3
D1
Disable
Active HIGH inputs used to tri-state H-Bridge outputs for H-Bridge B and
H-Bridge A, respectively. When terminals are logic HIGH, outputs are tri-stated.
12
26
EB
EA
Enable
Enable controls for H-Bridge B and H-Bridge A, respectively; e.g., EB logic
HIGH = Half-Bridge B Operational, EB logic LOW = Half-Bridge B asleep.
13, 27
29
AGND
PGND
Analog Ground
Power Ground
Low-current analog signal ground.
High-current power ground.
33922/34922
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Supply Voltage
V+
40
V
Input Voltage (Note 1)
VIN
VSF
IOUT
-0.1 to 7.0
7.0
V
V
A
V
SFA, SFB Status Output (Note 2)
Continuous Current, Each H-Bridge (Note 3)
4.0
ESD Voltage
Human Body Model (Note 4)
Each Terminal to AGND
Each Terminal to PGND
Each Terminal to V+
Each I/O to All Other I/Os
Machine Model (Note 5)
V
±1000
±1500
±2000
±2000
±200
ESD1
V
V
V
V
ESD1
ESD1
ESD1
ESD2
Storage Temperature
T
-65 to 150
°C
°C
STG
Ambient Operating Temperature (Note 6)
T
A
MC33922
MC34922
-40 to 125
0 to 85
Junction Operating Temperature
MC33922
T
°C
J
-40 to 150
0 to 110
MC34922
Terminal Soldering Temperature (Note 7)
T
220
°C
SOLDER
Approximate Junction-to-Board Thermal Resistance (and Package
Dissipation) (Note 6), (Note 8)
R
°C/W
θJB
PQFN (4.0 W)
~6.0
Notes
1. Exceeding the input voltage on IN1, IN2, IN3, IN4, EA, EB, D1, D2, D3, or D4 may cause a malfunction or permanent damage to the device.
2. Exceeding the pull-up resistor voltage on the open drain SFA and SFB terminals may cause permanent damage to the device.
3. Continuous current capability so long as junction temperature is ≤ 150°C.
4. ESD1 testing is performed in accordance with the Human Body Model (C
= 100 pF, R
= 1500 Ω).
ZAP
ZAP
5. ESD2 testing is performed in accordance with the Machine Model (C
= 200 pF, R
= 0 Ω).
ZAP
ZAP
6. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.
7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
8. Exposed heatsink pad plus the power and ground terminals comprise the main heat conduction paths. The actual RθJB (junction-to-PC board)
values will vary depending on solder thickness and composition and copper trace thickness.
33922/34922
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 36 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER SUPPLY
Operating Voltage Range (Note 9)
V+
5.0
–
–
40
50
V
Sleep State Supply Current, Each H-Bridge (Note 10)
I
µA
Q(sleep)
V
= 0 V, I
= 0 A
25
EN
OUT
Standby Supply Current, Each H-Bridge
= 5.0 V, I = 0 A
I
mA
Q(standby)
V
–
–
20
EN
OUT
Threshold Supply Voltage
Switch-OFF
V+
4.15
4.5
150
4.4
4.75
–
4.65
5.0
–
V
V
mV
(thres-OFF)
V+
Switch-ON
Hysteresis
(thres-ON)
V+
(hys)
CHARGE PUMP
Charge Pump Voltage
V+ = 5.0 V
V
-V+
V
V
CP
3.35
–
–
–
–
20
8.0 V ≤ V+ ≤ 40 V
CONTROL INPUTS
Input Voltage (IN1, IN2, IN3, IN4, D1, D2, D3, D4)
V
V
V
3.5
–
0.7
–
–
1.0
–
1.4
–
Threshold HIGH
Threshold LOW
Hysteresis
IH
IL
HYS
Input Current (IN1, IN2, IN3, IN4, D1, D3)
I
I
µA
µA
INP
V
- 0.0 V
-200
–
-80
25
–
IN
Input Current (D2, D4, EA, EB)
V = 5.0 V
INP
100
Notes
9. Specifications are characterized over the range of 5.0 V ≤ V+ ≤ 36 V. Operation >36 V will cause some parameters to exceed listed min/max
values. Refer to typical operating curves to extrapolate values for operation > 36 V but ≤ 40 V.
10.
I
is with sleep mode function enabled.
Q(sleep)
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 36 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUTS (M1, M2, M3, M4)
Output-ON Resistance (Note 11)
5.0 V ≤ V+ ≤ 36 V, T = 25°C
R
mΩ
DS(ON)
–
–
–
120
–
–
–
225
300
J
8.0 V ≤ V+ ≤ 36 V, T = 150°C
J
5.0 V ≤ V+ ≤ 8.0 V, T = 150°C
J
Active Current Limiting Threshold (via Internal Constant OFF-Time PWM)
High-Side Short Circuit Detection Threshold
Low-Side Short Circuit Detection Threshold
Leakage Current (Note 12)
I
5.2
11
6.5
–
7.8
–
A
A
LIM
I
SCH
I
8.0
–
–
A
SCL
OUT(leak)
I
µA
–
–
100
30
200
60
V
V
= V+
= GND
OUT
OUT
Output FET Body Diode Forward Voltage Drop
= 3.0 A
V
V
F
I
–
–
2.0
OUT
Overtemperature Shutdown
Thermal Limit
°C
T
175
10
–
–
–
30
LIM
Hysteresis
T
HYS
HIGH-SIDE CURRENT SENSE FEEDBACK
Feedback Current
I
FB
I
I
I
I
I
= 0 mA
= 500 mA
= 1.5 A
= 3.0 A
= 6.0 A
–
1.07
3.6
7.2
14.4
–
600
1.60
4.4
8.8
17.6
µA
mA
mA
mA
mA
OUT
OUT
OUT
OUT
OUT
1.33
4.0
8.0
16
FAULT STATUS (Note 13)
Fault Status Leakage Current (Note 14)
ISF(
leak
µA
)
V
SF = 5.0 V
Fault Status Set Voltage (Note 15)
SF = 300 µA
Notes
–
–
–
–
10
VSF(LOW)
V
I
1.0
11. Output-ON resistance as measured from output to V+ and ground.
12. Outputs switched OFF with D1, D2, D3, or D4.
13. Fault Status output is an open drain output requiring a pull-up resistor to 5.0 V.
14. Fault Status Leakage Current is measured with Fault Status HIGH and not set.
15. Fault Status Set Voltage is measured with Fault Status LOW and set with ISF = 300 µA.
33922/34922
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 36 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency (Note 16)
f
–
–
10
–
–
kHz
kHz
µs
PWM
Maximum Switching Frequency During Active Current Limiting (Note 17)
f
20
MAX
Output ON Delay (Note 18)
V+ = 14 V
t
d(ON)
–
–
18
Output OFF Delay (Note 18)
V+ = 14 V
t
µs
d(OFF)
–
–
18
26
21
µs
µs
Output Latch-OFF Time
t
t
15
12
20.5
16.5
a
b
Output Blanking Time
Output Rise and Fall Time (Note 19)
t , t
µs
f
r
V+ = 14 V, I
= 3.0 A
2.0
5.0
8.0
OUT
Short Circuit/Overtemperature Turn-OFF Time (Note 20)
Disable Delay Time (Note 21)
t
–
–
4.0
–
–
µs
µs
FAULT
t
8.0
5.0
5.0
–
d(disable)
Power-ON Delay Time (Note 22)
t
–
1.0
1.0
–
ms
pod
wud
Wake-Up Delay Time (Note 22)
t
–
ms
ns
Output FET Body Diode Reverse Recovery Time (Note 23)
t
100
rr
Notes
16. The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM pulse
train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. See
Typical Switching Waveforms, Figures 11 through 18, pp. 12–13.
17. The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant OFF-
time PWM of the output. The output load characteristics affect the switching frequency.
18. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the M1 or M2 signal, respectively, and of the IN3 or IN4 input signal to the 10% or 90% point (dependent on the transition
direction) of the M3 or M4 signal, respectively. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal
to the 90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal
to the 10% point of the output response signal. See Figure 2, page 8.
19. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 4, page 8.
20. Increasing currents will become limited at I . Hard shorts will breach the I
or I
limit, forcing the output into an immediate tri-state
LIM
SCH
SCL
latch-OFF. See Figures 6 and 7, page 9. Output current limiting will cause junction temperatures to rise. A junction temperature above 160°C
will cause the active current limiting to progressively “fold-back”, or decrease, to 2.5 A typical at 175°C where thermal latch-OFF will occur.
See Figure 5, page 8.
21. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See Figure 3,
page 8.
22. Parameter has been characterized but not production tested.
23. Parameter is guaranteed by design but not production tested.
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Timing Diagrams
5.0
0
50%
50%
td(OFF)
td(ON)
90%
V+
10%
0
TIME
Figure 2. Output Delay Time
5.0 V
0 V
∞ Ω
0 Ω
Figure 3. Disable Delay Time
V+
tf
tr
90%
90%
10%
10%
0
Figure 4. Output Switching Time
6.5
6.6
2.5
Thermal Shutdown
160
175
T , JUNCTION TEMPERATURE (oC)
J
Figure 5. Active Current Limiting Versus Temperature (Typical)
33922/34922
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Load Capacitance and/or
Diode Reverse Recovery Spikes
I
Short Circuit Detect Threshold
SCL
8.0
6.5
for Low-Side FETs
Typical Current Limiting
Threshold
Active
Current
Had Sot etct nLatc-OFF
Hard Short Detect and Latch-Off
Limiting
(
(See Figure 7)
0
IN1 or IN2
I1I2
IN2 or IN1
IN1 OR IN2
[1]
IN1 or IN2
IN2IN1
IN2 or IN1
IN2IN1
IN1 IN2
I2
[0]
[1]
[0]
[1]
[0]
[1]
[0]
Outputs
Outputs Operational
Outputs
(per Input Control Condition)
Tri-stated
Tri-stated
TIME
Figure 6. Active Current Limiting Versus Time
I Short Circuit Detect Threshold
SCL
8.0
6.5
t = Output Latch-OFF Time
a
ta
tb
t
= Output Blanking Time
b
Typical Current
Limiting Waveform
Hard Short Detect
Latch-Off Prevented During t
b
TIME
Figure 7. Active Current Limiting Detail
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Electrical Performance Curves
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.0
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
Volts
Figure 8. Typical High-Side RDS(ON) Versus V+
0.13
0.128
0.126
0.124
0.122
0.12
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
Volts
Figure 9. Typical Low-Side RDS(ON) Versus V+
33922/34922
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9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
Volts
Figure 10. Typical Quiescent Supply Current Versus V+
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Typical Switching Waveforms
Important For all plots, the following applies:
• Ch2=2.0 A per division
• LLOAD=533 µH @ 1.0 kHz
• LLOAD=530 µH @ 10.0 kHz
• RLOAD=4.0 Ω
Output Voltage
(M1)
Output Voltage
(M1)
IOUT
IOUT
Input Voltage
(IN1)
Input Voltage
(IN1)
V+ = 24 V
f
= 1.0 kHz Duty Cycle = 10%
V+ = 34 V
f
= 1.0 kHz Duty Cycle = 90%
PWM
PWM
Figure 11. Output Voltage and Current vs. Input Voltage at
V+ = 24 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 10%
Figure 13. Output Voltage and Current vs. Input Voltage at
V+ = 34 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 90%, Showing Device in
Current Limiting Mode
Output Voltage
(M1)
Output Voltage
(M1)
IOUT
IOUT
Input Voltage
(IN1)
Input Voltage
(IN1)
V+ = 24 V
f
= 1.0 kHz Duty Cycle = 50%
PWM
V+ = 22 V
f
= 1.0 kHz Duty Cycle = 90%
PWM
Figure 12. Output Voltage and Current vs. Input Voltage at
V+ = 24 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 50%
Figure 14. Output Voltage and Current vs. Input Voltage at
V+ = 22 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 90%
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Output Voltage
(M1)
Output Voltage
(M1)
IOUT
IOUT
Input Voltage
(IN1)
Input Voltage
(IN1)
V+ = 12 V
f
= 20 kHz Duty Cycle = 50%
PWM
V+ = 24 V
f
= 10 kHz Duty Cycle = 50%
PWM
Figure 15. Output Voltage and Current vs. Input Voltage at
V+ = 24 V, PMW Frequency of 10 kHz,
Figure 17. Output Voltage and Current vs. Input Voltage at
V+ = 12 V, PMW Frequency of 20 kHz,
and Duty Cycle of 50%
and Duty Cycle of 50% for a Purely Resistive Load
Output Voltage
(M1)
Output Voltage
(M1)
IOUT
IOUT
Input Voltage
(IN1)
Input Voltage
(IN1)
V+ = 12 V
f
= 20 kHz Duty Cycle = 90%
PWM
V+ = 24 V
f
= 10 kHz Duty Cycle = 90%
PWM
Figure 16. Output Voltage and Current vs. Input Voltage at
V+ = 24 V, PMW Frequency of 10 kHz,
Figure 18. Output Voltage and Current vs. Input Voltage at
V+ = 12 V, PMW Frequency of 20 kHz,
and Duty Cycle of 90%
and Duty Cycle of 90% for a Purely Resistive Load
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Table 1. Truth Table (Each Bridge)
The tri-state conditions and the fault status are reset using D1, D2, D3, or D4. The truth table uses the following notations:
L = LOW, H = HIGH, X = HIGH or LOW, and Z = High impedance (all output power transistors are switched off).
Fault Status
Input Conditions
Output States
M1/M3 M2/M4
Flag
SFA/SFB
H
Device State
EA/EB
H
D1/D3
D2/D4
H
IN1/IN3
IN2/IN4
L
Forward
Reverse
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
X
L
H
L
H
H
H
L
L
L
H
L
Freewheeling Low
L
L
Freewheeling High
L
H
X
X
Z
X
X
X
X
X
X
X
X
H
X
X
X
Z
X
X
X
X
X
X
X
H
Z
Z
H
X
Z
Z
Z
Z
Z
Z
Z
H
Z
Z
X
H
Z
Z
Z
Z
Z
Z
Z
Disable 1/Disable 3 (D1/D3)
Disable 2/Disable 4 (D2/D4)
IN1/IN3 Disconnected
IN2/IN4 Disconnected
D1/D3 Disconnected
D2/D4 Disconnected
Undervoltage (Note 24)
Overtemperature (Note 25)
Short Circuit (Note 25)
Sleep Mode EA/EB
EA/EB Disconnected
Notes
H
X
L
L
H
H
X
Z
H
H
L
L
Z
X
X
X
X
X
X
L
X
X
X
X
X
L
L
L
H
H
Z
24. In the case of an undervoltage condition, the outputs tri-state and the fault status is set logic LOW. Upon undervoltage recovery, fault
status is reset automatically or automatically cleared and the outputs are restored to their original operating condition.
25. When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input
signals and the fault status flag is set logic LOW.
33922/34922
14
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
Numerous protection and operational features (speed,
Two independent inputs on each H-Bridge (IN1 and IN2 on
H-Bridge A and IN3 and IN4 on H-Bridge B) provide control of
the two totem-pole half-bridge outputs. Two pairs of disable
inputs (D1 and D2 and D3 and D4 on H-Bridge A and
H-Bridge B, respectively) provide the means to force the
H-Bridge outputs to a high-impedance state (all H-Bridge
switches OFF). Enable terminals EA and EB control enable
functions that allow the 33922/34922 to be placed in a power-
conserving sleep mode.
torque, direction, dynamic braking, PWM control, and closed-
loop control), in addition to the 5.0 A rms current capability,
make the 33922/34922 a very attractive, cost-effective solution
for controlling a broad range of small DC motors. In addition, the
33922/34922 device can be used to control a bipolar stepper
motor. The 33922/34922 can also be used to excite transformer
primary windings with a switched square wave to produce
secondary winding AC currents.
As shown in Figure 1, Simplified Internal Block Diagram,
page 2, the 33922/34922 comprises two fully protected
monolithic H-Bridges with Enable, Fault Status reporting, and
high-side current sense feedback to accommodate closed-loop
control. For a DC motor to run, the input conditions need be as
follows: Enable inputs EA and EB logic HIGH, D1 and D3 inputs
logic LOW, D2 and D4 inputs logic HIGH, SFA and SFB flags
cleared (logic HIGH), one IN logic LOW and the other IN logic
HIGH for each H-Bridge (to define output polarity). The 33922/
34922 can execute dynamic braking by simultaneously turning
on either all high-side MOSFETs or all low-side MOSFETs in
the output H-Bridges.
The 33922/34922 has undervoltage shutdown with
automatic recovery, active current limiting, output short circuit
latch-OFF, and overtemperature latch-OFF. An undervoltage
shutdown, output short-circuit latch-OFF, or overtemperature
latch-OFF fault condition will cause the outputs to turn OFF (i.e.,
become high impedance or tri-stated) and the fault output flag
to be set LOW. Either of the Disable inputs or V+ must be
“toggled” to clear the fault flag.
Active current limiting is accomplished by a constant OFF-
time PWM method employing active current limiting threshold
triggering. The active current limiting scheme is unique in that it
incorporates a junction temperature-dependent current-limit
threshold. This means the active current limiting threshold is
“ramped down” as the junction temperature increases above
160°C, until at 175°C the current will have been decreased to
about 2.5 A. Above 175°C, the overtemperature shutdown
(latch-OFF) occurs. This combination of features allows the
device to remain in operation for a longer period of time with
unexpected loads, while still retaining adequate protection for
both the device and the load.
The 33922/34922 outputs are capable of providing a
continuous DC load current of 4.0 A from a 40 V V+ source.
Internal charge pumps support PWM frequencies to 20 kHz.
External pull-up resistors are required at the SF terminals for
fault status reporting. The 33922/34922 has analog feedback
(current mirror) output terminals (the FBA and FBB terminals)
that provide a constant-current source ratioed to the active
high-side MOSFETs. This can be used to provide “real time”
monitoring of load current to facilitate closed-loop operation for
motor speed/torque control.
33922/34922
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FUNCTIONAL TERMINAL DESCRIPTION
A disable timer (time tb) incorporated to detect currents that
PGND and AGND
are higher than current limit is activated at each output
transition to facilitate hard short detection (see Figure 7,
page 9).
The power and analog ground terminals should be
connected together with a very low impedance connection.
V+ (V+A and V+B)
CA and CB
V+ terminals are the power supply inputs to the device. All V+
terminals must be connected together on the printed circuit
board with as short as possible traces offering as low
impedance as possible between the terminals.
CA and CB are charge pump output terminals for H-Bridge A
and H-Bridge B, respectively. A filter capacitor (up to 33 nF) can
be connected from the charge pump output terminals and the
PGND terminals. The device can operate without external
capacitors, although the CA and CB capacitors help to reduce
noise and allow the device to perform at maximum speed,
timing, and PWM frequency.
V+ terminals have an undervoltage threshold. If the supply
voltage drops below a V+ undervoltage threshold, the output
power stage switches to a tri-state condition and the fault status
flag is set and the Fault Status terminal voltage switched to a
logic LOW. When the supply voltage returns to a level that is
above the threshold, the power stage automatically resumes
normal operation according to the established condition of the
input terminals and the fault status flag is automatically reset
logic HIGH.
EA and EB
The Enable terminals are used to place the device in a sleep
mode so as to consume very low currents. When the voltage of
the Enable terminals is a logic LOW state, the device is in the
sleep mode. The device is enabled and fully operational when
the voltage of the Enable terminals is logic HIGH. Internal pull-
down resistors maintain the device in sleep mode in the event
the Enable terminals are driven through a high impedance I/O
or an unpowered microcontroller, or the Enable inputs become
disconnected.
Fault Status (SFA and SFB)
These terminals are the device fault status outputs. The
outputs are active LOW open drain structures, each requiring a
pull-up resistor to 5.0 V. Refer to Table 1, Truth Table (Each
Bridge), page 14.
FBA and FBB
IN1, IN2, IN3, IN4, D1, D2, D3, and D4
The device has dual feedback outputs, one for each
H-Bridge, for “real time” monitoring of H-Bridge high-side
currents to facilitate closed-loop operation for motor speed and
torque control.
These terminals are input control terminals used to control
the outputs. These terminals are 5.0 V CMOS-compatible
inputs with hysteresis. The IN1 and IN2 independently control
M1 and M2, respectively, and IN3 and IN4 independently
control M3 and M4, respectively. D1 and D2 are complementary
inputs used to tri-state disable H-Bridge A outputs, and D3 and
D4 are complementary inputs used to tri-state disable
H-Bridge B outputs.
The Feedback terminals provide current sensing feedback of
H-Bridge high-side drivers. When running in the forward or
reverse direction, a ground referenced 1/375th (0.00266) of
load current is output to each Feedback terminal. Through the
use of external resistors to ground, the proportional feedback
current can be converted to a proportional voltage equivalent
and the controlling microcontroller can “read” the current
proportional voltage with its analog-to-digital converter (ADC).
This is intended to provide the user with motor current feedback
for motor torque control. The accuracy is ±20% at load currents
<1.5 A and ±10% at load currents >1.5 A.
When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic
LOW) in the disable state, outputs M1 and M2 are both tri-state
disabled; however, the rest of H-Bridge A circuitry is fully
operational and the supply IQ(standby) current is reduced to a few
milliamperes. The case is true for D3 or D4 for H-Bridge B as
well. Refer to Table 1, Truth Table (Each Bridge), and STATIC
ELECTRICAL CHARACTERISTICS table, page 5.
If PWM-ing is implemented using inputs from the Disable
terminals (either D1 or D2 for H-Bridge A and D3 or D4 for
H-Bridge B), a small filter capacitor (1.0 µF or less) may be
required in parallel for each H-Bridge, with the external resistor
to ground for fast spike suppression.
M1, M2, M3, and M4
These terminals are the outputs of the H-Bridges with
integrated output FET body diodes. H-Bridge A outputs (M1
and M2) are controlled using the IN1, IN2, D1, and D2 inputs
and H-Bridge B outputs (M3 and M4) are controlled using the
IN3, IN4, D3, and D4 inputs. The outputs have active current
limiting above 6.5 A typical. The outputs also have thermal
shutdown (tri-state latch-OFF) with hysteresis as well as short
circuit latch-OFF protection.
33922/34922
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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16
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PERFORMANCE FEATURES
The current limiting threshold value is dependent upon the
Short Circuit Protection
device junction temperature. When -40°C ≤ TJ ≤ 160°C, ILIM is
between 5.2 A and 7.8 A. When TJ exceeds 160°C, the ILIM
If an output short circuit condition is detected, the power
outputs tri-state (latch-OFF) independent of the input (IN1
through IN4) states, and the fault status output flags are SET
logic LOW. If the D1 and D3 inputs change from logic HIGH to
logic LOW, or if the D2 and D4 inputs change from logic LOW to
logic HIGH, the output bridges will become operational again
and the fault status flags will be reset (cleared) to a logic HIGH
state.
current decreases linearly down to 2.5 A typical at 175°C.
Above 175°C the device overtemperature circuit detects TLIM
and overtemperature shutdown occurs (see Figure 5, page 8).
This feature allows the device to remain operational for a longer
time but at a regressing output performance level at junction
temperatures above 160°C.
The output stage will always switch into the mode defined by
the input terminals (IN1, IN2, D1, and D2 for H-Bridge A and
IN3, IN4, D3, and D4 for H-Bridge B), provided the device
junction temperature is within the specified operating
temperature range.
Overtemperature Shutdown and Hysteresis
If an overtemperature condition occurs, the power outputs
are tri-stated (latched-OFF) and the fault status flags are SET
to logic LOW.
To reset from this condition, D1 must change from logic
HIGH to logic LOW, or D2 must change from logic LOW to logic
HIGH for H-Bridge A and D3 must change from logic HIGH to
logic LOW, or D4 must change from logic LOW to logic HIGH for
H-Bridge B. When reset, the output stage switches ON again,
provided that the junction temperature is now below the
overtemperature threshold limit minus the hysteresis.
Active Current Limiting
The maximum current flow under normal operating
conditions is internally limited to ILIM (5.2 A and 7.8 A). When
the maximum current value is reached, the output stages are tri-
stated for a fixed time (t ) of 20 µs typical. Depending on the
a
time constant associated with the load characteristics, the
current decreases during the tri-state duration until the next
output ON cycle occurs (see Figures 7 and 13, page 9 and
page 12, respectively).
Note Resetting from the fault condition will clear the fault
status flags.
33922/34922
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APPLICATIONS
A typical application schematic is shown in Figure 19. For
precision high-current applications in harsh, noisy
environments, the V+ by-pass capacitor may need to be
substantially larger.
DC
MOTOR
V+A
33922/34922
V+A
CA
H-Bridge A
+
33 nF
47 µF
AGND
M1
M2
EA
D2
EA
FBA
D2
D1
SFA
IN1
IN2
+
1.0 µF
D1
100 Ω
100 Ω
SFA
IN1
IN2
PGND
FBB
FBA
FBB
IN3
IN4
SFB
D3
IN3
IN4
SFB
D3
+
1.0 µF
PGND
D4
D4
EB
M4
EB
M3
V+B
AGND
V+B
CB
+
H-Bridge B
33 nF
47 µF
DC
MOTOR
Figure 19. 33922/34922 Typical Application Schematic
33922/34922
18
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
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PACKAGE DIMENSIONS
PNB SUFFIX
29-TERMINAL PQFN
PLASTIC PACKAGE
CASE 1469-02
ISSUE A
10
A
PIN 1
INDEX AREA
M
28 27
26 25
2X
0.1 C
G
1
2
3
4
5
6
7
24
23
22
21
20
19
18
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
4. COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
10
8
9
10
17
16
15
11 12
13 14
M
PIN NUMBER
REFERENCE ONLY
2X
0.1 C
B
0.1 C
2.20
1.95
2.2
2.0
0.05 C
4
7.5
(0.55)
(0.8)
0.05
0.00
6.15
5.85
0.1 A B C
SEATING PLANE
C
DETAIL G
°
ROTATED 90 CLOCKWISE
VIEW A
PIN NUMBER
REFERENCE ONLY
25 26
27 28
1
24
23
2.95
9.55
9.25
2
3
4
22
21
20
29
22X
1.13
0.8
0.1 A B C
4X 0.88
5
7.65
7.2
7.35 19
6
18
17
16
15
7
0.90
0.65
8X
8
9
10
M
M
0.1
C A B
C
0.05
14 13
12 11
0.65
28X 0.48
0.05 C
VIEW M-M
0.4
1.65
16X1.40
VIEW A
33922/34922
19
MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfToArmation On This Product,
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
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© Motorola, Inc. 2003
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MC33922/D
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