PC33926PNB/R2_技术文档

Document Number: MC33926

Rev. 7.0, 6/2007

Freescale Semiconductor

Product Preview

5.0 A Throttle Control H-Bridge

33926

The 33926 is a monolithic H-Bridge Power IC designed primarily

for automotive electronic throttle control, but is applicable to any low-

voltage DC servo motor control application within the current and

voltage limits stated in this specification.

AUTOMOTIVE THROTTLE H-BRIDGE

ACTUATOR/ MOTOR EXCITER

The 33926 is able to control inductive loads with currents up to

5.0 A peak. RMS current capability is subject to the degree of

heatsinking provided to the device package. Internal peak-current

limiting (regulation) is activated at load currents above 6.5 A ± 1.5 A.

Output loads can be pulse width modulated (PWM’ed) at frequencies

up to 20 kHz. A load current feedback feature provides a proportional

(0.24% of the load current) current output suitable for monitoring by a

microcontroller’s A/D input. A Status Flag output reports

undervoltage, overcurrent, and overtemperature fault conditions.

Two independent inputs provide polarity control of two half-bridge

totem-pole outputs. Two independent disable inputs are provided to

force the H-Bridge outputs to tri-state (high impedance off-state). An

invert input changes the IN1 and IN2 inputs to LOW = true logic.

Bottom View

SCALE 2:1

PNB SUFFIX (Pb-FREE)

98ARL10579D

32-PIN PQFN

Features

• 8.0 V to 28 V Continuous Operation (Transient Operation from 5.0

V to 40 V)

• 225 mΩ maximum R_DS(ON)@ 150°C (each H-Bridge MOSFET)

• 3.0 V and 5.0 V TTL / CMOS Logic Compatible Inputs

• Overcurrent Limiting (Regulation) via Internal Constant-Off-Time

PWM

• Output Short Circuit Protection (Short to VPWR or Ground)

• Temperature-Dependant Current-Limit Threshold Reduction

ORDERING INFORMATION

Temperature

Device

Package

Range (T )

A

PC33926PNB/R2

- 40°C to 125°C

32 PQFN

• All Inputs have an Internal Source/Sink to Define the Default (Floating Input) States

• Sleep Mode with Current Draw < 50 µA (with Inputs Floating or Set to Match Default Logic States)

• Pb-Free Packaging Designated by Suffix Code PNB

V

PWR

DD

33926

SF

VPWR

CCP

FB

IN1

IN2

INV

SLEW

D1

OUT1

MOTOR

MCU

OUT2

D2

PGND

AGND

EN

Figure 1. 33926 Simplified Application Diagram

*This document contains certain information on a product under development. Free-

scale reserves the right to change or discontinue this product without notice

INTERNAL BLOCK DIAGRAM

VPWR

VDD

LOGIC SUPPLY

VCP

CHARGE

PUMP

HS1

HS2

LS2

CCP

OUT1

OUT2

TO GATES

EN

IN1

HS1

LS1

HS2

LS2

IN2

PGND

D2

GATE DRIVE

AND

PROTECTION

LOGIC

D1

VSENSE

INV

SLEW

SF

CURRENT MIRROR

AND

CONSTANT OFF-TIME

ILIM PWM

PWM CURRENT REGULATOR

FB

AGND

PGND

Figure 2. 33926 Simplified Internal Block Diagram

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Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

1

2

32 31 30 29 28 27 26 25

IN2

IN1

NC

24

23

22

PGND

SF

3

4

5

6

7

SLEW

VPWR

AGND

VPWR

INV

Transparent Top

View of Package

21

AGND

20

19

18

PGND

8

9

FB

NC

10 11 12 13 14 15 16 17

NC

Figure 3. 33926 Pin Connections

Table 1. 33926 Pin Definitions

A functional description of each pin can be found in the Functional Description section beginning on page 12.

Function

Pin Name

Formal Name

Definition

Logic input control of OUT2; e.g., when IN2 is logic HIGH, OUT2 is set to V_PWR

and when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger input with

~80 µA source so default condition = OUT2 HIGH.)

,

1

Logic Input

Input 2

IN2

Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to V_PWR

2

IN1

Logic Input

Input 1

and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger Input with

~80 µA source so default condition = OUT1 HIGH.)

Logic input to select fast or slow slew rate. (Schmitt trigger input with ~80 µA

sink so default condition = slow.)

3

SLEW

Logic Input

Power Input

Slew Rate

These pins must be connected together physically as close as possible and

directly soldered down to a wide, thick, low resistance supply plane on the PCB.

4, 6, 11, 31

VPWR

AGND

Positive Power

Supply

The low current analog signal ground must be connected to PGND via low

impedance path (<<10 mΩ, 0 Hz to 20 kHz). Exposed copper pad is also the

main heatsinking path for the device.

5,

Analog

Ground

Analog Signal

Ground

Exposed

Pad

Sets IN1 and IN2 to logic LOW = TRUE. (Schmitt trigger input with ~80 µA sink

so default condition = non-inverted.)

7

INV

FB

Logic Input

Input Invert

Feedback

Load current feedback output provides ground referenced 0.24% of H-Bridge

high-side output current. (Tie pin to GND through a resistor if not used.)

8

Analog

Output

No internal connection is made to this pin.

9, 17, 25

10

NC

EN

No Connect

Enable Input

When EN is logic HIGH, the device is operational. When EN is logic LOW, the

device is placed in Sleep mode. (logic input with ~80 µA sink so default

condition = Sleep mode.)

Logic Input

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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PIN CONNECTIONS

Table 1. 33926 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Description section beginning on page 12.

Function

Pin Name

Formal Name

Definition

Source of high-side MOSFET1 and drain of low-side MOSFET1.

12, 13,

14, 15

OUT1

Power

Output

H-Bridge Output 1

When D2 is logic LOW, both OUT1 and OUT2 are tri-stated. (Schmitt trigger

input with ~80 µA sink so default condition = disabled.)

16

D2

Logic Input

Disable Input 2

(Active Low)

High-current power ground pins must be connected together physically as

close as possible and directly soldered down to a wide, thick, low resistance

ground plane on the PCB.

18–20,

22–24

PGND

Power

Ground

Power Ground

Open drain active LOW Status Flag output (requires an external pullup resistor

to V . Maximum permissible load current < 0.5 mA. Maximum V

< 0.4 V @ 0.3 mA. Maximum permissible pullup voltage < 7.0 V.)

21

26

SF

Logic

Output -

Status Flag

(Active Low)

DD

CEsat

Open Drain

Logic Input

When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger

input with ~80 µA source so default condition = disabled.

D1

OUT2

CCP

Disable Input 1

(Active High)

Source of high-side MOSFET2 and drain of low-side MOSFET2.

27, 28,

29, 30

Power

Output

H-Bridge Output 2

External reservoir capacitor connection for internal charge pump; connected to

VPWR. Allowable values are 30 νF to 100 νF. Note This capacitor is required

for the proper performance of the device.

32

Analog

Output

Charge Pump

Capacitor

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device. These parameters are not production tested.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Power Supply Voltage

V

Normal Operation (Steady-State)

Transient Overvoltage ⁽¹⁾

V_PWR(SS)

V_PWR(t)

-0.3 to 28

-0.3 to 40

Logic Input Voltage ⁽²⁾

SF Output ⁽³⁾

V

-0.3 to 7.0

5.0

V

A

V

IN

V

SF

Continuous Output Current ⁽⁴⁾

I

OUT(CONT)

ESD Voltage ⁽⁵⁾

Human Body Model

OUT1 and OUT2 to GND

All Other Pins

V

ESD1

ESD2

±500

±2000

±200

Machine Model

Charge Device Model

Corner Pins (1,9,17,25)

All Other Pins

±750

±500

THERMAL RATINGS

Storage Temperature

T

- 65 to 150

°C

STG

Operating Temperature ⁽⁶⁾

Ambient

T

-40 to 125

-40 to 150

A

Junction

T

J

Notes

1. Device will survive repetitive transient overvoltage conditions for durations not to exceed 500 ms @ duty cycle not to exceed 10%.

External protection is required to prevent device damage in case of a reverse battery condition.

2. Exceeding the maximum input voltage on IN1, IN2, EN, INV, SLEW, D1, or D2 may cause a malfunction or permanent damage to the

device.

3. Exceeding the pullup resistor voltage on the open drain SF pin may cause permanent damage to the device.

4. Continuous output current capability is dependent on sufficient package heatsinking to keep junction temperature ≤150°C.

5. ESD1 testing is performed in accordance with the Human Body Model (C

= 100 pF, R

= 1500 Ω), ESD2 testing is performed in

ZAP

accordance with the Machine Model (C

= 200 pF, R

= 0 Ω), and the Charge Device Model (CDM), Robotic (C_ZAP= 4.0pF).

ZAP

6. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief

non-repetitive excursions of junction temperature above 150°C can be tolerated provided the duration does not exceed 30 seconds

maximum. (Non-repetitive events are defined as not occurring more than once in 24 hours.)

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Analog Integrated Circuit Device Data

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ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device. These parameters are not production tested.

Ratings

Symbol

Value

Unit

(8)

Peak Package Reflow Temperature During Reflow ⁽⁷⁾

,

°C

T_PPRT

250

Approximate Junction-to-Board Thermal Resistance ⁽⁹⁾

R

<1.0

°C/W

θJB

Notes

7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

9. Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual R_θJB(junction-to-PC board)

values will vary depending on solder thickness and composition and copper trace thickness and area. Maximum current at maximum

die temperature represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the R_θJAmust be

<5.0°C/W for maximum current at 70°C ambient. Module thermal design must be planned accordingly.

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 8.0 V ≤ V_PWR≤ 28 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUTS (VPWR)

Operating Voltage Range ⁽¹⁰⁾

V

Steady-State

Transient (t < 500 ms) ⁽¹¹⁾

V

8.0

–

28

40

PWR(SS)

V

PWR(t)

Quasi-Functional (R_DS(ON)May Increase by 50%)

V

5.0

8.0

PWR(QF)

Sleep State Supply Current ⁽¹²⁾

I

µA

PWR(SLEEP)

EN, D2, INV, SLEW = Logic [0], IN1, IN2, D1 = Logic [1], and

–

50

20

I

= 0 A

OUT

Standby Supply Current (Part Enabled)

= 0 A, V = 5.0 V

I

mA

PWR(STANDBY)

I

OUT

EN

Undervoltage Lockout Thresholds

V

4.15

–

V

PWR(falling)

UVLO(ACTIVE)

V

5.0

350

PWR(rising)

UVLO(INACTIVE)

Hysteresis

V

150

200

mV

UVLO(HYS)

CHARGE PUMP

Charge Pump Voltage (CP Capacitor = 33 nF)

V

- V

V

CP

PWR

V

= 5.0 V

= 28 V

3.5

–

PWR

12

CONTROL INPUTS

Operating Input Voltage (EN, IN1, IN2, D1, D2, INV, SLEW)

V_I

–

5.5

Input Voltage (IN1, IN2, D1, D2, INV, SLEW) ⁽¹³⁾

Logic Threshold HIGH

V

2.0

–

1.0

–

V

IH

Logic Threshold LOW

V

IL

Hysteresis

V

250

400

mV

HYS

Input Voltage (EN) Threshold

V_TH

1.0

–

2.0

V

Logic Input Currents, VPWR = 8.0V

I

µA

IN

Inputs EN, D2, INV, SLEW (internal pull-downs), V_IH= 5.0V

Inputs IN1, IN2, D1 (internal pull-ups), VIL = 0V

20

80

200

-20

-200

-80

Notes

10. Device specifications are characterized over the range of 8.0 V ≤ V

≤ 28 V. Continuous operation above 28 V may degrade device

PWR

reliability. Device is operational down to 5.0 V, but below 8.0 V the output resistance may increase by 50 percent.

11. Device will survive the transient overvoltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once

every 10 seconds.

12.

I

is with Sleep mode activated and EN, D2, INV, SLEW = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating.

PWR(sleep)

13. SLEW Input Voltage Hysteresis is guaranteed by design.

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 8.0 V ≤ V_PWR≤ 28 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUTS OUT1, OUT2

Output-ON Resistance ⁽¹⁵⁾, I_LOAD= 3.0A

R

mΩ

DS(ON)

V_PWR= 8.0V, T = 25°C

–

120

–

J

V_PWR= 8.0V, T = 150°C

225

325

J

V_PWR= 5.0V, T = 150°C

–

J

Output Current Regulation Threshold

T_J< T_FB

I

A

LIM

5.2

–

6.5

4.2

8.0

–

T_J≥ T_FB(Fold back Region - see Figure 9 and Figure 11) ⁽¹⁴⁾

High-Side Short Circuit Detection Threshold (Short Circuit to Ground) ⁽¹⁴⁾

I

11

13

11

16

14

A

SCH

(14)

Low-Side Short Circuit Detection Threshold (Short Circuit to V_PWR

Output Leakage Current ⁽¹⁶⁾, Outputs off, V_PWR= 28V

)

I

9.0

SCL

OUTLEAK

I

µA

V

= V_PWR

–

100

–

OUT

= Ground

–60

Output MOSFET Body Diode Forward Voltage Drop

= 3.0 A

V

F

I

–

2.0

OUT

Overtemperature Shutdown ⁽¹⁴⁾

°C

Thermal Limit @ T

J

T

175

–

200

–

LIM

Hysteresis @ T

J

T

12

HYS

(14)

Current Foldback at T

J

T_FB

165

10

–

185

15

°C

Current Foldback to Thermal Shutdown Separation ⁽¹⁴⁾

T_SEP

HIGH-SIDE CURRENT SENSE FEEDBACK

Feedback Current (pin FB sourcing current) ⁽¹⁷⁾

I

FB

I

= 0 mA

0.0

–

50

750

µA

OUT

= 300 mA

= 500 mA

= 1.5 A

270

0.35

2.86

5.71

11.43

0.775

3.57

7.14

14.29

1.56

4.28

8.57

17.15

mA

= 3.0 A

= 6.0 A

STATUS FLAG ⁽¹⁸⁾

Status Flag Leakage Current ⁽¹⁹⁾

I

µA

SFLEAK

V

= 5.0 V

–

5.0

0.4

SF

Status Flag SET Voltage ⁽²⁰⁾

= 300 µA

V

SFLOW

I

SF

Notes

14. This parameter is Guaranteed By Design.

15. Output-ON resistance as measured from output to VPWR and from output to GND.

16. Outputs switched OFF via D1 or D2.

17. Accuracy is better than 20% from 0.5 A to 6.0 A. Recommended terminating resistor value: R_FB= 270 Ω.

18. Status Flag output is an open drain output requiring a pullup resistor to logic V

.

DD

19. Status Flag Leakage Current is measured with Status Flag HIGH and not SET.

20. Status Flag Set Voltage measured with Status Flag LOW and SET with I = 300 µA. Maximum allowable sink current from this pin is

FS

< |500 µA|. Maximum allowable pullup voltage < 7.0 V.

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 8.0 V ≤ V_PWR≤ 28 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

TIMING CHARACTERISTICS

PWM Frequency ⁽²¹⁾

f

–

20

kHz

µs

PWM

Maximum Switching Frequency During Current Limit Regulation ⁽²²⁾

Output ON Delay ⁽²³⁾

f

MAX

DON

t

V

= 14 V

–

18

PWR

Output OFF Delay ⁽²³⁾

= 14 V

t

µs

DOFF

V

–

15

12

–

12

32

27

8.0

PWR

I_LIMOutput Constant-OFF Time ⁽²⁴⁾

I_LIMBlanking Time ⁽²⁵⁾

µs

t

20.5

16.5

–

A

B

Disable Delay Time ⁽²⁶⁾

t

µs

DDISABLE

Output Rise and Fall Time ⁽²⁷⁾

SLEW = SLOW

t , t

F

R

1.5

0.2

3.0

–

6.0

SLEW = FAST

1.45

Short Circuit/Overtemperature Turn-OFF (Latch-OFF) Time ^{(28) (29)}

Power-ON Delay Time ⁽²⁹⁾

t

–

8.0

5.0

150

–

µs

FAULT

t

1.0

100

7.0

ms

POD

Output MOSFET Body Diode Reverse Recovery Time ⁽²⁹⁾

Charge Pump Operating Frequency ⁽²⁹⁾

Notes

ns

t

75

–

RR

f_CP

MHz

21. The maximum PWM frequency is obtained when the device is set to Fast Slew Rate via the SLEW pin. PWM-ing when SLEW is set to

SLOW should be limited to frequencies <11 kHz in order to allow the internal high-side driver circuitry time to fully enhance the high-side

MOSFETs.

22. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s

inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM

frequency during current limit.

23. Output Delay is the time duration from 1.5V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)

of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5V on the input signal to the 80% point of the

output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5V on the input signal to the 20% point of the output

response signal. See Figure 4, page 10.

24. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.

25. The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time

to act.

26. Disable Delay Time measurement is defined in Figure 5, page 10.

27. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with V

= 14 V,

PWR

R

= 3.0 ohm. See Figure 6, page 10.

LOAD

28. Load currents ramping up to the current regulation threshold become limited at the I_LIMvalue (see Figure 7). The short circuit currents

possess a di/dt that ramps up to the I or I threshold during the I_LIMblanking time, registering as a short circuit event detection and

SCH

SCL

causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode

may cause junction temperatures to rise. Junction temperatures above ~160°C will cause the output current limit threshold to “fold back”,

or decrease, until ~175°C is reached, after which the T_LIMthermal latch-OFF will occur. Permissible operation within this fold back region

is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).

29. Parameter is Guaranteed By Design.

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Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

5.0

1.5V

0

t

DON

80%

t

DOFF

V_PWR

20%

0

TIME

Figure 4. Output Delay Time

5.0 V

0 V

1.5V

^tDDISABLE

90%

0 ς

TIME

Figure 5. Disable Delay Time

.

t

R

F

V_PWR

90%

10%

0

TIME

Figure 6. Output Switching Time

Overload Condition

I_SCShort Circuit Detection Threshold

9.0

6.5

t

= I Blanking Time

lim

B

t

= Constant-OFF Time (OUT1 and OUT2 Tri-Stated)

A

t

A

B

I

lim

0.0

5.0

t

ON

TIME

Figure 7. Current Limit Blanking Time and Constant-OFF Time

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Analog Integrated Circuit Device Data

Freescale Semiconductor

10

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Short Circuit Condition

t

FAULT

I_SCShort Circuit Detection Threshold

9.0

6.5

Hard Short Occurs

OUT1, OUT2 Tri-Stated,

SF set Low

t

B

I

lim

0.0

5.0

(~16 us)

t

TIME

B

Figure 8. Short Circuit Detection Turn-OFF Time t_FAULT

.

Nominal Current Limit Threshold

Current Limit Threshold Foldback.

Operation within this region must be

limited to non-repetitive events not to

exceed 30 s per 24 hr.

6.5

4.2

T_LIM

T_SEP

T_HYS

Thermal Shutdown

T_LIM

T_FB

Figure 9. Output Current Limiting Foldback Region

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Analog Integrated Circuit Device Data

Freescale Semiconductor

11

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

Numerous protection and operational features (speed,

torque, direction, dynamic breaking, PWM control, and

closed-loop control) make the 33926 a very attractive, cost-

effective solution for controlling a broad range of small DC

motors. The 33926 outputs are capable of supporting peak

DC load currents of up to 5.0 A from a 28 V_PWRsource. An

internal charge pump and gate drive circuitry are provided

that can support external PWM frequencies up to 20 kHz.

that allows the IC to be placed in a power-conserving Sleep

mode.

The 33926 has Output Current Limiting (via Constant

OFF-Time PWM Current Regulation), Output Short-Circuit

Detection with Latch-OFF, and Overtemperature Detection

with Latch-OFF. Once the device is latched-OFF due to a

fault condition, either of the Disable inputs (D1 or D2), V_PWR

or EN must be “toggled” to clear the status flag.

,

The 33926 has an analog feedback (current mirror) output

pin (the FB pin) that provides a constant-current source

ratioed to the active high-side MOSFETs’ current. This can be

used to provide “real time” monitoring of output current to

facilitate closed-loop operation for motor speed/torque

control, or for the detection of open load conditions.

Current limiting (Load Current Regulation) is

accomplished by a constant-OFF time PWM method using

current limit threshold triggering. The current limiting scheme

is unique in that it incorporates a junction temperature-

dependent current limit threshold. This means that the

current limit threshold is “reduced to around 4.2 A” as the

junction temperature increases above 160°C. When the

temperature is above 175°C, overtemperature shutdown

(latch-OFF) will occur. This combination of features allows

the device to continue operating for short periods of time (<30

seconds) with unexpected loads, while still retaining

adequate protection for both the device and the load.

Two independent inputs, IN1 and IN2, provide control of

the two totem-pole half-bridge outputs. An input invert, INV,

changes IN1 and IN2 to LOW = true logic. Two different

output slew rates are selectable via the SLEW input. Two

independent disable inputs, D1 and D2, provide the means to

force the H-Bridge outputs to a high impedance state (all H-

Bridge switches OFF). An EN pin controls an enable function

FUNCTIONAL PIN DESCRIPTION

that the current is being commanded to flow through the load

attached between OUT1 and OUT2, changing the logic level

at INV will have the effect of reversing the direction of current

commanded. Thus, the INV input may be used as a “forward/

reverse” command input. If both IN1 and IN2 are the same

logic level, then changing the logic level at INV will have the

effect of changing the bridge’s output from freewheeling high

to freewheeling low or vice versa.

POWER GROUND AND ANALOG GROUND

(PGND AND AGND)

The power and analog ground pins should be connected

together with a very low impedance connection.

POSITIVE POWER SUPPLY (VPWR)

VPWR pins are the power supply inputs to the device. All

VPWR pins must be connected together on the printed circuit

board with as short as possible traces, offering as low

impedance as possible between pins.

SLEW RATE (SLEW)

The SLEW pin is the logic input that selects fast or slow

slew rate. Schmitt trigger input with ~80 µA sink so the default

condition is SLOW. When SLEW is set to SLOW, PWM-ing

should be limited to frequencies less than 11 kHz in order to

allow the internal high-side driver circuitry time to fully

enhance the high-side MOSFETs.

Transients on V_PWRwhich go below the Under Voltage

Threshold will result in the protection activating. It is essential

to use an input filter capacitor of sufficient size and low ESR

to sustain a V_PWRgreater than V_UVLOwhen the load is

switched (See 33926 Typical Application Schematic on page

18).

INPUT 1,2 AND DISABLE INPUT 1,2

(IN1, IN2, AND D1, D2)

STATUS FLAG (SF)

This pin is the device fault status output. This output is an

active LOW open drain structure requiring a pullup resistor to

V_DD. The maximum V_DDis <7.0 V. Refer to Table 5, Truth

Table, page 16 for the SF Output status definition.

These pins are input control pins used to control the

outputs. These pins are 3.0 V/5.0 V CMOS-compatible

inputs with hysteresis. IN1 and IN2 independently control

OUT1 and OUT2, respectively. D1 and D2 are

complementary inputs used to tri-state disable the H-Bridge

outputs.

INPUT INVERT (INV)

The Input Invert Control pin sets IN1 and IN2 to

LOW = TRUE. This is a Schmitt trigger input with ~80 µA sink;

the default condition is non-inverted. If IN1 and IN2 are set so

When either D1 or D2 is SET (D1 = logic HIGH or

D2 = logic LOW) in the disable state, outputs OUT1 and

OUT2 are both tri-state disabled; however, the rest of the

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

device circuitry is fully operational and the supply

I_PWR(STANDBY)current is reduced to a few mA. Refer to Table

3, Static Electrical Characteristics, page 7.

a logic LOW state, the device is in the Sleep mode. The

device is enabled and fully operational when the EN pin

voltage is logic HIGH. An internal pulldown resistor maintains

the device in Sleep mode in the event EN is driven through a

high impedance I/O or an unpowered microcontroller, or the

EN input becomes disconnected.

H-BRIDGE OUTPUT (OUT1, OUT2)

These pins are the outputs of the H-Bridge with integrated

free-wheeling diodes. The bridge output is controlled using

the IN1, IN2, D1, and D2 inputs. The outputs have PWM

current limiting above the I_LIMthreshold. The outputs also

have thermal shutdown (tri-state latch-OFF) with hysteresis

as well as short circuit latch-OFF protection.

FEEDBACK (FB)

The 33926 has a feedback output (FB) for “real time”

monitoring of H-Bridge high-side output currents to facilitate

closed-loop operation for motor speed and torque control.

A disable timer (time t_b) is incorporated to distinguish

between load currents that are higher than the I_LIMthreshold

and short circuit currents. This timer is activated at each

output transition.

The FB pin provides current sensing feedback of the

H-Bridge high-side drivers. When running in the forward or

reverse direction, a ground-referenced 0.24% of load current

is output to this pin. Through the use of an external resistor to

ground, the proportional feedback current can be converted

to a proportional voltage equivalent and the controlling

microcontroller can “read” the current proportional voltage

with its analog-to-digital converter (ADC). This is intended to

provide the user with only first-order motor current feedback

for motor torque control. The resistance range for the linear

operation of the FB pin is 100 <R_FB<300 W.

CHARGE PUMP CAPACITOR (CCP)

This pin is the charge pump output pin and connection for

the external charge pump reservoir capacitor. The allowable

value is from 30 nF to 100 nF. This capacitor must be

connected from the CCP pin to the VPWR pin. The device

cannot operate properly without the external reservoir

capacitor.

If PWM-ing is implemented using the disable pin inputs

(either D1 or D2), a small filter capacitor (~1.0 µF) may be

required in parallel with the R_FBresistor to ground for spike

suppression.

ENABLE INPUT (EN)

The EN pin is used to place the device in a Sleep mode so

as to consume very low currents. When the EN pin voltage is

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

VOLTAGE

CURRENT SENSE

33926

REGULATION

CHARGE

PUMP

TEMPERATURE

SENSE

H-BRIDGE

ANALOG CONTROL AND PROTECTION

OUTPUT DRIVERS

OUT1 - OUT2

PWM CONTROLLER

MCU

INTERFACE

COMMAND AND FAULT REGISTERS

PROTECTION LOGIC CONTROL

GATE CONTROL LOGIC

Figure 10. Functional Internal Block Diagram

two half-bridge totem-pole outputs. Two independent disable

inputs are provided to force the H-Bridge outputs to tri-state

(high impedance off-state).

ANALOG CONTROL AND PROTECTION

CIRCUITRY:

The on-chip Voltage Regulator supplies 3.3V to the

internal logic. The charge pump provides gate drive for the H-

Bridge MOSFETs. The Current and Temperature sense

circuitry provides detection and protection for the output

drivers. Output undervoltage protection shuts down the

MOSFETS.

H-BRIDGE OUTPUT DRIVERS: OUT1 AND OUT2

The H-Bridge is the power output stage. The current flow

from OUT1 to OUT2 is reversible and under full control of the

user by way of the Input Control Logic. The output stage is

designed to produce full load control under all system

conditions. All protective and control features are integrated

into the Control and Protection blocks. The sensors for

current and temperature are integrated directly into the

output MOSFET for maximum accuracy and dependability.

GATE CONTROL LOGIC:

The 33926 is a monolithic H-Bridge Power IC designed

primarily for any low-voltage DC servo motor control

application within the current and voltage limits stated for the

device. Two independent inputs provide polarity control of

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

9.0

6.5

Typical Short Circuit Detection Threshold

Typical Current Limit Threshold

High Current Load Being Regulated via Constant-OFF-Time PWM

Moderate Current Load

PWM

Current

Limiting

Hard Short Detection and Latch-OFF

0

IN1 or IN2

IN2 or IN1

IN1 or IN2

IN2 or IN1

[1]

IN1 IN2

[0]

[1]

[0]

[1]

[0]

[1]

[0]

Outputs

Tri-Stated

Outputs

Tri-Stated

Outputs Operation

(per Input Control Condition)

Time

Figure 11. Operating States

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 5. Truth Table

The tri-state conditions and the status flag are reset using D1 or D2. The truth table uses the following notations: L = LOW, H =

HIGH, X = HIGH or LOW, and Z = High Impedance. All output power transistors are switched off.

Input Conditions

Status

Outputs

OUT1 OUT2

Device State

EN

D1

D2

IN1

IN2

SF

Forward

Reverse

H

L

H

X

L

H

L

H

L

H

L

H

L

H

L

Free Wheeling Low

Free Wheeling High

Disable 1 (D1)

L

H

X

Z

X

H

X

Z

X

H

Z

H

X

Z

H

Z

X

H

Z

H

X

L

Disable 2 (D2)

L

IN1 Disconnected

IN2 Disconnected

D1 Disconnected

D2 Disconnected

Undervoltage Lockout ⁽³⁰⁾

Overtemperature ⁽³¹⁾

Short Circuit ⁽³¹⁾

Sleep Mode EN

EN Disconnected

Notes

H

X

Z

H

L

Z

X

L

X

L

H

Z

30. In the event of an undervoltage condition, the outputs tri-state and status flag is SET logic LOW. Upon undervoltage recovery, status

flag is reset automatically or automatically cleared and the outputs are restored to their original operating condition.

31. When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input

signals and the status flag is latched to logic LOW. To reset from this condition requires the toggling of either D1, D2, EN, or V

.

PWR

Reverse

Forward

Low-Side Recirculation

(Forward)

High-Side Recirculation

V

(Forward)

V

PWR

V

PWR

V

PWR

V

PWR

Load

Current

Load

Current

Load

Current

ON

OUT1

OFF

OUT2

OFF

OUT1

ON

OUT2

OFF

OUT1

OFF

OUT2

ON

OUT1

ON

OUT2

LOAD

OFF

ON

OFF

Load

Current

ON

OFF

PGND

Figure 12. 33926 Power Stage Operation

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSTIC FEATURES

OVERTEMPERATURE SHUTDOWN AND

SHORT CIRCUIT PROTECTION

HYSTERESIS

If an output short circuit condition is detected, the power

outputs tri-state (latch-OFF) independent of the input (IN1

and IN2) states, and the fault status output flag (SF) is SET

to logic LOW. If the D1 input changes from logic HIGH to logic

LOW, or if the D2 input changes from logic LOW to logic

HIGH, the output bridge will become operational again and

the fault status flag will be reset (cleared) to a logic HIGH

state.

If an overtemperature condition occurs, the power outputs

are tri-stated (latched-OFF) and the fault status flag (SF) is

SET to logic LOW.

To reset from this condition, D1 must change from logic

HIGH to logic LOW, or D2 must change from logic LOW to

logic HIGH. When reset, the output stage switches ON again,

provided that the junction temperature is now below the

overtemperature threshold limit minus the hysteresis.

The output stage will always switch into the mode defined

by the input pins (IN1, IN2, D1, and D2), provided the device

junction temperature is within the specified operating

temperature range.

Important Resetting from the fault condition will clear the

fault status flag. Powering down and powering up the device

will also reset the 33926 from the fault condition.

INTERNAL PWM CURRENT LIMITING

OUTPUT AVALANCHE PROTECTION

The maximum current flow under normal operating

conditions should be less than 5.0 A. The instantaneous load

currents will be limited to I_LIMvia the internal PWM current

limiting circuitry. When the I_LIMthreshold current value is

reached, the output stages are tri-stated for a fixed time (T_A)

of 20 µs typical. Depending on the time constant associated

with the load characteristics, the output current decreases

during the tri-state duration until the next output ON cycle

occurs.

If VPWR were to become an open circuit, the outputs

would likely tri-state simultaneously due to the disable logic.

This could result in an unclamped inductive discharge. The

VPWR input to the 33926 should not exceed 40 V during this

transient condition, to prevent electrical overstress of the

output drivers.This can be accomplished with a zener clamp

or MOV, and/or an appropriately valued input capacitor with

sufficiently low ESR (see Figure 13).

The PWM current limit threshold value is dependent on the

device junction temperature. When -40°C <T_J< 160°C, I_LIMis

between the specified minimum/maximum values. When T_J

exceeds 160 °C, the I_LIMthreshold decreases to 4.2 A.

Shortly above 175 °C the device overtemperature circuit will

detect T_LIMand an overtemperature shutdown will occur. This

feature implements a graceful degradation of operation

before thermal shutdown occurs, thus allowing for

V

PWR

VPWR

Bulk

Low ESR

Cap.

100nF

OUT1

OUT2

intermittent unexpected mechanical loads on the motor’s

gear-reduction train to be handled.

M

Important Die temperature excursions above 150°C are

permitted only for non-repetitive durations <30 seconds.

Provision must be made at the system level to prevent

prolonged operation in the current-foldback region.

9

I/Os

AGND PGND

Figure 13. Avalanche Protection

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

TYPICAL APPLICATIONS

INTRODUCTION

TYPICAL APPLICATIONS

INTRODUCTION

A typical application schematic is shown in Figure 14. For

precision high-current applications in harsh, noisy

environments, the V_PWRby-pass capacitor may need to be

substantially larger.

V

PWR

100µF

LOW ESR

100nF

VPWR

33NF

VDD

LOGIC SUPPLY

VCP

CHARGE

PUMP

HS1

LS1

HS2

LS2

CCP

OUT1

OUT2

M

TO GATES

HS1

EN

IN1

LS1

IN2

D2

HS2

LS2

PGND

GATE DRIVE

AND

D1

PROTECTION

LOGIC

+5.0V

VSENSE

ILIM PWM

INV

SLEW

SF

CURRENT MIRRORS

AND

CONSTANT OFF-TIME

STATUS

FLAG

PWM CURRENT REGULATOR

FB

TO

ADC

R

FB

270Ω

1.0µF

AGND

PGND

Figure 14. 33926 Typical Application Schematic

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the 98Axxxxxxxxx listed

below.

PNB SUFFIX

98ARL10579D

32-PIN PQFN

ISSUE C

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

PACKAGING

PACKAGE DIMENSIONS

PNB SUFFIX

98ARL10579D

32-PIN PQFN

ISSUE C

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

ADDITIONAL DOCUMENTATION

33926

THERMAL ADDENDUM (REV 2.0)

Introduction

This thermal addendum is provided as a supplement to the MC33926 technical

datasheet. The addendum provides thermal performance information that may be

critical in the design and development of system applications. All electrical,

application, and packaging information is provided in the datasheet.

32-PIN

PQFN

Packaging and Thermal Considerations

The MC33926 is offered in a 32 pin PQFN, single die package. There is a single

heat source (P), a single junction temperature (T_J), and thermal resistance (R_θJA).

T_J

.

=

R_θJA

P

PNB SUFFIX

98ARL10579D

32-PIN PQFN

The stated values are solely for a thermal performance comparison of one

package to another in a standardized environment. This methodology is not meant

to and will not predict the performance of a package in an application-specific

environment. Stated values were obtained by measurement and simulation

according to the standards listed below.

8.0 mm x 8.0 mm

Note For package dimensions, refer to

the 33926 data sheet.

STANDARDS

Table 6. Thermal Performance Comparison

Thermal Resistance

[°C/W]

1.0

(1),(2)

0.2

Ρ_θJA

Ρ_θJB

Ρ_θJA

28

12

80

1.0

(2),(3)

(1), (4)

0.2

Ρ_θϑΧ ⁽⁵⁾

Notes

* All measurements

are in millimeters

1. Per JEDEC JESD51-2 at natural convection, still air

condition.

2. 2s2p thermal test board per JEDEC JESD51-5 and

JESD51-7.

3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the center lead.

4. Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

Figure 15. Surface Mount for Power PQFN

with Exposed Pads

5. Thermal resistance between the die junction and the

exposed pad surface; cold plate attached to the package

bottom side, remaining surfaces insulated.

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

1

2

32 31 30 29 28 27 26 25

IN2

IN1

NC

24

23

22

PGND

SF

A

3

4

5

6

7

SLEW

VPWR

AGND

VPWR

INV

21

20

19

18

AGND

PGND

8

9

FB

NC

10 11 12 13 14 15 16 17

33926PNB Pin Connections

32-Pin PQFN

0.80 mm Pitch

8.0 mm x 8.0 mm Body

Figure 16. Thermal Test Board

Device on Thermal Test Board

Table 7. Thermal Resistance Performance

A [mm²]

Ρ_θJA[°C/W]

Material:

Single layer printed circuit board

0

81

49

40

FR4, 1.6 mm thickness

Cu traces, 0.07 mm thickness

300

600

Outline:

Area A:

80 mm x 100 mm board area,

including edge connector for thermal

testing

Ρθ_JAισ τηε τηερµαλ ρεσιστανχε βετωεεν διε ϕυνχτιον ανδ

αµβιεντ αιρ.

Cu heat-spreading areas on board

surface

Ambient Conditions: Natural convection, still air

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

90

80

70

60

50

40

30

20

10

0

Ρ_θ

JA [

°C/W]

x

0

300

600

Heat Spreading Area A [mm²]

Figure 17. Device on Thermal Test Board Ρθ_JA

100

10

1

Ρ_θ

x

JA [

°C/W]

0.1

1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04

Time[s]

Figure 18. Transient Thermal Resistance Rθ_JA,

1 W Step response, Device on Thermal Test Board Area A = 600 (mm²)

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

REVISION HISTORY

REVISION DATE

DESCRIPTION

• Updated formatting and technical content throughout entire document.

• Updated formatting and technical content throughout entire document

1.0

2.0

3.0

4.0

5.0

6.0

3/2006

6/2007

10/2006

12/2006

2/2007

3/2007

• Changed Human Body Model, Charge Pump Voltage (CP Capacitor = 33 nF), No PWM and PWM =

20kHz, Slew Rate = Fast, Output Rise and Fall Time ⁽²⁷⁾

• Added second paragraph to Positive Power Supply (VPWR)

• Added “Low ESR” to 100µF on 33926 Typical Application Schematic

• Changed status to Advance Information

7.0

6/2007

33926

Analog Integrated Circuit Device Data

Freescale Semiconductor

24

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USA/Europe or Locations Not Listed:

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Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

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MC33926

Rev. 7.0

6/2007


型号：	PC33926PNB/R2
厂家：	Freescale
描述：	5.0 A Throttle Control H-Bridge 5.0油门控制H桥
文件：	总25页 (文件大小：620K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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