PC33894PNCR2 [NXP]
IC,PERIPHERAL DRIVER,4 DRIVER,LLCC,24PIN,PLASTIC;
| 型号： | PC33894PNCR2 |
| 厂家： | 
NXP |
| 描述： | IC,PERIPHERAL DRIVER,4 DRIVER,LLCC,24PIN,PLASTIC 驱动 驱动器 |
| 文件： | 总28页 (文件大小：808K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Document order number: MC33894
Rev 1.0, 03/2004
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
33894
Quad Intelligent High-Side Switch
(Quad 35 mΩ)
The 33894 is one in a family of devices designed for low-voltage automotive
and industrial lighting and motor control applications. Its four low RDS(ON)
QUAD INTELLIGENT
HIGH-SIDE SWITCH
MOSFETs (four 35 mΩ) can control the high sides of four separate resistive or
inductive loads or serve as high-side switches for a pair of DC motors.
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each output has its own parallel input for PWM control
if desired. The 33894 allows the user to program via the SPI the fault current
trip levels and duration of acceptable lamp inrush or motor stall intervals. Such
programmability allows tight control of fault currents and can protect wiring
harnesses and circuit boards as well as loads.
The 33894 is packaged in a power-enhanced 10x 10 nonleaded Power
QFN package with exposed tabs.
PNC SUFFIX
CASE 1558-02
Features
• Quad 35 mΩ High-Side Switches (at 25°C)
24-TERMINAL PQFN
• Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 µA
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe
Terminal Status, and Program Status
• Analog Current Feedback with Selectable Ratio
• Enhanced 16 V Reverse Polarity VPWR Protection
ORDERING INFORMATION
Temperature
Device
PC33894PNC/R2
Package
Range (TA)
24 PQFN
-40°C to 125°C
33894 Simplified Application Diagram
V
PWR
V
V
V
V
V
DD
DD
DD
PWR
33894
V
DD
PWR
HS0
WAKE
SI
SO
SCLK
CS
LOAD 0
LOAD 1
SCLK
CS
HS1
HS2
HS3
SI
SO
I/O
RST
FS
MCU
I/O
I/O
IN0
IN1
IN2
IN3
CSNS
LOAD 2
LOAD 3
I/O
I/O
I/O
A/D
FSI
GND
GND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
For More Information On This Product,
© Motorola, Inc. 2004
Go to: www.freescale.com
Freescale Semiconductor, Inc.
V
V
PWR
DD
Internal
Over/Undervoltage
Protection
Regulator
Selectable Slew
Rate Gate Drive
CS
SPI
3.0 MHz
SCLK
HS0
SO
SI
Selectable Current Limit
HS[0:3]: 35 A or 50 A
RST
WAKE
FS
Logic
Selectable Current
Selectable Over-
current Detection
Detection Time
IN0
0.15 ms–620 ms
HS[0:3]: 2.4 A–9.1 A
IN1
IN2
IN3
Open
Load
Detection
Overtemperature
Detection
HS0
HS1
HS1
HS2
HS3
Programmable
Watchdog
310 ms–2500 ms
HS2
HS3
FSI
Selectable Output Current
Recopy (Analog MUX)
HS[0:3]: 1/6500 or 1/20000
GND
CSNS
Figure 1. 33894 Simplified Internal Block Diagram
33894
2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
Transparent Top View of Package
10
9
8
7
6
5
4
3
2
1
24
VDD
SO
11
12
13
IN0
23
22
CSNS
FSI
GND
GND
HS3
14
15
21
HS2
16
VPWR
HS1
17
18
19
HS0
20 HS0
HS1
TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal Name
Formal Name
Definition
1
2
IN1
IN2
IN3
IN0
Serial Inputs
The IN0–IN3 high-side input terminals are used to directly control HS0–HS3 high-
side output terminals, respectively. An SPI register determines if each input is
activated or if the input logic state is ORed or ANDed with the SPI instruction. These
terminals are to be driven with 5.0 V CMOS levels, and they have an internal active
pull-down current source.
3
24
4
5
Fault Status
(Active Low)
This terminal is an open drain configured output requiring an external pull-up resistor
to VDD for fault reporting. If a device fault condition is detected, this terminal is active
LOW. Specific device diagnostic faults are reported via the SPI SO terminal.
FS
WAKE
Wake
This terminal is an input that controls the device mode and watchdog timeout feature
if enabled. An internal clamp protects this terminal from high damaging voltages when
the output is current limited with an external resistor. This input has an internal passive
pull-down.
6, 13, 15
7
GND
RST
Ground
Reset
These terminals are the ground for the logic and analog circuitry of the device.
This terminal is an input used to initialize the device configuration and fault registers,
as well as place the device in a low-current sleep mode. The terminal also starts the
watchdog timer when transitioning from logic [0] to logic [1]. This terminal should not
be allowed to be logic [1] until VDD is in regulation. This terminal has an internal
passive pull-down.
8
9
Chip Select
(Active Low)
This terminal is an input terminal connected to a chip select output of a master
microcontroller (MCU). The MCU determines which device is addressed (selected) to
receive data by pulling the CS terminal of the selected device logic LOW, thereby
enabling SPI communication with the device. Other unselected devices on the serial
link having their CS terminals pulled up logic HIGH disregard the SPI communication
data sent. This terminal has an internal active pull-up current source and requires
CMOS logic levels.
CS
SCLK
Serial Clock
This terminal is an input terminal connected to the MCU providing the required bit shift
clock for SPI communication. It transitions one time per bit transferred at an operating
frequency, fSPI, defined by the communication interface. The 50 percent duty cycle
CMOS level serial clock signal is idle between command transfers. The signal is used
to shift data into and out-of the device. This terminal has an internal active pull-down.
33894
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TERMINAL FUNCTION DESCRIPTION (continued)
Terminal
Terminal Name
Formal Name
Definition
10
SI
Serial Input
This terminal is a command data input terminal connected to the SPI Serial Data
Output of the MCU or to the SO terminal of the previous device of a daisy chain of
devices. The input requires CMOS logic level signals and incorporates an internal
active pull-down. Device control is facilitated by the input's receiving the MSB first of
a serial 8-bit control command. The MCU ensures data is available upon the falling
edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that
bit command into the internal command shift register. This terminal has an internal
active pull-down.
11
12
VDD
SO
Digital Drain Voltage
(Power)
This terminal is an external voltage input terminal used to supply power to the SPI
circuit. In the event VDD is lost, an internal supply provides power to a portion of the
logic, ensuring limited functionality of the device.
Serial Output
This terminal is an output terminal connected to the SPI Serial Data Input terminal of
the MCU or to the SI terminal of the next device of a daisy chain of devices. This output
will remain tri-stated (high-impedance OFF condition) so long as the CS terminal of the
device is logic HIGH. SO is only active when the CS terminal of the device is asserted
logic LOW. The generated SO output signals are CMOS logic levels. SO output data
is available on the falling edge of SCLK and transitions immediately on the rising edge
of SCLK.
14
HS3
High-Side Outputs
Protected 35 mΩ high-side power output terminals to the load.
17, 18
19, 20
21
HS1 (Note 1)
HS0 (Note 2)
HS2
16
VPWR
Positive Power Supply
Fail-Safe Input
This terminal connects to the positive power supply and is the source of operational
power for the device. The VPWR contact is the backside surface mount tab of the
package.
22
FSI
The value of the resistance connected between this terminal and ground determines
the state of the outputs after a Watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF or the output HSO only is ON. If the FSI terminal is
left to float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in
the Fail-Safe state. When the FSI terminal is connected to GND, the Watchdog circuit
and Fail-Safe operation are disabled. This terminal incorporates an active internal
pull-up.
23
CSNS
Output Current
Monitoring
The Current Sense terminal sources a current proportional to the designated HS0–
HS3 output. That current is fed into a ground referenced resistor and its voltage is
monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This
terminal can be tri-stated through SPI.
Notes
1. HS1 output (17 and 18) must be connected externally on the PCB as close as possible to the terminals.
2. HS0 output (19 and 20) must be connected externally on the PCB as close as possible to the terminals.
33894
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Operating Voltage Range
Steady-State
VPWR(SS)
V
-16 to 41
0 to 5.5
VDD Supply Voltage
VDD
V
V
Input/Output Voltage (Note 3)
V
IN[0:3], RST, FSI,
-0.3 to 7.0
CSNS, SI, SCLK,
CS, FS
SO Output Voltage (Note 3)
WAKE Input Clamp Current
CSNS Input Clamp Current
Output Current (Note 4)
VSO
ICL(WAKE)
ICL(CSNS)
IHS[0:3]
ECL[0:3]
TSTG
-0.3 to VDD+0.3
2.5
V
mA
mA
A
10
11
Output Clamp Energy (Note 5)
Storage Temperature
TBD
J
-55 to 150
-40 to 125
-40 to 150
°C
Operating Ambient Temperature
Operating Junction Temperature
TA
°C
TJ
°C
Thermal Resistance
Junction to Case
°C/W
R
R
<1.0
TBD
JC
JA
θ
Junction to Ambient
θ
ESD Voltage
V
Human Body Model (Note 6)
Machine Model (Note 7)
VESD1
VESD2
±2000
±200
Terminal Soldering Temperature (Note 8)
Notes
TSOLDER
240
°C
3. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, SI, SO, SCLK, CS, or FS terminals may cause a malfunction or permanent damage
to the device.
4. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output
current using package thermal resistance is required.
5. Active clamp energy using single-pulse method (L = 16 mH, RL = 0 Ω, VPWR = 12 V, TJ = 150°C).
6. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
7. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω) and in accordance with the system module
specification with a capacitor > 0.01 µF connected from high-side outputs to GND.
8. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
33894
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Battery Supply Voltage Range
Fully Operational
VPWR
V
6.0
–
–
–
27
20
IPWR(
mA
VPWR Operating Supply Current
Outputs ON, IHS = 0 A
)
on
V
PWR Supply Current
IPWR(
sby
mA
)
Outputs OFF, Open Load Detection Disabled, WAKE > 0.7 VDD
RST = VLOGIC HIGH
,
–
–
5.0
IPWR(
sleep
µA
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V)
)
–
–
–
–
10
50
TJ = 25°C
TJ = 85°C
V
V
DD Supply Voltage
VDD(
on
4.5
5.0
5.5
V
)
DD Supply Current
IDD(
mA
)
on
No SPI Communication
3.0 MHz SPI Communication
–
–
–
–
1.0
5.0
V
DD Sleep State Current
IDD(
–
–
5.0
µA
)
sleep
VPWR(OV)
VPWR(OVHYS)
VPWR(UV)
VPWR(UVHYS)
VPWR(UVPOR)
Overvoltage Shutdown Threshold
Overvoltage Shutdown Hysteresis
Undervoltage Shutdown Threshold (Note 9)
Undervoltage Hysteresis (Note 10)
Undervoltage Power-ON Reset
Notes
28
0.2
4.75
–
32
0.8
5.24
0.25
–
36
1.5
5.75
–
V
V
V
V
V
–
5.0
9. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not
go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the
external VDD supply is within specification.
10. This applies when the undervoltage fault is not latched (IN = 0).
33894
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS HS0 TO HS3
RDS(ON)25
mΩ
Output Drain-to-Source ON Resistance (IHS = 10 A, TJ = 25°C)
–
–
–
–
–
–
55
35
35
VPWR = 6.0 V
VPWR = 10 V
VPWR = 13 V
RDS(ON)150
mΩ
Output Drain-to-Source ON Resistance (IHS = 10 A, TJ = 150°C)
–
–
–
–
–
–
94
60
60
VPWR = 6.0 V
VPWR = 10 V
VPWR = 13 V
Output Source-to-Drain ON Resistance (Note 13)
RDS(ON)
mΩ
–
–
70
I
HS = 15 A, TJ = 25°C, VPWR = -12 V
Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)
A
IOCH0
IOCH1
40
28
50
35
62
43
SOCH = 0
SOCH = 1
Overcurrent Low Detection Levels (SOCL[2:0], 9.0 V < VPWR < 16 V)
A
IOCL0
IOCL1
IOCL2
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
7.2
6.5
5.7
5.0
4.2
3.4
2.6
1.9
9.1
8.15
7.2
6.25
5.25
4.3
11
9.8
8.7
7.5
6.3
5.2
4.1
2.9
000
001
010
011
100
101
110
111
3.35
2.4
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
–
CSR0
CSR1
–
–
1/6500
1/20000
–
–
DICR D2 = 0
DICR D2 = 1
Current Sense Ratio (CSR0) Accuracy
CSR0_ACC
%
Output Current
2.0 A
-20
-14
-13
-12
-13
-13
–
–
–
–
–
–
20
14
13
12
13
13
5.0 A
10 A
12.5 A
15 A
20 A
Notes
11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
12. Guaranteed by process monitoring. Not production tested.
13. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR
.
33894
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS HS0 TO HS3 (continued)
Current Sense Ratio (CSR1) Accuracy
CSR1_ACC
%
Output Current
5.0 A
-25
-19
-18
-17
-18
-18
–
–
–
–
–
–
25
19
18
17
18
18
10 A
12.5 A
15 A
20 A
25 A
Maximum Current Sense Clamp Voltage
VCL(MAXCSNS)
V
I
CSNS = 15 mA
4.5
30
6.0
–
7.0
Open Load Detection Current (Note 14)
IOLDC
100
µA
Output Fault Detection Threshold
Output Programmed OFF
VOFD(THRES)
V
2.0
-20
3.0
–
4.0
–
Output Negative Clamp Voltage
VCL
TSD
V
0.5 A < = IHS < = 2.0 A, Output OFF
Overtemperature Shutdown (Note 15)
°C
°C
150
5.0
175
–
190
20
TA = 125°C, Output OFF
Overtemperature Shutdown Hysteresis (Note 15)
Notes
TSD(HYS)
14. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
15. Guaranteed by process monitoring. Not production tested.
33894
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE
Input Logic High Voltage (Note 16)
VIH
VIL
0.7VDD
–
–
–
–
0.2VDD
750
20
V
V
Input Logic Low Voltage (Note 16)
Input Logic Voltage Hysteresis (Note 16)
Input Logic Pull-Down Current (SCLK, IN, SI, IN[0:3])
RST Input Voltage Range
VIN(HYS)
IDWN
100
5.0
4.5
–
350
–
mV
µA
V
VRST
5.0
–
5.5
SO, FS Tri-State Capacitance (Note 17)
Input Logic Pull-Down Resistor (RST) and WAKE
Input Capacitance (Note 18)
CSO
20
pF
kΩ
pF
V
IDWN
100
–
200
4.0
400
12
CIN
Wake Input Clamp Voltage (Note 19)
VCL(WAKE)
I
CL(WAKE) < 2.5 mA
Wake Input Forward Voltage
CL(WAKE) = -2.5 mA
SO High-State Output Voltage
OH = 1.0 mA
FS, SO Low-State Output Voltage
OL = -1.6 mA
7.0
-2.0
0.8VDD
–
–
–
14
-0.3
–
VF(WAKE)
V
V
I
VSOH
I
–
VSOL
V
I
0.2
0
0.4
5.0
20
SO Tri-State Leakage Current
CS > 0.7VDD
ISO(LEAK)
µA
µA
kΩ
-5.0
5.0
IUP
Input Logic Pull-Up Current (Note 20)
CS, VIN > 0.7VDD
–
FSI Input terminal External Pull-Down Resistance (Note 21)
FSI Disabled, HS[0:3] Indeterminate
FSI Enabled, all HS OFF
FSI Enabled, HS0 ON, HS[1:3] OFF
FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF
RFS
RFSdis
RFSoffoff
RFSonoff
RFSonon
–
0
6.5
17
1.0
7.0
19
–
6.0
15
30
Infinite
Notes
16. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST signals
may be supplied by a derived voltage referenced to VPWR
.
17. Parameter is guaranteed by process monitoring but is not production tested.
18. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
19. The current must be limited by a series resistance when using voltages > 7.0 V.
20. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD
.
21. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the
resistance value will always be within the desired (specified) range.
33894
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING HS0 TO HS3
Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 22)
9.0 V < VPWR < 16 V
SRRA_SLOW
SRRB_SLOW
SRRA_FAST
SRRB_FAST
SRFA_SLOW
SRFB_SLOW
SRFA_FAST
SRFB_FAST
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
0.1
0.015
0.2
0.3
0.05
0.5
0.5
0.15
1.5
Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 23)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 22)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 23)
9.0 V < VPWR < 16 V
0.015
0.1
0.05
0.3
0.5
Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 22)
9.0 V < VPWR < 16 V
0.5
Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 23)
9.0 V < VPWR < 16 V
0.015
0.4
0.05
1.0
0.15
2.0
Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 22)
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 23)
9.0 V < VPWR < 16 V
0.05
0.175
0.6
Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 24)
DICR = 0, DICR = 1
tDLY(ON)
tDLY_SLOW(OFF)
tDLY_FAST(OFF)
fPWM
µs
µs
µs
2.0
40
30
200
Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 25)
DICR = 0
460
1000
Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 25)
DICR = 1
20
–
120
–
400
300
Direct Input Switching Frequency (DICR D3 = 0)
Hz
ms
Overcurrent Low Detection Blanking Time (OCLT[1:0])
tOCL0
tOCL1
tOCL2
tOCL3
00
01
10
11
108
434
55
155
620
75
202
806
95
0.08
0.15
0.25
Notes
22. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR-3.5 V (see Figure 2, page 13). These
parameters are guaranteed by process monitoring.
23. Rise and Fall Slew Rates B measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR-3.5 V (see Figure 2). These
parameters are guaranteed by process monitoring.
24. Turn-ON delay time measured from rising edge of any signal (IN, SCLK, CS) that would turn the output ON to VHS = 0.5 V with RL = 5.0 Ω
resistive load.
25. Turn-OFF delay time measured from falling edge of any signal (IN, SCLK, CS) that would turn the output OFF to VHS = VPWR-0.5 V with
RL = 5.0 Ω resistive load.
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING HS0 TO HS3 (continued)
Overcurrent High Detection Blanking Time
tOCH
1.0
–
10
–
20
10
µs
µs
CNSVAL
CS to CSNS Valid Time (Note 26)
Watchdog Timeout (WD[1:0]) (Note 27)
ms
tWDTO0
tWDTO1
tWDTO2
tWDTO3
00
01
10
11
496
248
2000
1000
620
310
2500
1250
806
403
3250
1625
Notes
26. Time necessary for the CSNS to be with ±5% of the targeted value.
27. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output driven
OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog
timeouts.
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
–
–
–
–
–
–
–
–
–
–
–
50
–
3.0
350
300
5.0
167
167
167
167
83
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
fSPI
tWRST
tCS
Required Low State Duration for RST (Note 28)
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 29)
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 29)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 29)
Required High State Duration of SCLK (Required Setup Time) (Note 29)
Required Low State Duration of SCLK (Required Setup Time) (Note 29)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 29)
SI to Falling Edge of SCLK (Required Setup Time) (Note 30)
–
tENBL
50
–
tLEAD
tWSCLKh
tWSCLKl
tLAG
–
50
25
25
tSI(SU)
tSI(HOLD)
tRSO
Falling Edge of SCLK to SI (Required Setup Time) (Note 30)
83
SO Rise Time
CL = 200 pF
–
25
50
SO Fall Time
CL = 200 pF
ns
tFSO
–
–
–
–
–
25
–
50
50
ns
ns
ns
ns
ns
tRSI
tFSI
SI, CS, SCLK, Incoming Signal Rise Time (Note 30)
–
50
SI, CS, SCLK, Incoming Signal Fall Time (Note 30)
–
145
145
tSO(EN)
tSO(DIS)
tVALID
Time from Falling Edge of CS to SO Low Impedance (Note 31)
Time from Rising Edge of CS to SO High Impedance (Note 32)
65
Time from Rising Edge of SCLK to SO Data Valid (Note 33)
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF
–
65
105
Notes
28. RST low duration measured with outputs enabled and going to OFF or disabled condition.
29. Maximum setup time required for the 33894 is the minimum guaranteed time needed from the microcontroller.
30. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
31. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
32. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
33. Time required to obtain valid data out from SO following the rise of SCLK.
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Timing Diagrams
CS
V
PWR
VPWR-0.5V
SR
SRfB
FB
SR
SRrB
RB
VPWR-3.5 V
SR
SRfA
FA
SSRRrA
RA
0.5 V
t
DLY(OFF)
t
DLY(ON)
Figure 2. Output Slew Rate and Time Delays
IOCHx
ILOAD2
Load
Current
ILOAD1
tOCH
IOCLx
tOCLx
Time
Figure 3. Overcurrent Shutdown
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I
I
I
OCH
0
OCH1
OCL0
OCL1
I
I
OCL2
Load
Current
I
OCL3
I
I
I
I
OCL4
OCL5
OCL6
OCL7
Time
t
t
t
t
t
OCL0
OCH
OCL3
OCL2
OCL1
Figure 4. Overcurrent Low and High Detection
VIH
RST
0.2 VDD
0.2 VDD
VIL
VIL
tCS
tENBL
tWRST
VIH
VIH
0.7 V
DD
CS
00..77VVDD
DD
VIL
VIL
tRSI
TrSI
tWSCLKh
tTlead
LEAD
tLAG
Tag
VIH
VIH
0.7 VDD
SCLK
SCLK
0.2 VDD
0.2VDD
VIL
tSI(SU)
t
TwSCLKl
WSCLKl
tFSI
t
TSI(hold)
SI(HOLD)
VIH
VIH
00..77 VVDD
DD
Don’t Care
Don’t Care
Don’t Care
Valid
Valid
SI
00..22VVDD
DD
V
IH
Figure 5. Input Timing Switching Characteristics
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tRSI
tFSI
VOH
3.5 V
50%
SCLK
1.0 V
VOL
tSO(EN)
0.2V
VOH
0.7 V
DD
SO
DD
VOL
Low to High
tRSO
tVALID
tFSO
SO
VOH
0.7 V
DD
High to Low
0.2 VDD
O
VOL
tSO(DIS)
Figure 6. SCLK Waveform and Valid SO Data Delay Time
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33894 is one in a family of devices designed for low-
own parallel input for PWM control if desired. The 33894 allows
the user to program via the SPI the fault current trip levels and
duration of acceptable lamp inrush or motor stall intervals. Such
programmability allows tight control of fault currents and can
protect wiring harnesses and circuit boards as well as loads.
voltage automotive and industrial lighting and motor control
applications. Its four low RDS(ON) MOSFETs (two 10 mΩ, two
35 mΩ) can control the high sides of four separate resistive or
inductive loads or serve as high-side switches for a pair of DC
motors.
The 33894 is packaged in a power-enhanced 10 x 10 PQFN
package with exposed tabs.
Programming, control, and diagnostics are accomplished
using a 16-bit SPI interface. Additionally, each output has its
FUNCTIONAL DESCRIPTION
Serial Clock (SCLK)
SPI Protocol Description
The SCLK terminal clocks the internal shift registers of the
33894 device. The serial input (SI) terminal accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output (SO) terminal shifts data information out
of the SO line driver on the rising edge of the SCLK signal. It is
important the SCLK terminal be in a logic low state whenever
CS makes any transition. For this reason, it is recommended the
SCLK terminal be in a logic [0] whenever the device is not
accessed (CS logic [1] state). SCLK has an internal pull-down.
When CS is logic [1], signals at the SCLK and SI terminals are
ignored and SO is tri-stated (high impedance) (see Figure 7,
page 17).
The SPI interface has a full duplex, three-wire synchronous
data transfer with four I/O lines associated with it: Serial Input
(SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select
(CS).
The SI/SO terminals of the 33894 follow a first-in first-out
(D15 to D0) protocol, with both input and output words
transferring the most significant bit (MSB) first. All inputs are
compatible with 5.0 V CMOS logic levels.
The SPI lines perform the following functions:
Serial Input (SI)
This is a serial interface (SI) command data input terminal.
Each SI bit is read on the falling edge of SCLK. A 16-bit stream
of serial data is required on the SI terminal, starting with D15 to
D0. The internal registers of the 33894 are configured and
controlled using a 5-bit addressing scheme described in
Table 1, page 17. Register addressing and configuration are
described in Table 2, page 18. The SI input has an internal pull-
Chip Select (CS)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33894 latches in data
from the Input Shift registers to the addressed registers on the
rising edge of CS. The device transfers status information from
the power output to the Shift register on the falling edge of CS.
The SO output driver is enabled when CS is logic [0]. CS should
transition from a logic [1] to a logic [0] state only when SCLK is
down, IDWN
.
Serial Output (SO)
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high-impedance state
until the CS terminal is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO terminal
changes state on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and input status descriptions are
provided in Table 9, page 21.
a logic [0]. CS has an internal pull-up, IUP
.
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CSB
CS
SCLK
SI
D15
D14
D13
D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Notes 1. RST is a logic [1] state during the above operation.
2. D15–D0 relate to the most recent ordered entry of data into the device.
3. OD15–OD0 relate to the first 16 bits of ordered fault and status data out of the device.
Figure 7. Single 16-Bit Word SPI Communication
Serial Input Communication
Table 1. SI Message Bit Assignment
SPI communication is accomplished using 16-bit
messages. A message is transmitted by the MCU starting with
the MSB D15 and ending with the LSB, D0 (Table 1). Each
incoming command message on the SI terminal can be
interpreted using the following bit assignments: the MSB, D15,
is the watchdog bit. In some cases, output channel selection is
done with bits D12–D11. The next three bits, D10–D8, are
used to select the command register. The remaining five bits,
D4–D0, are used to configure and control the outputs and their
protection features.
Message Bit Description
Bit Sig SI Msg Bit
MSB D15
Watchdog in: toggled to satisfy watchdog
requirements.
D14–D15 Not used.
D12–D11 Register address bits used in some cases for
output channel selection.
D10–D8
Register address bits.
Not used.
D7–D5
D4–D1
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
LSB
D0
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
The 33894 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 2, page 18, summarizes the SI registers.
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Table 2. Serial Input Address and Configuration Bit Map
SI Data
SI Register
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
D4
D3
D2
D1
D0
STATR
OCR0
WDIN
WDIN
WDIN
WDIN
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
1
0
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x
SOA4
SOA3
SOA2
SOA1
SOA0
x
x
x
IN_SPI3
CSNS EN3
SOCH_s
IN_SPI2
IN_SPI1
IN_SPI0
OCR1
x
1
CSNS EN2 CSNS EN1 CSNS EN0
A1
A0
SOCL2_s
SOCL1_s
OCLT1_s
SOCL0_s
OCLT0_s
A/O_s
SOCHLR_s
WDIN
WDIN
x
x
x
x
A1
A1
A0
A0
0
1
1
0
1
0
x
x
x
x
x
x
x
x
OL_DIS_s
OCL_DIS_s
CDTOLR_s
FAST_SR_s CSNS_high_s DIR_DIS_s
DICR_s
UOVR
WDIN
WDIN
WDIN
WDIN
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
x
1
1
1
1
0
0
1
1
1
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
UV_DIS
WD1
OV_DIS
WD0
WDR
NAR
No Action (Allow Toggling of D15–WDIN)
Motorola Internal Use (Test)
TEST
x=Don’t care.
s=Output selection with the bits A1A0 as defined in Table 3.
summed. In the event that all bits D[3:0] are logic [0], the output
CSNS will then tri-stated. This is useful when several CSNS
terminals of several devices share the same A/D converter.
Device Register Addressing
The following section describes the possible register
addresses and their impact on device operation.
Address A1A0010—Select Overcurrent High and Low
Register (SOCHLR_s)
Address xx000—Status Register (STATR)
The STATR register is used to read the device status and the
various configuration register contents without disrupting the
device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO data.
In addition to the device status, this feature provides the ability
to read the content of the OCR0, OCR1, SOCHLR, CDTOLR,
DICR, UOVR, WDR, and NAR registers. (Refer to the section
entitled Serial Output Communication (Device Status Return
Data) beginning on page 20.)
The SOCHLR_s register allows the MCU to configure the
output overcurrent low and high detection levels, respectively.
Each output “s” is independently selected for configuration
based on the state of the D12–D11 bits (Table 3).
Table 3. Channel Selection
A1 (D12) A0 (D11)
HS_s
HS0
HS1
HS2
HS3
0
0
1
1
0
1
0
1
Address x0001—Output Control Register (OCR0)
The OCR0 register allows the MCU to control the ON/OFF
state of four outputs through the SPI. Incoming message bit
D[3:0] reflects the desired states of the four high-side outputs
(IN_SPI), respectively. A logic [1] enables the corresponding
output switch and a logic [0] turns it OFF.
Each output can be configured to different levels. In addition
to protecting the device, this slow blow fuse emulation feature
can be used to optimize the load requirements matching system
characteristics. Bits D2–D0 set the overcurrent low detection
level to one of eight possible levels, as shown in Table 4,
page 19. Bit D3 sets the overcurrent high detection level to one
of two levels, as outlined in Table 5, page 19.
Address x1001—Output Control Register (OCR1)
Incoming message bit D[3:0] reflects the desired channel
that will be mirrored on the Current Sense (CSNS) terminal. A
logic [1] on message bit D[3:0] enables the CSNS terminal for
the outputs HS3–HS0, respectively. In the event that the
current sense is enabled for multiple outputs, the current will be
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A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent
Table 4. Overcurrent Low Detection Levels
Overcurrent Low
low detection feature. When disabled, there is no timeout for
the selected output and the overcurrent low detection feature is
disabled.
SOCL2_s* SOCL1_s* SOCL0_s*
Detection (Amperes)
(D2)
(D1)
(D0)
HS0 to HS3
9.1
A logic [1] on bit D3 (OL_DIS_s) disables the open load (OL)
detection feature for the channel corresponding to the state of
bits D12–D11.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8.15
7.2
Address A1A0100—Direct Input Control Register (DICR)
6.25
5.25
4.3
The DICR register is used by the MCU to enable, disable, or
configure the direct IN terminal control of each output. Each
output is independently selected for configuration based on the
state bits D12–D11 (refer to Table 3, page 18).
3.35
2.4
For the selected output, a logic [0] on bit D1 (DIR_DIS_s)
will enable the output for direct control. A logic [1] on bit D1 will
disable the output from direct control.
* “_s” refers to the channel, which is selected through bits D12–D11;
refer to Table 3, page 18.
While addressing this register, if the Input was enabled for
direct control, a logic [1] for the D0 (A/O_s) bit will result in a
Boolean AND of the IN terminal with its corresponding IN_SPI
D[4:0] message bit when addressing OCR0. Similarly, a logic
[0] on the D0 terminal results in a Boolean OR of the IN terminal
to the corresponding message bits when addressing the
OCR0. This register is especially useful if several loads are
required to be independently PWM controlled. For example,
the IN terminals of several devices can be configured to
operate all of the outputs with one PWM output from the MCU.
If each output is then configured to be Boolean ANDed to its
respective IN terminal, each output can be individually turned
OFF by SPI while controlling all of the outputs, commanded on
with the single PWM output.
Table 5. Overcurrent High
Detection Levels
Overcurrent High
SOCH_s*
(D3)
Detection (Amperes)
HS0 to HS3
0
1
50
35
* “_s” refers to the channel, which is
selected through bits D12–D11; refer to
Table 3, page 18.
A logic [1] on bit D2 (CSNS_high_s) is used to select the
high ratio on the CSNS terminal for the selected output. The
default value [0] is used to select the low ratio (Table 7).
Address A1A0011—Current Detection Time and Open
Load Register (CDTOLR)
Table 7. Current Sense Ratio
The CDTOLR register is used by the MCU to determine the
amount of time the device will allow an overcurrent low
condition before an output latches OFF. Each output is
independently selected for configuration based on A1A0, which
Current Sense Ratio
CSNS_high_s* (D2)
HS0 to HS3
0
1
1/6500
are the state of the D12–D11 bits (refer to Table 3, page 18).
1/20000
Bits D1–D0 (OCLT[1:0]_s) allow the MCU to select one of
four overcurrent fault blanking times defined in Table 6. Note
that these timeouts apply only to the overcurrent low detection
levels. If the selected overcurrent high level is reached, the
device will latch off within 20 µs.
* “_s” refers to the channel, which is selected
through bits D12–D11; refer to Table 3, page 18.
A logic [1] on bit D3 (FAST_SR_s) is used to select the high
speed slew rate for the selected output, the default value [0]
corresponds to the low speed slew rate
Table 6. Overcurrent Low Detection
Blanking Time
Address x0101—Undervoltage/Overvoltage Register
Timing
155 ms
620 ms
75 ms
OCLT[1:0]_s*
(UOVR)
00
01
10
11
The UOVR register disables the undervoltage (D1) and/or
overvoltage (D0) protection. When these two bits are [0], the
under- and overvoltage are active (default value).
150 µs
* “_s” refers to the channel, which is selected through
bits D12–D11; refer to Table 3, page 18.
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Address x1101— Watchdog Register (WDR)
SO data will represent information ranging from fault status
to register contents, user selected by writing to the STATR bits
OD4, OD3, OD2, OD1, and OD0. The value of the previous bits
SOA4 and SOA3 will determine which output the SO
The WDR register is used by the MCU to configure the
Watchdog timeout. The Watchdog timeout is configured using
bits D1 and D0. When D1 and D0 bits are programmed for the
desired watchdog timeout period (Table 8), the WDSPI bit
should be toggled as well, ensuring the new timeout period is
programmed at the beginning of a new count sequence.
information applies to for the registers which are output specific;
viz., Fault, SOCHLR, CDTOLR, and DICR registers.
Note that the SO data will continue to reflect the information
for each output (depending on the previous OD4, OD3 state)
that was selected during the most recent STATR write until
changed with an updated STATR write.
Table 8. Watchdog Timeout
WD[1:0] (D1, D0)
Timing (ms)
620
The output status register correctly reflects the status of the
STATR-selected register data at the time that the CS is pulled
to a logic [0] during SPI communication, and/or for the period of
time since the last valid SPI communication, with the following
exceptions:
00
01
10
11
310
2500
1250
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an under-
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following an undervoltage VPWR condition should be
ignored.
• The RST terminal transition from a logic [0] to [1] while the
WAKE terminal is at logic [0] may result in incorrect data
loaded into the Status register. The SO data transmitted
to the MCU during the first SPI communication following
this condition should be ignored.
Address xx110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy-chain SPI configuration. This would allow
devices to be unaffected by commands being clocked over a
daisy-chained SPI configuration. By toggling the WD bit (D15)
the watchdog circuitry would continue to be reset while no
programming or data read back functions are being requested
from the device.
Address xx111—TEST
The TEST register is reserved for test and is not accessible
with SPI during normal operation.
Serial Output Bit Assignment
Serial Output Communication (Device Status Return
Data)
When the CS terminal is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB- (OD15-) first
as the new message data is clocked into the SI terminal. The
first sixteen bits of data clocking out of the SO, and following a
CS transition, is dependent upon the previously written SPI
word.
The 16 bits of serial output data depend on the previous
serial input message, as explained in the following paragraphs.
Table 9, page 21, summarizes SO returned data for bits OD15
through OD0.
• Bit OD15 is the MSB; it reflects the state of the Watchdog
bit from the previously clocked-in message.
• Bit OD14 remains logic [0] except when an undervoltage
condition occurred.
• Bit OD13 remains logic [0] except when an overvoltage
condition occurred.
Any bits clocked out of the Serial Output (SO) terminal after
the first 16 bits will be representative of the initial message bits
clocked into the SI terminal since the CS terminal first
transitioned to a logic [0]. This feature is useful for daisy
chaining devices as well as message verification.
• Bits OD[12:8] reflect the state of the bits SOA[4:0] from the
previously clocked in message.
• Bits OD[7:4] give the fault status flag of the outputs HS3,
HS2, HS1, and HS0, respectively.
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the data
is latched into the appropriate registers. A valid message length
is a multiple of 16 bits. At this time, the SO terminal is tri-stated
and the fault status register is now able to accept new fault
status information.
• The contents of bits OD[3:0] depend on bits D[4:0] from
the most recent STATR command SOA[4:0] as explained
in the paragraphs following the table.
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Table 9. Serial Output Bit Map Description
SO Returned Data
Previous STATR
SO SO SO SO SO
A4 A3 A2 A1 A0
OD OD OD OD OD OD
OD9 OD8 OD7 OD6 OD5 OD4
OD3
OD2
OD1
OD0
15
14
13
12
11
10
WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0
A
A
OTF_s
OCHF_s
OCLF_s
IN_SPI1
OLF_s
0
0
0
0
0
0
0
1
0
1
1
0
1
0
WDIN UVF
WDIN UVF
WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST2
ST2
ST1
ST1
ST1
ST0
ST0
ST0
x
0
IN_SPI3
CSNS EN3
SOCH_s
IN_SPI2
CSNS EN2
SOCL2_s
IN_SPI0
x
1
CSNS EN1 CSNS EN0
A
A
SOCL1_s
OCLT1_s
SOCL0_s
OCLT0_s
A/O_s
1
1
1
0
0
0
WDIN UVF
WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST2
ST1
ST1
ST0
ST0
A
A
A
A
OL_DIS_s
OCL_DIS_s
0
1
1
Fast_SR_s CSNS_high_s DIR_DIS_s
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
WDIN UVF
WDIN UVF
WDIN UVF
WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST2
ST2
ST2
ST1
ST1
ST1
ST1
ST0
ST0
ST0
ST0
x
0
–
–
UV_DIS
WD1
OV_DIS
WD0
x
x
x
1
0
1
–
WDTO
HS0_failsaf
IN2
HS2_failsaf
IN3
WD_en
IN1
WAKE
IN0
x=Don’t care.
s=Output selection with the bits A A as defined in Table 3, page 18.
1
0
Previous Address SOA[4:0]=A1A0000
Previous Address SOA[4:0]=A1A0011
The bits OD[3:0] will reflect the current state of the Fault
Register (FLTR) corresponding to the output previously
selected with the bits A1A0 (Table 10).
The returned data contains the programmed values in the
CDTOLR register for the output selected with A1A0.
Previous Address SOA[4:0]=A1A0100
Table 10. Channel-Specific Fault Register
The returned data contains the programmed values in the
DICR register for the output selected with A1A0.
OD3
OD2
OD1
OD0
OTF_s
OCHF_s
OCLF_s
OLF_s
s=Selection of the output.
Previous Address SOA[4:0]=A1A0101
The returned data contains the programmed values in the
UOVR register.
Note The FS terminal reports all faults. For latched faults,
this terminal is reset by a new Switch ON command (via SPI or
direct input IN).
Previous Address SOA[4:0]=x1101
Previous Address SOA[4:0]=x0001
The returned data contains the programmed values in the
WDR register. Bit OD2 (WDTO) reflects the status of the
watchdog circuitry. If WDTO bit is [1], the watchdog has timed
out and the device is in Fail-Safe mode. IF WDTO is [0], the
device is in Normal mode (assuming the device is powered and
not in the Sleep mode), with the watchdog either enabled or
disabled.
Data in bits OD[3:0] contains IN_SPI[3:0]-programmed bits
for channel from HS3 to HS0, respectively.
Previous Address SOA[4:0]=x1001
Data in bits OD[3:0] contains the programmed CSNS EN[3:0]
bits for channels HS3 to HS0, respectively.
Previous Address SOA[4:0]=x0110
Previous Address SOA[4:0]=A1A0010
The returned data OD3 and OD2 contain the state of the
outputs HS2 and HS0, respectively, in case of Fail-Safe state.
This information is stated with the external resistance placed at
the FSI terminal. OD1 indicates if the watchdog is enabled or
not. OD0 returns the state of the WAKE terminal.
Data returned in bits OD[3:0] are programmed current values
for the overcurrent high detection level (refer to Table 5,
page 19) and the overcurrent low detection level (refer to
Table 4, page 19), corresponding to the output previously
selected with A1A0.
Previous Address SOA[4:0]=x1110
The returned data OD[3:0] reflects the state of the direct
terminals IN3 to IN0, respectively.
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MODES OF OPERATION
The 33894 has four operating modes. They are Sleep,
Fail-Safe Mode
Normal, Fault, and Fail-Safe. Table 11 summarizes details
contained in succeeding paragraphs.
Fail-Safe Mode and Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input terminal
transitions from logic [0] to [1]. The WAKE input is capable of
being pulled up to VPWR with a series of limiting resistance
limiting the internal clamp current according to the specification.
Table 11. Fail-Safe Operation and Transitions
to Other 33894 Modes
Mode
Sleep
FS Wake RST WDTO
Comments
x
0
0
x
Device is in Sleep mode. All
outputs are OFF
The Watchdog timeout is a multiple of an internal oscillator
and is specified in the Table 8, page 20. As long as the WD bit
(D15) of an incoming SPI message is toggled within the
minimum watchdog timeout period (WDTO), based on the
programmed value of the WDR, the device will operate
normally. If an internal watchdog timeout occurs before the WD
bit, the device will revert to a Fail-Safe mode until the device is
reinitialized.
Normal
Fault
1
x
1
No
Normal mode. Watchdog is
active if enabled.
0
0
0
1
1
1
1
1
x
0
1
1
1
0
1
1
1
0
Device is currently in fault
mode. The faulted output(s) is
(are) OFF.
No
Watchdog has timed out and
the device is in Fail-Safe
Mode. The outputs are as
configured with the RFS
resistor connected to FSI.
RST and WAKE must be
transitioned to logic [0]
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI pin,
regardless of the state of the various direct inputs and modes
(Table 12).
Fail-
Safe
Yes
simultaneously to bring the
device out of the Fail-safe
mode or momentarily tied the
FSI pin to ground.
Table 12. Output State During
Fail-Safe Mode
RFS (kΩ)
High-Side State
Fail-Safe Mode Disabled
All HS OFF
0
x = Don’t care.
6.0
15
HS0 ON
HS[1:3] OFF
Sleep Mode
The Default mode of the 33894 is the Sleep mode. This is the
30
HS0 and HS2 ON
HS1 and HS3 OFF
state of the device after first applying battery voltage (VPWR
)
prior to any I/O transitions. This is also the state of the device
when the WAKE and RST are both logic [0]. In the Sleep mode,
the output and all unused internal circuitry, such as the internal
5.0 V regulator, are off to minimize current draw. In addition, all
SPI-configurable features of the device are as if set to logic [0].
The 33894 will transition to the Normal or Fail-Safe operating
modes based on the WAKE and RST inputs as defined in
Table 11.
In the Fail-Safe mode, the SPI register content is retained
except for overcurrent high and low detection levels and timing,
which are reset to their default value (SOCL, SOCH, and
OCTL). Then the watchdog, overvoltage, overtemperature, and
overcurrent circuitry (with default value) are fully operational.
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is logic [1] when the
device is in Fail-Safe mode. The device can be brought out of
the Fail-Safe mode by transitioning the WAKE and RST pins
from logic [1] to logic [0] or forcing the FSI pin to logic [0].
Table 11 summarizes the various methods for resetting the
device from the latched Fail-Safe mode.
Normal Mode
The 33894 is in Normal mode when:
• VPWR is within the normal voltage range.
RST terminal is logic [1].
• No fault has occurred.
•
If the FSI pin is tied to GND, the Watchdog Fail-Safe
operation is disabled.
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Loss of VDD
level then returns above 5.75 V, the 33894 can be returned to
the state that it was in prior to the low VPWR excursion. Once
the output latches OFF, the outputs must be turned OFF and
ON again to re-enable them. In the case IN[1:0]=0, this fault is
non-latched.
If the external 5.0 V supply is not within specification, or
even disconnected, all register content is reset. The outputs
can still be driven by the direct inputs IN[0:3]. The 33894 uses
the battery input to power the output MOSFET-related current
sense circuitry and any other internal logic providing fail-safe
device operation with no VDD supplied. In this state, the
watchdog, overvoltage, overtemperature, and overcurrent
circuitry are fully operational with default values.
The undervoltage protection can be disabled through SPI
(bit UV_DIS). When disabled, the returned SO bit OD14 still
reflects any undervoltage condition (undervoltage warning).
Open Load Fault (Non-Latching)
Fault Mode
The 33894 incorporates open load detection circuitry on the
output. Output open load fault (OLF) is detected and reported
as a fault condition when the output is disabled (OFF). The
open load fault is detected and latched into the status register
after the internal gate voltage is pulled low enough to turn OFF
the output. The OLF fault bit is set in the status register. If the
open load fault is removed, the status register will be cleared
after reading the register.
This 33894 indicates the faults below as they occur by
driving the FS terminal to [0]:
• Overtemperature fault
• Overvoltage and undervoltage fault
• Open load fault
• Overcurrent fault (high and low)
The open load protection can be disabled trough SPI (bit
OL_DIS).
The FS terminal will automatically return to [1] when the fault
condition is removed, except for overcurrent and in some
cases undervoltage.
Overcurrent Fault (Latching)
Fault information is retained in the fault register and is
available (and reset) via the SO terminal during the first valid
SPI communication (refer to Table 10, page 21).
The 33894 has eight programmable overcurrent low
detection levels (IOCL) and two programmable overcurrent high
detection levels (IOCH) for maximum device protection. The
Overtemperature Fault (Non-Latching)
two selectable, simultaneously active overcurrent detection
levels, defined by IOCH and IOCL, are illustrated in Figure 4,
The 33894 incorporates overtemperature detection and
shutdown circuitry in the output structure. Overtemperature
detection is enabled when the output is in the ON state.
page 14. The eight different overcurrent low detect levels
(IOCL0, IOCL1, IOCL2, IOCL3, IOCL4, IOCL5, IOCL6, and IOCL7) are
illustrated in Figure 4.
For the output, an overtemperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely
until action is taken by the MCU to shut OFF the output, or until
the offending load is removed.
If the load current level ever reaches the selected
overcurrent low detection level and the overcurrent condition
exceeds the programmed overcurrent time period (tOC ), the
x
device will latch the output OFF.
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF
When experiencing this fault, the OTF fault bit will be set in
the status register and cleared after either a valid SPI read or
a power reset of the device.
the output, regardless of the selected tOCL driver.
x
For both cases, the device output will stay off indefinitely
until the device is commanded OFF and then ON again.
Overvoltage Fault (Non-Latching)
The 33894 shuts down the output during an overvoltage
fault (OVF) condition on the VPWR terminal. The output
remains in the OFF state until the overvoltage condition is
removed. When experiencing this fault, the OVF fault bit is set
in the bit D1 and cleared after either a valid SPI read or a power
reset of the device.
Reverse Battery
The output survives the application of reverse voltage as
low as -16 V. Under these conditions, the output’s gate is
enhanced to keep the junction temperature less than 150°C.
The ON resistance of the output is fairly similar to that in the
Normal mode. No additional passive components are required.
The overvoltage protection can be disabled through SPI (bit
OV_DIS). When disabled, the returned SO bit OD13 still
reflects any overvoltage condition (overvoltage warning).
Ground Disconnect Protection
Undervoltage Shutdown (Latching or Non-Latching)
In the event the 33894 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless of the state of the output at the time of
disconnection.
The output latches OFF at some battery voltage between
4.75 V and 5.75 V. As long as the VDD level stays within the
normal specified range, the internal logic states within the
device will be sustained. This ensures that when the battery
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PACKAGE DIMENSIONS
PNC SUFFIX
24-TERMINAL POWER QFN
NON-LEADED PACKAGE
CASE 1558-02
ISSUE A
SHEET 1 OF 2
10
A
DETAIL G
M
5
2X
10
2
1
0.1 C
11
13
24
22
5
14
21
10
PIN 1
INDEX AREA
17
18
19
20
M
2X
B
0.1 C
PIN NUMBER
REF. ONLY
5.85
PIN NUMBER
REF. ONLY
4.95
4.65
VIEW A
0.1
C
A B
1
2
10
24
22
11
2X 0.65
3.2
13
14
3.0
2.7
15
0.1
C
A
B
2.525
21
1.375
2.45
2.05
4.45
4.05
16
0.1
C A B
(0.25)
(0.25)
2.3
2X 1.43
0.93
2X 1.8
20
19
18
17
(0.1)
(1.25)
0.5
(0.25)
(0.75)
2X 1.3
0.8
(0.25)
NOTES:
(0.25)
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2.2
2X1.8
0.1
C
A B
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
4. COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
5. METAL PADS CONNECTED TO THE GND.
6. MINIMUM METAL GAP SHOULD BE 0.25MM.
1.65
7.2
6.8
2X
1.35
0.1
C A B
0.1
C A B
9.70
9.30
0.1
C A B
VIEW M M
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PNC SUFFIX
24-TERMINAL POWER QFN
NON-LEADED PACKAGE
CASE 1558-02
ISSUE A
SHEET 2 OF 2
0.1 C
2.20
1.95
2.2
2.0
4
0.05 C
0.05
0.00
(0.65)
DETAIL G
SEATING
PLANE
(0.4)
C
VIEW ROTATED 90˚ CW
3.5
1.20
0.95
2X
0.47
16X 0.33
0.1
9X 0.65
0.325
M
C A B
1.20
0.95
6X
M
C
0.05
(0.05)
10
(0.2)
0.90
0.65
11
8X
0.3 0.2
5
X0.3 0.2
0.1
C
A
B
3.025
2 PLACES
5
0.25 0.2
X0.25 0.2
0.1
2.5
C
A B
2 PLACES
1.8
1.3
2.0
1.6
1.0
0.6
(0.25)
2.8
2.6
0.6
0.2
2 PLACES
VIEW A
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NOTES
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NOTES
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