CP3263,512_技术文档

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

4 kB/8 kB 3 V Flash with 256-byte data RAM

Rev. 05 — 15 December 2004

Product data

1. General description

The P89LPC930/931 are single-chip microcontrollers designed for applications

demanding high-integration, low cost solutions over a wide range of performance

requirements. The P89LPC930/931 is based on a high performance processor

architecture that executes instructions in two to four clocks, six times the rate of

standard 80C51 devices. Many system-level functions have been incorporated into

the P89LPC930/931 in order to reduce component count, board space, and system

cost.

2. Features

■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to

222 ns for all instructions except multiply and divide when executing at 18 MHz.

This is 6 times the performance of the standard 80C51 running at the same clock

frequency. A lower clock frequency for the same performance results in power

savings and reduced EMI.

■ 2.4 V to 3.6 V V_DDoperating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

■ 4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.

■ Byte-erase allowing code memory to be used for data storage.

■ Flash program operation completes in 2 ms.

■ Flash erase operation completes in 2 ms.

■ 256-byte RAM data memory.

■ Two 16-bit counter/timers. Each timer may be conﬁgured to toggle a port output

upon timer overﬂow or to become a PWM output.

■ Real-Time clock that can also be used as a system timer.

■ Two analog comparators with selectable inputs and reference source.

■ Enhanced UART with fractional baud rate generator, break detect, framing error

detection, automatic address detection and versatile interrupt capabilities.

■ 400 kHz byte-wide I²C-bus communication port.

■ SPI communication port.

■ Eight keypad interrupt inputs, plus two additional external interrupt inputs.

■ Four interrupt priority levels.

■ Watchdog timer with separate on-chip oscillator, requiring no external

components. The Watchdog time-out time is selectable from 8 values.

■ Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A reset counter and reset glitch suppression circuitry prevent

spurious and incomplete resets. A software reset function is also available.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

■ Low voltage reset (Brownout detect) allows a graceful system shutdown when

power fails. May optionally be conﬁgured as an interrupt.

■ Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator

allowing it to perform an oscillator fail detect function.

■ Conﬁgurable on-chip oscillator with frequency range and RC oscillator options

(selected by user programmed Flash conﬁguration bits). The RC oscillator (factory

calibrated to ±1 %) option allows operation without external oscillator

components. Oscillator options support frequencies from 20 kHz to the maximum

operating frequency of 18 MHz. The RC oscillator option is selectable and ﬁne

tunable.

■ Programmable port output conﬁguration options:

◆ Quasi-bidirectional

◆ Open drain

◆ Push-pull

◆ Input-only

■ Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value

of the pins match or do not match a programmable pattern.

■ Second data pointer.

■ Schmitt trigger port inputs.

■ LED drive capability (20 mA) on all port pins. Maximum combined I/O current of

100 mA.

■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately

10 ns minimum ramp times.

■ 23 I/O pins minimum (28-pin package). Up to 26 I/O pins while using on-chip

oscillator and reset options.

■ Only power and ground connections are required to operate the P89LPC930/931

using on-chip oscillator and on-chip reset options.

■ Serial Flash programming allows in-circuit production coding. Flash security bits

prevent reading of sensitive programs.

■ In-Application Programming of the Flash code memory. This allows changing the

code in a running application.

■ Idle and two different Power-down reduced power modes. Improved wake-up from

Power-down mode (a low interrupt input starts execution). Typical Power-down

current is 1 µA (total Power-down with voltage comparators disabled).

■ 28-pin TSSOP package.

■ Emulation support.

9397 750 14472

Product data

Rev. 05 — 15 December 2004

2 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

P89LPC930FDH

P89LPC931FDH

TSSOP28 plastic thin shrink small outline package;

28 leads; body width 4.4 mm

SOT361-1

TSSOP28 plastic thin shrink small outline package;

28 leads; body width 4.4 mm

SOT361-1

3.1 Ordering options

Table 2:

Part options

Type number

Program memory Temperature range

Frequency

P89LPC930FDH

P89LPC931FDH

4 kB

8 kB

−45 °C to +85 °C

0 MHz to 18 MHz

9397 750 14472

Product data

Rev. 05 — 15 December 2004

3 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

4. Block diagram

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

4 kB/8 kB

CODE FLASH

UART

INTERNAL BUS

256-BYTE

DATA RAM

2

I C

PORT 3

CONFIGURABLE I/Os

SPI

PORT 2

CONFIGURABLE I/Os

REAL-TIME CLOCK/

SYSTEM TIMER

PORT 1

CONFIGURABLE I/Os

TIMER 0

TIMER 1

PORT 0

CONFIGURABLE I/Os

WATCHDOG TIMER

AND OSCILLATOR

KEYPAD

INTERRUPT

ANALOG

COMPARATORS

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

CLOCK

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

CRYSTAL

OR

RESONATOR

ON-CHIP

RC

OSCILLATOR

CONFIGURABLE

OSCILLATOR

002aaa428

Fig 1. Block diagram.

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Product data

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

5. Pinning information

5.1 Pinning

handbook, halfpage

P2.0

P2.1

1

2

3

4

5

6

7

8

9

28 P2.7

27 P2.6

KBIO/CMP2/P0.0

P1.7

26 P0.1/CIN2B/KBI1

25 P0.2/CIN2A/KBI2

24 P0.3/CIN1B/KBI3

23 P0.4/CIN1A/KBI4

22 P0.5/CMPREF/KBI5

P1.6

RST/P1.5

V

SS

XTAL1/P3.1

21 V

DD

CLKOUT/XTAL2/P3.0

20 P0.6/CMP1/KBI6

19 P0.7/T1/KBI7

18 P1.0/TXD

INT1/P1.4 10

SDA/INT0/P1.3 11

SCL/T0/P1.2 12

MOSI/P2.2 13

17 P1.1/RXD

16 P2.5/SPICLK

15 P2.4/SS

MISO/P2.3 14

002aaa429

Fig 2. DIP28 pin conﬁguration.

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Product data

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5 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

5.2 Pin description

Table 3:

Pin description

Symbol

Type

Description

P0.0 - P0.7

3, 26, 25, I/O

24, 23, 22,

20, 19

Port 0: Port 0 is an 8-bit I/O port with a user-conﬁgurable output type. During reset

Port 0 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of Port 0 pins as inputs and outputs depends upon the port

conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section

8.11.1 “Port conﬁgurations” and Table 7 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

P0.0 — Port 0 bit 0.

3

I/O

O

CMP2 — Comparator 2 output.

KBI0 — Keyboard input 0.

I

26

25

24

23

22

20

19

I/O

P0.1 — Port 0 bit 1.

I

CIN2B — Comparator 2 positive input B.

KBI1 — Keyboard input 1.

I

I/O

P0.2 — Port 0 bit 2.

I

CIN2A — Comparator 2 positive input A.

KBI2 — Keyboard input 2.

I

I/O

P0.3 — Port 0 bit 3.

I

CIN1B — Comparator 1 positive input B.

KBI3 — Keyboard input 3.

I

I/O

P0.4 — Port 0 bit 4.

I

CIN1A — Comparator 1 positive input A.

KBI4 — Keyboard input 4.

I

I/O

I

P0.5 — Port 0 bit 5.

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

I

I/O

O

I

P0.6 — Port 0 bit 6.

CMP1 — Comparator 1 output.

KBI6 — Keyboard input 6.

I/O

I

P0.7 — Port 0 bit 7.

T1 — Timer/counter 1 external count input or overﬂow output.

KBI7 — Keyboard input 7.

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6 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Table 3:

Pin description…continued

Pin Type Description

18, 17, 12, I/O, I ^[1]Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable output type, except for

Symbol

P1.0 - P1.7

11, 10, 6,

5, 4

three pins as noted below. During reset Port 1 latches are conﬁgured in the input only

mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins

as inputs and outputs depends upon the port conﬁguration selected. Each of the

conﬁgurable port pins are programmed independently. Refer to Section 8.11.1 “Port

conﬁgurations” and Table 7 “DC electrical characteristics” for details. P1.2 - P1.3 are

open drain when used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P1.0 — Port 1 bit 0.

18

17

12

I/O

O

TxD — Transmitter output for the serial port.

P1.1 — Port 1 bit 1.

I/O

I

RXD — Receiver input for the serial port.

P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O

T0 — Timer/counter 0 external count input or overﬂow output (open-drain when used

as output).

I/O

SCL — I²C serial clock input/output.

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

SDA — I²C serial data input/output.

P1.4 — Port 1 bit 4.

11

I

I/O

10

6

I

INT1 — External interrupt 1 input.

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during Power-on or if selected via UCFG1. When

functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O

ports and peripherals to take on their default states, and the processor begins

execution at address 0. Also used during a power-on sequence to force In-System

Programming mode. When using an oscillator frequency above 12 MHz, the

reset input function of P1.5 must be enabled. An external circuit is required to

hold the device in reset at power-up until V_DDhas reached its speciﬁed level.

When system power is removed V_DDwill fall below the minimum speciﬁed

operating voltage. When using an oscillator frequency above 12 MHz, in some

applications, an external brownout detect circuit may be required to hold the

device in reset when V_DDfalls below the minimum speciﬁed operating voltage.

5

4

I/O

P1.6 — Port 1 bit 6.

P1.7 — Port 1 bit 7.

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Table 3:

Pin description…continued

Symbol

Type

Description

P2.0 - P2.7

1, 2, 13,

14, 15, 16,

27, 28

I/O

Port 2: Port 2 is a 8-bit I/O port with a user-conﬁgurable output type. During reset

Port 2 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of port 2 pins as inputs and outputs depends upon the port

conﬁguration selected. Each port pin is conﬁgured independently. Refer to the

section on I/O port conﬁguration and the DC Electrical Characteristics for details.

This port is not available in 20-pin package and is conﬁgured automatically as

outputs to conserve power. The alternate functions for these pins must not be

enabled.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described below.

P2.0 — Port 2 bit 0.

1

I/O

2

P2.1 — Port 2 bit 1.

13

P2.2 — Port 2 bit 2.

MOSI — SPI master out slave in. When conﬁgured as master, this pin is output,

when conﬁgured as slave, this pin is input.

14

I/O

P2.3 — Port 2 bit 3.

MISO — SPI master in slave out. When conﬁgured as master, this pin is input, when

conﬁgured as slave, this pin is output.

15

16

I/O

I

P2.4 — Port 2 bit 4.

SS — SPI Slave select.

P2.5 — Port 2 bit 5.

I/O

SPICLK — SPI clock. When conﬁgured as master, this pin is output, when

conﬁgured as slave, this pin is input.

27

28

I/O

P2.6 — Port 2 bit 6.

P2.7 — Port 2 bit 7.

9397 750 14472

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Table 3:

Pin description…continued

Symbol

Type

Description

P3.0 - P3.1

9, 8

I/O

Port 3: Port 3 is an 2-bit I/O port with a user-conﬁgurable output type. During reset

Port 3 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of Port 3 pins as inputs and outputs depends upon the port

conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section

8.11.1 “Port conﬁgurations” and Table 7 “DC electrical characteristics” for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

P3.0 — Port 3 bit 0.

9

I/O

O

XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is

selected via the FLASH conﬁguration).

O

CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It

can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or

external clock input, except when XTAL1/XTAL2 are used to generate clock source

for the real time clock/system timer.

8

I/O

I

P3.1 — Port 3 bit 1.

XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

selected via the FLASH conﬁguration). It can be a port pin if internal RC oscillator or

Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not

used to generate the clock for the real time clock/system timer.

V_SS

V_DD

7

I

Ground: 0 V reference.

21

Power Supply: This is the power supply voltage for normal operation as well as Idle

and Power Down modes.

[1] Input/Output for P1.0-P1.4, P1.6, P1.7. Input for P1.5.

9397 750 14472

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

6. Logic symbol

V

SS

DD

KBI0

CMP2

TxD

RxD

T0

INT0

INT1

RST

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

T1

SCL

SDA

CLKOUT

XTAL2

XTAL1

MOSI

MISO

SS

SPICLK

002aaa427

Fig 3. Logic symbol.

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

7. Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following

ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the

SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in

future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

9397 750 14472

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

8. Functional description

Remark: Please refer to the P89LPC930/931 User’s Manual for a more detailed

functional description.

8.1 Enhanced CPU

The P89LPC930/931 uses an enhanced 80C51 CPU which runs at 6 times the speed

of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and

most instructions execute in one or two machine cycles.

8.2 Clocks

8.2.1 Clock deﬁnitions

The P89LPC930/931 device has several internal clocks as deﬁned below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four

clock sources (see Figure 4) and can also be optionally divided to a slower frequency

(see Section 8.7 “CPU CLOCK (CCLK) modiﬁcation: DIVM register”).

Note: f_oscis deﬁned as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per

machine cycle, and most instructions are executed in one to two machine cycles (two

or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is CCLK/2

8.2.2 CPU clock (OSCCLK)

The P89LPC930/931 provides several user-selectable oscillator options in generating

the CPU clock. This allows optimization for a range of needs from high precision to

lowest possible cost. These options are conﬁgured when the FLASH is programmed

and include an on-chip Watchdog oscillator, an on-chip RC oscillator, an oscillator

using an external crystal, or an external clock source. The crystal oscillator can be

optimized for low, medium, or high frequency crystals covering a range from 20 kHz

to 12 MHz.

8.2.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic

resonators are also supported in this conﬁguration.

8.2.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic

resonators are also supported in this conﬁguration.

8.2.5 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic

resonators are also supported in this conﬁguration. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An

external circuit is required to hold the device in reset at power-up until V_DDhas

reached its speciﬁed level. When system power is removed V_DDwill fall below

9397 750 14472

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

the minimum speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when V_DDfalls below the minimum

speciﬁed operating voltage.

8.2.6 Clock output

The P89LPC930/931 supports a user-selectable clock output function on the

XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if

another clock source has been selected (on-chip RC oscillator, Watchdog oscillator,

external clock input on X1) and if the Real-Time clock is not using the crystal

oscillator as its clock source. This allows external devices to synchronize to the

P89LPC930/931. This output is enabled by the ENCLK bit in the TRIM register. The

frequency of this clock output is ¹⁄₂that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.3 On-chip RC oscillator option

The P89LPC930/931 has a 6-bit TRIM register that can be used to tune the

frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory

pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±1% at room

temperature. End-user applications can write to the Trim register to adjust the on-chip

RC oscillator to other frequencies.

8.4 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This

oscillator can be used to save power when a high clock frequency is not needed.

8.5 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving

the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin

may be used as a standard port pin or a clock output. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An

external circuit is required to hold the device in reset at power-up until V_DDhas

reached its speciﬁed level. When system power is removed V_DDwill fall below

the minimum speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when V_DDfalls below the minimum

speciﬁed operating voltage.

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

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XTAL1

XTAL2

High freq.

Med. freq.

Low freq.

RTC

OSCCLK

CCLK

DIVM

CPU

WDT

RC

OSCILLATOR

2

(7.3728 MHz)

WATCHDOG

OSCILLATOR

(400 kHz)

PCLK

TIMER 0 and

TIMER 1

BAUD RATE

GENERATOR

2

SPI

I C

UART

002aaa431

Fig 4. Block diagram of oscillator control.

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

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8.6 CPU CLock (CCLK) wake-up delay

The P89LPC930/931 has an internal wake-up timer that delays the clock until it

stabilizes depending to the clock source used. If the clock source is any of the three

crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK

cycles plus 60 to 100 µs. If the clock source is either the internal RC oscillator,

Watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus

60 to 100 µs.

8.7 CPU CLOCK (CCLK) modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 256 times by conﬁguring a

dividing register, DIVM, to generate CCLK. This feature makes it possible to

temporarily run the CPU at a lower rate, reducing power consumption. By dividing the

clock, the CPU can retain the ability to respond to events that would not exit Idle

mode by executing its normal program at a lower rate. This can also allow bypassing

the oscillator start-up time in cases where Power-down mode would otherwise be

used. The value of DIVM may be changed by the program at any time without

interrupting code execution.

8.8 Low power select

The P89LPC930/931 is designed to run at 18 MHz (CCLK) maximum. However, if

CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the

power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.9 Memory organization

The various P89LPC930/931 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect

addressing, using instruction other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of

the Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and

status registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC930/931 has 4 kB/ 8 kB of on-chip Code memory.

9397 750 14472

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

8.10 Interrupts

The P89LPC930/931 uses a four priority level interrupt structure. This allows great

ﬂexibility in controlling the handling of the many interrupt sources. The

P89LPC930/931 supports 13 interrupt sources: external interrupts 0 and 1, timers 0

and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect,

watchdog/real-time clock, I²C, keyboard, and comparators 1 and 2, and SPI.

Each interrupt source can be individually enabled or disabled by setting or clearing a

bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a

global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt,

but not by another interrupt of the same or lower priority. The highest priority interrupt

service cannot be interrupted by any other interrupt source. If two requests of

different priority levels are pending at the start of an instruction, the request of higher

priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an

internal polling sequence determines which request is serviced. This is called the

arbitration ranking. Note that the arbitration ranking is only used to resolve pending

requests of the same priority level.

8.10.1 External interrupt inputs

The P89LPC930/931 has two external interrupt inputs as well as the Keypad Interrupt

function. The two interrupt inputs are identical to those present on the standard

80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered

by setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode if successive samples of the INTn pin show a HIGH in one

cycle and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set,

causing an interrupt request.

If an external interrupt is enabled when the P89LPC930/931 is put into Power-down

or Idle mode, the interrupt will cause the processor to wake-up and resume operation.

Refer to Section 8.13 “Power reduction modes” for details.

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IE0

EX0

IE1

EX1

BOF

EBO

RTCF

KBIF

EKBI

WAKE-UP

(IF IN POWER-DOWN)

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF2

CMF1

EC

EA (IE0.7)

TF0

ET0

TF1

ET1

TI & RI/RI

ES/ESR

INTERRUPT

TO CPU

TI

EST

SI

EI2C

002aaa432

SPIF

ESPI

Fig 5. Interrupt sources, interrupt enables, and power-down wake-up sources.

8.11 I/O ports

The P89LPC930/931 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1

and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available

depend upon the clock and reset options chosen, as shown in Table 5.

Table 5:

Number of I/O pins available

Clock source

Reset option

Number of I/O pins

(20-pin package)

On-chip oscillator or

Watchdog oscillator

No external reset (except during power-up) 26

External RST pin supported^[1]

25

No external reset (except during power-up) 25

External RST pin supported^[1]

24

No external reset (except during power-up) 24

External clock input

Low/medium/high

speed oscillator

(external crystal or

resonator)

External RST pin supported^[1]

23

[1] Required for operation above 12 MHz.

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8.11.1 Port conﬁgurations

All but three I/O port pins on the P89LPC930/931 may be conﬁgured by software to

one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51

port outputs), push-pull, open drain, and input-only. Two conﬁguration registers for

each port select the output type for each port pin.

P1.5 (RST) can only be an input and cannot be conﬁgured.

P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be conﬁgured to be either input-only or

open-drain.

8.11.2 Quasi-bidirectional output conﬁguration

Quasi-bidirectional outputs can be used as both an input and output without the need

to reconﬁgure the port. This is possible because when the port outputs a logic HIGH,

it is weakly driven, allowing an external device to pull the pin LOW. When the pin is

driven LOW, it is driven strongly and able to sink a fairly large current. These features

are somewhat similar to an open-drain output except that there are three pull-up

transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC930/931 is a 3 V device, but the pins are 5 V-tolerant. In

quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current

ﬂowing from the pin to V_DD, causing extra power consumption. Therefore, applying

5 V in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch

suppression circuit.

8.11.3 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the

pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be

used as a logic output, a port conﬁgured in this manner must have an external

pull-up, typically a resistor tied to V_DD

.

An open-drain port pin has a Schmitt-triggered input that also has a glitch

suppression circuit.

8.11.4 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt-triggered input

that also has a glitch suppression circuit.

8.11.5 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous

strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be

used when more source current is needed from a port output. A push-pull port pin

has a Schmitt-triggered input that also has a glitch suppression circuit.

8.11.6 Port 0 analog functions

The P89LPC930/931 incorporates two Analog Comparators. In order to give the best

analog function performance and to minimize power consumption, pins that are being

used for analog functions must have the digital outputs and digital inputs disabled.

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Digital outputs are disabled by putting the port output into the Input-Only (high

impedance) mode as described in Section 8.11.4.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register,

bits 1:5. On any reset, PT0AD1:5 defaults to ‘0’s to enable digital functions.

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8.11.7 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different

from the LPC76x series of devices.

• After power-up, all I/O pins except P1.5, may be conﬁgured by software.

• Pin P1.5 is input only. Pins P1.2 and P1.3 and are conﬁgurable for either input-only

or open-drain.

Every output on the P89LPC930/931 has been designed to sink typical LED drive

current. However, there is a maximum total output current for all ports which must not

be exceeded. Please refer to Table 7 “DC electrical characteristics” for detailed

speciﬁcations.

All ports pins that can function as an output have slew rate controlled outputs to limit

noise generated by quickly switching output signals. The slew rate is factory-set to

approximately 10 ns rise and fall times.

8.12 Power monitoring functions

The P89LPC930/931 incorporates power monitoring functions designed to prevent

incorrect operation during initial power-up and power loss or reduction during

operation. This is accomplished with two hardware functions: Power-on Detect and

Brownout detect.

8.12.1 Brownout detection

The Brownout detect function determines if the power supply voltage drops below a

certain level. The default operation is for a Brownout detection to cause a processor

reset, however it may alternatively be conﬁgured to generate an interrupt.

Brownout detection may be enabled or disabled in software.

If Brownout detection is enabled, the brownout condition occurs when V_DDfalls below

the brownout trip voltage, V_BO(see Table 7 “DC electrical characteristics”), and is

negated when V_DDrises above V_BO. If the P89LPC930/931 device is to operate with

a power supply that can be below 2.7 V, BOE should be left in the unprogrammed

state so that the device can operate at 2.4 V, otherwise continuous brownout reset

may prevent the device from operating.

For correct activation of Brownout detect, the V_DDrise and fall times must be

observed. Please see Table 7 “DC electrical characteristics” for speciﬁcations.

8.12.2 Power-on detection

The Power-on Detect has a function similar to the Brownout detect, but is designed to

work as power comes up initially, before the power supply voltage reaches a level

where Brownout detect can work. The POF ﬂag in the RSTSRC register is set to

indicate an initial power-up condition. The POF ﬂag will remain set until cleared by

software.

8.13 Power reduction modes

The P89LPC930/931 supports three different power reduction modes. These modes

are Idle mode, Power-down mode, and total Power-down mode.

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8.13.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor

when an interrupt is generated. Any enabled interrupt source or reset may terminate

Idle mode.

8.13.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption.

The P89LPC930/931 exits Power-down mode via any reset, or certain interrupts. In

Power-down mode, the power supply voltage may be reduced to the RAM keep-alive

voltage V_RAM. This retains the RAM contents at the point where Power-down mode

was entered. SFR contents are not guaranteed after V_DDhas been lowered to V_RAM

therefore it is highly recommended to wake up the processor via reset in this case.

V_DDmust be raised to within the operating range before the Power-down mode is

exited.

,

Some chip functions continue to operate and draw power during Power-down mode,

increasing the total power used during Power-down. These include: Brownout detect,

Watchdog Timer, Comparators (note that Comparators can be powered-down

separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is

disabled unless both the RC oscillator has been selected as the system clock and the

RTC is enabled.

8.13.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry

and the voltage comparators are also disabled to conserve additional power. The

internal RC oscillator is disabled unless both the RC oscillator has been selected as

the system clock and the RTC is enabled. If the internal RC oscillator is used to clock

the RTC during Power-down, there will be high power consumption. Please use an

external low frequency clock to achieve low power with the Real-Time Clock running

during Power-down.

8.14 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital

input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the

external reset input function on P1.5. When cleared, P1.5 may be used as an input

pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin

will always function as a reset input. An external circuit connected to this pin

should not hold this pin LOW during a power-on sequence as this will keep the

device in reset. After power-up this input will function either as an external reset

input or as a digital input as deﬁned by the RPE bit. Only a power-up reset will

temporarily override the selection deﬁned by RPE bit. Other sources of reset will not

override the RPE bit.

Remark: During a power cycle, V_DDmust fall below V_POR(see Table 7 “DC electrical

characteristics” on page 42) before power is reapplied, in order to ensure a power-on

reset.

Reset can be triggered from the following sources:

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• External reset pin (during power-up or if user conﬁgured via UCFG1. This option

must be used for an oscillator frequency above 12 MHz.)

• Power-on detect

• Brownout detect

• Watchdog Timer

• Software reset

• UART break character detect reset

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can

read this register to determine the most recent reset source. These ﬂag bits can be

cleared in software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit

may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain

set.

8.14.1 Reset vector

Following reset, the P89LPC930/931 will fetch instructions from either address 0000h

or the Boot address. The Boot address is formed by using the Boot Vector as the high

byte of the address and the low byte of the address = 00h.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot

Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on

(see P89LPC930/931 User’s Manual). Otherwise, instructions will be fetched from

address 0000H.

8.15 Timers/counters 0 and 1

The P89LPC930/931 has two general purpose counter/timers which are upward

compatible with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to

operate either as timers or event counter. An option to automatically toggle the T0

and/or T1 pins upon timer overﬂow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition

at its corresponding external input pin, T0 or T1. In this function, the external input is

sampled once during every machine cycle.

Timer 0 and Timer 1 have ﬁve operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1,

2 and 6 are the same for both Timers/Counters. Mode 3 is different.

8.15.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured

as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

8.15.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

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8.15.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload.

Mode 2 operation is the same for Timer 0 and Timer 1.

8.15.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit

counters and is provided for applications that require an extra 8-bit timer. When

Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

8.15.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

8.15.6 Timer overﬂow toggle output

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a

timer overﬂow occurs. The same device pins that are used for the T0 and T1 count

inputs are also used for the timer toggle outputs. The port outputs will be a logic ‘1’

prior to the ﬁrst timer overﬂow when this mode is turned on.

8.16 Real-Time clock/system timer

The P89LPC930/931 has a simple Real-Time clock that allows a user to continue

running an accurate timer while the rest of the device is powered-down. The

Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a

23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down

counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF

ﬂag will be set. The clock source for this counter can be either the CPU clock (CCLK)

or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU

clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as

its clock source. Only power-on reset will reset the Real-Time clock and its

associated SFRs to the default state.

8.17 UART

The P89LPC930/931 has an enhanced UART that is compatible with the

conventional 80C51 UART except that Timer 2 overﬂow cannot be used as a baud

rate source. The P89LPC930/931 does include an independent Baud Rate

Generator. The baud rate can be selected from the oscillator (divided by a constant),

Timer 1 overﬂow, or the independent Baud Rate Generator. In addition to the baud

rate generation, enhancements over the standard 80C51 UART include Framing

Error detection, automatic address recognition, selectable double buffering and

several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit

UART, 9-bit UART, and CPU clock/32 or CPU clock/16.

8.17.1 Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at ¹⁄₁₆of the CPU clock

frequency.

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8.17.2 Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logic ‘0’),

8 data bits (LSB ﬁrst), and a stop bit (logic ‘1’). When data is received, the stop bit is

stored in RB8 in Special Function Register SCON. The baud rate is variable and is

determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in

Section 8.17.5 “Baud rate generator and selection”).

8.17.3 Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logic ‘0’),

8 data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logic ‘1’). When

data is transmitted, the 9^thdata bit (TB8 in SCON) can be assigned the value of ‘0’ or

‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When

data is received, the 9^thdata bit goes into RB8 in Special Function Register SCON,

while the stop bit is not saved. The baud rate is programmable to either ¹⁄₁₆or ¹⁄₃₂of

the CPU clock frequency, as determined by the SMOD1 bit in PCON.

8.17.4 Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit (logic ‘0’),

8 data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logic ‘1’). In fact,

Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in

Mode 3 is variable and is determined by the Timer 1 overﬂow rate or the Baud Rate

Generator (described in section Section 8.17.5 “Baud rate generator and selection”).

8.17.5 Baud rate generator and selection

The P89LPC930/931 enhanced UART has an independent Baud Rate Generator.

The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and

BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a

similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for

other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 6).

Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent Baud Rate Generator uses OSCCLK.

SMOD1 = 1

SBRGS = 0

SBRGS = 1

Timer 1 Overflow

(PCLK-based)

2

Baud Rate Modes 1 and 3

SMOD1 = 0

Baud Rate Generator

(CCLK-based)

002aaa419

Fig 6. Baud rate sources for UART (Modes 1, 3).

8.17.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0

(PCON.6) is ‘1’, framing errors can be made available in SCON.7 respectively. If

SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)

are set up when SMOD0 is ‘0’.

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8.17.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the

device and force the device into ISP mode.

8.17.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to

be written to SBUF while the ﬁrst character is being transmitted. Double buffering

allows transmission of a string of characters with only one stop bit between any two

characters, as long as the next character is written between the start bit and the stop

bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART

is compatible with the conventional 80C51 UART. If enabled, the UART allows writing

to SnBUF while the previous data is being shifted out. Double buffering is only

allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be

disabled (DBMOD = ‘0’).

8.17.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated

when the double buffer is ready to receive new data.

8.17.10 The 9^thbit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as

long as TB8 is updated some time before that bit is shifted out. TB8 must not be

changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8

will be double-buffered together with SBUF data.

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8.18 I²C-bus serial interface

I²C-bus uses two wires (SDA and SCL) to transfer information between devices

connected to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves.

• Multimaster bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of

serial data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate

via one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend

and resume serial transfer.

• The I²C-bus may be used for test and diagnostic purposes.

A typical I²C-bus conﬁguration is shown in Figure 7. The P89LPC930/931 device

provides a byte-oriented I²C-bus interface that supports data transfers up to 400 kHz.

R

P

SDA

SCL

2

I C-BUS

P1.3/SDA

P1.2/SCL

OTHER DEVICE

WITH I C-BUS

INTERFACE

OTHER DEVICE

WITH I C-BUS

INTERFACE

2

P89LPC930/931

002aaa433

Fig 7. I²C-bus conﬁguration.

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8

I2ADR

ADDRESS REGISTER

COMPARATOR

P1.3

INPUT

FILTER

P1.3/SDA

SHIFT REGISTER

8

ACK

I2DAT

OUTPUT

STAGE

BIT COUNTER /

ARBITRATION &

SYNC LOGIC

CCLK

INPUT

FILTER

TIMING

&

CONTROL

LOGIC

P1.2/SCL

SERIAL CLOCK

GENERATOR

OUTPUT

STAGE

INTERRUPT

TIMER 1

OVERFLOW

I2CON

I2SCLH

I2SCLL

P1.2

CONTROL REGISTERS &

SCL DUTY CYCLE REGISTERS

8

STATUS

DECODER

STATUS BUS

I2STAT

STATUS REGISTER

8

002aaa421

Fig 8. I²C-bus serial interface block diagram.

8.19 Serial Peripheral Interface (SPI)

LPC930/931 provides another high-speed serial communication interface - the SPI

interface. SPI is a full-duplex, high-speed, synchronous communication bus with two

operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported

in Master or 3.0 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write

Collision Flag Protection.

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S

M

MISO

P2.3

CPU clock

M

S

8-BIT SHIFT REGISTER

READ DATA BUFFER

MOSI

P2.2

DIVIDER

BY 4, 16, 64, 128

SPICLK

P2.5

clock

SPI clock (master)

S

M

SELECT

SS

P2.4

CLOCK LOGIC

MSTR

SPEN

SPI CONTROL

SPI CONTROL REGISTER

SPI STATUS REGISTER

SPI

interrupt

request

internal

data

bus

002aaa434

Fig 9. SPI block diagram.

The SPI interface has four pins: SPICLK, MOSI, MISO, and SS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and

ﬂows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal

is output in the master mode and is input in the slave mode. If the SPI system is

disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port

functions.

• SS is the optional slave select pin. In a typical conﬁguration, an SPI master asserts

one of its port pins to select one SPI device as the current slave. An SPI slave

device uses its SS pin to determine whether it is selected.

Typical connections are shown in Figures 10, 11, and 12.

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8.19.1 Typical SPI conﬁgurations

Master

Slave

MISO

MOSI

MISO

8-BIT SHIFT

REGISTER

8-BIT SHIFT

REGISTER

MOSI

SPICLK

PORT

SPICLK

SS

SPI CLOCK

GENERATOR

002aaa435

Fig 10. SPI single master single slave conﬁguration.

Master

Slave

MISO

MOSI

8-BIT SHIFT

REGISTER

8-BIT SHIFT

REGISTER

MOSI

SPICLK

SS

SPICLK

SS

SPI CLOCK

GENERATOR

SPI CLOCK

GENERATOR

002aaa436

Fig 11. SPI dual device conﬁguration, where either can be a master or a slave.

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Master

Slave

MISO

MOSI

MISO

8-BIT SHIFT

REGISTER

8-BIT SHIFT

REGISTER

MOSI

SPICLK

port

SPICLK

SS

SPI CLOCK

GENERATOR

Slave

MISO

MOSI

8-BIT SHIFT

REGISTER

SPICLK

SS

port

002aaa437

Fig 12. SPI single master multiple slaves conﬁguration.

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8.20 Analog comparators

Two analog comparators are provided on the P89LPC930/931. Input and output

options allow use of the comparators in a number of different conﬁgurations.

Comparator operation is such that the output is a logic 1 (which may be read in a

register and/or routed to a pin) when the positive input (one of two selectable pins) is

greater than the negative input (selectable from a pin or an internal reference

voltage). Otherwise the output is a ‘0’. Each comparator may be conﬁgured to cause

an interrupt when the output value changes.

The overall connections to both comparators are shown in Figure 13. The

comparators function to V_DD= 2.4 V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are

not guaranteed to be stable for 10 microseconds. The corresponding comparator

interrupt should not be enabled during that time, and the comparator interrupt ﬂag

must be cleared before the interrupt is enabled in order to prevent an immediate

interrupt service.

When a comparator is disabled the comparator’s output, COx, goes HIGH. If the

comparator output was LOW and then is disabled, the resulting transition of the

comparator output from a LOW to HIGH state will set the comparator ﬂag, CMFx.

This will cause an interrupt if the comparator interrupt is enabled. The user should

therefore disable the comparator interrupt prior to disabling the comparator.

Additionally, the user should clear the comparator ﬂag, CMFx, after disabling the

comparator.

CP1

Comparator 1

OE1

(P0.4) CIN1A

(P0.3) CIN1B

CO1

CMP1 (P0.6)

(P0.5) CMPREF

V

Change Detect

REF

CMF1

CN1

Interrupt

Change Detect

EC

CP2

Comparator 2

CMF2

(P0.2) CIN2A

(P0.1) CIN2B

CMP2 (P0.0)

CO2

OE2

002aaa422

CN2

Fig 13. Comparator input and output connections.

8.20.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to

as V_REF, is 1.23 V ±10%.

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8.20.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag

is set whenever the comparator output changes state. The ﬂag may be polled by

software or may be used to generate an interrupt. The two comparators use one

common interrupt vector. If both comparators enable interrupts, after entering the

interrupt service routine, the user needs to read the ﬂags to determine which

comparator caused the interrupt.

8.20.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is

activated, but both comparators are disabled automatically in Total Power-down

mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of

the comparator output state will generate an interrupt and wake up the processor. If

the comparator output to a pin is enabled, the pin should be conﬁgured in the

push-pull mode in order to obtain fast switching times while in power-down mode. The

reason is that with the oscillator stopped, the temporary strong pull-up that normally

occurs during switching on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the

normal operating mode. This fact should be taken into account when system power

consumption is an issue. To minimize power consumption, the user can disable the

comparators via PCONA.5, or put the device in Total Power-down mode.

8.21 Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be

generated when Port 0 is equal to or not equal to a certain pattern. This function can

be used for bus address recognition or keypad recognition. The user can conﬁgure

the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins

connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)

is used to deﬁne a pattern that is compared to the value of Port 0. The Keypad

Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when

the condition is matched while the Keypad Interrupt function is active. An interrupt will

be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register

(KBCON) is used to deﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x

series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then

any key connected to Port 0 which is enabled by the KBMASK register will cause the

hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt

may be used to wake up the CPU from Idle or Power-down modes. This feature is

particularly useful in handheld, battery-powered systems that need to carefully

manage power consumption yet also need to be convenient to use.

In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held

longer than 6 CCLKs.

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8.22 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure

to feed the timer prior to the timer reaching its terminal count. It consists of a

programmable 12-bit prescaler, and an 8-bit down counter. The down counter is

decremented by a tap taken from the prescaler. The clock source for the prescaler is

either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can

only be reset by a power-on reset. When the Watchdog feature is disabled, it can be

used as an interval timer and may generate an interrupt. Figure 14 shows the

watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte

sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,

the watchdog is disabled. The watchdog timer has a time-out period that ranges from

a few µs to a few seconds. Please refer to the P89LPC930/931 User’s Manual for

more details.

WDL (C1H)

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

Watchdog

oscillator

8-BIT DOWN

COUNTER

PRESCALER

÷32

RESET

see note (1)

PCLK

SHADOW

REGISTER

FOR WDCON

CONTROL REGISTER

PRE2

PRE1

PRE0

–

WDRUN WDTOF WDCLK

WDCON (A7H)

002aaa423

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

Fig 14. Watchdog timer in Watchdog mode (WDTE = ‘1’).

8.23 Additional features

8.23.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor

completely, as if an external reset or Watchdog reset had occurred. Care should be

taken when writing to AUXR1 to avoid accidental software resets.

8.23.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the

address used with certain instructions. The DPS bit in the AUXR1 register selects

one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so

that the DPS bit may be toggled (thereby switching Data Pointers) simply by

incrementing the AUXR1 register, without the possibility of inadvertently altering other

bits in the register.

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8.24 Flash program memory

8.24.1 General description

The P89LPC930/931 Flash memory provides in-circuit electrical erasure and

programming. The Flash can be read, erased, or written as bytes. The Sector and

Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The Chip

Erase operation will erase the entire program memory. In-System Programming and

standard parallel programming are both available. On-chip erase and write timing

generation contribute to a user-friendly programming interface. The P89LPC930/931

Flash reliably stores memory contents even after more than 100,000 erase and

program cycles. The cell is designed to optimize the erase and programming

mechanisms. The P89LPC930/931 uses V_DDas the supply voltage to perform the

Program/Erase algorithms.

8.24.2 Features

• Byte-erase allowing code memory to be used for data storage.

• Internal ﬁxed boot ROM, containing low-level In-Application Programming (IAP)

routines.

• User programs can call these routines to perform In-Application Programming

(IAP).

• Default loader providing In-System Programming via the serial port, located in

upper end of user program memory.

• Boot vector allows user-provided Flash loader code to reside anywhere in the

Flash memory space, providing ﬂexibility to the user.

• Programming and erase over the full operating voltage range.

• Programming/Erase using ISP/IAP.

• Any ﬂash program/erase operation in 2 ms.

• Parallel programming with industry-standard commercial programmers.

• Programmable security for the code in the Flash for each sector.

• More than 100,000 typical erase/program cycles for each byte.

• 10 year minimum data retention.

8.24.3 Using Flash as data storage

The Flash code memory array of this device supports individual byte erasing and

programming. Any byte in the code memory array may be read using the MOVC

instruction, provided that the sector containing the byte has not been secured (a

MOVC instruction is not allowed to read code memory contents of a secured sector).

Thus any byte in a non-secured sector may be used for non-volatile data storage.

8.24.4 ISP and IAP capabilities of the P89LPC930/931

Flash organization: The P89LPC930/931 program memory consists of eight 1 KB

sectors. Each sector can be further divided into 64-byte pages. In addition to sector

erase and page erase, a 64-byte page register is included which allows from 1 to 64

bytes of a given page to be programmed at the same time, substantially reducing

overall programming time. An In-Application Programming (IAP) interface is provided

to allow the end user’s application to erase and reprogram the user code memory. In

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addition, erasing and reprogramming of user-programmable bytes including UCFG1,

the Boot Status Bit, and the Boot Vector is supported. As shipped from the factory,

the upper 512 bytes of user code space contains a serial In-System Programming

(ISP) routine allowing for the device to be programmed in circuit through the serial

port.

Flash programming and erasing: There are three methods of erasing or

programming of the Flash memory that may be used. First, the Flash may be

programmed or erased in the end-user application by calling low-level routines

through a common entry point. Second, the on-chip ISP boot loader may be invoked.

This ISP boot loader will, in turn, call low-level routines through the same common

entry point that can be used by the end-user application. Third, the Flash may be

programmed or erased using the parallel method by using a commercially available

EPROM programmer which supports this device. This device does not provide for

direct veriﬁcation of code memory contents. Instead this device provides a 32-bit

CRC result on either a sector or the entire 8 kbytes of user code space.

Boot ROM: When the microcontroller programs its own Flash memory, all of the low

level details are handled by code that is contained in a Boot ROM that is separate

from the Flash memory. A user program simply calls the common entry point in the

Boot ROM with appropriate parameters to accomplish the desired operation. The

Boot ROM include operations such as erase sector, erase page, program page, CRC,

program security bit, etc. The Boot ROM occupies the program memory space at the

top of the address space from FF00 to FEFF hex, thereby not conﬂicting with the user

program memory space.

Power-on reset code execution: The P89LPC930/931 contains two special Flash

elements: the Boot Vector and the Boot Status Bit. Following reset, the

P89LPC930/931 examines the contents of the Boot Status Bit. If the Boot Status Bit

is set to zero, power-up execution starts at location 0000H, which is the normal start

address of the user’s application code. When the Boot Status Bit is set to a value

other than zero, the contents of the Boot Vector is used as the high byte of the

execution address and the low byte is set to 00H. The factory default setting is 01EH

(0EH for the LPC930), corresponds to the address 1E00H (0E00h for the LPC930) for

the default ISP boot loader. This boot loader is pre-programmed at the factory into

this address space and can be erased by the user. Users who wish to use this

loader should take cautions to avoid erasing the 1 kbyte sector from 1C00H to

1FFFH (0C00H to 0FFFH for the LPC930). Instead, the page erase function can

be used to erase the eight (four for the LPC930) 64-byte pages located from

1C00H to 1DFFH (0C00H to 0DFFH for the LPC930). A custom boot loader can be

written with the Boot Vector set to the custom boot loader, if desired.

Hardware activation of the boot loader: The boot loader can also be executed by

forcing the device into ISP mode during a power-on sequence (see the

P89LPC930/931 User’s Manual for speciﬁc information). This has the same effect as

having a non-zero status byte. This allows an application to be built that will normally

execute user code but can be manually forced into ISP operation. If the factory default

setting for the Boot Vector (1EH for the lPC931, 0EH for the LPC930) is changed, it

will no longer point to the factory pre-programmed ISP boot loader code. If this

happens, the only way it is possible to change the contents of the Boot Vector is

through the parallel programming method, provided that the end user application

does not contain a customized loader that provides for erasing and reprogramming of

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the Boot Vector and Boot Status Bit. After programming the Flash, the status byte

should be programmed to zero in order to allow execution of the user’s application

code beginning at address 0000H.

In-System Programming (ISP): In-System Programming is performed without

removing the microcontroller from the system. The In-System Programming facility

consists of a series of internal hardware resources coupled with internal ﬁrmware to

facilitate remote programming of the P89LPC930/931 through the serial port. This

ﬁrmware is provided by Philips and embedded within each P89LPC930/931 device.

The Philips In-System Programming facility has made in-system programming in an

embedded application possible with a minimum of additional expense in components

and circuit board area. The ISP function uses ﬁve pins (V_DD, V_SS, TxD, RxD, and

RST). Only a small connector needs to be available to interface your application to an

external circuit in order to use this feature.

In-Application Programming (IAP): Several In-Application Programming (IAP) calls

are available for use by an application program to permit selective erasing, reading,

and programming of Flash sectors, pages, security bits, conﬁguration bytes, and

device id. All calls are made through a common interface, PGM_MTP. The

programming functions are selected by setting up the microcontroller’s registers

before making a call to PGM_MTP at FF00H.

8.25 User conﬁguration bytes

A number of user-conﬁgurable features of the P89LPC930/931 must be deﬁned at

power-up and therefore cannot be set by the program after start of execution. These

features are conﬁgured through the use of the Flash byte UCFG1. Please see the

P89LPC930/931 User’s Manual for additional details.

8.26 User sector security bytes

There are eight User Sector Security Bytes, each corresponding to one sector.

Please see the P89LPC930/931 User’s Manual for additional details.

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9. Limiting values

Table 6:

In accordance with the Absolute Maximum Rating System (IEC 60134).

Limiting values^[1]

Symbol

T_amb(bias)

T_stg

Parameter

Conditions

Min

Max

+125

+150

V_DD+ 0.5

+5.5

20

Unit

°C

V

operating bias ambient temperature

storage temperature range

−55

−65

V_xtal

voltage on XTAL1, XTAL2 pin to V_SS

voltage on any other pin to V_SS

HIGH-level output current per I/O pin

LOW-level output current per I/O pin

-

V_n

−0.5

V

I_OH(I/O)

I_OL(I/O)

-

mA

W

20

I_{I/O(tot)(max)}maximum total I/O current

100

P_tot(pack)

total power dissipation per package

based on package heat

transfer, not device power

consumption

1.5

[1] The following applies to Limiting values:

a) Stresses above those listed under Table 6 may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any conditions other than those described in Table 7 “DC electrical characteristics”, Table 8 “AC

characteristics” and Table 9 “AC characteristics” of this speciﬁcation are not implied.

b) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

c) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

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10. Static characteristics

Table 7:

DC electrical characteristics

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

11

Max

18

23

5

Unit

mA

µA

[2]

I_DD(oper)

power supply current, operating 3.6 V; 12 MHz

3.6 V; 18 MHz

-

14

I_DD(idle)

power supply current, Idle

mode

3.6 V; 12 MHz

3.6 V; 18 MHz

3.6 V

3.25

5

7

I_DD(PD)

power supply current,

55

80

Power-down mode, voltage

comparators powered-down

[2]

I_DD(TPD)

power supply current, Total

Power-down mode

3.6 V

-

1

5

µA

(dV_DD/dt)_r

(dV_DD/dt)_f

V_POR

V_DDrise rate

-

2

mV/µs

V_DDfall rate

-

50

0.2

-

mV/µs

Power-on reset detect voltage

RAM keep-alive voltage

-

V

V_RAM

1.5

-

V_th(HL)

negative-going threshold

voltage

except SCL, SDA

SCL, SDA only

0.22V_DD

0.4V_DD

-

V_IL

LOW-level input voltage

−0.5

-

0.3V_DD

0.7V_DD

5.5

V

V_th(LH)

V_IH

positive-going threshold voltage except SCL, SDA

-

0.6V_DD

-

HIGH-level input voltage

hysteresis voltage

SCL, SDA only

Port 1

0.7V_DD

V_hys

V_OL

-

0.2V_DD

0.6

-

[3]

LOW-level output voltage; all

ports, all modes except Hi-Z

I_OL= 20 mA;

V_DD= 2.4 V to 3.6 V

1.0

I_OL= 3.2 mA;

-

0.2

0.3

-

V

V_DD= 2.4 V to 3.6 V

V_OH

HIGH-level output voltage, all

ports

I_OH= −20 µA;

V_DD= 2.4 V to 3.6 V;

quasi-bidirectional mode

V

_DD− 0.3

_DD− 0.7

V

-

_DD− 0.2

_DD− 0.4

I_OH= −3.2 mA;

-

V

V_DD= 2.4 V to 3.6 V;

push-pull mode

I_OH= −20 mA;

0.8V_DD

V_DD= 2.4 V to 3.6 V;

push-pull mode

[4]

[5]

[6]

[7]

C_ig

I_IL

input/output pin capacitance

logic 0 input current, all ports

-

15

pF

µA

V_IN= 0.4 V

-

−80

±10

−450

I_LI

input leakage current, all ports V_IN= V_ILor V_IH

-

I_TL

logic 1-to-0 transition current,

all ports

V_IN= 2.0 V at

V_DD= 3.6 V

−30

R_RST

internal reset pull-up resistor

10

-

30

kΩ

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Table 7:

DC electrical characteristics…continued

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

V_BO

brownout trip voltage with

BOV = ‘0’, BOPD = ‘1’

2.4 V < V_DD< 3.6 V

2.40

-

2.70

V

V_REF

bandgap reference voltage

1.11

-

1.23

10

1.34

20

V

TC_(VREF)

bandgap temperature

coefﬁcient

ppm/°

C

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] The I_DD(oper), I_DD(idle), and I_DD(PD)speciﬁcations are measured using an external clock with the following functions disabled: comparators,

brownout detect, and watchdog timer.

[3] See Table 6 “Limiting values^[1]” on page 41 for steady state (non-transient) limits on I_OLor I_OH. If I_OL/I_OHexceeds the test condition,

V_OL/V_OHmay exceed the related speciﬁcation.

[4] Pin capacitance is characterized but not tested.

[5] Measured with port in quasi-bidirectional mode.

[6] Measured with port in high-impedance mode.

[7] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest

when V_INis approximately 2 V.

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11. Dynamic characteristics

Table 8:

AC characteristics

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz

Unit

Min

Max

7.557

520

Min

Max

7.557

520

f_RCOSC

f_WDOSC

internal RC oscillator frequency

7.189

320

7.189

320

MHz

kHz

internal watchdog oscillator

frequency

f_osc

oscillator frequency

clock cycle

0

12

-

MHz

ns

t_CLCL

see Figure 20

83

0

f_CLKP

CLKLP active frequency

8

MHz

Glitch ﬁlter

glitch rejection, P1.5/RST pin

-

50

-

50

-

ns

signal acceptance, P1.5/RST pin

125

-

125

-

glitch rejection, any pin except

P1.5/RST

15

signal acceptance, any pin except

P1.5/RST

50

-

50

-

ns

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

HIGH time

see Figure 20

33

-

t

_CLCL− t_CLCX

33

-

ns

LOW time

rise time

fall time

t_CLCL− t_CHCX33

-

8

-

8

-

Shift register (UART mode 0)

t_XLXL

serial port clock cycle time

16 t_CLCL

13 t_CLCL

-

1333

1083

-

ns

t_QVXH

output data set-up to clock rising

edge

t_XHQX

t_XHDX

output data hold after clock rising

edge

-

t_CLCL+ 20

-

103

ns

input data hold after clock rising

edge

-

0

-

0

-

t_DVXH

input data valid to clock rising edge

150

SPI interface

f_SPI

Operating frequency

2.0 MHz (Slave)

3.0 MHz (Master)

Cycle time

CCLK

0

-

⁄

0

-

2.0

-

MHz

6

CCLK

⁄

4

t_SPICYC

see Figures

15, 16, 17, 18

6

2.0 MHz (Slave)

3.0 MHz (Master)

⁄

-

500

-

ns

CCLK

4

⁄

CCLK

t_SPILEAD

Enable lead time (Slave)

see Figures

17, 18

2.0 MHz

250

-

250

-

ns

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Table 8:

AC characteristics…continued

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz

Unit

Min

Max

Min

Max

t_SPILAG

Enable lag time (Slave)

see Figures

17, 18

2.0 MHz

250

-

250

-

ns

t_SPICLKH

SPICLK high time

see Figures

15, 16, 17, 18

2

Master

⁄

-

340

190

-

ns

CCLK

3

Slave

⁄

CCLK

t_SPICLKL

SPICLK low time

see Figures

15, 16, 17, 18

2

3

Master

Slave

⁄

-

340

190

100

-

ns

CCLK

t_SPIDSU

t_SPIDH

t_SPIA

Data set-up time (Master or Slave) see Figures

15, 16, 17, 18

100

0

Data hold time (Master or Slave)

see Figures

15, 16, 17, 18

-

100

0

-

ns

Access time (Slave)

see Figures

17, 18

120

t_SPIDIS

Disable time (Slave)

see Figures

17, 18

2.0 MHz

0

240

-

240

ns

t_SPIDV

Enable to output data valid

see Figures

15, 16, 17, 18

2.0 MHz

0

240

167

-

240

167

-

ns

3.0 MHz

-

t_SPIOH

t_SPIR

Output data hold time

see Figures

0

15, 16, 17, 18

Rise time

see Figures

15, 16, 17, 18

SPI outputs (SPICLK, MOSI,

MISO)

-

100

-

100

ns

SPI inputs (SPICLK, MOSI,

MISO, SS)

2000

t_SPIF

Fall time

see Figures

15, 16, 17, 18

SPI outputs (SPICLK, MOSI,

MISO)

-

100

-

100

ns

SPI inputs (SPICLK, MOSI,

MISO, SS)

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

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Table 9:

AC characteristics

V_DD= 3.0 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Variable clock

f_osc= 18 MHz

Unit

Min

Max

7.557

520

Min

Max

7.557

520

f_RCOSC

f_WDOSC

internal RC oscillator frequency

7.189

320

7.189

320

MHz

kHz

internal Watchdog oscillator

frequency

[2]

f_osc

oscillator frequency

clock cycle

0

18

-

MHz

ns

t_CLCL

see Figure 20

55

0

f_CLKP

CLKLP active frequency

8

MHz

Glitch ﬁlter

glitch rejection, P1.5/RST pin

-

50

-

50

-

ns

signal acceptance, P1.5/RST pin

125

-

125

-

glitch rejection, any pin except

P1.5/RST

15

signal acceptance, any pin except

P1.5/RST

50

-

50

-

ns

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

HIGH time

see Figure 20

22

-

t

_CLCL− t_CLCX

22

-

ns

LOW time

rise time

fall time

t_CLCL− t_CHCX22

-

5

-

5

-

Shift register (UART mode 0)

t_XLXL

serial port clock cycle time

16 t_CLCL

13 t_CLCL

-

888

722

-

ns

t_QVXH

output data set-up to clock rising

edge

t_XHQX

t_XHDX

output data hold after clock rising

edge

-

t_CLCL+ 20

-

75

0

ns

input data hold after clock rising

edge

-

0

-

t_DVXH

input data valid to clock rising edge

150

-

SPI interface

f_SPI

Operating frequency

3.0 MHz (Slave)

4.5 MHz (Master)

Cycle time

CCLK

0

-

⁄

0

-

3

MHz

6

CCLK

⁄

4.5

4

t_SPICYC

see Figures

15, 16, 17, 18

6

3.0 MHz (Slave)

4.5 MHz (Master)

⁄

-

333

222

-

ns

CCLK

4

⁄

CCLK

9397 750 14472

Product data

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46 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Table 9:

AC characteristics…continued

V_DD= 3.0 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Variable clock

f_osc= 18 MHz

Unit

Min

250

Max

Min

250

Max

t_SPILEAD

Enable lead time (Slave)

see Figures

17, 18

3.0 MHz

-

ns

t_SPILAG

Enable lag time (Slave)

see Figures

17, 18

3.0 MHz

t_SPICLKH

SPICLK high time

see Figures

15, 16, 17, 18

2

Master

⁄

-

111

167

-

ns

CCLK

3

Slave

⁄

CCLK

t_SPICLKL

SPICLK low time

see Figures

15, 16, 17, 18

2

3

Master

Slave

⁄

-

111

167

100

-

ns

CCLK

t_SPIDSU

t_SPIDH

t_SPIA

Data set-up time (Master or Slave) see Figures

15, 16, 17, 18

100

0

Data hold time (Master or Slave)

see Figures

15, 16, 17, 18

-

100

0

-

ns

Access time (Slave)

see Figures

17, 18

80

t_SPIDIS

Disable time (Slave)

see Figures

17, 18

3.0 MHz

0

160

-

160

ns

t_SPIDV

Enable to output data valid

see Figures

15, 16, 17, 18

3.0 MHz

0

160

111

-

160

111

-

ns

4.5 MHz

-

t_SPIOH

t_SPIR

Output data hold time

see Figures

0

15, 16, 17, 18

Rise time

see Figures

15, 16, 17, 18

SPI outputs (SPICLK, MOSI,

MISO)

-

100

-

100

ns

SPI inputs (SPICLK, MOSI,

MISO, SS)

2000

9397 750 14472

Product data

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47 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Table 9:

AC characteristics…continued

V_DD= 3.0 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Variable clock

f_osc= 18 MHz

Unit

Min

Max

Min

Max

t_SPIF

Fall time

see Figures

15, 16, 17, 18

SPI outputs (SPICLK, MOSI,

MISO)

-

100

-

100

ns

SPI inputs (SPICLK, MOSI,

MISO, SS)

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

[2] When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to

hold the device in reset at power-up until V_DDhas reached its speciﬁed level. When system power is removed V_DDwill fall below the

minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout

detect circuit may be required to hold the device in reset when V_DDfalls below the minimum speciﬁed operating voltage.

SS

t

CLCL

t

SPIR

SPIF

t

SPICLKL

t

SPICLKH

SPICLK

(CPOL = 0)

(output)

t

SPIR

SPIF

t

SPICLKL

t

SPICLKH

SPICLK

(CPOL = 1)

(output)

t

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIDV

t

SPIR

SPIOH

SPIDV

t

SPIF

MOSI

(output)

Master MSB/LSB out

Master LSB/MSB out

002aaa156

Fig 15. SPI master timing (CPHA = 0).

9397 750 14472

Product data

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48 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

SS

t

CLCL

t

SPIF

SPIR

t

SPICLKL

t

SPICLKH

SPICLK

(CPOL = 0)

(output)

t

SPIR

SPIF

t

SPICLKL

t

SPICLKH

SPICLK

(CPOL = 1)

(output)

t

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIDV

t

SPIOH

SPIDV

t

SPIDV

t

SPIR

SPIF

MOSI

(output)

Master MSB/LSB out

Master LSB/MSB out

002aaa157

Fig 16. SPI master timing (CPHA = 1).

SS

t

SPIR

t

SPIR

t

CLCL

t

SPIF

t

SPILEAD

t

SPIR

SPILAG

t

SPICLKL

t

SPICLKH

SPICLK

(CPOL = 0)

(input)

t

SPIR

SPIF

t

SPICLKL

t

SPICLKH

SPICLK

(CPOL = 1)

(input)

t

SPIOH

t

SPIOH

t

SPIA

t

SPIDIS

SPIDV

MISO

(output)

Slave MSB/LSB out

Slave LSB/MSB out

Not defined

t

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa158

Fig 17. SPI slave timing (CPHA = 0).

9397 750 14472

Product data

Rev. 05 — 15 December 2004

49 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

SS

t

SPIR

t

SPIR

t

CLCL

t

SPIF

t

SPILEAD

t

SPIR

SPILAG

t

SPICLKL

t

SPICLKH

SPICLK

(CPOL = 0)

(input)

t

SPIR

SPIF

t

SPICLKL

t

SPICLKH

SPICLK

(CPOL = 1)

(input)

t

SPIOH

t

SPIDV

SPIDIS

SPIDV

t

SPIA

MISO

(output)

Slave LSB/MSB out

Slave MSB/LSB out

Not defined

t

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa159

Fig 18. SPI slave timing (CPHA = 1).

t

XLXL

Clock

t

XHQX

t

QVXH

Output Data

0

1

2

3

4

5

6

7

Write to SBUF

t

XHDX

t

Set TI

XHDV

Input Data

Valid

Clear RI

Set RI

002aaa425

Fig 19. Shift register mode timing.

V

- 0.5 V

0.45 V

DD

0.2 V

+ 0.9

DD

0.2 V

- 0.1 V

DD

t

CHCX

t

CLCX

t

CHCL

CLCH

t

C

002aaa416

Fig 20. External clock timing.

9397 750 14472

Product data

Rev. 05 — 15 December 2004

50 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Table 10: AC characteristics, ISP entry mode

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

Symbol

t_VR

Parameter

Conditions

Min

50

1

Typ

Max

Unit

µs

RST delay from V_DDactive

RST HIGH time

RST LOW time

-

t_RH

32

-

µs

t_RL

1

µs

V

DD

t

VR

t

RH

RST

002aaa426

t

RL

Fig 21. ISP entry waveform.

12. Comparator electrical characteristics

Table 11: Comparator electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

Symbol

V_IO

Parameter

Conditions

Min

Typ

Max

Unit

mV

V

offset voltage comparator inputs

common mode range comparator inputs

common mode rejection ratio

response time

-

±20

V_CR

0

-

V_DD− 0.3

[1]

CMRR

-

−50

500

10

dB

ns

-

250

comparator enable to output valid

input leakage current, comparator

-

µs

I_IL

0 < V_IN< V_DD

-

±10

µA

[1] This parameter is characterized, but not tested in production.

9397 750 14472

Product data

Rev. 05 — 15 December 2004

51 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

13. Package outline

TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm

SOT361-1

D

E

A

X

c

H

v

M

y

A

E

Z

15

28

Q

A

2

(A )

3

A

pin 1 index

1

θ

L

p

L

1

14

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

9.8

9.6

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.8

0.5

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT361-1

MO-153

Fig 22. SOT361-1 (TSSOP28).

9397 750 14472

Product data

Rev. 05 — 15 December 2004

52 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

14. Revision history

Table 12: Revision history

Rev Date

CPCN

-

Description

05 20041215

Product data (9397 750 14472)

Modiﬁcation:

• Added 18 MHz information.

04 20040106

03 20031006

02 20030526

01 20030514

-

Product data (9397 750 12284); ECN 853-2406 01-A15015 dated 16 December 2003

Product data (9397 750 12122); ECN 853-2406 30390 dated 30 September 2003

Objective data (9397 750 11536)

Preliminary data (9397 750 11386)

9397 750 14472

Product data

Rev. 05 — 15 December 2004

53 of 55

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

15. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

16. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

18. Licenses

Purchase of Philips I²C components

17. Disclaimers

Purchase of Philips I²C components conveys a license

under the Philips’ I²C patent to use the components in the

I²C system provided the system conforms to the I²C

speciﬁcation deﬁned by Philips. This speciﬁcation can be

ordered using the code 9398 393 40011.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

54 of 55

9397 750 14472

Product data

Rev. 05 — 15 December 2004

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Philips Semiconductors

Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

8.17.1

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Baud rate generator and selection . . . . . . . . . . . . . . 28

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Transmit interrupts with double buffering

8.17.2

8.17.3

8.17.4

8.17.5

8.17.6

8.17.7

8.17.8

8.17.9

2

3

3.1

4

5

Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5.1

5.2

enabled (Modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . 29

The 9^thbit (bit 8) in double buffering (Modes 1, 2 and

3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

I²C-bus serial interface . . . . . . . . . . . . . . . . . . . . . . . 30

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . 31

Typical SPI conﬁgurations. . . . . . . . . . . . . . . . . . . . . 33

Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 35

Internal reference voltage . . . . . . . . . . . . . . . . . . . . . 35

Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 36

Comparators and power reduction modes . . . . . . . . 36

Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 36

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 38

General description. . . . . . . . . . . . . . . . . . . . . . . . . . 38

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Using Flash as data storage. . . . . . . . . . . . . . . . . . . 38

ISP and IAP capabilities of the P89LPC930/931 . . . 38

User conﬁguration bytes . . . . . . . . . . . . . . . . . . . . . . 40

User sector security bytes . . . . . . . . . . . . . . . . . . . . 40

6

7

Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Special function registers. . . . . . . . . . . . . . . . . . . . . 11

8.17.10

8

Functional description . . . . . . . . . . . . . . . . . . . . . . . 16

Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clock deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 16

Low speed oscillator option . . . . . . . . . . . . . . . . . . . 16

Medium speed oscillator option . . . . . . . . . . . . . . . . 16

High speed oscillator option. . . . . . . . . . . . . . . . . . . 16

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 17

Watchdog oscillator option. . . . . . . . . . . . . . . . . . . . 17

External clock input option . . . . . . . . . . . . . . . . . . . . 17

CPU CLock (CCLK) wake-up delay . . . . . . . . . . . . . 19

CPU CLOCK (CCLK) modiﬁcation: DIVM register. . 19

Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 19

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

External interrupt inputs. . . . . . . . . . . . . . . . . . . . . . 20

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Port conﬁgurations . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Quasi-bidirectional output conﬁguration. . . . . . . . . . 22

Open-drain output conﬁguration. . . . . . . . . . . . . . . . 22

Input-only conﬁguration . . . . . . . . . . . . . . . . . . . . . . 22

Push-pull output conﬁguration . . . . . . . . . . . . . . . . . 22

Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 22

Additional port features . . . . . . . . . . . . . . . . . . . . . . 24

Power monitoring functions . . . . . . . . . . . . . . . . . . . 24

Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 24

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Total Power-down mode. . . . . . . . . . . . . . . . . . . . . . 25

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reset vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 26

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Timer overﬂow toggle output . . . . . . . . . . . . . . . . . . 27

Real-Time clock/system timer . . . . . . . . . . . . . . . . . 27

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.18

8.19

8.1

8.2

8.19.1

8.20

8.20.1

8.20.2

8.20.3

8.21

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10

8.10.1

8.11

8.11.1

8.11.2

8.11.3

8.11.4

8.11.5

8.11.6

8.11.7

8.12

8.12.1

8.12.2

8.13

8.13.1

8.13.2

8.13.3

8.14

8.22

8.23

8.23.1

8.23.2

8.24

8.24.1

8.24.2

8.24.3

8.24.4

8.25

8.26

9

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 42

Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 44

Comparator electrical characteristics . . . . . . . . . . . 51

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10

11

12

13

14

15

16

17

18

8.14.1

8.15

8.15.1

8.15.2

8.15.3

8.15.4

8.15.5

8.15.6

8.16

8.17

Printed in the U.S.A.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 15 December 2004

Document order number: 9397 750 14472


型号：	CP3263,512
厂家：	NXP
描述：	P89LPC930FDH PC
文件：	总55页 (文件大小：236K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CP3263,512 [NXP]

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