NTE65101 [NTE]
Integrated Circuit 256 x 4-Bit Static Random Access Memory (SRAM); 集成电路256 ×4位的静态随机存取存储器（ SRAM）的
| 型号： | NTE65101 |
| 厂家： | 
NTE ELECTRONICS |
| 描述： | Integrated Circuit 256 x 4-Bit Static Random Access Memory (SRAM) |
| 文件： | 总4页 (文件大小：34K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTE65101
Integrated Circuit
256 x 4–Bit Static Random Access Memory (SRAM)
Description:
The NTE65101 is a CMOS 1024–bit device organized in 256 words by 4 bits in a 22–Lead DIP type
package. This device offers ultra low power and fully static operation with a single 5V supply. Sepa-
rate data inputs and data outputs permit maximum flexibility in bus–oriented systems. Data retention
at a power supply as low as 2V over temperature readily allows design into applications using battery
backup for nonvolatility. The NTE65101 is fully static and does not require clocking in standby mode.
Features:
D Organized as 256 Bytes of 4–Bits
D Static Operation
D Low Standby Power
D Three–State Output
D Single 5V Power Supply
D Data Retention to 2V
D TTL Compatible
D Maximum Access Time: 450ns
Absolute Maximum Ratings: (Voltages referenced to VSS Pin8)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to +7V
Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to VCC +0.3V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40° to +85°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high impedance circuit.
DC Electrical Characteristics: (VCC = 5V ±5%, TA = 0° to +70°C unless otherwise specified)
Parameter
Input Current
Symbol
Iin
Test Conditions
Min Typ Max Unit
Note 3
–
2.2
–0.3
2.4
–
5.0
–
–
nA
V
Input High Voltage
Input Low Voltage
VIH
VCC
0.65
–
VIL
–
V
Output High Voltage
Output Low Voltage
Output Leakage Current
Operating Current
VOH
VOL
ILO
IOH = –1mA
–
V
IOL = 2mA
–
0.4
V
CE1 = 2.2V, VOL = 0V to VCC, Note 3
–
–
±1.0 µA
ICC1
Vin = VCC, except CE1 ≤ 0.65V,
Outputs open
–
9.0
22
27
10
mA
mA
µA
ICC2
ICCL
Vin = 2.2V, except CE1 ≤ 0.65V,
Outputs open
–
–
13
Standby Current
CE2 ≤ 0.2V, Note 3, Note 4
–
Note 2. Typical values are TA = +25°C and nominal voltage.
Note 3. Current through all inputs and outputs included in ICCL measurement.
Note 4. Low current state is for CE2 = 0 only.
Capacitance:
Parameter
Input Capacitance
Output Capacitance
Symbol
Cin
Test Conditions
Min Typ Max Unit
Vin = 0V
–
–
4.0
8.0
pF
Cout
Vout = 0V
8.0 12.0 pF
Note 2. Typical values are TA = +25°C and nominal voltage.
Low VCC Retention Characteristics: (TA = 0° to +70°C unless otherwise specified)
Parameter
VCC for Data Retention
Symbol
Test Conditions
Min Typ Max Unit
VDR
2.0
–
–
–
V
Data Retention Current
ICCDR1 CE2 ≤ 0.2V, VDR = 2V
0.14 10
µA
ns
ns
Chip Deselect to Data Retention Time
Operation Recovery Time
tCDR
0
–
–
–
–
tR
Note 5
tRC
Note 2. Typical values are TA = +25°C and nominal voltage.
Note 5. tRC = Read Cycle Time.
AC Operating Conditions and Characteristics: (Full operating voltage and temperature unless
otherwise specified)
AC Test Conditions:
Condition
Value
+0.65V to 2.2V
20ns
Input Pulse Levels
Input Rise and Fall Times
Output Load –
1 TTL Gate and CL = 100pF
1.5V
Timing Measurement Reference Level
AC Operating Conditions and Characteristics (Cont’d): (Full operating voltage and temperature
unless otherwise specified)
Read Cycle:
Parameter
Parameter
Symbol Min Max Unit
Read Cycle Time
Access Time
tRC
tA
450
–
ns
–
450 ns
Read Cycle (Cont’d):
Symbol Min Max Unit
Address Setup Time
tAS
tAH
20
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
Address Hold Time
Chip Enable (CE1) to Output
Chip Enable (CE2) to Output
Output Disable to Output
Data Output to High Z State
tCO1
tCO2
tOD
–
400
500
250
130
–
–
–
tDF
0
Previous Read Data Valid with Respect to Address Change
Previous Read Data Valid with Respect to Chip Enable
tOH1
tOH2
0
0
–
Write Cycle:
Parameter
Write Cycle
Symbol Min Max Unit
tWC
tAW
tCW1
tCW2
tDW
tDH
450
130
350
350
250
50
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Delay
Chip Enable (CE1) to Write
Chip Enable (CE2) to Write
Data Setup
Data Hold
Write Pulse
tWP
tWR
tDS
250
50
Write Recovery
Output Disable Setup
130
Truth Table:
CE1
H
CE2
X
OD
X
R/W
X
Din
X
Output
High Z
High Z
High Z
High Z
Din
Mode
Not Selected
Not Selected
X
L
X
X
X
X
X
H
H
L
H
X
Output Disable
Write
L
H
L
X
L
H
L
X
Write
L
H
L
H
X
Dout
Read
Pin Connection Diagram
A3 1
A2 2
A1 3
A0 4
A5 5
22
VCC
21 A4
20 R/W
19
18
CE 1
OD
A6 6
A7 7
17 CD 2
DO 4
16
GND 8
15 DI 4
14 DO 3
13 DI 3
12 DO 2
9
DI 1
DO 1
10
DI 2 11
22
1
12
11
.410
(11.41)
1.300 (33.0)
.400
(10.16)
.216
(5.5)
.100 (2.54)
1.000 (25.4)
.110 (2.79)
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