NTE6821 [NTE]
Integrated Circuit Peripheral Interface Adapter (PIA), NMOS, 1MHz; 集成电路外设接口适配器（ PIA ） ， NMOS ， 1MHz的
| 型号： | NTE6821 |
| 厂家： | 
NTE ELECTRONICS |
| 描述： | Integrated Circuit Peripheral Interface Adapter (PIA), NMOS, 1MHz |
| 文件： | 总5页 (文件大小：48K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTE6821
Integrated Circuit
Peripheral Interface Adapter (PIA),
NMOS, 1MHz
Description:
The NTE6821 is a peripheral interface adapter (PIA) in a 40–Lead DIP type package capable of inter-
facing the Microprocessing Unit (MPU) to peripherals through two 8–Bit bidirectional peripheral data
buses and four control lines. No external logic is required for interfacing to most peripheral devices.
The functional configuration of the PIA is programmed by the MPU during system initialization. Each
of the peripheral data lines can be programmed to act as an input or output, and each of the four con-
trol/interrupt lines may be programmed for one of several control modes. This allows a high degree
of flexibility in the over–all operation of the interface.
Features:
D 8–Bit Bidirectional Data Bus for Communication with the MPU
D Two Bidirectional 8–Bit Buses for Interface to Peripherals
D Two Programmed Control Registers
D Two Programmed Data Direction Registers
D Four Individually–Controlled Interrupt Input Lines; Two Usable as Peripheral Control Outputs
D Handshake Control Logic for Input and Output Peripheral Operation
D High–Impedance 3–State and Direct Transistor Drive Peripheral Lines
D Program Controlled Interrupt and Interrupt Disable Capability
D CMOS Drive Capability on Side A Peripheral Lines
D Two TTL Drive Capability on All A and B Side Buffers
D TTL Compatible
D Static Operation
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7V
Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C
Thermal Resistance, Junction to Ambient, RΘ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.5°C/W
JA
Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high impedance.
Electrical Characteristics: (VCC = 5V ±5%, VSS = 0, TA = 0° to +70⁄C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Bus Control Inputs (R/W, Enable, Reset, RS0, RS1, CS0, CS1, CS2)
Input High Voltage
V
V
+2.0
–
–
V
CC
V
V
IH
SS
Input Low Voltage
V
V
SS
–0.3
V
+0.8
IL
SS
Input Leakage Current
Capacitance
I
V = 0 to 5.25V
–
1.0
–
2.5
7.5
µA
pF
in
in
C
V = 0, T = +25°C, f = 1MHz
–
in
in
A
Interrupt Outputs (IRQA, IRQB)
Output Low Voltage
Output Leakage Current (Off State)
Capacitance
V
I
= 3.2mA
= 2.4V
OH
–
–
–
–
1.0
–
V +0.4
SS
V
OL
Load
I
V
10
µA
pF
LOH
C
V = 0, T = +25°C, f = 1MHz
5.0
out
in
A
Data Bus (D0 – D7)
Input High Voltage
V
V
+2.0
–
–
V
CC
V
V
IH
SS
Input Low Voltage
V
V
SS
–0.3
V
+0.8
IL
SS
Three–State (Off State) Input Current
Output High Voltage
Output Low Voltage
Capacitance
I
V = 0.4 to 2.4V
–
2.0
–
10
µA
V
TSI
in
V
I
I
= –205µA
V +2.4
SS
–
OH
Load
Load
V
= 1.6mA
–
–
V
+0.4
V
OL
SS
C
V = 0, T = +25°C, f = 1MHz
–
–
12.5
2.5
pF
in
in
A
Peripheral Bus (PA0 – PA7, PB0 – PB7, CA1, CA2, CB1, CB2)
Input Leakage Current
I
in
R/W, Reset, RS0, RS1, CS0,
V = 0 to 5.25V
in
–
1.0
µA
CS1, CS2, CA1, CB1, Enable
Three–State (Off State) Input Current
PB0 – PB7, CB2
I
TSI
V = 0.4 to 2.4V
–
–200
–1.0
–
2.0
–400
–
10
–
µA
µA
in
Input High Current
I
IH
PA0 – PA7, CA2
V
IH
= 2.4V
Darlington Drive Current
I
OH
PB0 – PB7, CB2
V = 1.5V
O
–10
–2.4
mA
mA
Input Low Current
I
IL
PA0 – PA7, CA2
V = 0.4V
IL
–1.3
Output High Voltage
V
OH
PA0 – PA7, PB0 – PB7, CA2, CB2
I
I
I
= –200µA
= 10µA
V
+2.4
–
–
–
–
–
–
V
V
Load
Load
Load
SS
PA0 – PA7, CA2
Output Low Voltage
Capacitance
V
CC
–1.0
V
OL
= 3.2mA
–
V
+0.4
V
SS
C
in
V = 0, T = +25°C, f = 1MHz
–
10
pF
in
A
Power Requirements
Power Dissipation
P
D
–
–
550
mW
Bus Timing Characteristics: (VCC = 5V ±5%, VSS = 0, TA = 0° to +70°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
1000
450
430
–
Typ Max Unit
Enable Cycle Time
t
–
–
–
–
–
–
ns
ns
ns
ns
cycE
Enable Pulse Width, High
PW
EH
Enable Pulse Width, Low
PW
–
EL
Enable Pulse Rise and Fall Times
t , t
Er Ef
25
Bus Timing Characteristics (Cont’d): (VCC = 5V ±5%, VSS = 0, TA = 0° to +70°C unless otherwise
specified)
Parameter
Symbol
Test Conditions
Min
Typ Max Unit
Setup Time, Address and R/W Valid to
Enable Positive Transition
t
AS
160
–
–
ns
Address Hold Time
t
10
–
–
–
–
–
–
–
320
–
ns
ns
ns
ns
ns
AH
Data Delay Time, Read
Data Hold Time, Read
Data Setup Time, Write
data Hold Time, Write
t
t
DDR
DHR
10
195
10
t
–
DSW
DHW
t
–
Peripheral Timing Characteristics: (VCC = 5V ±5%, VSS = 0, TA = 0° to +70°C unless otherwise
specified)
Parameter
Symbol Min Max Unit
Peripheral Data Setup Time
Peripheral Data Hold Time
t
200
0
–
ns
ns
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
µs
µs
µs
ns
µs
PDSU
t
–
PDH
Delay Time, Enable negative transition to CA2 negative transition
Delay Time, Enable negative transition to CA2 positive transition
Rise and fall Times for CA1 and CA2 input signals
Delay Time from CA1 active transition to CA2 positive transition
Delay Time, Enable negative transition to Peripheral Data Valid
Delay Time, Enable negative transition to Peripheral CMOS Data Valid PA0 – PA7, CA2
Delay Time, Enable positive transition to CB2 negative transition
Delay Time, Peripheral Data Valid to CB2 negative transition
Delay Time, Enable positive transition to CB2 postivie transition
Peripheral Control Output Pulse Width, CA2/CB2
Rise and Fall Time for CB1 and CB2 input signals
Delay Time, CB1 active transition to CB2 positive transition
Interrupt Release Time, IRQA and IRQB
t
–
1.0
1.0
1.0
2.0
1.0
2.0
1.0
–
CA2
t
–
RS1
t , t
–
r
f
t
–
RS2
t
–
PDW
t
–
CMOS
t
t
–
CB2
t
20
–
DC
1.0
–
RS1
PW
550
–
CT
t , t
1.0
2.0
2.0
1.0
–
r
f
t
–
RS2
t
IR
–
Interrupt Response Time
t
–
RS3
Interrupt Input Pulse Width
PW
500
1.0
I
Reset Low Time (Note 2)
t
RL
–
Note 2. The Reset line must be high a minimum of 1.0µs before addressing the PIA.
Expanded Block Diagram
40 CA1
39 CA2
IRQA
38
Interrupt Status
Control A
Control
Register A
(CRA)
D0 33
Data Direction
Register A
(DDRA)
D1 32
D2 31
Data Bus
Buffers
(DBB)
D3 30
D4 29
Output Bus
D5 28
D6 27
2
3
4
5
6
7
8
9
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Output
Register A
(ORA)
D7 26
Peripheral
Interface
A
Bus Input
Register
(BIR)
V
V
=
=
PIN20
PIN1
CC
SS
10 PB0
11 PB1
12 PB2
13 PB3
14 PB4
15 PB5
16 PB6
17 PB7
Output
Register B
(ORB)
Peripheral
Interface
B
CS0 22
CS1 24
Chip
Select
and
CS2 23
RS0 36
RS1 35
R/W
Control
R/W 21
Enable 25
Reset 34
Data Direction
Register B
(DDRB)
Control
Register B
(CRB)
18 CB1
19 CB2
Interrupt Status
Control B
IRQB
37
Pin Connection Diagram
1
2
3
4
5
6
7
8
9
40
V
CA1
39 CA2
38
SS
PA0
PA1
PA2
PA3
IRQA
37 IRQB
RS0
36
35
34
PA4
PA5
PA6
PA7
RS1
RESET
33 D0
D1
D2
D3
32
31
30
PB0 10
11
PB1
PB2 12
29 D4
28
PB3
PB4
13
14
D5
27 D6
26 D7
PB5 15
PB6 16
25
24 CS1
23
E
PB7
17
18
19
20
CB1
CB2
CS2
22 CS0
R/W
V
21
CC
40
21
20
1
.550 (13.9)
Max
2.055 (52.2)
.155 (3.9)
.100 (2.54)
.019 (0.5)
.137
(3.5)
.650 (16.5)
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