NTE6850 [NTE]
Integrated Circuit NMOS, Asynchronous Communications Interface Adapter; 集成电路NMOS ，异步通信接口适配器
| 型号： | NTE6850 |
| 厂家： | 
NTE ELECTRONICS |
| 描述： | Integrated Circuit NMOS, Asynchronous Communications Interface Adapter |
| 文件： | 总3页 (文件大小：35K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTE6850
Integrated Circuit
NMOS, Asynchronous Communications
Interface Adapter
Description:
The NTE6850 Asynchronous Communications Interface Adapter provides the data formatting and
control to interface serial asynchronous data communications information to bus organized systems
such as the NTE6800 Microprocessing Unit.
The bus interface of the NTE6850 includes select, enable, read/write, interrupt and bus interface logic
to allow data transfer over an 8–bit bidirectional data bus. The parallel data of the bus system is serial-
ly transmitted and received by the asynchronous data interface, with proper formatting and error
checking. The functional configuration of the ACIA is programmed via the data bus during system
initialization. A programmable control register provides variable word lengths, clock division ratios,
transmit control, receive control, and interrupt control. For peripheral or modem operation, three con-
trol lines are provided. These lines allow the ACIA to interface directly with the NTE6860 0–600 bps
digital modem.
Features:
D 8–Bit and 9–Bit Transmission
D Optional Even and Odd Parity
D Parity, Overrun and Framing Error Checking
D Programmable Control Register
D Optional ÷1, ÷16, and ÷64 Clock Modes
D Up to 1.0 Mbps Transmission
D False Start Bit Deletion
D Peripheral/Modem Control Functions
D Double Buffered
D One–Stop or Two–Stop Bit Operation
Absolute Maximum Ratings:
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0V
Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 70°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C
Thermal Resistance, Junction–to–Ambient, RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.
either VSS or VCC).
Electrical Characteristics: (VCC = 5V ± 5%, VSS = 0, TA = 0° to +70°C unless otherwise specified)
Parameter
Input High Voltage
Input Low Voltage
Symbol
Test Conditions
Min
V +2.0
Typ
–
Max
Unit
V
V
IH
V
CC
SS
V
IL
V –0.3
SS
–
V +0.8
SS
V
Input Leakage Current
R/W, CS0, CS1, CS2,
I
in
V = 0 to 5.25V
in
–
1.0
2.5
µA
Enable, RS, R D, R C,
X
X
CTS, DCD
Hi–Z (Off–State) Input Current
D0 – D7
I
V = 0.4 to 2.4V
–
2.0
–
10.0
–
µA
V
TSI
in
Output High Voltage
V
I
= 205µA, Enable Pulse Width < 25µs V +2.4
OH
Load SS
D0 – D7
Output High Voltage
I
= 100µA, Enable Pulse Width < 25µs V +2.
–
–
V
Load
SS
T Data, RTS
X
Output Low Voltage
V
I
= 1.6A, Enable Pulse Width < 25µs
–
–
–
V +0.4
V
OL
Load
SS
Output Leakage Current
I
V
= 2.4V
1.0
10
525
12.5
7.5
µA
LOH
OH
(Off–State) IRQ
Internal Power Dissipation
P
INT
T = 0°C, Note 2
–
–
–
300
10.0
7.0
mW
pF
A
Internal Input Capacitance
D0 – D7
C
V = 0, T = +25°C, f = 1MHz
in A
in
Internal Input Capacitance
E, T CLK, R CLK, R/W,
pF
X
X
RS, R Data, CS0, CS1,
X
CS2, CTS, DCD
Output Capacitance
RTS, T Data
C
out
V = 0, T = +25°C, f = 1MHz
–
–
–
–
10
5
pF
pF
X
in
A
Output Capacitance
IRQ
Note 2. For temperatures less than TA = 0°C, PINT maximum will increase.
Serial Data Timing Characteristics:
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Data Clock Pulse Width, Low
PW
B16, B64 Modes
600
900
600
900
–
–
–
–
–
–
–
–
–
–
–
–
–
450
650
450
650
ns
ns
ns
ns
CL
B1 Mode
Data Clock Pulse Width, High
Data Clock Frequency
PW
B16, B64 Modes
B1 Mode
CH
f
C
B16, B64 Modes
B1 Mode
0.8 MHz
500 kHz
–
Data Clock–to–Data Delay for Transmitter
Receive Data Setup Time
t
t
–
600
–
ns
ns
ns
µs
ns
µs
TDD
B1 Mode
B1 Mode
250
250
–
RDS
RDH
Receive Data Hold Time
t
–
Interrupt Request Release Time
Request–to–Send Delay Time
Input Rise and Fall Times
t
R
1.2
560
1.0
t
–
RTS
t , t
r
or 10% of the pulse width if smaller
–
f
Bus Timing Characteristics: (VL ≤ 4V, VH ≥ 2.4V, measurement points 0.8V and 2V unless
otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Cycle Time
t
1.0
430
450
–
–
–
–
–
–
–
–
–
–
–
–
–
10.0
9500
µs
cyc
Pulse Width, E Low
PW
ns
EL
Pulse Width, E High
PW
9500 ns
EH
Clock Rise and Fall Time
Address Hold Time
t , t
r
25
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
t
10
80
80
10
20
10
–
AH
Address Setup Time Before E
Chip Select Setup Time Before E
Chip Select Hold Time
Read Data Hold Time
Write Data Hold Time
Output data Delay Time
Input Data Setup Time
t
–
AS
t
t
–
CS
CH
–
t
Note 3
50
–
DHR
t
t
DHW
DHW
290
–
t
165
DSW
Note 3. The data bus output buffers are no longer sourcing or sinking current by tDHRmax (High
Impedance).
Pin Connection Diagram
1
24
23
22
V
CTS
DCD
D0
SS
Rx Data 2
3
Cx Clk
Tx Clk 4
21 D1
5
20
D2
RTS
Tx Data 6
19 D3
18 D4
17 D5
16 D6
15 D7
7
IRQ
CS0 8
9
CS2
CS1
RS
10
11
12
14
13
E
R/W
V
DD
24
1
13
12
1.300 (33.02)
Max
.520
(13.2)
.225
(5.73)
Max
.100 (2.54)
.126
(3.22)
Min
1.100 (27.94)
.600
(15.24)
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