NTE6810 [NTE]
Integrated Circuit 128 x 8-Bit Static Random Access Memory (SRAM); 集成电路128× 8位的静态随机存取存储器（ SRAM）的
| 型号： | NTE6810 |
| 厂家： | 
NTE ELECTRONICS |
| 描述： | Integrated Circuit 128 x 8-Bit Static Random Access Memory (SRAM) |
| 文件： | 总4页 (文件大小：45K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTE6810
Integrated Circuit
128 x 8–Bit Static Random Access Memory (SRAM)
Description:
The NTE6810 is a byte–orgainzed memory in a 24–Lead DIP type package designed for use in bus–
organized systems. It is fabricated with N–channel silicon–gate technology. For ease of use, this
device operates from a single power supply, has compatibility with TTL and DTL, and needs no clocks
or refreshing because of static operation.
The memory is compatible with the 6800 Microcomputer Family, providing random storage in byte
increments. Memory expansion is provided through multiple Chip Select inputs.
Features:
D Organized as 128 Bytes of 8–Bits
D Static Operation
D Bidirectional Three–State Data Input/Output
D Six Chip Select Inputs (Four Active Low, Two Active High)
D Single 5V Power Supply
D TTL Compatible
D Maximum Access Time: 450ns
Absolute Maximum Ratings:
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7V
Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Thermal Resistance, Junction to Ambient, RΘ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +120°C/W
JA
Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an appropriate logic voltage (e.g., either
VSS or VCC).
DC Electrical Characteristics: (VCC = 5V ±5%, VSS = 0, TA = 0° to +70°C unless otherwise specified)
Parameter
Input High Voltage
Input Low Voltage
Symbol
VIH
Test Conditions
Min
Max
Unit
V
VSS +2.0
VCC
VIL
VSS –0.3 VSS +0.8
V
Input Current
Iin
Vin = 0 to 5.25V
–
2.5
µA
(An, R/W, CSn)
Output High Voltage
Output Low Voltage
VOH
VOL
ITSI
IOH = –205µA
2.4
–
–
V
V
IOL = 1.6mA
0.4
10
Output Leakage Current
CS = 0.8V or CS = 2V,
–
µA
(Three–State)
Vout = 0.4V to 2.4V
Supply Current
ICC
Cin
VCC = 5.25V, All other pins grounded
–
–
80
mA
pF
Input Capacitance
Vin = 0, TA = +25°C, f = 1MHz
7.5
(An, R/W, CSn, CSn)
Output Capacitance (Dn)
Cout
Vout = 0, TA = +25°C, f = 1MHz, CSO = 0
–
12.5
pF
AC Operating Conditions and Characteristics:
Parameter
Symbol
Min
Max
Unit
Read Cycle (VCC = 5V ±5%, VSS = 0, TA = 0° to +70° unless otherwise specified)
Read Cycle Time
tcyc(R)
tacc
450
–
–
450
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Access Time
Address Setup Time
Address Hold Time
tAS
20
0
tAH
–
Data Delay Time (Read)
Read to Select Delay Time
Data Hold from Address
Output Hold Time
tDDR
tRCS
tDHA
tH
–
230
–
0
10
10
10
0
–
–
Data Hold from Read
Read Hold from Chip Select
tDHR
tRH
80
–
Write Cycle (VCC = 5V ±5%, VSS = 0, TA = 0° to +70° unless otherwise specified)
Write Cycle Time
tcyc(W)
tAS
450
20
0
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
tAH
Chip Select Pulse Width
Write to Chip Select Delay Time
Data Setup Time (Write)
Input Hold Time
tCS
300
0
tWCS
tDSW
tH
190
10
0
Write Hold Time from Chip Select
tWH
Read Cycle Timing
t
cyc(R)
t
acc
Address
t
t
AS
AH
CS
CS
t
DDR
t
RH
t
RCS
R/W
t
DHA
t
DHR
t
H
Data Valid
Data In
= Don’t Care
Note 1. Voltage levels shown are V ≤ 0.4V, V ≥ 2.4V, unless otherwise specified.
L
H
Note 2. Measurement pointas shown are 0.8V and 2.0V, unless otherwise specified.
Note 3. CS and CS have same timing.
Write Cycle Timing
t
cyc(W)
Address
t
t
t
AH
CS
AS
CS
CS
t
WH
t
WCS
R/W
t
t
H
DSW
Data in Stable
Data In
= Don’t Care
Note 1. Voltage levels shown are V ≤ 0.4V, V ≥ 2.4V, unless otherwise specified.
L
H
Note 2. Measurement pointas shown are 0.8V and 2.0V, unless otherwise specified.
Note 3. CS and CS have same timing.
Pin Connection Diagram
GND
D0
1
2
3
4
5
24 V
CC
23 A0
D1
22 A1
21 A2
D2
D3
20
A3
D4
D5
6
7
19 A4
18 A5
D6
D7
8
9
17 A6
16 R/W
CS0
CS5
CS4
10
15
14
11
12
CS1
CS2
13 CS3
24
1
13
12
.520
(13.2)
1.300 (33.02)
Max
.225
(5.73)
Max
.100 (2.54)
.126
(3.22)
Min
1.100 (27.94)
.600
(15.24)
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