NTE6508 [NTE]
Integrated Circuit CMOS, 1K Static RAM (SRAM); 集成电路的CMOS， 1K静态RAM （ SRAM）的
| 型号： | NTE6508 |
| 厂家： | 
NTE ELECTRONICS |
| 描述： | Integrated Circuit CMOS, 1K Static RAM (SRAM) |
| 文件： | 总4页 (文件大小：40K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTE6508
Integrated Circuit
CMOS, 1K Static RAM (SRAM)
Description:
The NTE6508 is a 1024 x 1 fully static CMOS RAM in a 16–Lead DIP type package fabricated using
self–aligned silicon gate technology. Synchronous circuit design techniques are employed to acheive
high performance and low power operation. On chip latches are provided for address allowing effeci-
ent interfacing with microprocessor systems. The data output buffers can be forced to a high imped-
ance state for use in expanded memory arrays.
Features:
D Low Power Standby: 50µW Max
D Low Power Operation: 20mW/MHz Max
D Fast Access Time: 300ns Max
D Data Retention: 2V Min
D TTL Compatible Input/Output
D High Output Drive: 2 TTL Loads
D On–Chip Address Register
Absolute Maximum Ratings: (Note 1)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.3V to VCC +0.3V
Typical Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5mA/MHz increase in ICC(OP)
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925 Gates
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Lead Temperature (During Soldering, 10s max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
Note 1. Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress only rating and operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not im-
plied. This device is sensitive to electrostatic discharge, users should follow proper IC han-
dling procedures.
Recommended Operating Conditions:
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40° to +85°C
DC Electrical Characteristics: VCC = 5V ±10%, TA = –40° to +85°C unless otherwise specified)
Parameter
Standby Supply Current
Operating Supply Current
Symbol
Test Conditions
Min
Typ
Max
10
4
Unit
I
I = 0, V = V or GND, V = 5V
–
–
µA
CC(SB)
CC(OP)
O
I
CC
CC
I
I
E = 1MHz, I = 0, V = V or GND,
–
–
mA
O
I
CC
V
CC
= 5.5V, Note 2
Data Retention Supply Current
V
CC
= 2V, I = 0, V = V or GND,
–
–
10
µA
CC(DR)
O
I
CC
E = V
CC
Data Retention Supply Voltage
Input Leakage Current
Output Leakage Current
Input Voltage, LOW
V
2.0
–
–
–
–
–
–
–
–
V
µA
µA
V
CC(DR)
I
I
V = V or GND, V = 5.5V
–1.0
–1.0
–0.3
+1.0
+1.0
+0.8
I
CC
CC
I
V = V or GND, V = 5.5V
OZ
O
CC
CC
V
IL
V
CC
V
CC
= 4.5V
Input Voltage, HIGH
V
IH
= 5.5V
V
–2
V
+0.3
V
CC
CC
Output Voltage, LOW
Output Voltage, HIGH
V
I = 3.2mA, V = 4.5V
–
0.4
V
OL
OH
O
CC
V
I = –0.4mA, V = 4.5V
2.4
–
V
O
CC
Note 2. Typical derating 1.5mA/MHz increase in ICC(OP)
.
Capacitance: (TA = +25°C unless otherwise specified)
Parameter
Input Capacitance
Output Capacitance
Symbol
Test Conditions
Min
Typ Max Unit
C
I
–
–
–
–
6
pF
pF
f = 1MHz, All measurements are ref-
erenced to device GND
C
O
10
AC Electrical Characteristics: VCC = 5V ±10%, TA = –40° to +85°C unless otherwise specified)
Parameter
Chip Enable Access Time
Address Access Time
Symbol
Test Conditions
Min
Typ Max Unit
TELQV Note 3, Note 5
TAVQV Note 3, Note 5, & Note 6
TELQX Note 4, Note 5
TWLQZ Note 4, Note 5
TEHQZ Note 4, Note 5
TELEH Note 3, Note 5
TEHEL Note 3, Note 5
TAVEL Note 3, Note 5
TELAX Note 3, Note 5
TDVWH Note 3, Note 5
TWHDX Note 3, Note 5
TWLEH Note 3, Note 5
TELWH Note 3, Note 5
TWLWH Note 3, Note 5
TELEL Note 3, Note 5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
300
300
160
160
160
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
Chip Enable Output Enable Time
Write Enable Output Disable Time
Chip Enable Output Disable Time
Chip Enable Pulse Negative Width
Chip Enable Pulse Positive Width
Address Setup Time
5
–
–
300
100
0
–
–
Address Hold Time
50
110
0
–
Data Setup Time
–
Data Hold Time
–
Chip Enable Write Pulse Setup Time
Chip Enable Write Pulse Hold Time
Write Enable Pulse Width
Read or Write Cycle Time
130
130
130
350
–
–
–
–
Note 3. Input pulse levels: 0.8V to VCC –2V; Input rise and fall times: 5ns (max); Input and output
timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) – for CL
greater than 50pF, access time is derated by 0.15ns per pF.
Note 4. Tested at initial design and after major design changes.
Note 5. VCC = 4.5V and 5.5V.
Note 6. TAVQV = TELQV + TAVEL.
Read Cycle Truth Table:
Inputs
Outputs
E
W
X
A
X
V
X
X
X
X
V
D
X
X
X
X
X
X
X
Q
Z
Z
X
V
V
Z
Z
Time Reference
Function
Memory Disabled
–1
0
H
H
H
H
H
X
Cycle Begins, Addresses are Latched
Output Enables
1
L
L
2
Output Valid
3
Read Accomplished
4
H
Prepare for Next Cycle (Same as –1)
Cycle Ends, Next Cycle Begins (Same as 0)
5
H
In the NTE6508 Read Cycle, the address information is latched into the on chip registers on the falling
edge of E (T = 0). Minimum address setup and hold time requirements must be met. After the required
hold time, the addresses may change state without affecting device operation. During time (T = 1)
the data output becomes enabled; however, the data is not valid until during time (T = 2). W must
remain high for the read cycle. After the output data has been read, E may return high (T = 3). This
will disable the chip and force the output buffer to a high impedance state. After the required E high
time (TEHEL) the RAM is ready for the next memory cycle (T = 4).
Write Cycle Truth Table:
Inputs
Outputs
E
W
X
A
X
V
X
X
X
X
V
D
X
X
X
V
X
X
X
Q
Z
Z
Z
Z
Z
Z
Z
Time Reference
Function
Memory Disabled
–1
0
H
X
Cycle Begins, Addresses are Latched
Write Period Begins
1
L
L
2
Data is Written
3
H
X
X
Write Completed
4
H
Prepare for Next Cycle (Same as –1)
Cycle Ends, Next Cycle Begins (Same as 0)
5
The write cycle is initiated by the falling edge of E which latches the address information into the on
chip registers. The write portion of the cycle is defined as both E and W being low simultaneously.
W may go low anytime during the cycle provided that the write enable pulse setup time (TWLEH) is
met. The write portion of the cycle is terminated by the first rising edge of either E or W. Data setup
and hold times must be referenced to the terminating signal.
If a series of consecutive write cycles are to be performed, the W line may remain low until all desired
locations have been written. When this method is used, data setup and hold times must be referenced
to the rising edge of E. By positioning the W pulse at different times within the E low time (TELEH),
various types of write cycles may be performed.
If the E low time (TELEH) is greater than the W pulse (TWLWH) plus an output enable time (TELQX),
a combination read write cycle is executed. Data may be modified an indefinite number of times dur-
ing any write cycle (TELEH). The data input and data output pins may be tied together for use with
a common I/O data bus structure. When using the RAM in this method allow a minimum of one output
disable time (TWLQZ) after W goes low before applying input data to the bus. This will insure that
the output buffers are not active.
Pin Connection Diagram
E
1
16 V
CC
A0
A1
2
3
15 D
14
W
A2
A3
4
5
13 A9
12
A8
A4
Q
6
7
8
11 A7
10 A6
GND
9
A5
16
9
8
1
.870 (22.0)
Max
.260 (6.6)
Max
.200 (5.08)
Max
.100 (2.54)
.099 (2.5) Min
.700 (17.78)
相关型号：
NTE68
Silicon Complementary Transistors General Purpose High Power Audio, Disk Head Positioner for Linear Applications
NTE
©2020 ICPDF网 联系我们和版权申明