NJU6645CJ_技术文档

Preliminar

NJU6645

16-CHARACTER 6-LINE LCD

DRIVER with JAPANESE KANJI ROM

ꢀ GENERAL DESCRIPTION

ꢀ PACKAGE OUTLINE

The NJU6645 is a 16-character 6-line (16x16dots size

Japanese Kanji) or 96 x 256 dots LCD driver with

Japanese Kanji ROM.

It contains 8-bit parallel or serial interface, instruction

decoder, character generator ROM/RAM, common and

segment drivers, bleeder resistor and voltage booster.

The NJU6645 supports the character font of JIS level-1

and level-2, non-kanji and half-size character and symbol.

It is suitable for the low operation voltage and low power

applications by low operating voltage 2.4 to 3.6V.

NJU6645CJ

ꢀ FEATURES

ꢀ

16-character 6-line Kanji Character Display or 96 x 256 dots Graphic Display LCD controller driver

LCD Driver Output : 96-common x 256-segment + 2-icon com

8-bit Parallel Interface

Serial Interface

Display Data RAM

1,536 bits

at Full-size 96 Characters

Character Generator ROM

:JIS Level-1 Kanji 16 x 16 dots 2,965 fonts

:JIS Level-2 Kanji 16 x 16 dots 3,388 fonts

:JIS Non-Kanji

:Half Size Display

24,576 bits

16 x 16 dots 524 fonts

8 x 16 dots 256 fonts

8 x 16 dots 192 fonts

Maximum 512 icons

ꢀ

Character Generator RAM

Icon Display RAM

Duty Ratio

512 bits

1/18, 1/34, 1/50, 1/66, 1/82, 1/98 (Programmable)

1/4 ~ 1/11 (Programmable)

Bias Ratio

Common and Segment driver Location order Select Function (Programmable)

Common Wiring Select Function

Useful Instruction Set

RE Flag Set, Status Read, Display Clear, Cursor Home, Display Control,

Stand-by, Cursor Control, Display / Entry Mode, Scroll Start Line,

Scroll Start Row, Display Start Line, Display Duty Ratio, N-line inversion,

Driver Output Control, Oscillation Control, Discharge, Boost Level,

Bias Ratio, Electrical Volume, Power Control, RAM Address Set,

Address Shift, RAM Data Writing / Reading

2 to 6-time

ꢀ

Built-in Voltage Boost

Built-in Electrical Volume

Oscillation Circuit

128-step

External Resistor Required

Built-in Bleeder Resistor

Operating Voltage

+2.4 to 3.6V

+4.5 to 17.0V

-40 to +85°C

LCD Driving Voltage

Operation Temperature Range

C-MOS Technology (P-sub )

Package Outline

Bump Chip

Ver.2009-05-20

- 1 -

Preliminar

NJU6645

ꢀ PAD ALIGNMENT

ALI_B1

ALI_A2

316:DUMMY91

317:DUMMY92

318:DUMMY93

319:SEG255

260:DUMMY84

259:DUMMY83

258:DUMMY82

257:C5-

256:C5-

320:SEG254

X

Y

TOP VIEW

NJU6645

573:SEG1

574:SEG0

575:DUMMY94

576:DUMMY95

5:DUMMY4

4:TESTOUT

3:DUMMY3

2:DUMMY2

577:DUMMY96

ALI_B2

1:DUMMY1

ALI_A1

Chip Size

: 14.16mm x 3.16mm (T.B.D.)

Chip Center

Pad Pitch

Bump Height

: X=0µm, Y=0µm

Chip Thickness : 625µm 25µm

: 50µm pitch

Bump Size

: 31µm x 130µm

: 17.5µm(Typ.)

Bump Material

: Au

Ver.2009-05-20

- 2 -

Preliminar

NJU6645

Alignment Mark

- Type A

Center Coordinates : ALI_A1 (X, Y) = (-6682, -1447)

: ALI_A2 (X, Y) = (6682, -1447)

70µm

- Type B

Center Coordinates : ALI_B1 (X, Y) = (6710, 1427)

: ALI_B2 (X, Y) = (-6710, 1427)

70µm

Ver.2009-05-20

- 3 -

Preliminar

NJU6645

ꢀ PAD COORDINATES 1

Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm)

PAD No. PAD name

X= µm

-6475

Y= µm

-1412.5

PAD No. PAD name

X= µm

-3975

Y= µm

-1412.5

1

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

DUMMY1

DUMMY2

DUMMY3

TESTOUT

DUMMY4

DUMMY5

SEL68

DUMMY27

D3

2

-6425

-6375

-6325

-6275

-6225

-6175

-6125

-6075

-6025

-5975

-5925

-5875

-5825

-5775

-5725

-5675

-5625

-5575

-5525

-5475

-5425

-5375

-5325

-5275

-5225

-5175

-5125

-5075

-5025

-4975

-4925

-4875

-4825

-4775

-4725

-4675

-4625

-4575

-4525

-4475

-4425

-4375

-4325

-4275

-4225

-4175

-4125

-4075

-4025

-1412.5

-3925

-3875

-3825

-3775

-3725

-3675

-3625

-3575

-3525

-3475

-3425

-3375

-3325

-3275

-3225

-3175

-3125

-3075

-3025

-2975

-2925

-2875

-2825

-2775

-2725

-2675

-2625

-2575

-2525

-2475

-2425

-2375

-2325

-2275

-2225

-2175

-2125

-2075

-2025

-1975

-1925

-1875

-1825

-1775

-1725

-1675

-1625

-1575

-1525

-1412.5

3

D3

4

DUMMY28

DUMMY29

D4

5

6

7

D4

8

DUMMY6

VPUP

DUMMY30

DUMMY31

D5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

DUMMY7

PS

D5

DUMMY8

VPUP

DUMMY32

DUMMY33

D6/SCL

DUMMY34

DUMMY35

D7/SDA

DUMMY36

OSC2

DUMMY9

CSEL

DUMMY10

DUMMY11

RSTb

DUMMY12

DUMMY13

CSb

OSC2

CSb

DUMMY37

VDD

DUMMY14

DUMMY15

RS

VDD

RS

VDD

DUMMY16

VPDN

VDD

DUMMY17

WRb/RW

DUMMY18

DUMMY19

RDb/E

DUMMY38

OSC1

DUMMY39

VSS

RDb/E

VSS

DUMMY20

VPUP

VSS

DUMMY21

D0

VSS

DUMMY40

DUMMY41

VLCD

D0

DUMMY22

DUMMY23

D1

VLCD

D1

VLCD

DUMMY24

DUMMY25

D2

VLCD

DUMMY42

DUMMY43

V1

D2

DUMMY26

Ver.2009-05-20

- 4 -

Preliminar

NJU6645

ꢀ PAD COORDINATES 2

Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm)

PAD No. PAD name

X= µm

-1475

Y= µm

-1412.5

PAD No. PAD name

X= µm

1025

Y= µm

-1412.5

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

V1

VSS

V1

-1425

-1375

-1325

-1275

-1225

-1175

-1125

-1075

-1025

-975

-925

-875

-825

-775

-725

-675

-625

-575

-525

-475

-425

-375

-325

-275

-225

-175

-125

-75

-1412.5

VSS

1075

1125

1175

1225

1275

1325

1375

1425

1475

1525

1575

1625

1675

1725

1775

1825

1875

1925

1975

2025

2075

2125

2175

2225

2275

2325

2375

2425

2475

2525

2575

2625

2675

2725

2775

2825

2875

2925

2975

3025

3075

3125

3175

3225

3275

3325

3375

3425

3475

-1412.5

V1

DUMMY58

DUMMY59

VOUT

DUMMY103

DUMMY104

VDCOUT

DUMMY60

DUMMY61

VEE

V1

DUMMY44

DUMMY45

V2

DUMMY46

DUMMY47

V3

DUMMY48

DUMMY49

V4

VEE

V4

VEE

V4

VEE

DUMMY50

DUMMY51

VREG

DUMMY52

DUMMY53

VREF

DUMMY54

DUMMY55

VBA

VEE

DUMMY62

DUMMY63

C1+

-25

25

C1+

75

C1+

125

C1+

175

C1+

225

C1+

275

DUMMY64

DUMMY65

C1-

325

375

425

C1-

475

C1-

525

C1-

VBA

575

C1-

VBA

625

C1-

VBA

675

DUMMY66

DUMMY67

C2+

DUMMY56

DUMMY57

VSS

725

775

825

C2+

VSS

875

C2+

VSS

925

C2+

VSS

975

C2+

Ver.2009-05-20

- 5 -

Preliminar

NJU6645

ꢀ PAD COORDINATES 3

Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm)

PAD No. PAD name

X= µm

3525

Y= µm

-1412.5

PAD No. PAD name

X= µm

Y= µm

-1412.5

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

C2+

DUMMY81

C5-

6025

DUMMY68

DUMMY69

C2-

3575

3625

3675

3725

3775

3825

3875

3925

3975

4025

4075

4125

4175

4225

4275

4325

4375

4425

4475

4525

4575

4625

4675

4725

4775

4825

4875

4925

4975

5025

5075

5125

5175

5225

5275

5325

5375

5425

5475

5525

5575

5625

5675

5725

5775

5825

5875

5925

5975

-1412.5

6075

6125

-1412.5

-1352

-1302

-1252

-1202

-1152

-1102

-1052

-1002

-952

-902

-852

-802

-752

-702

-652

-602

-552

-502

-452

-402

-352

-302

-252

-202

-152

-102

-52

C5-

6175

C2-

C5-

6225

C2-

C5-

6275

C2-

C5-

6325

C2-

DUMMY82

DUMMY83

DUMMY84

DUMMY85

DUMMY86

DUMMY87

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COM64

COM65

COM66

COM67

COM68

COM69

COM70

COM71

COM72

COM73

COM74

COM75

COM76

COM77

COM78

COM79

COM80

COM81

COM82

COM83

COM84

6375

C2-

6425

DUMMY70

DUMMY71

C3+

6475

6918.5

C3+

DUMMY72

DUMMY73

C3-

DUMMY74

DUMMY75

C4+

DUMMY76

DUMMY77

C4-

-2

C4-

48

C4-

98

C4-

148

DUMMY78

DUMMY79

C5+

198

248

298

C5+

348

C5+

398

C5+

448

C5+

498

C5+

548

DUMMY80

598

Ver.2009-05-20

- 6 -

Preliminar

NJU6645

ꢀ PAD COORDINATES 4

Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm)

Y= µm PAD No. PAD name X= µm Y= µm

4775 1412.5

PAD No. PAD name

X= µm

6918.5

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

COM85

COM86

COM87

COM88

COM89

COM90

COM91

COM92

COM93

COM94

COM95

COMMK1

DUMMY88

DUMMY89

DUMMY90

DUMMY91

DUMMY92

DUMMY93

SEG255

SEG254

SEG253

SEG252

SEG251

SEG250

SEG249

SEG248

SEG247

SEG246

SEG245

SEG244

SEG243

SEG242

SEG241

SEG240

SEG239

SEG238

SEG237

SEG236

SEG235

SEG234

SEG233

SEG232

SEG231

SEG230

SEG229

SEG228

SEG227

SEG226

SEG225

SEG224

648

698

748

SEG223

SEG222

SEG221

SEG220

SEG219

SEG218

SEG217

SEG216

SEG215

SEG214

SEG213

SEG212

SEG211

SEG210

SEG209

SEG208

SEG207

SEG206

SEG205

SEG204

SEG203

SEG202

SEG201

SEG200

SEG199

SEG198

SEG197

SEG196

SEG195

SEG194

SEG193

SEG192

SEG191

SEG190

SEG189

SEG188

SEG187

SEG186

SEG185

SEG184

SEG183

SEG182

SEG181

SEG180

SEG179

SEG178

SEG177

SEG176

SEG175

SEG174

6918.5

6525

4725

4675

4625

4575

4525

4475

4425

4375

4325

4275

4225

4175

4125

4075

4025

3975

3925

3875

3825

3775

3725

3675

3625

3575

3525

3475

3425

3375

3325

3275

3225

3175

3125

3075

3025

2975

2925

2875

2825

2775

2725

2675

2625

2575

2525

2475

2425

2375

2325

1412.5

798

848

898

948

998

1048

1098

1148

1198

1248

1298

1348

1412.5

6475

6425

6375

6325

6275

6225

6175

6125

6075

6025

5975

5925

5875

5825

5775

5725

5675

5625

5575

5525

5475

5425

5375

5325

5275

5225

5175

5125

5075

5025

4975

4925

4875

4825

Ver.2009-05-20

- 7 -

Preliminar

NJU6645

ꢀ PAD COORDINATES 5

Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm)

Y= µm PAD No. PAD name X= µm Y= µm

1412.5 1412.5

PAD No. PAD name

X= µm

2275

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

460

461

462

463

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

SEG173

SEG172

SEG171

SEG170

SEG169

SEG168

SEG167

SEG166

SEG165

SEG164

SEG163

SEG162

SEG161

SEG160

SEG159

SEG158

SEG157

SEG156

SEG155

SEG154

SEG153

SEG152

SEG151

SEG150

SEG149

SEG148

SEG147

SEG146

SEG145

SEG144

SEG143

SEG142

SEG141

SEG140

SEG139

SEG138

SEG137

SEG136

SEG135

SEG134

SEG133

SEG132

SEG131

SEG130

SEG129

SEG128

SEG127

SEG126

SEG125

SEG124

SEG123

SEG122

SEG121

SEG120

SEG119

SEG118

SEG117

SEG116

SEG115

SEG114

SEG113

SEG112

SEG111

SEG110

SEG109

SEG108

SEG107

SEG106

SEG105

SEG104

SEG103

SEG102

SEG101

SEG100

SEG99

SEG98

SEG97

SEG96

SEG95

SEG94

SEG93

SEG92

SEG91

SEG90

SEG89

SEG88

SEG87

SEG86

SEG85

SEG84

SEG83

SEG82

SEG81

SEG80

SEG79

SEG78

SEG77

SEG76

SEG75

SEG74

-225

-275

-325

2225

2175

2125

2075

2025

1975

1925

1875

1825

1775

1725

1675

1625

1575

1525

1475

1425

1375

1325

1275

1225

1175

1125

1075

1025

975

1412.5

-375

-425

-475

-525

-575

-625

-675

-725

-775

-825

-875

-925

-975

-1025

-1075

-1125

-1175

-1225

-1275

-1325

-1375

-1425

-1475

-1525

-1575

-1625

-1675

-1725

-1775

-1825

-1875

-1925

-1975

-2025

-2075

-2125

-2175

-2225

-2275

-2325

-2375

-2425

-2475

-2525

-2575

-2625

-2675

925

875

825

775

725

675

625

575

525

475

425

375

325

275

225

175

125

75

25

-25

-75

-125

-175

Ver.2009-05-20

- 8 -

Preliminar

NJU6645

ꢀ PAD COORDINATES 6

Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm)

PAD No. PAD name

X= µm

-2725

Y= µm

1412.5

PAD No. PAD name

X= µm

Y= µm

1412.5

501

502

503

504

505

506

507

508

509

510

511

512

513

514

515

516

517

518

519

520

521

522

523

524

525

526

527

528

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547

548

549

550

551

552

553

554

555

556

557

558

559

560

561

562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580

581

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596

597

598

599

600

SEG73

SEG72

SEG71

SEG70

SEG69

SEG68

SEG67

SEG66

SEG65

SEG64

SEG63

SEG62

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

-5225

-2775

-2825

-2875

-2925

-2975

-3025

-3075

-3125

-3175

-3225

-3275

-3325

-3375

-3425

-3475

-3525

-3575

-3625

-3675

-3725

-3775

-3825

-3875

-3925

-3975

-4025

-4075

-4125

-4175

-4225

-4275

-4325

-4375

-4425

-4475

-4525

-4575

-4625

-4675

-4725

-4775

-4825

-4875

-4925

-4975

-5025

-5075

-5125

-5175

1412.5

SEG22

-5275

-5325

1412.5

1348

SEG21

SEG20

-5375

SEG19

-5425

SEG18

-5475

SEG17

-5525

SEG16

-5575

SEG15

-5625

SEG14

-5675

SEG13

-5725

SEG12

-5775

SEG11

-5825

SEG10

-5875

SEG9

-5925

SEG8

-5975

SEG7

-6025

SEG6

-6075

SEG5

-6125

SEG4

-6175

SEG3

-6225

SEG2

-6275

SEG1

-6325

SEG0

-6375

DUMMY94

DUMMY95

DUMMY96

DUMMY97

DUMMY98

DUMMY99

COM47

COM46

COM45

COM44

COM43

COM42

COM41

COM40

COM39

COM38

COM37

COM36

COM35

COM34

COM33

COM32

COM31

COM30

COM29

COM28

-6425

-6475

-6525

-6918.5

1298

1248

1198

1148

1098

1048

998

948

898

848

798

748

698

648

598

548

498

448

398

348

298

248

Ver.2009-05-20

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Preliminar

NJU6645

ꢀ PAD COORDINATES 7

Chip Size 14.16mm x 3.16mm (Chip Center X=0µm, Y=0µm)

PAD No. PAD name

X= µm

-6918.5

Y= µm

PAD No. PAD name

X= µm

Y= µm

601

602

603

604

605

606

607

608

609

610

611

612

613

614

615

616

617

618

619

620

621

622

623

624

625

626

627

628

629

630

631

632

COM27

COM26

COM25

COM24

COM23

COM22

COM21

COM20

COM19

COM18

COM17

COM16

COM15

COM14

COM13

COM12

COM11

COM10

COM9

198

-6918.5

148

98

48

-2

-52

-102

-152

-202

-252

-302

-352

-402

-452

-502

-552

-602

-652

-702

-752

-802

-852

-902

-952

-1002

-1052

-1102

-1152

-1202

-1252

-1302

-1352

COM8

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

COMMK0

DUMMY100

DUMMY101

DUMMY102

Ver.2009-05-20

- 10 -

Preliminar

NJU6645

ꢀ LCD DISPLAY EXAMPLE

- Mix display (Full-size / Half-size / Graphics)

Ver.2009-05-20

- 11 -

Preliminar

NJU6645

ꢀ BLOCK DIAGRAM

Address

Counter

Display

Counter

N-line

Inversion

PS

SEL68

CSb

RS

Display Data RAM(DD RAM)

1,536-bit

Graphics

Counter

COM0~

COM95,

COMM0,

COMM1

WRb/RW

RDb/E

D7/SDA

D6/SCL

D5~D0

CSEL

Full/Half/ODD/EVEN

Discrimination Circuit

TESTOUT

Character

Icon Display

SEG0~

Generator ROM

(Full-size FCGROM)

2M-bit

Generator

RAM

(MKRAM)

512-bit

SEG255

Reset

Circuit

RAM(CGRAM)

24,576-bit

RSTb

(Half-size HCGROM)

32k-bit

OSC1

OSC2

Oscillator

Circuit

Timing

Generator

VDD

VSS

VPUP

VPDN

Attribute, Cursor,

Inversion

Reference

Voltage

VBA

VOUT

VREG

+

-

+

-

VLCD

V1

VREF

+

-

+

-

Gain

Control

+

-

V2

E.V.R.

+

-

V3

+

-

V4

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

Boost Level

Register

E.V.R. Register

Voltage

Booster

VEE

VDCOUT

Ver.2009-05-20

- 12 -

Preliminar

NJU6645

ꢀ TERMINAL DESCRIPTION

No.

SYMBOL

VDD

I/O

FUNCTION

Power Supply (Logic, I/F)

VDD=2.4 to 3.6V

74 to 79

Power

84 to 89,

147 to 152

141 to 144

135 to 138

128 to 132

GND (Logic, I/F, High voltage)

Power

VSS

VSS=0V

Reference-Voltage Generator Output

Voltage Regulator Input

VBA

VREF

VREG

Output

Input

Output

Voltage Regulator Output

Voltage Booster Input

172 to 177

VEE

Power

Output

VEE is normally connected to VDD.

High Voltage Power Supply Input (External supply)

Input of LCD power supply circuit.

Voltage Booster Output

155 to 160

VOUT

163 to 169 VDCOUT

Output of voltage booster circuit.

LCD Bias Voltages

92 to 97

100 to 104

107 to 111

114 to 118

VLCD

V1

V2

V3

When the internal LCD power supply is used, internal LCD bias

voltages (VLCD and V1~V4) are activated by the “Power Control”

instruction. Stabilizing capacitors are required between each bias

voltage and VSS.

Power/

Output

When the external LCD power supply is used, LCD bias voltages are

externally supplied on VLCD, V1, V2, V3 and V4 individually, with the

following relation maintained :

121 to 125

V4

VSS<V4<V3<V2<V1<VDD

VPUP is internally connected to VDD to fix SEL68 or PS or CSEL to “H” if

necessary, and cannot be used as main power supply.

VPUP should be open if not used.

Power/

Output

9,13,38

29

VPUP

VPDN

VPDN is internally connected to VSS to fix SEL68 or PS or CSEL to “L” if

necessary, and cannot be used as main GND.

Power/

Output

VPDN should be open if not used.

Capacitor Connection for Voltage Booster

180 to 185

188 to 193

196 to 201

204 to 209

212 to 217

220 to 225

228 to 233

236 to 241

244 to 249

252 to 257

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

Output

Resistor Connection for Oscillation Circuit

81,82

OSC1

Input

When the internal oscillator is used, connect OSC1 and VDD with an

external resistor. And fix OSC2 to “H” or “L”.

External Clock Input

71,72

18,19

15

OSC2

RSTb

CSEL

Input

When the internal oscillator is not used, input external clock to OSC2

and leave OSC1 open.

Reset

Active “L”

COM Output Select

“L” : Both sides wiring

“H” : Comb wiring

Ver.2009-05-20

- 13 -

Preliminar

NJU6645

No.

11

SYMBOL

I/O

FUNCTION

Parallel / Serial Interface Mode Select

“L” : Serial Interface

“H” : Parallel Interface

PS

Input

*In the serial interface mode (PS=”L”)

D5 to D0 should be fixed to “H” or “L”.

MPU Mode Select

Parallel Interface (PS=”H”)

“L” : 80-series

Input

7

SEL68

“H” : 68-series

Serial Interface (PS=”L”)

Not used. SEL68 should be fixed to “H” or “L”.

Chip Select

Input

22,23

26,27

CSb

RS

Active “L”

Register Select

This signal interprets transferred data as display data or instruction.

“L” : Instruction

“H” : Display Data

80-series MPU Interface (PS=”H”, SEL68=”L”)

Data Write (WRb) Signal

Active “L”

68-series MPU Interface (PS=”H”, SEL68=”H”)

Data Read or Write (RW) Signal

“L” : Write

Input

31,32

WRb/RW

RDb/E

“H” : Read

Serial Interface (PS=”L”)

Data Read or Write (RW) Signal

80-series MPU Interface (PS=”H”, SEL68=”L”)

Data Read (RDb) Signal

Active “L”

68-series MPU Interface (PS=”H”, SEL68=”H”)

Enable Signal

35,36

Active “H”

Serial Interface (PS=”L”)

Not used. RDb/E should be fixed to “H” or “L”.

Parallel Interface (PS=”H”)

In the parallel interface mode (PS=“H”), D7 to D0 are connected to 8-bit

bi-directional MPU bus.

68,69

64,65

60,61

56,57

52,53

48,49

44,45

40,41

D7/SDA

D6/SCL

D5

D7 to D0 : 8-bit Bi-directional Bus

Serial Interface (PS=”L”)

D4

Input/

Output

D3

D7 : Serial Data (SDA)

D2

D6 : Serial Clock (SCL)

D5 to D0 should be fixed to “H” or “L”.

D1

D0

Ver.2009-05-20

- 14 -

Preliminar

NJU6645

No.

SYMBOL

I/O

FUNCTION

SEG0~

Segment Drivers

319 to 574

Output

Segment drivers output an one level from VLCD, V2, V3 and VSS.

SEG255

264 to 311, COM0~

581 to 628 COM95

Common Drivers

Output

Common drivers output an one level from VLCD, V1, V4 and VSS.

Common Drivers for Icons

COMMK0,

COMMK1

629,312

Output

4

-

TESTOUT Output For Testing

Dummy PAD

DUMMYx

-

Dummy x is normally open.

Ver.2009-05-20

- 15 -

Preliminar

NJU6645

ꢀ FUNCTION DESCRIPTION

(1) MPU INTERFACE

(1-1) Selection of Parallel / Serial Interface Mode

The PS selects a parallel or a serial interface mode, as shown in Table 1.

Table 1 Selection of Parallel / Serial Interface Mode

PS

H

I/F Mode

Parallel I/F

Serial I/F

CSb

RS

RDb

-

WRb SEL68

SDA

SCL

Data

D7~D0

-

WRb

-

L

Note) “-“ : Fix to ”H” or ”L”

(1-2) Data Recognition

The data from MPU is interpreted as display data or instruction according to the combination of the RS, RDb

and WRb(RW) signals, as shown in Table 2.

Table 2 Data Recognition

Function

68-series

80-series

Serial

RS

RW

1

RDb

WRb

RW

1

0

1

0

1

0

1

0

1

0

Read Instruction

Write Instruction

Read Display Data

Write display Data

0

1

0

Ver.2009-05-20

- 16 -

Preliminar

NJU6645

(1-3) Selection of MPU Mode

In the parallel interface mode, the SEL68 selects 68 or 80-series MPU mode, as shown in Table 3.

Table 3 Selection of MPU Mode

SEL68

MPU Mode

68-series MPU

80-series MPU

CSb

RS

RDb

E

RDb

WRb

RW

WRb

Data

D7~D0

H

L

When the CSb signal is “H”, the interface is reset. The data of one character is processed by writing two times.

In the DDRAM data writing, CSb is required to change to “H” once every two times. Because, it is

recognized as upper 1-byte after CSb is changed from “H” to “L”.

The data is latched at the rising edge of the WRb signal in the 80-series MPU mode, or at the falling edge of

the E signal in the 68-series MPU mode.

In the DDRAM read sequence, be sure to execute a dummy read right after setting an address or right after

writing display data or instruction. Therefore a dummy data is read out by the 1st “Display Data Read”

instruction. After that, the display data is read out from a specified address by the 2nd instruction. When the

RS switches, it should be CSb="H".

• 80-series parallel data transmission (PS=”H”, SEL68=”L”)

<Write>

RS

(Note) When the DDRAM data writing, CSb should be changed to "H" once every 2-byte.

CSb

WRb

D7~D0

(Data bus direction)

Input

<Read>

RS

CSb

RDb

D7~D0

1st reading out is dummy.

(Data bus direction)

Input

Output

Input

Output

Input

Output

Input

The data bus is output at CSb=”L” and RDb=”L”.

Ver.2009-05-20

- 17 -

Preliminar

NJU6645

• 68-series parallel data transmission (PS=”H”, SEL68=”H”)

<Write>

RS

RW

(Note) When the DDRAM data writing, CSb should be changed to "H" once every 2-byte.

CSb

E

D7~D0

(Data bus direction)

Input

<Read>

RS

RW

CSb

E

D7~D0

1st reading out is dummy.

(Data bus direction) Input

Output

Input

Output

Input

Output

Input

The data bus is output at RW=”H”, CSb=”L” and E=”H”.

Ver.2009-05-20

- 18 -

Preliminar

NJU6645

(1-4) Serial Interface

The serial interface is transmitted with 5-line. While the chip select is active (CSb=“L”), the SDA and SCL

are enabled. While the chip select is inactive (CSb=“H”), the SDA and SCL are disabled, and the internal shift

register and the internal counter are being initialized. The data is interpreted as writes or reads according to

the RS.

8-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of D7, D6,…, and D0, and

converted into 8-bit parallel data at the timing of the internal signal produced from the 8th SCL signal. The

data on the SDA is interpreted as display data or instruction according to the RS.

When the CSb signal is “H”, the interface is reset. The data of 1-character is processed by writing 2-byte. In

the DDRAM data writing, CSb is required to change to “H” once every 2-bytes. Because, it is recognized as

1-byte after CSb is changed from “H” to “L”.

Note that the SCL should be set to “L” right after data transmission or during non-access because the serial

interface is susceptible to external noises which may cause malfunctions.

In the read mode, selected address RAM data is read out after 1-dummy as for parallel interface. When the

RS and RW switches, it should be CSb="H".

Ver.2009-05-20

- 19 -

Preliminar

NJU6645

• Serial data transmission (PS=”L”)

<Write>

RW

(Data bus direction)

Input

The data bus is Input at RW=”L”.

RS

(Note) When the DDRAM data writing, CSb should be changed to "H" once every 2-byte.

CSb

SCL

SDA

<Read>

RW

(Data bus direction)

Output

Input

The data bus is output at RW=”H” and CSb=”L”.

RS

CSb

SCL

SDA

Ver.2009-05-20

- 20 -

Preliminar

NJU6645

(2) ADDRESS COUNTER

The NJU6645 has the address counter of 12-bit for read/write of RAM data. The address is set by "RAM

address set" instruction. In case of the RDM=”0”, the address is incremented after the RAM data writing and

reading. In case of the RDM=”1”, the address is incremented only after the RAM data writing. The address

doesn't change after the RAM data reading.

The address shifts as follows within range of the address DDRAM, MKRAM, and CGRAM. The DDRAM

address shifts in each line.

DDRAM (1-line)

DDRAM (2-line)

DDRAM (3-line)

DDRAM (4-line)

DDRAM (5-line)

DDRAM (6-line)

MKRAM

: (000)H → (001)H → --- → (01F)H → (000)H

: (020)H → (021)H → --- → (03F)H → (020)H

: (040)H → (041)H → --- → (05F)H → (040)H

: (060)H → (061)H → --- → (07F)H → (060)H

: (080)H → (081)H → --- → (09F)H → (080)H

: (0A0)H → (0A1)H → --- → (0BF)H → (0A0)H

: (100)H → (101)H → --- → (13F)H → (100)H

: (200)H → (201)H → --- → (DFF)H → (200)H

CGRAM

The address is shifted to +1 or -1 by "address shift (ARL)" instruction. When ARL="0" is input, whenever it

is input the address is shifted -1. When ARL="1" is input, whenever it is input the address is shifted +1. The

address shifts as follows within range of the address DDRAM, MKRAM and CGRAM.

DDRAM (1-line)

DDRAM (2-line)

DDRAM (3-line)

DDRAM (4-line)

DDRAM (5-line)

DDRAM (6-line)

MKRAM

: (000)H ↔ (001)H ↔ --- ↔ (01F)H ↔ (000)H

: (020)H ↔ (021)H ↔ --- ↔ (03F)H ↔ (020)H

: (040)H ↔ (041)H ↔ --- ↔ (05F)H ↔ (040)H

: (060)H ↔ (061)H ↔ --- ↔ (07F)H ↔ (060)H

: (080)H ↔ (081)H ↔ --- ↔ (09F)H ↔ (080)H

: (0A0)H ↔ (0A1)H ↔ --- ↔ (0BF)H ↔ (0A0)H

: (100)H ↔ (101)H ↔ --- ↔ (13F)H ↔ (100)H

: (200)H ↔ (201)H ↔ --- ↔ (DFF)H ↔ (200)H

CGRAM

Ver.2009-05-20

- 21 -

Preliminar

NJU6645

(3) DATA RAM

(3-1) RAM Address Map

Display Data RAM (DDRAM), Character Generator RAM(CGRAM), and Icon Data RAM(MKRAM) are

stored at the following addresses. The address is set in the address counter by "RAM address set" instruction.

RAM Address Map

RAM ADDRESS – UPPER 4bit

1H 2H

0H

---

DH

EH FH

00H

01H

02H

03H

*

3EH

3FH

40H

*

BEH

BFH

C0H

*

FEH

FFH

DDRAM address

(1 address = 11-bit)

MKRAM address

(1 address = 7-bit)

CGRAM address

(1 address = 8-bit)

--- DDRAM (Display Data RAM)

--- MKRAM (Icon RAM)

--- CGRAM (Character Generator RAM)

* : Invalid Data

Ver.2009-05-20

- 22 -

Preliminar

NJU6645

(3-2) DDRAM

Display Data RAM (DDRAM) is RAM that memorizes the attribute display data, data for the capital letters

and small letters distinction, and the character-code data. RAM address uses "000H" ~ "0BFH ". The RAM

Capacity has 192 addresses of 11-bit/address. At this time, the full-size data is using 2 addresses for a

character, and the half-size data is using one address for a character. In the DDRAM address and the position

where the panel is displayed, there are relations of the following.

Correspondence of display position on panel and DDRAM address (SEL1=”0", SEL2=”0")

1-digit

2-digit

3-digit

4-digit

5-digit

6-digit

7-digit

8-digit

9-digit

10-digit

11-digit 12-digit 13-digit

14-digit

15-digit

16-digit

1-line

2-line

3-line

4-line

5-line

6-line

000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F

020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 038 039 03A 03B 03C 03D 03E 03F

040 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058 059 05A 05B 05C 05D 05E 05F

060 061 062 063 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070 071 072 073 074 075 076 077 078 079 07A 07B 07C 07D 07E 07F

080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D 08E 08F 090 091 092 093 094 095 096 097 098 099 09A 09B 09C 09D 09E 09F

0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF

Correspondence of display position on panel and DDRAM address (SEL1=”1", SEL2=”0")

1-digit

2-digit

3-digit

4-digit

5-digit

6-digit

7-digit

8-digit

9-digit

10-digit

11-digit 12-digit 13-digit

14-digit

15-digit

16-digit

1-line

2-line

3-line

4-line

5-line

6-line

0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF

080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D 08E 08F 090 091 092 093 094 095 096 097 098 099 09A 09B 09C 09D 09E 09F

060 061 062 063 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070 071 072 073 074 075 076 077 078 079 07A 07B 07C 07D 07E 07F

040 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058 059 05A 05B 05C 05D 05E 05F

020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 038 039 03A 03B 03C 03D 03E 03F

000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F

Correspondence of display position on panel and DDRAM address (SEL1=”0", SEL2=”1")

1-digit

2-digit

3-digit

4-digit

5-digit

6-digit

7-digit

8-digit

9-digit

10-digit

11-digit 12-digit 13-digit

14-digit

15-digit

16-digit

1-line

2-line

3-line

4-line

5-line

6-line

01F 01E 01D 01C 01B 01A 019 018 017 016 015 014 013 012 011 010 00F 00E 00D 00C 00B 00A 009 008 007 006 005 004 003 002 001 000

03F 03E 03D 03C 03B 03A 039 038 037 036 035 034 033 032 031 030 02F 02E 02D 02C 02B 02A 029 028 027 026 025 024 023 022 021 020

05F 05E 05D 05C 05B 05A 059 058 057 056 055 054 053 052 051 050 04F 04E 04D 04C 04B 04A 049 048 047 046 045 044 043 042 041 040

07F 07E 07D 07C 07B 07A 079 078 077 076 075 074 073 072 071 070 06F 06E 06D 06C 06B 06A 069 068 067 066 065 064 063 062 061 060

09F 09E 09D 09C 09B 09A 099 098 097 096 095 094 093 092 091 090 08F 08E 08D 08C 08B 08A 089 088 087 086 085 084 083 082 081 080

0BF 0BE 0BD 0BC 0BB 0BA 0B9 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1 0B0 0AF 0AE0AD 0AC 0AB0AA 0A9 0A8 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0

Correspondence of display position on panel and DDRAM address (SEL1=”1", SEL2=”1")

1-digit

2-digit

3-digit

4-digit

5-digit

6-digit

7-digit

8-digit

9-digit

10-digit

11-digit 12-digit 13-digit

14-digit

15-digit

16-digit

1-line

2-line

3-line

4-line

5-line

6-line

0BF 0BE 0BD 0BC 0BB 0BA 0B9 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1 0B0 0AF 0AE0AD 0AC 0AB0AA 0A9 0A8 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0

09F 09E 09D 09C 09B 09A 099 098 097 096 095 094 093 092 091 090 08F 08E 08D 08C 08B 08A 089 088 087 086 085 084 083 082 081 080

07F 07E 07D 07C 07B 07A 079 078 077 076 075 074 073 072 071 070 06F 06E 06D 06C 06B 06A 069 068 067 066 065 064 063 062 061 060

05F 05E 05D 05C 05B 05A 059 058 057 056 055 054 053 052 051 050 04F 04E 04D 04C 04B 04A 049 048 047 046 045 044 043 042 041 040

03F 03E 03D 03C 03B 03A 039 038 037 036 035 034 033 032 031 030 02F 02E 02D 02C 02B 02A 029 028 027 026 025 024 023 022 021 020

01F 01E 01D 01C 01B 01A 019 018 017 016 015 014 013 012 011 010 00F 00E 00D 00C 00B 00A 009 008 007 006 005 004 003 002 001 000

Note) The DDRAM is not initialized after the power supply turns on, therefore it is necessary to execute the

"Display Clear instruction" at first.

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NJU6645

(3-3) CGRAM

The character generator RAM (CG RAM) stores any kinds of character pattern written by the user program to

display user’s original character pattern. RAM address uses "200H" to "DFFH". The CG RAM is able to store

character of 5 x 8 dot for 4 kinds. Data "1" correspond to selection as a display, and Data "0" correspond to

non-selection as a display. When the character pattern stored in CGRAM is displayed, "0100H" to “015FH"

of the character-code is written in DDRAM. The following tables show the relation between the CGRAM

address, data, and the displayed pattern.

Correspondence of character code and CGRAM address

“0100”

“0101”

“0102”

“0103”

“0104”

“0105”

“0106”

“0107”

“0108”

“0109”

“010A”

“010B”

“010C”

“010D”

“010E”

“010F”

200 210 220 230 240 250 260 270 280 290 2A0 2B0 2C0 2D0 2E0 2F0 300 310 320 330 340 350 360 370 380 390 3A0 3B0 3C0 3D0 3E0 3F0

CG

:

Address

20F 21F 22F 23F 24F 25F 26F 27F 28F 29F 2AF 2BF 2CF 2DF 2EF 2FF 30F 31F 32F 33F 34F 35F 36F 37F 38F 39F 3AF 3BF 3CF 3DF 3EF 3FF

“0110”

“0111”

“0112”

“0113”

“0114”

“0115”

“0116”

“0117”

“0118”

“0119”

“011A”

“011B”

“011C”

“011D”

“011E”

“011F”

400 410 420 430 440 450 460 470 480 490 4A0 4B0 4C0 4D0 4E0 4F0 500 510 520 530 540 550 560 570 580 590 5A0 5B0 5C0 5D0 5E0 5F0

CG

:

Address

40F 41F 42F 43F 44F 45F 46F 47F 48F 49F 4AF 4BF 4CF 4DF 4EF 4FF 50F 51F 52F 53F 54F 55F 56F 57F 58F 59F 5AF 5BF 5CF 5DF 5EF 5FF

“0120”

“0121”

“0122”

“0123”

“0124”

“0125”

“0126”

“0127”

“0128”

“0129”

“012A”

“012B”

“012C”

“012D”

“012E”

“012F”

600 610 620 630 640 650 660 670 680 690 6A0 6B0 6C0 6D0 6E0 6F0 700 710 720 730 740 750 760 770 780 790 7A0 7B0 7C0 7D0 7E0 7F0

CG

:

Address

60F 61F 62F 63F 64F 65F 66F 67F 68F 69F 6AF 6BF 6CF 6DF 6EF 6FF 70F 71F 72F 73F 74F 75F 76F 77F 78F 79F 7AF 7BF 7CF 7DF 7EF 7FF

“0130”

“0131”

“0132”

“0133”

“0134”

“0135”

“0136”

“0137”

“0138”

“0139”

“013A”

“013B”

“013C”

“013D”

“013E”

“013F”

800 810 820 830 840 850 860 870 880 890 8A0 8B0 8C0 8D0 8E0 8F0 900 910 920 930 940 950 960 970 980 990 9A0 9B0 9C0 9D0 9E0 9F0

CG

:

Address

80F 81F 82F 83F 84F 85F 86F 87F 88F 89F 8AF 8BF 8CF 8DF 8EF 8FF 90F 91F 92F 93F 94F 95F 96F 97F 98F 99F 9AF 9BF 9CF 9DF 9EF 9FF

“0140”

“0141”

“0142”

“0143”

“0144”

“0145”

“0146”

“0147”

“0148”

“0149”

“014A”

“014B”

“014C”

“014D”

“014E”

“014F”

A00 A10 A20 A30 A40 A50 A60 A70 A80 A90 AA0 AB0 AC0 AD0 AE0 AF0 B00 B10 B20 B30 B40 B50 B60 B70 B80 B90 BA0 BB0 BC0 BD0 BE0 BF0

CG

:

Address

A0F A1F A2F A3F A4F A5F A6F A7F A8F A9F AAF ABF ACF ADF AEF AFF B0F B1F B2F B3F B4F B5F B6F B7F B8F B9F BAF BBF BCF BDF BEF BFF

“0150”

“0151”

“0152”

“0153”

“0154”

“0155”

“0156”

“0157”

“0158”

“0159”

“015A”

“015B”

“015C”

“015D”

“015E”

“015F”

C00 C10 C20 C30 C40 C50 C60 C70 C80 C90 CA0 CB0 CC0 CD0 CE0 CF0 D00 D10 D20 D30 D40 D50 D60 D70 D80 D90 DA0 DB0 DC0 DD0 DE0 DF0

CG

:

Address

C0F C1F C2F C3F C4F C5F C6F C7F C8F C9F CAF CBF CCF CDF CEF CFF D0F D1F D2F D3F D4F D5F D6F D7F D8F D9F DAF DBF DCF DDF DEF DFF

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NJU6645

Relation between the CGRAM address, data, and the displayed pattern

Character Code =”0100” (DDRAM Data)

Character Code =”0101” (DDRAM Data)

Upper Address 8bit=20H

Upper Address 8bit=21H

Upper Address 8bit=22H

Upper Address 8bit=23H

0H

1H

2H

3H

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

---

Character Code =”0110” (DDRAM Data)

Upper Address 8bit=40H

Upper Address 8bit=41H

0H

1H

2H

3H

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

---

Note) The CGRAM is not initialized after the power supply turns on, therefore it is necessary to write data into

CGRAM before display on.

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NJU6645

(3-4) MKRAM

The icon display generator RAM (MK RAM) is RAM that stores 512 output ON/OFF settings. RAM address

uses "100H" to "13FH". By storing data in this RAM, ON/OFF of each icon is set. Data "1" correspond to

selection as a display, and Data "0" correspond to non-selection as a display.

Correspondence of SEG/COM terminals and MKRAM address (SEL1=”0", SEL2=”0")

SEG

0

:

8

:

16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248

:

7

15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 231 239 247 255

MK

COM0

MK

100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F

120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F

COM1

Correspondence of SEG/COM terminals and each bit of MKRAM address (SEL1=”0", SEL2=”0”)

---

MK

---

Address=100H

Address=120H

Address=101H

Address=121H

Address=102H

Address=122H

Address=103H

Address=123H

Address=11FH

Address=13FH

COM0

MK

---

COM1

Note) The MKRAM is not initialized after the power supply turns on, therefore it is necessary to write data into

CGRAM before display on.

Note) Correspondence to the SEG/COM terminals are changed by the “Driver Output Control instruction” (SEL1,

SEL2). Refer to “(9) COMMON SHIFT DIRECTION / SEGMENT OUTPUT DIRECTION” for details.

Note) When the "Display Control instruction" is ALLON="1", display is all ON regardless of the content of RAM.

(3-5) FCGROM (Full-size font ROM)

Full-size font character generator ROM (FCGROM) generates 16 x 16 dots character pattern represented in

14-bit character codes. The NJU6645 has the Full-size font pattern of 8,128-font such as the JIS level-1,

level-2 and non-kanji. Refer to “(14) Full-size / Half-size Font Mix Display” for the correspondence of the

JIS code and the character code set to DDRAM.

(3-6) HCGROM (Half-size font ROM)

Half-size font character generator ROM (FCGROM) generates 8 x 16 dots character pattern represented in

8-bit character codes. The NJU6645 has the Half-size font pattern of 256-font. Refer to “(14) Full-size /

Half-size Font Mix Display” for the correspondence of the character code set to DDRAM.

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NJU6645

(3-7) Correspondence of the JIS Code, Input Data, RAM Data and RAM Address

(3-7-1) Write Data to DDRAM

(i) Half-size font character

The half-size data becomes the data of one character by the input data of 2-byte, and it is stored at one RAM

address. When the lower 6-bit of 1st byte is all “0”, it is recognized as half-size data. The attribute data is

allocated in upper 2-bit in the 1st input byte. When the half-size font, “1” is stored in the MSB of RAM data

as full-size/half-size discrimination bit.

1^stbyte

2^ndbyte

Half-size discrimination code

Half-size character code 8bit

Input Data

ALL”0” → D10=”1”

Character code 8bit

DDRAM

DDRAM address

n

Note) When the full-size character is overwritten by half-size character, the character is displayed unexpected.

Therefore, when the full-size character is overwritten by half-size character, it must write two character's

equivalent or rewrite all character.

- Prohibited matter

(1) In the 32nd half-size character of each line (right edge) prohibit overwriting the full-size character.

(2) In the only half left of full-size character prohibit overwriting the half-size character.

(3) In the only half right of full-size character prohibit overwriting the half-size (full-size) character.

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(ii) Full-size font character

The full-size data becomes the data of 1-character by the input data of 2-byte, and it is stored at two RAM

address. The attribute data is allocated in upper 2-bit in the 1st input byte. When the full-size font, “0” is

stored in the MSB of RAM data as Full-size/half-size discrimination bit. And, “0” or “1” is stored in the 2nd

bit of RAM as 1st byte/2nd byte discrimination data. (1st bit : “0”, 2nd bit : “1”)

The character code is 14-bit stuffed into the lower bit excluding 1-bit (code : ”0”) and 9-bit (code : ”0”) of JIS

codes (16-bit).

The relation between each bit allocation of JIS code and input data and the RAM is as follows.

0

JIS code upper 7bit

0

JIS code lower 7bit

JIS code

1^stbyte

2^ndbyte

Full-size character code 14bit

Input data

In case of 2nd byte

→ D9=”1”

In case of 1st byte

→ D9=”0”

Except for ALL”0”

→ D10=”0”

Character code upper 6bit

n

Character code lower 8bit

DDRAM

DDRAM address

n+1

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When the DDRAM is written, the address is incremented as follows once a 1-byte in case of the full-size data,

and once a 2-byte in case of the half-size data.

Full-size character data

1st byte 2nd byte

Half-size character data

3rd byte 4th byte

Full-size character data

5th byte 6th byte

- - -

Input data

DDRAM

address

- - -

n

n+1

n+2

n+3

n+4

The data is recognized without fail as the first byte, immediately after CSb becomes “L”. Therefore, when the

DDRAM data is written, it is necessary to make CSb = ”H” after it finishes writing the 2nd byte.

CSb

RS

WRb

D7~D0

n

n+1

n+2

n+3

n+4

n+5

Address Set n

m^thcharacter data

m+1^thcharacter data

m+2^thcharacter data

(3-7-2) Write Data to CGRAM

The CGRAM has 8-bit per an address, and the input value is stored in each bit as follows. The address is

incremented once a 1-byte at the data writing.

Relation between the interface, RAM data, and RAM address, in the CGRAM data writing

1st byte

2nd byte

3rd byte

- - -

Input data

- - -

RAM data

CGRAM

address

200H

201H

202H

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NJU6645

(3-7-3) Write Data to MKRAM

The CGRAM has 8-bit per an address, and the input value is stored in each bit as follows. The address is

incremented once a 1-byte at the data writing.

Relation between the interface, RAM data, and RAM address, in the MKRAM data writing

1st byte

2nd byte

3rd byte

- - -

Input data

- - -

RAM data

MKRAM

address

100H

101H

102H

(3-7-4) Write to Instruction Register

The instruction set is stored in the internal instruction register by the 8-bit input in the state of RS=”0”,

RW=”0”. The instruction code is applied to the item corresponding to the RE register set beforehand. Refer to

"(20) Instruction table" for the correspondence of input data and the instruction.

Write to instruction Register

Instruction data

Instruction code

Input data

Instruction

register

Instruction

discrimination

Instruction

register

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NJU6645

(3-8) Read Data from RAM

The data is read out from DDRAM, CGRAM, and MKRAM. When reading data from the RAM, it is

necessary to read after the address setting. The dummy reading is necessary right after the address setting.

After read out, the address is incremented automatically according to the entry mode.

(Note) When the DDRAM data reading, CSb should be changed to "H" once every 2-byte.

CSb

RS

WRb

RDb

D7~D0

n

n+1

n+2

n+3

n+4

Address Set n

Dummy read

Data read

(3-8-1) Read Data from DDRAM

The DDRAM reading discriminates whether the content of the DDRAM data is full-size/half-size, and is

output by an input and the same format. The data is recognized without fail as the 1st byte, immediately after

CSb becomes “L”. Therefore, when the DDRAM data is read, it is necessary to make CSb = ”H” after it

finishes reading the 2nd byte.

(i) Half-size font character

When the content of DDRAM data is half-size character code, the address data of one address is divided

2-byte. And after read the 2nd byte, the address is incremented according to the entry mode. The 3rd to 8th bit

in 1st byte is all output “0”.

DDRAM address

DDRAM

n

Output data

1st byte

2nd byte

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NJU6645

(ii) Full-size font character

When the content of DDRAM data is full-size character code, the address data of 1-address is read by 1-byte.

And after read, the address is incremented according to the entry mode.

DDRAM address

DDRAM

n

n+1

Output data

1st byte

2nd byte

(3-8-2) Read Data from CGRAM and MKRAM

The CGRAM and MKRAM read the address data of one address by 1-byte as follows. And after read, the

address is incremented according to the entry mode.

Relation between the interface, RAM data, and RAM address, in the CGRAM and MKRAM data reading

- - -

RAM data

CGRAM

address

n

n+1

n+2

- - -

Output data

1st byte

2nd byte

3rd byte

(3-9) Status Read

The status reading is output to the following bits. The dummy reading is not necessary for the status reading.

However, the dummy reading is necessary for the status reading at the serial interface.

Status Read

Output data

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NJU6645

Correspondence Table of Character code and JIS code (ROM version “00”)

- 0000 ~ 00FF : Half-size character code (256-character)

- 0100 ~ 015F : CGRAM character code (96-character)

- 10A1 ~ 3A7F : Full-size character code (8064-character)

Note) Refer to "Correspondence Table of Half-size character code and Character pattern" for the half-size

character.

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NJU6645

Correspondence Table of Half-size character code and Character pattern (ROM version “00”)

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NJU6645

(4) FULL SCREEN REVERSE DISPLAY FUNCTION

This function reverses the full character and graphic display part except the icon display part. It is possible to

reverse display easily without the RAM rewriting by this function. The cursor and the attribute display part

are reversed too.

The icon part doesn't change.

Character/graphic part is reversed.

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NJU6645

(5) CURSOR CONTROL

The method of displaying the cursor has 3-kind that are the reversing blink (BW=”1”) and the underline

blinks of 16th row (C=”1”) and the black blink (B=”1"). The “LC” register is possible to switch the cursor

display of 1-character corresponding to the DDRAM address set in the address counter and the cursor display

of the entire line including the setting address.

(5-1) Character Cursor

(5-1-1) Underline <C=”1”, LC=”0”, B=”0”, BW=”0”>

The underline is displayed to the 16th row. When there is ON data in the 16th row, the data displays the

logical add with original data.

Cursor

(5-1-2) Reverse Blink <C=”1”, LC=”0”, B=”0”, BW=”1”>

The character at the cursor position is blinking with the reversing display. And then, the reversing switches at

every 32-frame cycle.

It alternately displays at

every 32-frame cycle.

(5-1-3) Black Blink <C=”1”, LC=”0”, B=”1”, BW=”0”>

The character at the cursor position is blinking with the black pattern display. The blinking switches the all

black pattern and the character pattern at every 32-frame cycle.

It alternately displays at

every 32-frame cycle.

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NJU6645

(5-2) Line Cursor

(5-2-1) Line Unit Underline <C=”1”, LC=”1”, B=”0”, BW=”0”>

The 16th row of the line including the DDRAM address setting in the address counter is all ON. When there

is character data, the data displays the logical add.

Line Unit Underline

(5-2-2) Line Unit Reverse <C=”1”, LC=”1”, B=”0”, BW=”1”>

The line including the DDRAM address setting in the address counter is reversed display.

Line Unit Reverse

(5-2-3) Line Unit White Blink <C=”1”, LC=”1”, B=”1”, BW=”0”>

The line including the DDRAM address setting in the address counter is blinking with the white pattern

display. The blinking switches the all white pattern and the character data at every 32-frame cycle.

Line Unit White Blink

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NJU6645

(6) DISPLAY ATTRIBUTE SETTING

NJU6645 is set the Reverse Display, the White Blink Display and the Reverse Blink Display by the display

attribute code of each character in 2-bit. This display is applied in matrix unit of the 16 x 16 dots in the

full-size data and the 8 x 16 dots in the half-size data. The White Blink Display and the Reverse Blink

Display are switching at every 32-frame cycle.

< Relation between the input data at the data writing to DDRAM and the bit >

The attribute code of full-size / half-size character is allocated the 1st bit and 2nd bit in the 1st byte. When the

DDRAM data is written, it is necessary to select the attribute code of this bit and to input the attribute of each

character.

[Full-size character data]

1st byte

[Half-size character data]

1st byte

2nd byte

Half-size

attribute code

Half-size character

code 8bit

Full-size character code 14bit

< Correspondence of the attribute code and the display status >

The display status changes according to the following tables.

P1

0

P0

0

Display Status

Normal

0

1

Reverse

1

0

1

White blink

Reverse blink

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< Example of display when the display attribute is selected >

(i) Reverse

<Full-size character display>

<Half-size character display>

(ii) White blink

It alternately displays at

every 32-frame cycle.

(iii) Reverse blink

It alternately displays at

every 32-frame cycle.

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NJU6645

(7) RELATION BETWEEN ATTRIBUTE, BLINK and FULL SCREEN REVERSE DISPLAY

The attribute display, the cursor display, and full screen reverse display are sequentially processed as shown

in the following figures. The period that the data of various blinks is converted is reversed in the attribute

display processing block and the cursor display processing block. Therefore, when the part where the attribute

of the blink was selected and the cursor position of the blink overlap, the attribute display and the cursor

display are alternately displayed. The full screen reverse display reverses the data after the attribute display

processing and the cursor display processing are done.

CGROM,CGRAM

Attribute processing block

Cursor processing block

Period A is

Active

Setting

OFF

Reverse

Reverse blink

White blink

Processing Content

-

Reversing all bits. (INV)

Reversing all bits at period A. (INV)

Changing to the OFF data in all bits at period A. (NOR)

32-flame

Counter

Setting

OFF

Underline

Black blink

Processing Content

-

Changing to the all ON data in 16th row. (OR)

Changing to the ON data in all bits at period B. (OR)

Reversing all bits at period B. (INV)

Reverse blink

Underline(Line unit) Changing to the all ON data in 16th row within the line. (OR)

White blink(Line unit) Changing to the OFF data in all bits within the line at period B. (NOR)

Reverse(Line unit) Reversing all bits within the line. (INV)

Period B is

Active

Full screen reverse

processing block

Setting

Processing Content

-

OFF

Reverse

Reversing all bits. (INV)

Period B = Period A

Display Data

< Method of display when attribute selection overlaps with cursor display >

Attribute

Cursol

Attribute + Cursol display

OFF

A B C D E F G

=

Underline

Black blink

=

A B C D E F G

Nomal

Reverse blink

+

=

A B C D E F G

Underline

(Line unit)

White blink

(Line unit)

Reverse

(Line unit)

A B C D E F G

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NJU6645

Attribute

Cursol

Attribute + Cursol display

OFF

A B C D E F G

Reverse attribute selection part

A B C D E F G

=

Underline

Black blink

=

A B C D E F G

A B C E

F G

A B

C

D E

F G

Reverse

Reverse blink

+

=

A B C D E F G

Underline

(Line unit)

White blink

(Line unit)

Reverse

(Line unit)

A B C D E F G

A B C D E

F G

Attribute

Cursol

Attribute + Cursol display

OFF

A B C D E F G

=

A B C D E F G

Reverse blink attribute selection part

A B C D E F G

Underline

A B C D E F G

A B C D E

F G

A B C D E F G

Black blink

A B C D E F G

A B C D E

F G

A B C D E F G

Reverse

blink

Reverse blink

+

A B C D E F G

Underline

(Line unit)

A B C D E

F G

A B C D E F G

White blink

(Line unit)

A B C D E F G

Reverse (Line)

A B C D E

F G

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Preliminar

NJU6645

Attribute

Cursol

Attribute + Cursol display

OFF

A B C D E F G

A B F G

A B C D E F G

=

A B

A B C D E F G

A B

F G

A B C D E F G

A B

F G

A B C D E F G

A B F G

A B C D E F G

F G

White blink attribute selection part

Underline

Black blink

A B C D E F G

White

blink

Reverse blink

+

A B C D E F G

Underline

(Line unit)

A B

F G

A B C D E F G

White blink

(Line unit)

A B

F G

Reverse (Line)

A B C D E F G

A B D D D

F G

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Preliminar

NJU6645

(8) COMMON DRIVER OUTPUT SWITCHING

The common output order of NJU6645 is selected by CSEL terminal (Both sides wiring or Comb wiring).

When the CSEL="L", the COM0 to 47 connects on the upper half of the panel and the COM48 to 95 connects

on the lower half. When the CSEL="H", the COM is divided by 16, that is connected to the panel by the

comb pattern.

< Wiring image >

(i) CSEL=”L” Both sides wiring mode

COMMK0

COM0

:

Panel

COM47

COM48

(CSEL=”L”)

:

COM95

COMMK1

COM47

COMMK1

:

COM95

:

NJU6645

:

COM0

COMMK0

COM48

(ii) CSEL=”H” Comb wiring mode

COMMK0

COM0

:

COM48

:

COM15

COM16

:

COM63

Panel

(CSEL=”H”)

COM64

:

COM31

COM32

:

COM79

COM80

:

COM47

COM95

COMMK1

COM47

COMMK1

:

COM95

:

NJU6645

:

COM0

COMMK0

COM48

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Preliminar

NJU6645

(9) COMMON SHIFT DIRECTION / SEGMENT OUTPUT DIRECTION

The direction of COM scan and SEG output of the dot matrix part and icon part is changed by "Driver Output

Control" instruction (SEL1, SEL2). The output data of SEG and COM changes as follows.

COM output direction switching

< SEL1=”0" >

COM data

COM output terminal

< SEL1=”1" >

COM data

COM output terminal

SEG output direction switching

< SEL2=”0" >

SEG data

SEG output terminal

< SEL2=”1" >

SEG data

SEG output terminal

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NJU6645

The correspondence of the display position on the panel and the DDRAM address is changed as follows.

SEL1=”0”, SEL2=”0"

The correspondence of the display position on the panel and the DDRAM address (SEL1=”0", SEL2=”0")

1-digit

2-digit

3-digit

4-digit

5-digit

6-digit

7-digit

8-digit

9-digit

10-digit

11-digit 12-digit 13-digit

14-digit

15-digit

16-digit

1-line

2-line

3-line

4-line

5-line

6-line

000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F

020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 038 039 03A 03B 03C 03D 03E 03F

040 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058 059 05A 05B 05C 05D 05E 05F

060 061 062 063 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070 071 072 073 074 075 076 077 078 079 07A 07B 07C 07D 07E 07F

080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D 08E 08F 090 091 092 093 094 095 096 097 098 099 09A 09B 09C 09D 09E 09F

0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF

COM0

COM1

COM94

COM95

SEL1=”1”, SEL2=”0"

The correspondence of the display position on the panel and the DDRAM address (SEL1=”1", SEL2=”0")

1-digit

2-digit

3-digit

4-digit

5-digit

6-digit

7-digit

8-digit

9-digit

10-digit

11-digit 12-digit 13-digit

14-digit

15-digit

16-digit

1-line

2-line

3-line

4-line

5-line

6-line

0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF

080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D 08E 08F 090 091 092 093 094 095 096 097 098 099 09A 09B 09C 09D 09E 09F

060 061 062 063 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070 071 072 073 074 075 076 077 078 079 07A 07B 07C 07D 07E 07F

040 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058 059 05A 05B 05C 05D 05E 05F

020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 038 039 03A 03B 03C 03D 03E 03F

000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F

COM0

COM1

COM94

COM95

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NJU6645

SEL1=”0”, SEL2=”1"

The correspondence of the display position on the panel and the DDRAM address (SEL1=”0", SEL2=”1")

1-digit

2-digit

3-digit

4-digit

5-digit

6-digit

7-digit

8-digit

9-digit

10-digit

11-digit 12-digit 13-digit

14-digit

15-digit

16-digit

1-line

2-line

3-line

4-line

5-line

6-line

01F 01E 01D 01C 01B 01A 019 018 017 016 015 014 013 012 011 010 00F 00E 00D 00C 00B 00A 009 008 007 006 005 004 003 002 001 000

03F 03E 03D 03C 03B 03A 039 038 037 036 035 034 033 032 031 030 02F 02E 02D 02C 02B 02A 029 028 027 026 025 024 023 022 021 020

05F 05E 05D 05C 05B 05A 059 058 057 056 055 054 053 052 051 050 04F 04E 04D 04C 04B 04A 049 048 047 046 045 044 043 042 041 040

07F 07E 07D 07C 07B 07A 079 078 077 076 075 074 073 072 071 070 06F 06E 06D 06C 06B 06A 069 068 067 066 065 064 063 062 061 060

09F 09E 09D 09C 09B 09A 099 098 097 096 095 094 093 092 091 090 08F 08E 08D 08C 08B 08A 089 088 087 086 085 084 083 082 081 080

0BF 0BE 0BD 0BC 0BB 0BA 0B9 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1 0B0 0AF 0AE0AD 0AC 0AB0AA 0A9 0A8 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0

COM0

COM1

COM94

COM95

SEL1=”1”, SEL2=”1"

The correspondence of the display position on the panel and the DDRAM address (SEL1=”1", SEL2=”1")

1-digit

2-digit

3-digit

4-digit

5-digit

6-digit

7-digit

8-digit

9-digit

10-digit

11-digit 12-digit 13-digit

14-digit

15-digit

16-digit

1-line

2-line

3-line

4-line

5-line

6-line

0BF 0BE 0BD 0BC 0BB 0BA 0B9 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1 0B0 0AF 0AE0AD 0AC 0AB0AA 0A9 0A8 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0

09F 09E 09D 09C 09B 09A 099 098 097 096 095 094 093 092 091 090 08F 08E 08D 08C 08B 08A 089 088 087 086 085 084 083 082 081 080

07F 07E 07D 07C 07B 07A 079 078 077 076 075 074 073 072 071 070 06F 06E 06D 06C 06B 06A 069 068 067 066 065 064 063 062 061 060

05F 05E 05D 05C 05B 05A 059 058 057 056 055 054 053 052 051 050 04F 04E 04D 04C 04B 04A 049 048 047 046 045 044 043 042 041 040

03F 03E 03D 03C 03B 03A 039 038 037 036 035 034 033 032 031 030 02F 02E 02D 02C 02B 02A 029 028 027 026 025 024 023 022 021 020

01F 01E 01D 01C 01B 01A 019 018 017 016 015 014 013 012 011 010 00F 00E 00D 00C 00B 00A 009 008 007 006 005 004 003 002 001 000

COM0

COM1

COM94

COM95

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NJU6645

The correspondence of the SEG/COM terminals and the MKRAM address is changed as follows.

The correspondence of the SEG/COM terminals and MKRAM address (SEL1=”0", SEL2=”0")

SEG

0

:

8

:

16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248

:

7

15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 231 239 247 255

MK

COM0

MK

100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F

120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F

COM1

The correspondence of the SEG/COM terminals and MKRAM address (SEL1=”1", SEL2=”0")

SEG

0

:

8

:

16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248

:

7

15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 231 239 247 255

MK

COM0

MK

120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F

100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F

COM1

The correspondence of the SEG/COM terminals and MKRAM address (SEL1=”0", SEL2=”1")

SEG

0

:

8

:

16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248

:

7

15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 231 239 247 255

MK

COM0

MK

11F 11E 11D 11C 11B 11A 119 118 117 116 115 114 113 112 111 110 10F 10E 10D 10C 10B 10A 109 108 107 106 105 104 103 102 101 100

13F 13E 13D 13C 13B 13A 139 138 137 136 135 134 133 132 131 130 12F 12E 12D 12C 12B 12A 129 128 127 126 125 124 123 122 121 120

COM1

The correspondence of the SEG/COM terminals and MKRAM address (SEL1=”1", SEL2=”1")

SEG

0

:

8

:

16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248

:

7

15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 231 239 247 255

MK

COM0

MK

13F 13E 13D 13C 13B 13A 139 138 137 136 135 134 133 132 131 130 12F 12E 12D 12C 12B 12A 129 128 127 126 125 124 123 122 121 120

11F 11E 11D 11C 11B 11A 119 118 117 116 115 114 113 112 111 110 10F 10E 10D 10C 10B 10A 109 108 107 106 105 104 103 102 101 100

COM1

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Preliminar

NJU6645

(10) PARTIAL DISPLAY

The partial display is executed by combining the Display Duty Ratio instruction "DN2, 1, 0" with the Display

Start Position instruction "DST2, 1, 0". This function reduces the LCD driving voltage and the power

consumption when the duty set low like the clock display of stand-by.

1

2

3

Display Duty Ratio = 6th line

4

5

6

Display

Area

1

2

Non-display

Area

Display Duty Ratio = 2nd line

3

4

5

6

1

2

Display

Area

Display Start Position = 3rd line

Non-display

Area

When the Display Start Position is set to the 3rd line, the character data of the first line of the DDRAM

address is displayed from the 3rd line (33 to 48 rows). When the Display Duty Ratio is set to the 2nd line, the

duty corresponds to 2-line (16 rows x 2 + 2 rows of icon part).

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NJU6645

(11) VERTICAL SMOOTH SCROLL

NJU6645 is executed to the vertical smooth scroll display of 1-dot unit by combining the Scroll Start Row

with the Scroll Start Line. The display scroll is set by the “Scroll Start Line” instruction (0,1,2,3,4, and 5-line

scroll) at the unit of line (16-dot units). The display scroll is set by the “Scroll Start Row” instruction (0,1,2,

--- 14, and 15-dot scroll) at the 1 dot unit. The display shifts to the upside only the amount of “Scroll Start

Line” + “Scroll Start Row”. When it is made to scroll by Display Duty Ratio = 6-line, the display that pushed

outside the screen appears from the other side.

< Example of smooth scroll display >

1

(i) Scroll Start Line = ”0-line”

2

3

Scroll Start Row = “0-dot”

4

5

6

7

8

9

10

11

12

13

14

15

16

1

(ii) Scroll Start Line = ”0-line”

2

Scroll Start Row = “8-dot”

3

4

5

6

7

8

9

10

11

12

13

14

15

16

(iii) Scroll Start Line = ”1-line”

Scroll Start Row = “0-dot”

(iv) Scroll Start Line = ”2-line”

Scroll Start Row = “8-dot”

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Preliminar

NJU6645

< Example of 4-dot smooth scroll display >

When the scroll operation to above by 4-dot of the 5-line display, the sequence and the panel image are

shown below.

Display Duty Ratio = 5-line

(RE, DB7~0) =

(0 1001 0001)

No scroll

Display ON

(0 0010 0001)

4-dot Scroll

8-dot Scroll

(0 0111 0100)

8-dot Scroll

(0 0111 1000)

12-dot Scroll

(0 0111 1100)

12-dot Scroll

0-dot Scroll

(0 0111 0000)

16-dot Scroll

(1-line Scroll)

1-line Scroll

(0 0110 0001)

It is necessary to update the display data

in DDRAM or CGRAM of 6th line.

4-dot Scroll

20-dot Scroll

(0 0111 0100)

(1-line + 4-dot Scroll)

24-dot Scroll

8-dot Scroll

(1-line + 8-dot Scroll)

(0 0111 1000)

28-dot Scroll

12-dot Scroll

(0 0111 1100)

(1-line + 12-dot Scroll)

0-dot Scroll

(0 0111 0000)

32-dot Scroll

(2-line Scroll)

2-line Scroll

(0 0110 0010)

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Preliminar

NJU6645

(12) N-LINE INVERSION

NJU6645 sets the number of inversion line of the alternating signal for LCD to the optional values from 2 ~

98.

< Setting example >

- N-line inversion = 98-line

---

Frame

Inversion

98-line

- N-line inversion = 2-line

---

Frame

Inversion Inversion Inversion

2-line

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Preliminar

NJU6645

(13) DISPLAY MODE

NJU6645 sets the 3 kinds display mode by the SPR and GR instructions.

(13-1)Character Mode (SPR="0”, GR=”0”)

In the character mode, the font pattern that uses the CGROM and CGRAM is displayed. The font pattern is

displayed at the position that corresponds to the DDRAM address by the character code written in DDRAM.

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NJU6645

(13-2)Graphics Mode (SPR="0”, GR=”1”)

In the graphics mode, the graphics of maximum 256x96 dots is displayed by using only CGRAM. At this

time, the relation between the CGRAM address and the position of display is shown in the following tables.

Because all CGRAM is used for graphics, it is not possible to use it as a user font.

Besides, the setting of “Scroll Start Line” and “Scroll Start Row” instructions is not reflected in the graphics

mode.

Correspondence of display position on panel and CGRAM address. (In the graphics mode)

200 210 220 230 240 250 260 270 280 290 2A0 2B0 2C0 2D0 2E0 2F0 300 310 320 330 340 350 360 370 380 390 3A0 3B0 3C0 3D0 3E0 3F0

~

20F 21F 22F 23F 24F 25F 26F 27F 28F 29F 2AF 2BF 2CF 2DF 2EF 2FF 30F 31F 32F 33F 34F 35F 36F 37F 38F 39F 3AF 3BF 3CF 3DF 3EF 3FF

400 410 420 430 440 450 460 470 480 490 4A0 4B0 4C0 4D0 4E0 4F0 500 510 520 530 540 550 560 570 580 590 5A0 5B0 5C0 5D0 5E0 5F0

~

40F 41F 42F 43F 44F 45F 46F 47F 48F 49F 4AF 4BF 4CF 4DF 4EF 4FF 50F 51F 52F 53F 54F 55F 56F 57F 58F 59F 5AF 5BF 5CF 5DF 5EF 5FF

600 610 620 630 640 650 660 670 680 690 6A0 6B0 6C0 6D0 6E0 6F0 700 710 720 730 740 750 760 770 780 790 7A0 7B0 7C0 7D0 7E0 7F0

~

60F 61F 62F 63F 64F 65F 66F 67F 68F 69F 6AF 6BF 6CF 6DF 6EF 6FF 70F 71F 72F 73F 74F 75F 76F 77F 78F 79F 7AF 7BF 7CF 7DF 7EF 7FF

800 810 820 830 840 850 860 870 880 890 8A0 8B0 8C0 8D0 8E0 8F0 900 910 920 930 940 950 960 970 980 990 9A0 9B0 9C0 9D0 9E0 9F0

~

80F 81F 82F 83F 84F 85F 86F 87F 88F 89F 8AF 8BF 8CF 8DF 8EF 8FF 90F 91F 92F 93F 94F 95F 96F 97F 98F 99F 9AF 9BF 9CF 9DF 9EF 9FF

A00 A10 A20 A30 A40 A50 A60 A70 A80 A90 AA0 AB0 AC0 AD0 AE0 AF0 B00 B10 B20 B30 B40 B50 B60 B70 B80 B90 BA0 BB0 BC0 BD0 BE0 BF0

~

A0F A1F A2F A3F A4F A5F A6F A7F A8F A9F AAF ABF ACF ADF AEF AFF B0F B1F B2F B3F B4F B5F B6F B7F B8F B9F BAF BBF BCF BDF BEF BFF

C00 C10 C20 C30 C40 C50 C60 C70 C80 C90 CA0 CB0 CC0 CD0 CE0 CF0 D00 D10 D20 D30 D40 D50 D60 D70 D80 D90 DA0 DB0 DC0 DD0 DE0 DF0

~

C0F C1F C2F C3F C4F C5F C6F C7F C8F C9F CAF CBF CCF CDF CEF CFF D0F D1F D2F D3F D4F D5F D6F D7F D8F D9F DAF DBF DCF DDF DEF DFF

---

1

2

3

4

5

6

7

8

9

10

11

12

13

14

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

Address

Upper

8bit

Address

Upper

8bit

Address

Upper

8bit

Address

Upper

8bit

---

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

Address

Upper

8bit

Address

Upper

8bit

Address

Upper

8bit

Address

Upper

8bit

31

32

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NJU6645

(13-3)Superimpose mode (SPR="1”, GR=”*”)

The superimpose mode overlaps and displays the character mode and the graphics mode. The displayed data

is a logical addition of the character mode data and the graphics mode data. Because all CGRAM is used for

graphics, it is not possible to use it as a user font.

Besides, the setting of “Scroll Start Line” and “Scroll Start Row” instructions is reflected only in the character

part, and not reflected in the graphics part.

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NJU6645

(14) FULL-SIZE and HALF-SIZE MIXED DISPLAY

NJU6645 displays from the left end of the screen with mixing the full-size character (16 x 16 dots) and the

half-size character (8 x 16 dots). The distinction between full-size and half-size is decided by 1st bit of

DDRAM data writing of the 2-byte format. In case of the “0”, it is the full-size character. In case of the “1”, it

is the half-size character. 1-character of the full-size character is composed of two DDRAM addresses, and

1-character of the half-size character is composed of one DDRAM address.

The corresponding example of that input data, DDRAM data, and display are shown below.

Half-size"1"

Full-size"

"

Half-size"2" (Attribute=Reverse)

Full-size"

"

Input Data

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 1 1 0 1 1

1 1 1 0 1 1 1 0

0 1 0 0 0 0 0 0

0 0 0 0 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 1 1 1 0 0

000

001

002

003

004

005

RAM Address

RAM Data

1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0

Panel Display

Note) When the Full-size character is written to the half-size address of the end of line, the character is displayed

unexpected. The number of writing characters must become just 32-character at half-size by 1-line.

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NJU6645

(15) RESET FUNCTION

The reset function initializes the LSI by setting the RSTb terminal to "L". The reset operation is always

required after the power supply is turned on.

The reset status is as follows.

Item

Register

RE

Initial Value

0

RE Flag : 1st page

AC

000h

Address Counter : DDRAM left end of the 1st line

Dot Matrix Display : OFF

D

M

REV

0

Icon Display : OFF

0

Full Screen Reverse Display : OFF

Standby mode : OFF

HALT

0

C

0

Cursor Display : OFF

LC

0

Line Cursor Setting : OFF

B

0

Blink Setting : OFF

BW

0

Reverse Cursor Setting : OFF

Display Mode : Character Mode

Read Modify Write Mode : OFF

Scroll Start Line : 1st line

SPR / GR

RDM

0 / 0

0

SSN2,1,0

SSL3,2,1,0

DST2,1,0

DN2,1,0

NL6,5,4,3,2,1,0

SEL1,SEL2

INTCK

OC2,1,0

DIS

0,0,0

0,0,0,0

Scroll Start Row : 1st row

0,0,0

Display Start Line : 1st line

Display Duty Ratio : 6-line

N-line Inversion : 98

0,0,0

1,1,0,0,0,0,1

0,0

0

0,0,0

0

Driver Output Control : Forward Direction

Internal Oscillation / External Clock : Internal OSC

Internal Capacitance Adjust : Reference Value

Discharge : OFF

DCON

AMPON

VU2,1,0

BS3,2,1,0

EV6,5,4,3,2,1,0

0

Voltage Boost Circuit : OFF

Internal Power Circuit : OFF

Boost Level : No Boost

0,0,0

0,0,0,0

0,0,0,0,0,0,0

Bias Ratio: 1/11 Bias

Electrical Volume : Low (Minimum value)

Note) After the resetting, the DDRAM, CGRAM, and MKRAM are not initialized. After the data is written, it is

necessary to turn on the display.

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(16) OSCILLATION CIRCUIT

NJU6645 is equipped with the CR oscillation circuit with the external resistor used, and generates internal

clocks used for the display timing. The generating method of the clock selects by the internal oscillation or

external clock. When the internal oscillation circuit is used, connect OSC1 and VDD with an external resistor.

At this time, it is necessary to fix the OSC2 to "H" or "L". The internal capacity value of the internal

oscillation circuit is set by the instruction (0.7/0.8/0.9/1/1.1/1.2/1/3 times.). The oscillation frequency is

adjusted by setting the internal capacity value.

When the external clock is used, INTCK=”1” and the external clock is supplied from the OSC2. At this time,

the OSC1 opens.

< Using Internal Oscillation >

VDD

< Using External Clock >

47k

Ω

OSC1

OPEN

OSC2

“H” or “L”

External Clock

(17) POWER SUPPLY CIRCUIT

(17-1)LCD power supply

The internal LCD power supply is organized into the voltage converter and the voltage booster. The voltage

converter consists of the reference voltage generator, the voltage regulator with EVR and the LCD bias

voltage generator.

If the internal LCD power supply doesn't have enough capability to drive the particular LCD panel, use the

external LCD power supply. Otherwise, it may affect display quality.

The configuration of the LCD power supply is arranged by setting the D1 (AMPON) and D0 (DCON) bits of

the “Power Control” instruction. For this configuration, the internal LCD power supply can be partially used

in combination with an external supply voltage, as shown below.

Voltage

Booster

Inactive

Active

Voltage

DCON

AMPON

External Supply Voltage

Note

Converter

0

1

0

1

Inactive

Active

VOUT, VLCD, V1, V2, V3, V4

VOUT

VDCOUT is supplied to VOUT.

*1, 3

*2, 3

-

Note 1) No internal LCD power supply is used. The LCD bias voltages are externally supplied, and the C1+, C1-, C2+,

C2-, C3+, C3-, C4+, C4-, C5+, C5-, VREF, VREG and VEE are open.

Note 2) Only the voltage converter is used. The VOUT is externally supplied, and the C1+, C1-, C2+, C2-, C3+, C3-,

C4+, C4-, C5+, C5- and VEE are open. The reference voltage is supplied on the VREF.

Note 3) The following relation among each LCD bias voltages must be maintained.

VOUT ≥ VLCD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS

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(17-2)Voltage booster

The internal voltage booster generates up to 6xVEE voltage. The boost level is selected from 2x, 3x, 4x, 5x or

6x by setting the D2 to D0 (VU2 to VU0) bits of the “Boost Level” instruction. VDCOUT terminal and

VOUT terminal are connected on the outside and used.

The boost voltage VDCOUT must not exceed 17.0V, otherwise the voltage stress may cause a permanent

damage to the LSI.

Boost Voltage VDCOUT = VEE x N [V]

( N : Boost Level =2~6 )

VDCOUT=16.8V

VDCOUT=9.9V

VEE=3.3V

VSS=0V

VEE=2.8V

VSS=0V

3-time Boost

6-time Boost

- External Capacitor Connection of Voltage Booster

6-time Boost

5-time Boost

C₁+

C₁-

C₁+

C₁-

+

C₂+

C₂-

C₃+

C₃-

C₄+

C₄-

C₅+

C₅-

V_OUT

V_DCOUT

V_SS

V_OUT

V_DCOUT

V_SS

+

4-time Boost

3-time Boost

2-time Boost

C₁+

C₁-

C₁+

C₁-

C₁+

C₁-

+

C₂+

C₂-

C₃+

C₃-

C₄+

C₄-

C₅+

C₅-

V_OUT

V_DCOUT

V_SS

V_OUT

V_DCOUT

V_SS

V_OUT

V_DCOUT

V_SS

+

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(17-3)Reference voltage generator

The reference voltage generator produces the reference voltage.

Reference Voltage : VBA = 0.75 x VEE

When using the internal LCD power supply, connect the VBA and the VREF, or supply 0.75xVEE or lower

voltage on the VREF. When using an external LCD power supply, the VBA should be open.

(17-4)Voltage regulator

The voltage regulator consists of an operational amplifier with gain control and EVR. The VREF voltage is

multiplied to obtain the VREG voltage, and its multiple (boost level) is set by the D2 to D0 (VU2 to VU0)

bits of the “Boost Level” instruction. The formula is shown below.

VREG = VREF x N [V]

( N : Boost Level = 2~6 )

(17-5)Electrical variable Resistor (EVR)

The EVR is used to fine-tune the V LCD voltage to optimize display contrast. The EVR value is controlled in

128 steps by setting the D3 to D0 (DV6 to DV0) bits of the “EVR Control” instruction. The formula is shown

below.

VLCD = 0.5 x VREG + M(VREG –0.5VREG) / 127 [V]

( M : EVR Value = 0 to 127)

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(17-6)LCD bias circuit

The suitable bias is set by the bias register (BS3 to 0) according to the display duty. When the VLCD voltage

is close to minimum (nearly equal: 4.5V), it is recommended not to use it because there is a possibility of not

operating in 1/11 bias setting.

+

-

+

-

+

-

+

-

VLCD

V1

VLCD

V1

VLCD

V1

VLCD

V1

R

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

V2

7R

R

6R

R

5R

R

4R

R

+

-

+

-

+

-

+

-

V3

+

-

+

-

+

-

+

-

V4

R

<1/11 Bias>

<1/10 Bias>

<1/9 Bias>

<1/8 Bias>

+

-

+

-

+

-

+

-

VLCD

V1

VLCD

V1

VLCD

V1

VLCD

V1

R

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

V2

3R

R

2R

R

1.5R

R

+

-

+

-

+

-

+

-

V3

V4

V3

+

-

+

-

+

-

+

-

V4

R

<1/7 Bias>

<1/6 Bias>

<1/5.5 Bias>

<1/5 Bias>

+

-

+

-

VLCD

V1

VLCD

V1

R

+

-

+

-

+

-

+

-

V2

0.5R

R

+

-

+

-

V3

R

+

-

+

-

V4

R

<1/4.5 Bias>

<1/4 Bias>

Note) R = Reference resistor

LCD Bias Circuit

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(17-7)Discharge circuit

The LSI incorporates a discharge circuit for the VLCD and V1 to V4 and for the VOUT. The VLCD and V1

to V4 are discharged by setting "1" at the D0 (DIS) bit of the "Discharge ON/OFF" instruction or the reset by

the RESb. Be sure to turned off the internal or external LCD power supply when this instruction is executed,

otherwise it may function as a current load and affect an operating current. Refer to “(r) Discharge ON/OFF”.

(17-8)Power ON/OFF

To protect the LSI from overcurrent, the following sequences must be maintained to turn on and off the power

supply. In addition to the following discussions, refer to “(21) TYPICAL INSTRUCTION SEQUENCES”.

(i) Power ON/OFF in using external LCD supply

-Power ON

First “VDD and VEE ON”, next “Reset by RSTb”, then “External LCD power supply ON”. When using only

external VOUT, first “VDD ON”, next “Reset by RSTb”, then “External VOUT ON”, as well.

-Power OFF

First “Reset by RSTb or “HALT” instruction” to isolate external LCD bias voltage, next “VDD OFF”. For

more safety, placing a resistor in series on the VLCD line (or the VOUT line in using only the external

VOUT) is recommended. That resistance is usually between 50Ω and 100Ω.

(ii) Power ON/OFF in using internal LCD supply

-Power ON

First “VDD and VEE ON”, next “Reset by RSTb”, then “Internal LCD power supply ON”. Be sure to execute

the “Display ON” instruction later than the completion of this power ON sequence. Otherwise, unexpected

pixels may be turned on instantly.

-Power OFF

First “Reset by RSTb or “HALT” instruction”, next “VDD and VEE OFF”. If using different power sources

for the VDD and the VEE individually, the VEE must be turned off after the reset or the “HALT”. After that,

the VDD can be turned off, waiting until the LCD bias voltages (VLCD, V1, V2, V3 and V4) drop below the

threshold level of LCD pixels.

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- External Components for LCD Power Supply

Using Only Internal LCD Power Supply (6x boost)

Using Only External LCD Power Supply

VDD

CA1

VEE

VSS

CA1

VSS

VBA

VREF

VREG

VREF

VREG

CA3

VSS

CA1

C1-

C1+

C2-

C2+

C3-

C3+

C4-

C4+

C5-

C5+

C1-

C1+

C2-

C2+

C3-

C3+

C4-

C4+

C5-

C5+

CA1

NJU6645

VDCOUT

VOUT

VDCOUT

VOUT

CA1

VSS

VLCD

V1

VLCD

V1

VLCD

V1

CA2

External

V2

V3

Power

Circuit

V3

V4

VSS

CA2 CA2 CA2

CA2

Reference Values

VSS VSS VSS VSS

CA1

CA2

CA3

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

Note 1) B grade capacitor is recommended for CA1 to CA3. Make sure what is the best capacitor value in the

particular application.

Note 2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VOUT, VLCD, V1, V2, V3 and V4) reduces

step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality.

To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as

possible.

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NJU6645

Using Internal LCD Power Supply Without

Reference Voltage Generator (1)

(6x boost)

Using Internal LCD Power Supply Without

Reference Voltage Generator (2)

(6x boost)

VDD

VEE

VSS

CA1

VSS

CA1

VSS

VBA

VREF

VREG

VREF

VREG

CA3

VSS

CA3

VSS VSS

CA1

C1-

C1+

C2-

C2+

C3-

C3+

C4-

C4+

C5-

C5+

C1-

C1+

C2-

C2+

C3-

C3+

C4-

C4+

C5-

C5+

VSS

CA1

NJU6645

VDCOUT

VOUT

VDCOUT

VOUT

CA1

VSS

VLCD

V1

VLCD

V1

CA2

V2

V3

V4

VSS

Reference Values

CA1

CA2

CA3

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

Note 1) B grade capacitor is recommended for CA1 to CA3. Make sure what is the best capacitor value in the

particular application.

Note 2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VOUT, VLCD, V1, V2, V3 and V4) reduces

step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality.

To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as

possible.

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Using Internal LCD Power Supply Without

Voltage Booster

VDD

VEE

VSS

CA1

VBA

VSS

CA3

VREF

VREG

CA3

VSS

C1-

C1+

C2-

C2+

C3-

C3+

C4-

C4+

C5-

C5+

NJU6645

VDCOUT

VOUT

External

CA1

Power

Circuit

VLCD

V1

CA2

V2

V3

V4

VSS

Reference Values

CA1

CA2

CA3

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

Note 1) B grade capacitor is recommended for CA1 to CA3. Make sure what is the best capacitor value in the

particular application.

Note 2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VOUT, VLCD, V1, V2, V3 and V4) reduces

step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality.

To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as

possible.

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NJU6645

(18) COMMON DRIVERS AND SEGMENT DRIVERS

The LSI includes 256-segment drivers and 98-common drivers. 2 out of 98-common drivers are assigned to

the COMMK0 and COMMK1 for an icon display. The common drivers generates LCD driving waveforms

formed on the VLCD, V1, V4 and VSS levels. The segment drivers generates waveforms formed on the

VLCD, V2, V3 and VSS levels.

(19) LCD DRIVING WAVEFORMS

98

1

2

3

4

5

98

1

2

3

4

5

98

1

COM0

COM1

VLCD

V1

V2

V3

V4

COM0

COM1

VSS

VLCD

V1

V2

V3

V4

VSS

VLCD

V1

V2

V3

V4

VSS

SEG0

SEG1

VLCD

V1

V2

V3

V4

VSS

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(20) INSTRUCTION

Instruction Tables (1/2)

Code

Default

Instruction

Description

RE RS RW D7 D6 D5 D4 D3 D2 D1 D0

DDRAM, CGRAM, MKRAM Data

a

b

RAM Data Write

RAM Data Read

*

1

0

1

-

BF: Busy Flag

BF NF2 NF1 NF0 LF3 LF2 LF1 LF0

NF: Display Line at present

LF: Display Row at present

c

Status Read

*

0

1

-

* : Don’t care

Code

Default

Instruction

Description

RE RS RW D7 D6 D5 D4 D3 D2 D1 D0

Writing the half-size space code

“0020h” into all DDRAM.

Setting the DDRAM address “000h"

into address counter.

d

e

Display Clear

0

1

0

1

-

Setting the DDRAM address “000h"

into address counter.

Cursor Home

-

Initialization the Scroll Start Line

and the Scroll Start Row.

ALLON: All pixels ON/OFF

REV: Full Screen Reverse Display

ON/OFF

ALL

ON

REV

M

D

f

Display Control

0

1

0

000

M: Icon Display ON/OFF

D: Dot Matrix Display ON/OFF

HALT

C

g

h

Standby

0

1

0

1

0

*

0

BW: Reverse Cursor

B: Blink

BW

B

LC

Cursor Display

0000

LC: Line Cursor

C: Cursor

SPR: Superimpose Mode

GR: Graphics Mode

RDM: Read Modify Write

SPR GR RDM

SSN2 SSN1 SSN0

i

Display / Entry Mode

0

1

0

1

*

000

j

k

l

Scroll Start Line

Scroll Start Row

Display Start Line

0

1

0

1

0

1

0

1

000

0000

000

SSL3 SSL2 SSL1 SSL0

DST2 DST1 DST0

DN2 DN1 DN0

*

m Display Duty Ratio

N-line Inversion

000

NL6 NL5 NL4

0

1

0

1

0

*

110

(Upper)

N-line Inversion

(Lower)

n

NL3 NL2 NL1 NL0

0

1

0

1

0

1

0

0001

00

SEL1: COM Shift Direction Set

SEL2: SEG Output Direction Set

INTCK: Internal OSC /

External Clock

SEL1 SEL2

o

Driver Output Control

*

INT

CK

OC2 OC1 OC0

RE

p

q

Oscillation Control

RE Flag

0

*

0

1

0

1

0000

0

OC2,1,0: Internal Capacitance

Adjust

RE Flag Set

*

* : Don’t care

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NJU6645

Instruction Tables (2/2)

Instruction

Code

Default

Description

RE RS RW D7 D6 D5 D4 D3 D2 D1 D0

DIS

r

s

t

Discharge

1

0

1

0

1

0

*

0

VU2 VU1 VU0

BS3 BS2 BS1 BS0

VU2,1,0: Boost Level

Boost Level

Bias Ratio

000

0000

Electrical Volume

(Upper)

Electrical Volume

(Lower)

EV6 EV5 EV4

1

0

1

*

000

u

v

EV3 EV2 EV1 EV0

1

0

1

0

0000

AMPON: Internal Operational

Amplifier ON/OFF

DCON: Voltage Boost Circuit

ON/OFF

RAM Address 4bit (AD3 to AD0)

RAM Address 4bit (AD7 to AD4)

RAM Address 4bit (AD11 to AD8)

AMP DC

Power Control

1

0

1

0

1

*

00

ON ON

AD3 AD2 AD1 AD0

AD7 AD6 AD5 AD4

AD11 AD10 AD9 AD8

RAM Address Set 1

RAM Address Set 2

RAM Address Set 3

1

0

1

0

1

0

1

0

0000

w

x

ARL=”0” Address -1

ARL

Address Shift

1

0

1

0

1

*

-

ARL=”1” Address +1

TS3 TS2 TS1 TS0

TS7 TS6 TS5 TS4

TS11 TS10 TS9 TS8

Maker Test 1

Maker Test 2

Maker Test 3

Maker Test 4

Maker Test 5

RE Flag

1

*

0

1

0

1

0

1

0

1

0

1

0

1

-

Maker Test Instruction

(Not used usually.)

y

q

-

TS13 TS12

TSM3TSM2TSM1TSM0

RE

*

-

RE Flag Set

*

0

* : Don’t care

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< Instruction Descriptions >

(a) RAM Data Write

The "RAM Data Write" instruction writes display data on a specified address. The address is incremented

automatically by "Display / Entry Mode” instruction.

RE

*

RS

1

RW

0

D7

D6

D5

D4

D3

D2

D1

D0

WRITE DATA

(b) RAM Data Read

The "RAM Data Read" instruction reads out display data from a specified address. The address is

incremented automatically by "Display / Entry Mode” instruction.

RE

*

RS

1

RW

1

D7

D6

D5

D4

D3

D2

D1

D0

READ DATA

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(c) Status Read

The "Status Read" instruction reads out the busy flag (BF) that indicates the internal operation and the line /

row that displayed at present. The BF="1" indicates that internal operation is in progress. When the BF="1",

the next instruction is disabled. Check the busy flag status (BF="0") before the next write operation.

RE

*

RS

0

RW

1

D7

BF

D6

NF2

D5

NF1

D4

NF0

D3

LF3

D2

LF2

D1

LF1

D0

LF0

- Busy Flag Read

BF

0

1

Internal Operation

Instruction is enable

Operating (Instruction is disabled)

- Display Line Read

NF

000

001

010

011

100

101

110

111

Display Line

1st line

2nd line

3rd line

4th lint

5th line

6th line

-

- Display Row Read

LF

Display Row

1st row

0000

0001

2nd row

3rd row

4th row

0010

0011

0100

5th row

0101

6th row

0110

7th row

0111

8th row

1000

9th row

1001

10th row

11th row

12th row

13th row

14th row

15th row

16th row

1010

1011

1100

1101

1110

1111

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(d) Display Clear

When the "Display Clear" instruction is executed, the Half-size space code "0020h" is written into every DD

RAM address, the DD RAM address "000h" is set into the address counter. The MK RAM / CG RAM data is

unchanged.

RE

0

RS

0

RW

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

1

(e) Cursor Home

When the "Cursor Home" instruction is executed, the DD RAM address "000h" is set into the address counter.

The Scroll Start Line and the Scroll Start Row are set to default. The DD RAM contents are unchanged.

RE

0

RS

0

RW

0

D7

0

D6

0

D5

0

D4

1

D3

0

D2

0

D1

0

D0

1

(f) Display Control

The "Display Control" instruction controls the Dot Matrix Display ON/OFF, the Icon Display ON/OFF, the

Full Screen Reverse Display ON/OFF and All Pixels ON/OFF. The Icon Display ON/OFF and the Dot Matrix

Display ON/OFF are controlled separately. When the M=”0” and D=”0”, common / segment drivers are

turning OFF and output VSS level.

RE

0

RS

0

RW

0

D7

0

D6

0

D5

1

D4

0

D3

D2

D1

M

D0

D

ALLON REV

- All Pixels ON/OFF

ALLON

Display

0

1

Normal display

All ON display (Both dot matrix and Icon display)

- Full Screen Reverse Display ON/OFF

REV

0

Display

Normal display

1

Full screen reverse display

- Icon Display ON/OFF

M

0

1

Icon Display

OFF

ON

- Dot Matrix Display ON/OFF

D

0

1

Dot Matrix Display

OFF

ON

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(g) Standby

The "Standby" instruction controls the Standby mode ON/OFF.

RE

0

RS

0

RW

0

D7

0

D6

0

D5

1

D4

1

D3

*

D2

*

D1

*

D0

HALT

Function

OFF (Normal mode)

ON (Standby mode)

0

1

During the standby ON, operating current is down to the standby level. The internal state of the LSI in the

standby mode is listed below.

- Internal oscillator and internal LCD power supply are halted.

- All segment and common drivers are fixed at VSS level.

- External clock to the OSC2 cannot be accepted.

- Voltage booster is halted.

- Display data in the DDRAM and data in the instruction registers are being maintained.

- VLCD, V1, V2, V3 and V4 are in high impedance.

In the standby ON sequence, execute the "Display OFF" prior to the "Standby ON". In the standby OFF

sequence, execute the "Standby OFF" prior to the "Display ON". If the "Standby ON/OFF" instruction is

executed during the "Display ON", unexpected pixels may be turned on instantly.

(h) Cursor Display

The "Cursor Display" instruction controls the Cursor ON/OFF, the Line Cursor ON/OFF and display method.

RE

0

RS

0

RW

0

D7

0

D6

1

D5

0

D4

0

D3

BW

D2

B

D1

LC

D0

C

BW

*

B

*

0

1

0

1

0

1

0

1

LC

C

Display State

Cursor OFF

*

0

1

0

1

0

Underline cursor (Character unit)

0

Black blink cursor (Character unit)

Reverse blink cursor (Character unit)

Inhibited

1

0

Underline cursor (Line unit)

White blink cursor (Line unit)

Reverse cursor (Line unit)

Inhibited

0

1

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(i) Display Mode / Entry Mode

The "Display Mode / Entry Mode" instruction controls the Display Mode and Entry Mode.

RE

0

RS

0

RW

0

D7

0

D6

1

D5

0

D4

1

D3

*

D2

SPR

D1

GR

D0

RDM

- Display Mode

SPR

GR

0

Display state

Character Mode

Graphics Mode

0

1

*

Superimpose Mode

- Read Modify Write Mode

RDM

Function

0

1

OFF (Auto increment in writing and reading display data)

ON (Auto increment in writing display data only)

(j) Scroll Start Line

The "Scroll Start Line" instruction controls the Display Line from COM0 output.

RE

0

RS

0

RW

0

D7

0

D6

1

D5

1

D4

0

D3

*

D2

D1

D0

SSN2 SSN1 SSN0

SSN2

SSN1

SSN0

Scroll Start Line

1st line

0

1

0

1

0

1

0

1

0

1

0

1

*

2nd line

3rd line

4th line

5th line

6th line

Inhibited

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- Example of Display

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

SSN=”000”

(Default)

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SSN=”001”

SSN=”010”

SSN=”011”

SSN=”100”

SSN=”101”

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

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NJU6645

(k) Scroll Start Row

The "Scroll Start Row" instruction controls number of the Scroll Start Row.

RE

0

RS

0

RW

0

D7

0

D6

1

D5

1

D4

1

D3

D2

D1

D0

SSL3 SSL2 SSL1 SSL0

SSL3

SSL2

SSL1

SSL0

Scroll Start Row

0

1

0

1

0

1

1st row

2nd row

3rd row

4th row

:

1

16th row

- Example of Display

SSL3 to 0=0

SSL3 to 0=1

SSL3 to 0=2

--- SSL3 to 0=14

SSL3 to 0=15

---

(l) Display Start Line

The "Display Start Line" instruction controls the Display Start Line. The displayed data of the 1st line shifts

to the setting line.

RE

0

RS

0

RW

0

D7

1

D6

0

D5

0

D4

0

D3

*

D2

D1

D0

DST2 DST1 DST0

DST2

DST1

DST0

Display Start Line

1st line

0

1

0

1

0

1

0

1

0

1

0

1

*

2nd line

3rd line

4th line

5th line

6th line

Inhibited

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NJU6645

- Example of Display

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

DST=”000”

(Default)

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

DST=”001”

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

DST=”010”

DST=”011”

DST=”100”

DST=”101”

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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(m) Display Duty Ratio

The "Display Duty Ratio" instruction controls the number of display line, and is used to carry out the partial

display.

RE

0

RS

0

RW

0

D7

1

D6

0

D5

0

D4

1

D3

*

D2

DN2

D1

DN1

D0

DN0

DN2

DN1

DN0

Display Line (Duty)

6-line (1/98 Duty)

5-line (1/82 Duty)

4-line (1/66 Duty)

3-line (1/50 Duty)

2-line (1/34 Duty)

1-line (1/18 Duty)

Inhibited

0

1

0

1

0

1

0

1

0

1

0

1

*

(n) N-line Inversion

The "N-line Inversion" instruction controls the number of inversion line. The setting range are 2 to 98 lines,

and is alternated by setting (N+1).

RE

0

RS

0

RW

0

D7

1

D6

0

D5

1

D4

0

D3

*

D2

NL6

D1

NL5

D0

NL4

RE

0

RS

0

RW

0

D7

1

D6

0

D5

1

D4

1

D3

NL3

D2

NL2

D1

NL1

D0

NL0

NL6

NL5

NL4

NL3

NL2

NL1

NL0

Inversion Line

0

1

0

1

0

1

Inhibited

2

3

4

:

1

0

1

97

98

:

Inhibited

1

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(o) Driver Output Control

The "Driver Output Control" instruction controls the SEG / COM driver output direction.

RE

0

RS

0

RW

0

D7

1

D6

1

D5

0

D4

0

D3

*

D2

*

D1

D0

SEL1 SEL2

SEL1

0

1

Function

COM scan forward direction

COM scan backward direction

SEL2

0

1

Function

SEG output forward direction

SEG output backward direction

(p) Oscillation Control

The "Oscillation Control" instruction controls the system clock type and the internal capacitance of internal

oscillation circuits. The frame frequency is adjusted by internal capacitance setting. When the frame

frequency is set by this instruction, make sure what is the best setting in the particular application.

RE

0

RS

0

RW

0

D7

1

D6

1

D5

0

D4

1

D3

D2

D1

OC1

D0

OC0

INTCK OC2

INTCK

Function

Internal oscillation circuit

External oscillation input

0

1

OC2

OC1

OC0

Internal Capacitance

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reference capacitance

0.7 x Reference capacitance

0.8 x Reference capacitance

0.9 x Reference capacitance

1.1 x Reference capacitance

1.2 x Reference capacitance

1.3 x Reference capacitance

Inhibited

(q) RE Flag Set

The "RE Flag Set" instruction controls the access to the expanded register. When it accesses each instruction,

it is necessary to set the RE flag in advance.

RE

*

RS

0

RW

0

D7

1

D6

1

D5

1

D4

1

D3

*

D2

*

D1

*

D0

RE

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NJU6645

(r) Discharge

Discharge circuit is used to discharge out of the stabilizing capacitors placed on the VLCD, V1, V2, V3, V4

and VSS. This instruction prevents the unknown display at the power supply off.

RE

1

RS

0

RW

0

D7

0

D6

0

D5

0

D4

0

D3

*

D2

*

D1

*

D0

DIS

0

1

Function

Discharge OFF

Discharge ON

(s) Boost Level

The "Boost Level" instruction controls the level of Voltage Boost Circuit..

RE

1

RS

0

RW

0

D7

0

D6

0

D5

0

D4

1

D3

*

D2

VU2

D1

VU1

D0

VU0

VU2

VU1

VU0

Boost Level

1 time (No boost)

2 times

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3 times

4 times

5 times

6 times

Inhibited

(t) Bias Ratio

The "Bias Ratio" instruction controls the Bias Ratio.

RE

1

RS

0

RW

0

D7

0

D6

0

D5

1

D4

0

D3

BS3

D2

BS2

D1

BS1

D0

BS0

BS3

0

BS2

BS1

BS0

0

Bias Ratio

1/11

1/10

1/9

0

1

0

1

0

1

0

1

0

1

0

1

1/8

0

1/7

1/6

0

1

0

1/5.5

1/5

0

1

0

1/4.5

1/4

1

0

Inhibited

:

1

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(u) Electrical Volume

The "Electrical Volume" instruction adjusts VLCD to optimize display contrast. The voltage divided into 127

is set. The setting order requires upper byte first.

RE

1

RS

0

RW

0

D7

0

D6

0

D5

1

D4

1

D3

*

D2

EV6

D1

EV5

D0

EV4

RE

1

RS

0

RW

0

D7

0

D6

1

D5

0

D4

0

D3

EV3

D2

EV2

D1

EV1

D0

EV0

EV6

0

EV5

0

EV4

0

EV3

0

EV2

0

EV1

0

EV0

0

1

Output Voltage

Low

:

1

0

1

High

This instruction is finally effective when both upper and lower bytes are transmitted in order to prevent high

VLCD. The setting order is upper byte first, then lower byte.

Note) When the electrical volume setting is changed to wide range at keeping display on, there is possibility that

the unknown display appears. In this case, add waiting time and change the electrical volume value gradually.

< Example of the changing from EV=80 to EV=110 at keeping display on >

EV=80 → Wait (~ms) → EV=90 → Wait (~ms) → EV=100 → Wait (~ms) → EV=110

*

The wait time and electrical volume setting range is different depending on the capacitance value of V1 to

V4 and the panel size. Please make sure what is the best setting in the particular application.

(v) Power Control

RE

1

RS

0

RW

0

D7

0

D6

1

D5

0

D4

1

D3

*

D2

*

D1

D0

AMPON DCON

AMPON : This instruction controls ON/OFF of the operational amplifier parts of the internal power supply

circuits (Voltage regulator, electrical variable resistor, and voltage converter).

AMPON

Function

Internal operational amplifier OFF

Internal operational amplifier ON

0

1

DCON : This instruction controls Internal Voltage Booster ON/OFF,

DCON

Function

Voltage booster OFF

Voltage booster ON

0

1

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NJU6645

(w) RAM Address Set

The "RAM Address Set" instruction specifies the DDRAM, CGRAM, and MKRAM address.

The RAM address should set lower 4-bit (AD3 to AD0) at first. This instruction is finally effective when

upper 4-bit (AD11 to AD8) are transmitted.

RE

1

RS

0

RW

0

D7

0

D6

1

D5

1

D4

0

D3

AD3

D2

AD2

D1

AD1

D0

AD0

RE

1

RS

0

RW

0

D7

0

D6

1

D5

1

D4

1

D3

AD7

D2

AD6

D1

AD5

D0

AD4

RE

1

RS

0

RW

0

D7

1

D6

0

D5

0

D4

0

D3

D2

D1

D0

AD8

AD11 AD10 AD9

(x) Address Shift

The "Address Shift" instruction controls increment (+1) or decrement (-1) of the address. The address moves

whenever this instruction is executed.

RE

1

RS

0

RW

0

D7

1

D6

0

D5

0

D4

1

D3

*

D2

*

D1

*

D0

ARL

0

1

Function

Address –1

Address +1

(y) Maker Test

This instruction is using for device testing mode. Please do not use this instruction usually.

RE

1

RS

0

RW

0

D7

1

D6

0

D5

1

D4

0

D3

*

D2

*

D1

*

D0

*

RE

1

RS

0

RW

0

D7

1

D6

1

D5

1

D4

0

D3

*

D2

*

D1

*

D0

*

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(21) TYPICAL INSTRUCTION SEQUENCE

(21-1)Initialization Sequence in Using Internal LCD Power Supply

Power ON (VDD, VEE)

WAIT(*2)

(*1)

Reset (RSTb terminal)

WAIT(*3)

Refer to (15)RESET FUNCTION

-------------------- Instruction Code -------------------

----- Setting Example -----

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

1

Display Clear

RE Flag

Display clear

RE=”1”

1

0

1

0

1

0

1

0

1

0

1

0

1

*

0

*

0

*

1

0

1

0

*

0

1

0

1

Boost Level

6 times boost

1/11 bias

Bias Ratio

Electrical Volume (Upper)

Electrical Volume (Lower)

EV=“1,0,0,0,0,0,0”

Power Control

WAIT(*4)

Power Control

WAIT(*5)

End

Voltage booster ”ON”

0

1

0

1

*

1

Internal operational

amplifier ”ON”

*1 If different power sources are applied to the VDD and the VEE, turn ON the VDD first.

*2 Wait until the VDD and VEE are stabilized.

*3 Wait 1.5ms or more.

*4 Wait until the VDCOUT (VOUT) is stabilized.

*5 Wait until the VLCD and V1 to V4 are stabilized.

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(21-2)Initialization Sequence in Using External LCD Power Supply

Power ON (VDD)

WAIT(*1)

Reset (RSTb terminal)

WAIT(*2)

Refer to (15)RESET FUNCTION

External Power Supply ON

WAIT(*3)

-------------------- Instruction Code -------------------

----- Setting Example -----

Display clear

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

1

Display Clear

End

*1 Wait until the VDD is stabilized.

*2 Wait 1.5ms or more.

*3 Wait until the external LCD power supply (VOUT, VLCD, V1 to V4) are stabilized.

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(21-3)Display Data Write Sequence

Operational Status

-------------------- Instruction Code -------------------

----- Setting Example -----

RE=”1”

D7

1

D6

1

D5

1

D4

1

D3

*

D2

*

D1

*

D0

1

RE Flag

RAM Address Set 1

RAM Address Set 2

RAM Address Set 3

0

1

0

1

0

1

0

1st line DDRAM

address Set (000h)

RAM Data Write

*

1st line DDRAM data

writing

Repeating 2nd to 5th line

RAM Address Set 1

RAM Address Set 2

RAM Address Set 3

0

1

0

1

0

1

0

1

0

1

0

6th line DDRAM

address set (0A0h)

RAM Data Write

*

6th line DDRAM data

writing

RAM Address Set 1

RAM Address Set 2

RAM Address Set 3

0

1

0

1

0

1

0

1

MKRAM

address set (100h)

RAM Data Write

*

MKRAM data writing

RAM Address Set 1

RAM Address Set 2

RAM Address Set 3

0

1

0

1

0

1

0

1

0

CGRAM

address set (200h)

RAM Data Write

RE Flag

*

1

0

*

1

0

*

1

*

1

0

*

0

*

0

*

1

*

0

1

CGRAM Data Writing

RE=”0”

Display Control

Dot matrix display “ON”

Icon display ”ON”

Data Display

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(21-4)Power OFF Sequence in Using Internal LCD Power Supply

Operational Status

-------------------- Instruction Code -------------------

----- Setting Example -----

D7

1

D6

1

D5

1

D4

1

D3

*

D2

*

D1

*

D0

0

RE Flag

Display Control

Standby

RE=”0”

0

1

0

1

0

1

0

1

0

*

0

*

0

*

0

1

Display ”OFF"

Standby ”ON”

RE=”1”

RE Flag

Discharge

Discharge ”ON”

WAIT(*1)

Power OFF (VEE)

Power OFF (VDD)

*1 Wait until the discharge is completed.

(21-5)Power OFF Sequence in Using External LCD Power Supply

Operational Status

-------------------- Instruction Code -------------------

----- Setting Example -----

D7

1

D6

1

D5

1

D4

1

D3

*

D2

*

D1

*

D0

0

RE Flag

Display Control

Standby

RE=”0”

0

1

0

1

0

*

0

*

0

*

0

1

Display ”OFF"

Standby ”ON”

External Power OFF

RE Flag

1

0

1

0

1

0

1

0

*

1

RE=”1”

Discharge

WAIT(*1)

Discharge ”ON”

Power OFF (VEE)

Power OFF (VDD)

*1 Wait until the discharge is completed.

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(21-6)Partial Display Sequence [Example : Display Duty Ratio = 2-line (1/34 Duty), Display Start Line = 3rd line]

Operational Status

-------------------- Instruction Code -------------------

----- Setting Example -----

D7

1

D6

1

D5

1

D4

1

D3

*

D2

*

D1

*

D0

0

RE Flag

Display Control

RE Flag

RE=”0”

0

1

0

1

0

1

0

*

0

*

0

*

0

1

0

Display ”OFF"

RE=”1”

Power Control

Voltage booster ”OFF”

Internal operational

amplifier ”OFF”

WAIT(*1)

Boost Level

0

1

0

1

0

1

0

1

0

1

*

0

*

0

*

0

1

0

*

1

0

1

0

1

3 times boost

1/6 bias

Bias Ratio

Electrical Volume (Upper)

Electrical Volume (Lower)

EV=“1,0,0,0,0,0,0”

Power Control

WAIT(*2)

Voltage booster ”ON”

Power Control

WAIT(*3)

0

1

0

1

*

1

Internal operational

amplifier ”ON”

RE Flag

1

0

1

0

1

0

1

*

0

1

*

1

0

RE=”0”

Display Start line

3rd line

Display Duty Ratio

2-line (1/34Duty)

Display Control

0

1

0

1

Dot matrix display “ON”

Icon display ”ON”

Partial Display

*1 Wait until the discharge is completed.

*2 Wait until the VDCOUT (VOUT) is stabilized.

*3 Wait until the external LCD power supply (VOUT, VLCD, V1 to V4) are stabilized.

Refer to (10) PARTIAL DISPLAY .

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NJU6645

(21-7)Smooth Scroll Display Sequence [Example : 5-line display, 4-dot scroll]

5-line display, Display ON

-------------------- Instruction Code -------------------

----- Setting Example -----

D7

1

D6

1

D5

1

D4

1

D3

*

D2

*

D1

*

D0

0

RE Flag

RE=”0”

Scroll Start Row

0

1

0

1

0

1

0

4-row scroll

8-row scroll

12-row scroll

Scroll Start Row

Scroll Start Line

0

1

0

*

0

1

0-row scroll

1-line scroll

RE Flag

1

*

1

RE=”1”

RAM Address Set 1

RAM Address Set 2

RAM Address Set 3

0

1

0

1

0

1

0

1st line DDRAM

address set (000h)

RAM Data Write

RE Flag

*

1

0

*

1

*

1

*

1

*

0

1

*

1

0

1

*

0

*

0

1st line DDRAM data

writing

RE=”0”

Scroll Start Row

4-row scroll

8-row scroll

12-row scroll

Scroll Start Row

Scroll Start Line

0

1

0

*

0

1

0

0-row scroll

2-line scroll

Refer to (11) VERTICAL SMOOTH S SCROLL.

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NJU6645

(21-8)Superimpose Mode Display Sequence [Example : Character display on 2nd ~ 5th line]

Operational Status

-------------------- Instruction Code -------------------

----- Setting Example -----

D7

1

D6

1

D5

1

D4

1

D3

*

D2

*

D1

*

D0

0

RE Flag

Display / Entry Mode

RE Flag

RE=”0”

0

1

0

1

*

1

*

0

*

0

1

Superimpose mode

RE=”1”

RAM Address Set 1

RAM Address Set 2

RAM Address Set 3

0

1

0

1

0

1

0

1

0

2nd line DDRAM

address set (020h)

RAM Data Write

*

2nd line DDRAM data

writing

Repeating 3rd to 4th line

RAM Address Set 1

RAM Address Set 2

RAM Address Set 3

0

1

0

1

0

1

0

1

0

5th line DDRAM

address set (080h)

RAM Data Write

*

5th line DDRAM data

writing

RAM Address Set 1

RAM Address Set 2

RAM Address Set 3

0

1

0

1

0

1

0

1

0

CGRAM

address set (200h)

RAM Data Write

RE Flag

*

1

0

*

1

0

*

1

*

1

0

*

0

*

0

*

1

*

0

1

CGRAM data writing

RE=”0”

Display Control

Dot matrix display “ON”

Icon display ”ON”

Data Display

Refer to (13-3) Superimpose Mode.

Ver.2009-05-20

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Preliminar

NJU6645

ꢀ ABSOLUTE MAXIMUM RATINGS

PARAMETER

Supply Voltage (1)

Supply Voltage (2)

Supply Voltage (3)

Supply Voltage (4)

Supply Voltage (5)

Supply Voltage (6)

Input Voltage (1)

Operating

SYMBOL

VDD

CONDITION

TERMINAL

VDD

RATING

-0.3 to +4.0

UNIT

V

VEE

-0.3 to +4.0

V

VOUT, VDCOUT

VREG

VSS=0V

Common

Ta=+25°C

VOUT, VDCOUT

VREG

-0.3 to +19.0

-0.3 to VLCD+0.3

-0.3 to VDD+0.3

V

VLCD

V

V1, V2, V3, V4

VI

V1, V2, V3, V4

V

Topr

Tstg

-40 to +85

°C

Temperature

Storage Temperature

Bump Chip

-55 to +125

*1 If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI

within electrical characteristics is strongly recommended for normal operation. Use beyond the electric

characteristics conditions will cause malfunction and poor reliability.

*2 The order of turning on the power supply should turn on VDD earlier than other power supplies. When the

power supply is turned off, that requires turning off VDD at the last.

ꢀ RECOMMENDED OPERATING CONDITIONS

PARAMETER

Supply Voltage

SYMBOL

VDD1

VDD2

VEE

VLCD

VOUT

VDCOUT

VREG

VREF

TERMINAL

VDD

MIN

2.4

4.5

-

TYP

MAX

3.6

UNIT NOTE

-

V

*1

*2

*3

*4

3.6

VEE

VLCD

VOUT

VDCOUT

VREG

VREF

3.6

17.0

Operating Voltage

-

17.0

-

1.8

VOUTx0.9

3.6

*5

*6

*1 Applied to the condition when the reference voltage generator (VBA) is not used. (VSS common)

*2 Applied to the condition when the reference voltage generator (VBA) is used. (VSS common)

*3 Applied to the condition when the voltage booster is used.

*4 The following relation among the LCD bias voltages must be maintained.

VSS<V4<V3<V2<V1<VLCD≤VOUT

*5 When the voltage booster is used, there is possibility that the VDCOUT is changing by the ITO resistance

and the panel load. The setting of the VREG voltage is recommended to become a voltage that is lower than

the lowest value of the changing VOUT.

*6 Relation : VREF < VEE must be maintained.

*7 To stabilize the LSI operation, place decoupling capacitors between VDD and VSS, between VEE and VSS,

between VBA and VSS, between VREF and VSS, between VREG and VSS, between VLCD and VSS, and

between V1 to V4 and VSS.

Ver.2009-05-20

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Preliminar

NJU6645

ꢀ DC CHARACTERISTICS

VDD=+2.4 to 3.6V, VSS=0V, Ta=-40 to +85°C

SYM

PARAMETER

BOL

CONDITION

MIN

TYP

MAX

UNIT NOTE

“H” Level Input Voltage

“L” Level Input Voltage

VIH

VIL

0.8VDD

-

VDD

V

*1

*2

*3

*4

VSS

0.2VDD

“H” Level Output Voltage VOH IOH=-0.1mA

“L” Level Output Voltage VOL IOL= 0.1mA

VDD-0.2

-

0.2

1

-

-1

-

VI=VSS or VDD

VON|=0.5V, VLCD=10V

∆VON|=0.5V, VLCD=6V

Input Leakage Current

Output Leakage Current

ILI

-

µ

A

ILO

-

1

µ

A

RON1

RON2

fOSC

1

2

1

2

|

∆

|

k

Ω

Driver ON-resistance

*5

*6

*7

-

4

k

Oscillation Frequency

0.82

1.18

MHz

VDD=3V, Ta=25

°C, Rf=47kΩ

N-time boost (N=2 to 6)

Voltage Booster

Output Voltage

NxVEE

VOUT

IDD1

IDD2

-

V

x0.95

RL=500k

Ta=25 C, 6-time boost, All pixels ON,

VEE=2.4V, VREF=1.8V

Ta=25 C, 5-time boost, All pixels ON,

VEE=3.0V, VREF=2.25V

Ta=25 C, 4-time boost, All pixels ON,

VEE=3.6V, VREF=2.7V

Ω (VDCOUT-VSS)

°

Operating Current (1)

-

1.5

3.6

mA

°

*8

Operating Current (2)

°

Operating Current (3)

Operating Current (4)

VBA Output Voltage

IDD3

ISTB

VBA

1.5

-

(0.75VEE)x

0.98

10

(0.75VEE)x

1.02

*9

Ta=25

°

C, CSb=VDD, HALT="1”

VEE=2.4 to 3.6V

µA

0.75VEE

V

*10

VEE=2.4 to 3.6V

(VREFxN)x

0.95

(VREFxN)x

1.05

VREG Output Voltage

VREG

(VREFxN)

V

*11

N-time boost (N=2 to 6)

VLCD VEE=3.0V, VREF=2.25V,

-0.1

-

+0.1

V

VOUT=15V, Bias=1/4 to 1/11,

Electrical Volume=MAX., DCON=”0”,

Display OFF, No-load, AMPON=”1”,

Boost Level=5-time

V1

V2

V3

V4

-0.1

+0.1

LCD Bias Voltages

-0.1

+0.1

-0.1

+0.1

-0.1

+0.1

*1 D7 to D0, CSb, RS, WRb, RDb, SEL68, PS, CSEL, and RSTb terminals.

*2 D7 to D0 terminals.

*3 D7 to D0, CSb, RS, WRb, RDb, SEL68, PS, CSEL, RSTb, and OSC2 terminals.

*4 D7 to D0 in high impedance.

*5 SEG0 to SEG255, COM0 to COM95, and COMMK0 to COMMK1 terminals.

This parameter defines the resistance between each COM/SEG and each LCD bias (VLCD, V1, V2, V3, V4).

0.5V difference / 1/11 LCD bias

*6 Oscillation frequency of using the internal oscillation circuit.

(OS2, OS1, OS0) = ”0, 0, 0”

*7 VDCOUT terminal.

This parameter is applied to the condition that the internal LCD power supply and the internal oscillator are

used. N-time boost (N=2 to 6).

VEE=2.4V to 3.6V / Electrical Volume : Max = “1, 1, 1, 1, 1, 1, 1” / 1/11 LCD Bias / 1/98 Duty / No-load on

COM/SEG / RL=500k

Ω between VDCOUT and VSS / CA1=CA2=1.0uF / CA3=0.1uF / DCON=”1” /

AMPON=”1”

*8 VSS terminal.

This parameter is applied to the condition that the internal LCD power supply and the internal oscillator are

used, and the no accessing from MPU.

Electrical Volume : Max = “1, 1, 1, 1, 1, 1, 1” / All pixels ON or Checker Flag Display / No-load on

COM/SEG / VDD=VEE / VREF=0.75VEE / CA1=CA2=1.0uF / CA3=0.1uF / DCON=”1” / AMPON=”1” /

NL6 to 0=”1, 1, 0, 0, 0, 0, 1” (98-line) / 1/98 Duty / Ta=25°C

*9 VDD terminal.

Internal oscillator is halted. / CSb=VDD (No active) / No-load

Ver.2009-05-20

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Preliminar

NJU6645

*10 VBA terminal.

VBA=VREF / Boost Level (N)=”1” / DCON=”0” / VOUT=13.5V

*11 VREG terminal.

VEE=2.4V to 3.6V / VOUT=17V / 1/11 LCD Bias / 1/98 Duty / Electrical Volume : Max = “1, 1, 1, 1, 1, 1,

1” / Checker Flag Display / No-load on COM/SEG / Boost Level (N)=”2 to 6” / CA1=CA2=1.0uF /

CA3=0.1uF / DCON=”0” / AMPON=”1” / NL6 to 0=”1, 1, 0, 0, 0, 0, 1” (98-line)

Ver.2009-05-20

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Preliminar

NJU6645

ꢀ OSCILLATION FREQUENCY AND FRAME FREQUENCY

OSCILLATOR

/EXTERNAL

CLOCK

DISPLAY DUTY (1/D)

50

98

82

66

34

18

Using

f_OSC/(128xD) f_OSC/(128xD) f_OSC/(128xD) f_OSC/((128xD)/2) f_OSC/((128xD)/3) f_OSC/((128xD)/6)

f_CK/(128xD) f_CK/(128xD) f_CK/(128xD) f_CK/((128xD)/2) f_CK/((128xD)/3) f_CK/((128xD)/6)

Internal Oscillator

Using

External Clock

Ver.2009-05-20

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Preliminar

NJU6645

ꢀ AC CHARACTERISTICS

(1) Write Operation (Parallel Interface / 80-series MPU)

t_RSS8

t_RSH8

RS

t_WCS8

t_CSS8

t_CSH8

CSb

t_WRLW8

t_WRHW8

WRb

t_DS8

t_DH8

D7 to D0

t_CYC8

(VDD=2.4 to 3.6V, Ta=-40 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

RS Hold Time

t_RSH8

t_RSS8

t_CSH8

t_CSS8

30

ns

-

RS

RS Setup Time

30

CSb Hold Time

30

-

CSb

CSb Setup Time

30

CSb ”H” Level Pulse Width

System Cycle Time

Enable ”L” Level Pulse Time

Enable ”H” Level Pulse Time

Data Setup Time

t_WCS8

t_CYC8

t_WRLW8

t_WRHW8

t_DS8

180

80

-

WRb

80

70

D7 to D0

Data Hold Time

t_DH8

40

Note) Each timing is specified based on 20% and 80% of VDD.

Ver.2009-05-20

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Preliminar

NJU6645

(2) Read Operation (Parallel Interface / 80-series MPU)

t_RSS8

t_RSH8

RS

CSb

t_WCS8

t_CSS8

t_CSH8

t_WRLR8

t_WRHR8

RDb

t_RDH8

D7 to D0

t_RDD8

t_CYC8

(VDD=2.4 to 3.6V, Ta=-40 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

ns

TERMINAL

RS Hold Time

RS Setup Time

CSb Hold Time

CSb Setup Time

t_RSH8

40

-

RS

t_RSS8

40

ns

t_CSH8

40

ns

-

CSb

t_CSS8

40

ns

CSb ”H” Level Pulse Width

System Cycle Time

t_WCS8

t_CYC8

t_WRLR8

t_WRHR8

140

250

120

ns

-

RDb

Enable ”L” Level Pulse Time

Enable ”H” Level Pulse Time

Read Data Delay Time

ns

t_RDD8

CL=15pF

110

ns

D7 to D0

Read Data Hold Time

t_RDH8

0

ns

Note) Each timing is specified based on 20% and 80% of VDD.

Ver.2009-05-20

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Preliminar

NJU6645

(3) Write Operation (Parallel Interface / 68-series MPU)

t_RSS6

t_RSH6

RS

t_WCS6

t_CSS6

t_CSH6

CSb

RW

(WRb)

t_EHW6

t_ELW6

E

(RDb)

t_DS6

t_DH6

D7 to D0

t_CYC6

(VDD=2.4 to 3.6V, Ta=-40 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

RS Hold Time

t_RSH6

t_RSS6

t_CSH6

t_CSS6

t_WCS6

t_CYC6

t_ELW6

t_EHW6

t_DS6

30

ns

-

RS

RS Setup Time

30

CSb Hold Time

30

-

CSb

CSb Setup Time

30

CSb ”H” Level Pulse Width

System Cycle Time

Enable ”L” Level Pulse Time

Enable ”H” Level Pulse Time

Data Setup Time

180

80

-

E

80

70

D7 to D0

Data Hold Time

t_DH6

40

Note) Each timing is specified based on 20% and 80% of VDD.

Ver.2009-05-20

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Preliminar

NJU6645

(4) Read Operation (Parallel Interface / 68-series MPU)

t_RSS6

t_RSH6

RS

t_WCS6

t_CSS6

t_CSH6

CSb

RW

(WRb)

t_EHR6

t_ELR6

E

(RDb)

t_RDH6

D7 to D0

t_RDD6

t_CYC6

(VDD=2.4 to 3.6V, Ta=-40 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

RS Hold Time

RS Setup Time

CSb Hold Time

CSb Setup Time

t_RSH6

t_RSS6

t_CSH6

t_CSS6

t_WCS6

t_CYC6

t_ELR6

t_EHR6

40

ns

-

RS

40

-

CSb

40

CSb ”H” Level Pulse Width

System Cycle Time

140

250

120

-

E

Enable ”L” Level Pulse Time

Enable ”H” Level Pulse Time

Read Data Delay Time

t_RDD6

CL=15pF

110

D7 to D0

Read Data Hold Time

t_RDH6

0

Note) Each timing is specified based on 20% and 80% of VDD.

Ver.2009-05-20

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Preliminar

NJU6645

(5) Serial Interface

RS

t_AAS

t_AHS

RW

CSb

SCL

t_AAS

t_AHS

t_CSS

t_CYCS

t_CSH

t_WCSS

t_SHW

t_SLW

t_DSS

t_DHS

Input

SDA

Input

Input or

Output

Input or

Output

Input

t_SOD

Input

t_SOD

SDA

Input or

Output

Output Output

(VDD=2.4 to 3.6V, Ta=-40 to +85°C)

PARAMETER

Serial Clock Cycle

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

t_CYCS

t_SHW

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

t_SOD

t_CSS

160

75

35

-

ns

-

SCL

SCL ”H” Level Pulse Width

SCL ”L” Level Pulse Width

Address Setup Time

Address Hold Time

Data Setup Time

-

RS / RW

-

SDA

Data Hold Time

Serial Data Delay Time

CSb – SCL Time

40

35

CSb Hold Time

t_CSH

t_WCSS

35

-

CSb

CSb “H” Level Pulse Width

75

ns

Note) Each timing is specified based on 20% and 80% of VDD.

Ver.2009-05-20

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Preliminar

NJU6645

ꢀ External Clock Input Timing

OSC2

0.5VDD

f_CP

(VDD=2.4 to 3.6V, VSS=0V, Ta=-40 to +85°C)

PARAMETER

External Clock Operating Frequency

External Clock Duty

SYMBOL

f_CP

MIN.

MAX.

1.18

65

CONDITION

OSC2

UNIT

MHz

%

-

duty

35

ꢀ Reset Input Timing

t_RW

RSTb

t_R

Internal circuit

status

During reset

End of reset

(VDD=2.4 to 3.6V, VSS=0V, Ta=-40 to +85°C)

PARAMETER

Reset Time

RSTb “L” Level Pulse Width

SYMBOL

MIN.

-

1.5

MAX.

CONDITION

UNIT

µs

t_R

0.5

-

t_RW

ms

Ver.2009-05-20

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Preliminar

NJU6645

ꢀ APPLICATION CIRCUIT

(1) Microprocessor Interface Example

(i) 80 type MPU

2.4 to 3.6V

VCC

VDD

NJU6645

A0

RS

CSb

A1~A7

Decoder

8

7

15

7

(80 type MPU) IORQb

D0~D7

RDb

D0~D7

RDb

WRb

RESb

RSTb

GND

VSS

Reset input

(ii) 68 type MPU

2.4 to 3.6V

VCC

VDD

NJU6645

A0

A1~A15

RS

CSb

Decoder

8

(68 type MPU) VMA

D0~D7

E

R/W

RESb

D0~D7

RDb(E)

WRb(R/W)

RSTb

GND

VSS

Reset input

(iii) Serial Interface

2.4 to 3.6V

NJU6645

VCC

GND

VDD

A0

A1~A7

RS

CSb

Decoder

(CPU)

PORT1

PORT2

RESb

SDA

SCL

RSTb

VSS

Reset input

Ver.2009-05-20

- 108 -

Preliminar

NJU6645

(2) Connection with Panel Display

(i) SEL1=”0”, SEL2=”0”

ABCDEFG

HIJKLMN

OPQRSTU

VWXYZ

COMMK1

COM47

COM95

:

COM0

COMMK0

NJU6645

TOP VIEW

COM48

(ii) SEL1=”1”, SEL2=”1”

COMMK0

NJU6645

TOP VIEW

COM48

COM0

:

COM95

COM47

COMMK1

ABCDEFG

HIJKLMN

OPQRSTU

VWXYZ

Ver.2009-05-20

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Preliminar

NJU6645

(iii) SEL1=”1”, SEL2=”0”

COMMK0

NJU6645

BOTTOM VIEW

COM48

COM0

:

COM95

COM47

COMMK1

ABCDEFG

HIJKLMN

OPQRSTU

VWXYZ

(iv) SEL1=”0”, SEL2=”1”

ABCDEFG

HIJKLMN

OPQRSTU

VWXYZ

COMMK1

COM47

COM95

:

COM0

NJU6645

BOTTOM VIEW

COM48

COMMK0

Ver.2009-05-20

- 110 -

Preliminar

NJU6645

ꢀ COG WIRING EXAMPLE

COG

80type Parallel

CSEL="L"

Using Internal OSC

Using Voltage Boost

Using Internal OP-amp

NJU6645

C5N

C5P

C4N

C4P

C3N

C3P

C2N

C2P

C1N

C1P

VEE

*When the voltage booster is used,

VDCOUT

VOUT

VSS

VDCOUT terminal and VOUT terminal

should be not connect at ITO of inside panel,

and it requires to connect at outside of COG.

VBA

VREF

VREG

V4

V3

V2

V1

VLCD

VSS

OSC1

VDD

OSC2

D7

D6

D5

D4

D3

D2

D1

D0

VPUP

RDB

WRB

VPDN

RS

CSB

RSTB

CSEL

VPUP

PS

VPUP

SEL68

TESTOUT

Ver.2009-05-20

- 111 -

Preliminar

NJU6645

[CAUTION]

The specifications on this databook are only

given for information , without any guarantee

as regards either mistakes or omissions. The

application circuits in this databook are

described only to show representative usages

of the product and not intended for the

guarantee or permission of any right including

the industrial rights.

Ver.2009-05-20

- 112 -


型号：	NJU6645CJ
厂家：	NEW JAPAN RADIO
描述：	16-CHARACTER 6-LINE LCD DRIVER with JAPANESE KANJI ROM 16个字符的6行LCD驱动器，采用日本汉字ROM 显示驱动器驱动程序和接口接口集成电路 CD
文件：	总112页 (文件大小：2042K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NJU6645CJ [NJRC]

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