NJU6674CJ_技术文档

NJU6674

38-common x 132-segment+1-icon common

Bitmap LCD Driver

ꢀ GENERAL DESCRIPTION

ꢀ PACKAGE

The NJU6674 is a Bitmap LCD Driver to display

graphics or characters.

It contains 5,148 bits display data RAM, Microprocessor

interface circuits, instruction decoder, 38-common and

132-segment +1-icon common drivers.

The bit image display data is transferred to the display

data RAM by serial or 8-bit parallel interface.

39 x 132 dots graphics or 10-character 3-line by 12 x 13

dot character with icon are displayed by NJU6674 itself.

The wide operating voltage from 2.4V to 3.3V and low

operating current are suitable for small sized battery

operated items.

NJU6674CJ

ꢀ FEATURES

ꢁ Direct Correspondence between Display Data RAM and LCD Pixel

ꢁ Display Data RAM

ꢁ LCD Drivers

: 5,148-bit

: 132-seg, 38-com+1-icon com

ꢁ Bias select 1/5 bias or 1/6 bias

ꢁ Direct interface with 68 and 80 type MPU

ꢁ Serial interface (SI, SCL, A0, CS₁B, CS₂)

ꢁ Useful Instruction Set

Display ON/OFF ,Display Start Line Set, Page Address Set, Column Address Set, Status Read,

Display Data Write, Display Data Read, ADC Select, Inverse Display, Entire display ON/OFF, Bias Select,

Read Modify Write, End, Reset, Power control set, Internal resistor ratio set, EVR Register Set,

EVR Mode Set, Power saving

ꢁ Power Supply Circuits for LCD incorporated

Step up circuit (x2, x3, x4), Regulator, Voltage Follower x4, V₅level is adjusted by internal bleeder

resistancePrecision Electrical Variable Resistance (64-steps)

ꢁ

Bias Stabilization Capacitor less

ꢁ Low power consumption

ꢁ Operating Voltage (All the voltages are based on V_DD=0V.)

• Logic Operating

-2.4 to -3.3V

• Voltage Booster Operating Voltage

• LCD Driving voltage

-2.4 to -3.3 V

-5.0 to -10.0V

ꢁ Rectangle outlook for COG

ꢁ Package outline: Bump-chip

ꢁ C-MOS Technology

(Substrate: N)

Ver.2003-04-08

- 1 -

NJU6674

ꢀ PAD LOCATION

ALI_A1

ALI_B2

DUMMY₁

Chip Center

Chip Size

Chip Thickness

Bump Size

PAD Pitch

Bump Height

Bump Material

:X=0µm,Y=0µm

:X=10.38mm, Y= 2.51mm

:400µm±30µm

:78.16µm x 48.10µm

:72µm(Min)

S₁₃₁

S₁₃₀

DUMMY₁₅

CL

V_SS1

CS1B

CS2

V_DD

RESB

A0

V_SS1

:17.5µm(Typ)

:Au

Voltage Boosting Polarity

:Negative Voltage(V_DDcommon)

:N

WRB(R/WB)

RD(E)

V_DD

D₀

Substrate

D₁

D₂

D₃

D₄

•

Alignment marks

D₅

D₆(SCL)

D₇(SI)

V_DD

V_SS1

V_SS2

V_OUT

C₃-

110.34µm

C₃-

C₁+

C₁-

C₂-

C₂+

V_SS1

V_RS

V_DD

V₁

Y

70.38µm

X

V₁

V₂

ALI_B1, ALI_B2

V₂

V₃

V₄

V₅

VR

70.38µm

V_DD

TEST

V_DD

CLS

V_SS1

SEL68

P/S

V_DD

DUMMY₁₆

V_SS1

70.38µm

IRS

V_DD

DUMMY₁₇

ALI_A1, ALI_A2

DUMMY₂₅

Note) Alignment Marks are not contains window.

S₁

S₀

ALI_A2

ALI_B1

Ver.2003-04-08

- 2 -

NJU6674

ꢀ PAD COORDINATES

Chip Size 10.38x2.51mm(Chip Center X=0µm, Y=0µm)

PAD No.

1

Terminal

DUMMY₁

DUMMY₂

DUMMY₃

DUMMY₄

DUMMY₅

DUMMY₆

DUMMY₇

DUMMY₈

DUMMY₉

DUMMY₁₀

DUMMY₁₁

DUMMY₁₂

DUMMY₁₃

DUMMY₁₄

DUMMY₁₅

CL

V_SS1

CS1B

CS2

V_DD

RESB

A0

V_SS1

WRB

RDB

V_DD

D₀

PAD No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Terminal

C1+

X= µm

-4949

-4877

-4805

-4733

-4661

-4589

-4517

-4445

-4373

-4301

-4229

-4157

-4085

-4013

-3941

-3869

-3797

-3725

-3653

-3581

-3509

-3437

-3365

-3293

-3221

-3149

-2879

-2599

-2319

-2039

-1759

-1479

-1199

-919

-710

-638

-566

-494

-422

-350

-278

-206

-134

-62

10

82

154

226

298

370

Y= µm

-1098

X= µm

442

514

586

658

730

802

874

946

Y= µm

-1098

-943

2

3

4

5

6

7

8

9

C1-

C2-

C2+

V_SS1

V_RS

V_DD

V₁

V₂

V₃

V₄

V₅

VR

1018

1090

1162

1234

1306

1378

1450

1522

1594

1666

1738

1810

1882

1954

2026

2098

2170

2242

2314

2386

2458

2530

2602

2674

2746

2818

2890

2962

3034

3106

3178

3250

3322

3394

3466

3538

3610

3682

3754

5036

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

V_DD

TEST

V_DD

CLS

V_SS1

SEL68

P/S

V_DD

DUMMY₁₆

V_SS1

D₁

D₂

D₃

D₄

D₅

D₆(SCL)

D₇(SI)

V_DD

V_SS1

V_SS2

V_OUT

IRS

V_DD

DUMMY₁₇

DUMMY₁₈

DUMMY₁₉

DUMMY₂₀

DUMMY₂₁

DUMMY₂₂

DUMMY₂₃

DUMMY₂₄

DUMMY₂₅

ALI_A2

C₁₈

C3-

C1+

C₁₇

-871

Ver.2003-04-08

- 3 -

NJU6674

PAD No.

101

102

103

104

105

106

107

108

109

110

111

Terminal

PAD No.

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

Terminal

S₂₅

S₂₆

S₂₇

S₂₈

S₂₉

S₃₀

S₃₁

S₃₂

S₃₃

S₃₄

S₃₅

S₃₆

S₃₇

S₃₈

S₃₉

S₄₀

S₄₁

S₄₂

S₄₃

S₄₄

S₄₅

S₄₆

S₄₇

S₄₈

S₄₉

S₅₀

S₅₁

S₅₂

S₅₃

S₅₄

S₅₅

S₅₆

S₅₇

S₅₈

S₅₉

S₆₀

S₆₁

S₆₂

S₆₃

S₆₄

S₆₅

S₆₆

S₆₇

S₆₈

S₆₉

S₇₀

S₇₁

S₇₂

S₇₃

S₇₄

X= µm

5036

4716

4644

4572

4500

4428

4356

4284

4212

4140

4068

3996

3924

3852

3780

3708

3636

3564

3492

3420

3348

3276

3204

3132

3060

2988

Y= µm

-799

-727

-655

-583

-511

-439

-367

-295

-223

-151

-79

-7

65

137

209

281

353

425

569

X= µm

2916

2844

2772

2700

2628

2556

2484

2412

2340

2268

2196

2124

2052

1980

1908

1836

1764

1692

1620

1548

1476

1404

1332

1260

1188

1116

1044

972

900

828

756

684

612

540

468

396

324

252

180

108

36

-36

Y= µm

1098

C₁₆

C₁₅

C₁₄

C₁₃

C₁₂

C₁₁

C₁₀

C₉

C₈

C₇

C₆

C₅

C₄

C₃

C₂

C₁

C₀

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

COMS

DUMMY₂₆

DUMMY₂₇

DUMMY₂₈

DUMMY₂₉

DUMMY₃₀

DUMMY₃₁

ALI_B1

S₀

641

713

785

857

929

1089

1098

S₁

S₂

S₃

S₄

S₅

S₆

S₇

S₈

S₉

S₁₀

S₁₁

S₁₂

S₁₃

S₁₄

S₁₅

S₁₆

S₁₇

S₁₈

S₁₉

S₂₀

S₂₁

S₂₂

S₂₃

S₂₄

-108

-180

-252

-324

-396

-468

-540

-612

Ver.2003-04-08

- 4 -

NJU6674

PAD No.

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

Terminal

S₇₅

PAD No.

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

Terminal

S₁₂₅

X= µm

-684

-756

-828

-900

Y= µm

1098

X= µm

-4284

-4356

-4428

-4500

-4572

-4644

-4716

-5036

Y= µm

1098

1089

929

857

785

713

641

569

497

425

353

281

209

137

65

-7

-79

-151

-223

-295

-367

-439

-511

-583

-655

-727

-799

-871

-943

-1098

S₇₆

S₇₇

S₇₈

S₇₉

S₈₀

S₈₁

S₈₂

S₈₃

S₈₄

S₈₅

S₈₆

S₈₇

S₈₈

S₈₉

S₉₀

S₉₁

S₉₂

S₉₃

S₉₄

S₉₅

S₉₆

S₉₇

S₉₈

S₉₉

S₁₀₀

S₁₀₁

S₁₀₂

S₁₀₃

S₁₀₄

S₁₀₅

S₁₀₆

S₁₀₇

S₁₀₈

S₁₀₉

S₁₁₀

S₁₁₁

S₁₁₂

S₁₁₃

S₁₁₄

S₁₁₅

S₁₁₆

S₁₁₇

S₁₁₈

S₁₁₉

S₁₂₀

S₁₂₁

S₁₂₂

S₁₂₃

S₁₂₄

S₁₂₆

S₁₂₇

S₁₂₈

S₁₂₉

S₁₃₀

S₁₃₁

-972

-1044

-1116

-1188

-1260

-1332

-1404

-1476

-1548

-1620

-1692

-1764

-1836

-1908

-1980

-2052

-2124

-2196

-2268

-2340

-2412

-2484

-2556

-2628

-2700

-2772

-2844

-2916

-2988

-3060

-3132

-3204

-3276

-3348

-3420

-3492

-3564

-3636

-3708

-3780

-3852

-3924

-3996

-4068

-4140

-4212

ALI_B2

DUMMY₃₂

DUMMY₃₃

DUMMY₃₄

DUMMY₃₅

DUMMY₃₆

DUMMY₃₇

DUMMY₃₈

C₁₉

C₂₀

C₂₁

C₂₂

C₂₃

C₂₄

C₂₅

C₂₆

C₂₇

C₂₈

C₂₉

C₃₀

C₃₁

C₃₂

C₃₃

C₃₄

C₃₅

C₃₆

C₃₇

COMS

ALI_A1

Ver.2003-04-08

- 5 -

NJU6674

ꢀ BLOCK DIAGRAM

C₀

C₁₈S₀

S₁₃₁C₃₇

C₁₉

COMS

V_SS1

V_DD

C

O

M

S

Common

Drivers

Segment

Drivers

Common

Drivers

V₁to V₅

5

C1+

C1-

C2+

Common Timing

Generator

Shift

Register

Shift

Register

C2-

C3-

V_OUT

V_SS2

VR

Display Data Latch 132 bits

V_RS

IRS

Display Data RAM

132 x 39 bits

Column Address Decoder

Display

Timing

CL

Generator

Column Address Counter 8bit

Column Address Register 8bit

Oscillator

CLS

Multiplexer

Status

Instruction

Decoder

BF

Bus Holder

Internal Bus

Reset

RESB

MPU Interface

CS₁B CS₂

A0

P/S SEL68

RDB WRB

(E) (R/WB)

D₀to D₅

D₆(SCL)

D₇(SI)

Ver.2003-04-08

- 6 -

NJU6674

ꢀ TERMINAL DESCRIPTION

No.

1 to 15

85

Symbol

DUMMY₁to

DUMMY₃₈

I/O

Description

Dummy Terminals.

These are open terminals electrically.

89 to 97

119 to 124

259 to 265

20,26,

Power

V_DD

Power supply terminals.

35 to 38,

62 to 63,

76 to 77,

79,84,88

17,23,

V_SS1

GND Ground terminal.

39 to 41,

58 to 59,

81,86

42 to 45

60 to 61

64,65

Power

V_SS2

V_RS

V₁

Reference voltage for voltage booster

External reference voltage input terminal.

I

Power

LCD Driving Voltage Supplying Terminal. When the internal voltage

booster is not used, supply each level of LCD driving voltage from

outside with following relation.

66,67

68,69

V₂

V₃

70,71

V₄

V_DD≥V₁≥V₂≥V₃≥V₄≥V₅≥V_OUT

72,73

V₅

When the internal power supply is on, the internal circuits generate and

supply following LCD bias voltage from V₁to V₄terminal.

Bias

1/5 Bias

V₁

V₂

V₃

V₄

V₅+4/5 V_LCD

V₅+3/5 V_LCD

V₅+2/5 V_LCD

V₅+1/5 V_LCD

1/6 Bias

V₅+5/6 V_LCD

V₅+4/6 V_LCD

V₅+2/6 V_LCD

V₅+1/6 V_LCD

V_LCD=V_DD-V₅

50,51

52,53

56,57

54,55

48,49

46,47

C1+

C1-

C2+

C2-

C3-

V_OUT

O

Boosted capacitor connecting terminals used for voltage booster.

O

I

Voltage booster output terminal. Connect the boosted capacitor

between this terminal and V_SS1

.

74,75

VR

Voltage adjust terminal. V₅level is adjusted by external bleeder

resistance connecting between V_DDand V₅terminal.(IRS=”L”)

IRS terminal connect with "H" at the time of built-in resistance used.

“H” , this terminal must connect to "H" or "L".

27

28

29

30

31

32

33

34

87

D₀

D₁

D₂

D₃

D₄

I/O

P/S="H": Tri-state bi-directional Data I/O terminal in 8-bit parallel

operation.

P/S="L" : Serial data input terminal. (D₇)

Serial data clock signal input terminal. (D₆) Data from SI is

loaded at the rising edge of SCL and latched as the parallel

data at 8th rising edge of SCL.

D₅

D₆(SCL)

D₇(SI)

IRS

I

Internal resistor select terminal

“H”: Internal

“L”: External

This terminal must connect to "H" or "L".

Ver.2003-04-08

- 7 -

NJU6674

No.

22

Symbol

A0

I/O

I

Description

Connect to the Address bus of MPU. The data on the D₀to D₇is

distinguished between Display data and Instruction by status of A0.

A0

H

L

Discrimination.

Display Data

Instruction

21

I

Reset terminal. When the RESB terminal goes to “L”, the initialization is

performed.

RESB

Reset operation is executing during “L” state of RESB.

18

19

I

CS₁B

CS₂

Chip select terminal. Data Input/Output are available during CS₁B=”L” and

CS₂=”H”.

25

RDB(E)

RDB signal of 80 type MPU input terminal. Active "L"

During this signal is "L" , D₀to D₇terminals are output.

Enable signal of 68 type MPU input terminal. Active "H"

24

I

WRB(R/WB)

Connect to the 80 type MPU WRB signal. Active "L".

The data on the data bus input synchronizing the rise edge of this signal.

The read/write control signal of 68 type MPU input terminal.

R/WB

State

H

Read

L

Write

82

83

SEL68

P/S

I

MPU interface type selection terminal.

This terminal must connect to V_DDor V_SS.

SEL68

State

H

L

68 Type

80 Type

Serial or parallel interface selection terminal.

Chip

Select

Read

/Write

Data/Command

Serial Clock

P/S

Data

“H”

A0

D₀to D₇

-

CS₁B,

CS₂

RDB,

WRB

“L”

SI(D₇)

-

SCL(D₆)

CS₁B,

CS₂

RAM data and status read operation do not work in mode of the serial

interface.

In case of the serial interface (P/S="L"),RDB and WRB must be fixed "V_DD"

or " V_SS", and D₀to D₅are high impedance.

80

16

I

Terminal to select whether or enable or disable the display clock internal

oscillator circuit.

CLS=”H” : Internal oscillator circuit is enable

CLS=”L” : Internal oscillator circuit is disabled (requires external input)

When CLS=”L”, input the display clock through the CL terminal.

CLS

CL

I/O Display clock input/output terminal.

The following is true depending on the CLS status.

CLS

CL

“H”

Output

“L”

Input

Ver.2003-04-08

- 8 -

NJU6674

No.

117~99

266 to 284

Symbol

C₀to C₁₈

I/O

O

Description

LCD driving signal output terminals.

C

₁₉to C₃₇

ꢁ Common output terminals

ꢁ Segment output terminals

:C₀to C₃₇

:S₀to S₁₃₁

•

Common output terminal

The following output voltages are selected by the combination of

FR and status of common.

Scan Data

H

FR

H

L

H

L

Output Voltage

V₅

V_DD

V₁

L

V₄

126 to 257

S₀to S₁₃₁

O

Power Save

V_DD

•

Segment output terminal

The following output voltages are selected by the combination of

FR and data in the RAM.

RAM

Data

H

FR

Output Voltage

Normal

V_DD

V₅

Reverse

V₂

H

L

V₃

L

H

L

V₂

V₃

V_DD

V₅

Power Save

V_DD

118

285

COMS

TEST

O

I

COM output terminals for the indicator. Both terminals output the same

signal.

Leave these open if they are not used.

78

Maker testing terminal. Used for maker test (No connections )

Ver.2003-04-08

- 9 -

NJU6674

ꢀ Functional description

(1) Block circuits description

(1-1) Busy Flag (BF)

During internal operation, the LSI is being busy and can’t accept any instructions except “status read”.

The BF data is output through D₇terminal by the “status read” instruction.

When the cycle time (tcyc) mentioned in the “AC characteristics” is satisfied, the BF check isn’t required

after each instruction, so that MPU processing performance can be improved.

(1-2) Initial display line register

The initial display line register assigns a DDRAM line address, which corresponds, to COM₀by “initial

display line set” instruction. It is used for not only normal display but also vertical display scrolling and

page switching without changing the contents of the DDRAM.

However, the 39^thaddress for icon display can’t be assigned for initial display line address.

(1-3) Line counter

The line counter provides a DDRAM line address. It initializes its contents at the switching of frame

timing signal (FR), and also counts-up in synchronization with common timing signal.

(1-4) Column address counter

The column address counter is an 8-bit preset counter, which provides a DDRAM column address, and

it is independent of below-mentioned page address register.

It will increment (+1) the column address whenever “display data read” or “display data write”

instructions are issued. However, the counter will be locked when no-existing address above (84)H are

addressed. The count-lock will be able to be released by the “column address set” instruction again. The

counter can invert the correspondence between the column address and segment driver direction by

means of “ADC set” instruction.

(1-5) Page address register

The page address register provides a DDRAM page address.

The page address “1 to 3” should be used the D₀, D₁, D₂, D₃, D₄, D₅, D₆, D₇are valid.

The page address “4” should be used the only D₀, D₁, D₂, D₃, D₄, D₅are valid.

The last page address “5” should be used for icon display because the only D₀is valid.

(1-6) Display data RAM (DDRAM)

The DDRAM contains 5,148-bit, and stores display data, which are 1-to-1 correspondents to LCD panel

pixels.

When normal display mode, the display data “1” turns on and “0” turns off LCD pixels. When inverse

display mode, “1” turns off and “0” turns on.

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NJU6674

Page Address

(D₂,D₁,D₀)

Line

Address

Common

Driver

Data

Display Pattern

D₀

D₁

D₂

D₃

D₄

D₅

D₆

D₇

D₀

D₁

D₂

D₃

D₄

D₅

D₆

D₇

D₀

D₁

D₂

D₃

D₄

D₅

D₆

D₇

D₀

D₁

D₂

D₃

D₄

D₅

D₆

D₇

D₀

D₁

D₂

D₃

D₄

D₅

D₀

D₀=0

D₀=1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

C₀

C₁

C₂

C₃

C₄

C₅

C₆

C₇

C₈

0, 0, 0

0, 0, 1

0, 1, 0

0, 1, 1

Page 0

C₉

C₁₀

C₁₁

C₁₂

C₁₃

C₁₄

C₁₅

C₁₆

C₁₇

C₁₈

C₁₉

C₂₀

C₂₁

C₂₂

C₂₃

C₂₄

C₂₅

C₂₆

C₂₇

C₂₈

C₂₉

C₃₀

C₃₁

C₃₂

C₃₃

C₃₄

C₃₅

C₃₆

C₃₇

COMM*

Page 1

Page 2

Page 3

1, 0, 0

1, 0, 1

Page 4

Page 5

Column

Address(ADC)

00 01 02 03 04 05

83 82 81 80 7F 7E

82 83

01 00

Segment Drivers S₀S₁S₂S₃S₄S₅

S₁₃₀S₁₃₁

*: COMM is independent of the “Initial display line set” instruction and always corresponds to the 39^thline.

Fig.1 Display data RAM (DDRAM) Map

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NJU6674

(1-7) Common direction register

The common direction register specifies common driver’s scanning direction.

Table 1.

Common Drivers

99 284

C₁₈

PAD No. 117

Pin name C₀

266

C₁₉

C₃₇

Common direction

select(D₃)

“L”

“H”

COM₀

COM₃₇

COM₁₈

COM₁₉

COM₃₇

COM₀

COM₁₉

COM₁₈

The duty ratio setting and output assignment register are so controlled to operate independently that

duty ratio setting required to corresponding duty ratio for output assignment.

(1-8) Reset Circuit

The reset circuit initializes the LSI to the following status by using of the reset signal into the RESB

terminal.

• Reset status using the RES terminal:

1. Display off

2. Normal Display (Non-inverse display)

3. ADC select: Normal mode (D₀=0)

4. Power control register clear : D₂, D₁, D₀=”0, 0, 0”

5. Serial interface register clear

6. LCD bias select

: D₀=”0”(1/6 bias)

7. Entire display off

: D₀=”0” (Normal mode)

8. Read modify write off

9. Initial display line address : 00_H

10. Column address

11. Page address

: 00_H

: 0 page

12. Common direction register : Normal mode (D₃=0)

13. V₅level is adjusted by external bleeder resistance : D₂, D₁, D₀=”1, 0, 0”

14. EVR mode off and EVR register : D₅, D₄, D₃, D₂, D₁, D₀=”1, 0, 0, 0, 0, 0”

The RESB terminal should be connected to MPU’s reset terminal, and the reset operation should be

executed at the same timing of the MPU reset.

As described in the “DC characteristics”, it is necessary to input 10us(min.) or over “L” level signal

into the RESB terminal in order to carry out the reset operation. The LSI will return to normal operation

after about 1.0us(max.) from the rising edge of the rest signal.

In case of using external power supply for LCD driving voltage, the RESB terminal is required to be

being “L” level when the external power supply is turned-on.

The “Reset” instruction in Table.4 can’t be substituted for the reset operation by using of the RESB

terminal. It executes above-mentioned only 8 to 14 items.

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NJU6674

LCD driving circuits

(a) Common and segment drivers

LCD drivers consist of 38-common drivers, 132-segment divers and 1-icon-common driver.

As shown in “LCD driving waveform”, LCD driving waveforms are generated by the combination of

display data, common timing signal and internal FR timing signal.

(b) Display data latch circuit

The display data latch circuit temporally stores 132-bit display data transferred from the DDRAM in the

synchronization with the common timing signal, and then it transfers these stored data to the segment

drivers.

“Display on/off”, “inverse display on/off” and “entire display on/off” instructions control only the contents

of this latch circuit, they can’t change the contents of the DDRAM.

In addition, the LCD display isn’t affected by the DDRAM accesses during its displaying because the

data read-out timing from this latch circuit to the segment drivers is independent of accessing timing to the

DDRAM.

(c) Line counter and latch signal or latch Circuits

The clock line counter and latch signal to the latch circuits are generated from the internal display clock

(CL). The line address of display data RAM is renewed synchronizing with display clock (CL).

132bits display data are latched in display latch circuits synchronizing with display clock, and then

output to the LCD driving circuits. The display data transfer to the LCD driving circuits is executed

independently with RAM access by the MPU.

(d) Display timing generator

The display timing generates the timing signal for the display system bay combination of the master

clock CL and driving signal FR ( refer to Fig.2 ) The frame signal FR and LCD alternative signal generate

LCD driving waveform on the two frame alternative driving method.

(e) Common timing generation

The common timing is generated by display clock CL (refer to Fig.2)

37 38 1

2

3

4

5 6 7 8

36 37 38 1

2

3

4

5 6

7

CL

(LSI internal signal)

FR

C₀

V_DD

V₁

V₄

V₅

V_DD

V₁

C₁

V₄

V₅

RAM

DATA

V_DD

V₂

Sn

V₃

V₅

Fig.2 Waveform of Display Timing

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NJU6674

(f) Oscillator

This is the low power consumption CR oscillator which provides the display clock and voltage converter

timing clock. Either external or internal Oscillator can be selected by setting the CLS terminal to “L” or

“H” as shown in below.

CLS=”L” : External Oscillator

CLS=”H” : Internal Oscillator

When the internal oscillator is used, the CL terminal fixed to “H” or “L”.

When the external oscillator is used, the CL terminal into display clock.

(g) Internal power circuits

The internal power circuits are composed of x4 boost voltage converter, output voltage regulator

including 64-step EVR and voltage followers.

The optimum values of the external passive components for the internal power circuits, such as

capacitors for V₁to V₅terminals and feed back resistors for VR terminal, depend on LCD panel size.

Therefore, it is necessary to evaluate the actual LCD module with these external components in order to

determine the optimum values.

Each portion of the internal power circuits is controlled by “power control set” instruction as shown in

Table.2. In addition, the combination of power supply circuits is described in Table.3.

Table.2 Power control set

Bits

Portions

Status

D₂

D₁

D₀

Voltage converter

Voltage regulator

Voltage followers

1 :On

0: Off

Table.3 Power supply combinations

Status

D₂

D₁

D₀

Voltage

converter

Voltage

regulator

Voltage

followers

External

voltage

Capacitor

terminals

Using all internal power circuits

Using voltage regulator and

Voltage followers

1

0

1

On

Off

On

V_SS2

_OUT, V_SS2

Use

Open

V

Using voltage followers

0

1

0

Off

On

Off

V_OUT, V₅,

V_SS2

Open

Using only external power supply

V_OUT

,

V₁to V₅

Note1) Capacitor input terminals: C1+, C1-, C2+, C2-, C3-

Note2) Do not use other combinations except examples in Table.3.

Note3) Connect decoupling capacitors on V₁to V₅terminals whenever using the voltage followers.

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NJU6674

- Power Supply applications

Power Control Instruction

D₂: Boost Circuit

D₁: Voltage Regulator

D₀: Voltage Follower

(1) Internal power supply Example.

V₅level is adjusted by internal bleeder

resistance (IRS=”H”)

(2) Internal power supply Example.

V₅level is adjusted by internal bleeder

resistance (IRS=”L”)

All of the Internal Booster, Voltage Regulator,

Voltage Follower using. (D₂,D₁,D₀) = (1,1,1)

All of the Internal Booster, Voltage Regulator,

Voltage Follower using. (D₂,D₁,D₀) = (1,1,1)

IRS

V

DD

V

DD

+

C1^-

C1⁺

C3^-

C2⁺

C2^-

C1^-

C1⁺

C3^-

C2⁺

C2^-

1

+

2

3

4

V

5

V

5

OUT

SS2

V

DD

VR

V5

V

DD

VR

V5

*

:Bias capacitors are selected depending on the LCD panel.

The evaluation in various display patterns should be experimented in the application.

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NJU6674

(3) Only V_OUTSupply from outside Example.

(4) Only V_OUTSupply from outside Example.

V₅level is adjusted by internal bleeder

resistance (IRS=”L”)

V₅level is adjusted by internal bleeder

resistance (IRS=”H”)

Internal Voltage Regulator,

Voltage Follower using.

(D₂,D₁,D₀) = (0,1,1)

Internal Voltage Regulator,

Voltage Follower using.

(D₂,D₁,D₀) = (0,1,1)

IRS

V

DD

V

DD

+

1

2

+

3

+

4

V

5

V

5

OUT

SS2

V

DD

VR

V5

V

DD

VR

V5

(5) V_OUTand V₅Supply from outside Example.

Internal Voltage Follower using.

(D₂,D₁,D₀) = (0,0,1)

(6) External Power Supply Example.

All of V₁to V₅and V_OUTsupply from outside

(D₂,D₁,D₀) = (0,0,0)

V

DD

V

DD

+

1

2

3

4

V

5

V

5

OUT

SS2

OUT

SS2

: These switches should be open during the power save mode.

: *Bias capacitors are selected depending on the LCD panel.

The evaluation in various display patterns should be experimented in the application.

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NJU6674

ꢀ INSTRUCTION SET

The NJU6674 distinguishes the data on the data bus D₇to D₀as an instruction by combination of A0, RDB(E),

WRB(R/W) signals. The decoding of the instruction and execution performs with only high speed internal timing without

relation to the external clock. Therefore, no busy flag check required normally. In case of the serial interface, the data input

as MSB(D₇) first serially. Table.4 shows the instruction codes of the NJU6674.

Table.4 Instruction table

Instruction Code

Instruction

Description

A0 RDB WRB D₇D₆D₅D₄D₃D₂D₁D₀

LCD Display ON/OFF

D₀=0:OFF D₀=1:ON

(a) Display ON/OFF

0

1

0

1

0

1

0

1

0

1

0

1

0/1

Initial display

(b)

Determine the Display Line of

RAM to COM ₀

Start address

Page

Line set

Set the page of DD RAM to the

Page Address Register

Set the Higher order 4 bits Column

Address to the Reg.

(c) Page address set

1

0

1

0

*

Address

Column address set

(Upper 4-bit)

Higher Order

Culomn Address

(d)

Column address set

(Lower 4-bit)

Set the Lower order 4 bits Column

Address to the Reg.

Lower Order

0

1

0(1)

1

0

1

0

Culomn Address

(e) Status read

Status

0

Read out the internal Status

Write the data into the Display

Data RAM

(f) Display data write

Write Data

Read Data

Read the data from the Display

Data RAM

(g) Display data read

(h) ADC select

1

0

1

0

Set the DD RAM vs Segment

D₀=0:Normal D₀=1:Inverse

Inverse the ON and OFF Display

D₀=0:Normal D₀=1:Inverse

Whole Display Turns ON

D₀=0:Normal D₀=1: Whole Disp.

ON

1

0

1

0

1

0

1

0/1

Inverse display

(i)

On/Off

Entire display

On/Off

(j)

(k)

(l)

0

1

0

1

0

1

0

1

0

1

0

0/1

0

LCD bias select

Set the LCD bias ratio

D₀=0:1/6

Increment the Column Address

Register when writing but

no-change when reading

D₀=1:1/5

Read modify write

Release from the Read Modify

write Mode

(m) End

0

1

0

1

0

1

0

1

0

*

1

*

0

*

(n) Reset

Initialize the Internal Circuits

Select common direction

D₃=0:Normal D₃=1:Inverse

Set the status of internal power

Circuits

Common direction

(o)

(p)

(q)

0/1

select

Power control set

0

1

0

1

0

1

D₂D₁D₀

Internal resistor

ratio set

Set the status of internal

resistor ratio (Ra/Rb)

0

1

0

EVR mode set

EVR register set

Pawer save

(r)

(s)

(t)

0

1

0

1

*

0

1

Set EVR mode

*

Setting Data

Set EVR register

Set the Power Save Mode

(LCD Display OFF)

0

1

0

1

0

1

0

1

0

1

0

1

mode On/Off

(u) NOP

Reserve

0

1

0

1

*

1

0

*

1

*

0

*

0

1

*

0

1

*

1

0

*

1

0

*

(v)

Inhibited command

(Inhibited)

(w) Test

0

1

0

1

0

1

0

1

0/1

Inhibited command

(*Don’t Care)

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NJU6674

(2) Instruction description

(a) Display On/Off

The “Display ON/OFF” instruction is used to control the display ON or OFF without changing the

display data in the DDRAM.

All of the COM terminals at the time of “Display OFF” and SEG terminals are set to V_DDlevel.

A0

0

RDB WRB

D₇

1

D₆

0

D₅

1

D₄

0

D₃

1

D₂

1

D₁

1

D₀

D

1

0

D

0: Display Off

1: Display On

(b) Initial display line set

This instruction specifies the DDRAM line address which corresponds to the COM₀position.

By means of repeating this instruction, the initial display line address will be dynamically changed; it

means smooth display scrolling will be enabled.

A0

0

RDB WRB

D₇

0

D₆

1

D₅

A₅

D₄

A₄

D₃

A₃

D₂

A₂

D₁

A₁

D₀

A₀

1

0

A₅

0

:

A₄

0

:

A₃

0

:

A₂

A₁

A₀

Line address (HEX)

0

:

0

:

0

1

:

00

01

:

1

0

1

0

1

25

(c) Page address set

In order to access to the DDRAM for writing or reading display data, both “page address set” and

“column address set” instructions are required before accessing.

The last page address “5” should be used for icon display because the only D₀is valid.

A0

0

RDB WRB

D₇

1

D₆

0

D₅

1

D₄

1

D₃

*

D₂

A₂

D₁

A₁

D₀

A₀

1

0

(*: Don’t Care)

A₂

A₁

A₀

0

1

0

1

Page

0

1

0

1

0

1

2

3

4

5

0

1

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NJU6674

(d) Column address set

As above-mentioned, in order to access to the DDRAM for writing or reading display data, it is

necessary to execute both “page address set” and “column address set” before accessing. The 8-bit

column address data will be valid when both upper 4-bit and lower 4-bit data are set into the column

address register.

Once the column address is set, it will automatically increment (+1) whenever the DDRAM will be

accessed, so that the DDRAM will be able to be continuously accessed without “column address set”

instruction.

The column address will stop increment and the page address will not be changed when the last

address (83)H is addressed.

A0

0

RDB WRB

D₇

0

D₆

0

D₅

0

D₄

1

D₃

A₇

D₂

A₆

D₁

A₅

D₀

A₄

1

0

Upper 4-bit

Lower 4-bit

0

1

0

A₃

A₂

A₁

A₀

A₇

0

:

A₆

A₅

0

:

A₄

0

:

A₃

0

:

A₂

0

:

A₁

A₀Column address (HEX)

0

:

0

:

0

1

:

00

01

:

1

0

1

83

(e) Status read

This instruction reads out the internal status regarding “busy flag”, “ADC select”, “display on/off” and

“reset”.

A0

0

RDB WRB

D₇

BUSY

D₆

ADC

D₅

D₄

D₃

0

D₂

0

D₁

0

D₀

0

ON/OFF RESET

0

1

BUSY: When D₇is “1”, the LSI is being busy and can’t accept any instructions.

ADC: It shows the correspondence between the column address and segment drivers.

When D₆is “0”, the column address (131-n) corresponds to segment driver n.

When D₆is “1”, the column address (n) corresponds to segment driver n.

Please be careful that read out data is opposite of “ADC select” instruction data.

ON/OFF: It shows display on or off status.

When D₅is “0”, the LSI is in display-on status.

When D₅is “1”, the LSI is in display-off status.

Please be careful that read out data is opposite of “Display On/Off” instruction data.

RESET: It shows reset status.

When D₄is “0”, the LSI is in normal operation.

When D₄is “1”, the LSI is during reset operation.

(f) Display data write

This instruction writes display data into the selected column address on the DDRAM.

The column address automatically increments (+1) whenever the display data is written by this

instruction, so that this instruction can be continuously issued without “column address set” instruction.

A0

1

RDB WRB

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

1

0

Write Data

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NJU6674

(g) Display data read

This instruction reads out the display data stored in the selected column address on the DDRAM.

The column address automatically increments (+1) whenever the display data is read out by this

instruction, so that this instruction can be continuously issued without “column address set” instruction.

After the ”column address set” instruction, a dummy read will be required, please refer to the (4-5).

In case of using serial interface mode, this instruction can’t be used.

A0

1

RDB WRB

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

0

1

Read Data

(h) ADC select

This instruction selects segment driver direction.

The correspondence between the column address and segment driver direction is shown in Fig.1.

Segment Driver Output order is inverse, when this instruction executes, therefore, the placement

NJU6674 against the LCD panel becomes easy.

A0

0

RDB WRB

D₇

1

D₆

0

D₅

1

D₄

0

D₃

0

D₂

0

D₁

0

D₀

D

1

0

D

0: Clokwise Output(Normal)

1: Counterclockwise Output(Inverse)

(i) Inverse display On/Off

This instruction inverses the status of turn-on or turn-off of entire LCD pixels. It doesn’t change the

contents of the DDRAM.

A0

0

RDB WRB

D₇

1

D₆

0

D₅

1

D₄

0

D₃

0

D₂

1

D₁

1

D₀

D

1

0

D

0: Normal

1: Inverse

RAM data “1” correspond to “On”

RAM data “0” correspond to “On”

(j) Entire display On/Off

This instruction turns on entire LCD pixels regardless the contents of the DDRAM. It doesn’t change the

contents of DDRAM. This instruction executed prior to the “Normal or Inverse display On/Off Set”

Instruction.

A0

0

RDB WRB

D₇

1

D₆

0

D₅

1

D₄

0

D₃

0

D₂

1

D₁

0

D₀

D

1

0

D

0: Normal Display

1: Whole Display turns On

When the “Entire display On” instruction is executed at Display Off states, the NJU6674 operates in

Power Save Mode. (Refer “Power Save Mode”)

(k) LCD bias set

This instruction selects LCD bias value.

A0

0

RDB WRB

D₇

1

D₆

0

D₅

1

D₄

0

D₃

0

D₂

0

D₁

1

D₀

D

1

0

D

0: 1/6 bias

1: 1/5 bias

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NJU6674

(l) Read modify write

This instruction sets the Read Modify Write controlling the Column Address increment. In this mode,

Column Address only increments when execute the display data “Write” instruction; but no change when

the display data “Read” Instruction. This states is continued until the End instruction(m) execution. When

the End instruction is executed, the Column Address goes back to the start address before the execution

of this “Read Modify Write” instruction. This function reduces the load of MPU for repeating display data

change of the fixed area.

A0

0

RDB WRB

D₇

1

D₆

1

D₅

1

D₄

0

D₃

0

D₂

0

D₁

0

D₀

0

1

0

*) In this “Read Modify Write” mode, out of display data “Read”/”Write”, any instructions except

“Column Address Set” can be executed.

ꢁ The sequence of cursor blink display

Page Address Set

Set to the Start Address

of Cursor Display(*)

Column Address Set

Start the Read Modify Write

Read Modify Write

Dummy Read

Data Read

The data is ignored

Column Counter doesn’t increase

Data inverse by MPU

Data Write

Column Counter increase

Dummy Read

Column Counter doesn’t increase

Column Counter increase

Data Read

Data Write

Dummy Read

Data Read

Data Write

Column Counter doesn’t increase

Column Counter increase

End the Read Modify Write

End

No

Finish?

Yes

Column Address goes

back to the start address.(*)

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NJU6674

(m) End

The “end” instruction cancels the read modify write mode and makes the column address return to the

initial value just before “read modify write” is started.

A0

RDB WRB

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

0

1

0

1

0

1

0

Return

Column

Address

N

N+1

N+2

N+3

N+m

N

Read modify write

End

(n) Reset

This instruction reset the LSI to the following status, however it doesn’t change the contents of the

DDRAM. Please be careful that it can’t be substituted for the reset operation by using of the RESB

terminal.

Reset status by “reset” instruction:

1: Read modify write off

2: Initial display line address

3: Column address

: (00)_H

4: Page address

: (0) page

5: Common direction register : Normal mode (D₃=”0”)

6: V₅level is adjusted by external bleeder resistance (D₂, D₁, D₀=”1, 0, 0”)

7: EVR register

: (D₅, D₄, D₃, D₂, D₁, D₀=”1, 0, 0, 0, 0, 0”)

A0

0

RDB WRB

D₇

1

D₆

1

D₅

1

D₄

0

D₃

0

D₂

0

D₁

1

D₀

0

1

0

(o) Common driver direction select

This instruction selects common driver direction.

Please refer to (1-7) common driver direction for more detail

.

A0

0

RDB WRB

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

*

D₁

*

D₀

*

1

0

(*: Don’t Care)

D₃0: Normal (C₀→ C₃₇)

1: Inverse (C₃₇→ C₀)

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NJU6674

(p) Power control set

This instruction controls the status of internal power circuits. Please refer to the (1-9) LCD Driving

Circuits (g) internal power circuits for more detail.

A0

RDB WRB

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

0

1

0

1

0

1

D₂

D₁

D₀

D₂0: Voltage converter off

1: Voltage converter on

D₁0: Voltage regulator off

1: Voltage regulator on

D₀0: Voltage followers off

1: Voltage followers on

Note) The internal power supply must be Off when external power supply using.

* The wait time depends on the C₄to C₈, C_OUTcapacitors, and V_DDand V₅Voltage.

Therefore it requires the actual evaluation using the LCD module to get the correct time.

ꢁ LCD Driving power supply ON/OFF sequences.

The sequences below are required when the power supply turns ON/OFF. For the power supply turning on

operation after the power-save mode(p), refer the “power save release” mentioned after.

Turn ON seaquence

Turn OFF seaquence

E.V.R Register set

Display OFF

Entire Display ON

Internal resister

ratio set

Power control OFF

or

Power control ON

or

Ext. Power Supply OFF

Ext. Power Supply ON

(wait time *1)

Display OFF

(wait time *1)

Display ON

NJU6674 Power OFF

( 1) The Internal Power Supply rise time is depending on the condition of the Supply Voltage, V_LCD=V_DD-V₅,

External Capacitor of Booster, and External Capacitor connected to V₁to V₅. To know the rise time

correctly, test by using the actual LCD module. refer to (3-5) “LCD Driving Voltage Generation Circuits”.

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NJU6674

(q) Internal resistor ratio set

The “Internal resistor ratio set” instruction is used to determine the internal resistor ratio for the

voltage regulator.

A0

0

RDB WRB

D₇

0

D₆

0

D₅

1

D₄

0

D₃

0

D₂

A₂

D₁

A₁

D₀

A₀

1

0

D₂

0

1

D₁

0

1

0

1

D₀

0

1

0

1

0

1

0

1

Internal resistor ratio(1+Rb/Ra)

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.4

Minimum

:

Maximum

(r),(s) EVR set

(r) EVR mode set

This instruction sets the LSI into the EVR mode, and it is always used by the combination with

“EVR register set”.

The LSI can’t accept any instructions except the “EVR register set” during the EVR set mode. This

mode will be released after the “EVR register set” instruction.

A0

0

RDB WRB

D₇

1

D₆

0

D₅

0

D₄

0

D₃

0

D₂

0

D₁

0

D₀

1

0

(s) EVR register set

This instruction sets 6-bit data into the EVR register to determine the output voltage “V₅” of the

internal voltage regulator.

A0

0

RDB WRB

D₇

*

D₆

*

D₅

D₄

D₃

D₂

D₁

D₀

1

0

(*: Don’t Care)

D₅

0

:

D₄

0

:

D₃

0

:

D₂

D₁

D₀

V₅

Minimum

0

:

0

:

0

1

:

1

Maximum

When EVR doesn’t use, set the EVR register to D₅, D₄, D₃, D₂, D₁, D₀= ”1, 0, 0, 0, 0, 0”.

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NJU6674

(t) Power Save(complex command)

When Entire Display ON at the Display OFF states(inverse order also same), the internal cirsuits goes

to the Power Save Mode and the operating curent is dramatically reduced, almost same as the standby

current. The internal states in the Power Save Mode is shown as follows;

1: The Oscillation Circuits and the Internal Power Supply Circuits stop the operation.

2: LCD driving is stopped. Segment and Common drives output V_DDlevel Voltage.

3: The display data and the internal operating condition are remained and kept as just before enter the

Power Save Mode.

4: All the LCD driving bias voltage(V₁to V₅) is fixed to the V_DDlevel.

The power save and its release perform according to the following sequences.

Power Save Sequence *1

Power Save Releace Sequence *2

Display OFF

Entire Display OFF

(Wait Time) *3

Entire Display ON

*4

Display ON

*1: In the Power save sequence, the Power Save Mode starts after the Entire Display ON command is

executed.

*2: In the Power save Release sequence, Power Save Mode releases just after the Entire Display OFF

instruction. The Display ON instruction is allowed to execute at any time after the Entire Display OFF

instruction is completed.

*3: The Internal Power Supply rise time depending on the condition of the Supply Voltage, V_LCD=V_DD-V₅,

External Capactor of Booster, and External Capacitor connected to V₁to V₅. To Know the rise time

correctly, test by using the actual LCDmodule.

*4: LCD Driving waveform is output after the exection of the Display ON instruction execution.

*5: In case of the external power supply operation, the external power supply should be turned off before

the Power Save Mode and connected to the V_DDfor fixing the voltage. In this time, V_OUTterminal also

shold be made condition like as connection to V_SS.

(u) NOP

This instruction is Non Operation Instruction.

(v) Reserve, (w) Test

This instruction is used only for manufacturer’s tests. (Don’t Inhibited command)

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NJU6674

(3) Internal Power Supply

(3-1) Voltage converter

The voltage converter generates maximum 4x boosted negative-voltage from the voltage between V_DD

and V_SS2. The boosted voltage is output from the V_OUTterminal.

The internal oscillator is required to be operating when using this converter, because the divided signal

provided from the oscillator is used for the internal timing of this circuit.

The boosted voltage between V_DDand V_OUTmust not exceed 10.0V.

The voltage converter requires external capacitors for boosting as shown in below.

ꢁ The boosted voltage and V_DD, V_SS2

V_DD=+3V

V_DD=+2.5V

V

_SS2=0V

_OUT=-3V

_OUT=-6V

_OUT=-7.5V

2x boost

3x boost

4x boost

ꢁ Example for connecting the capacitors

4x boost

3x boost

2x boost

V_SS2

C1-

V_SS2

C1-

C1+

C3-

C2+

C1-

C1⁺

+

C1+

+

C3-

C2+

C3-

C2+

C2-

V_OUT

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NJU6674

(3-2) Contrast Adjustment by the EVR function

The EVR selects the V_REGvoltage out of following 64 conditions by setting 6-bit data into the EVR

register. When the EVR function, V_EV(refer:Fig-3-a Voltage Adjust Circuit) is controlled, and the LCD

display contrast is adjusted. The EVR controls the voltage of V_EVbay instruction and change the voltage

of V₅.

A step with EVR is set like table shown below.

n

63

62

61

:

EVR register

(0,0,0,0,0,0)

V

_EV[V]

V_LCD

Minimum

00_H

01_H

02_H

:

(99/162)V_REG

(100/162)V_REG

(101/162)V_REG

(0,0,0,0,0,1)

(0,0,0,0,1,0)

:

2

1

0

3D_H

3E_H

3F_H

(1,1,1,1,0,1)

(1,1,1,1,1,0)

(1,1,1,1,1,1)

(160/162)V_REG

(161/162)V_REG

(162/162)V_REG

:

Maximum

*1: V_LCD=V_DD-V₅

*2 : In use of the EVR function, the voltage adjustment circuit must turn on by the power control instruction.

(3-3) Setting for internal resistor ratio

Either external or internal feedback resistors can be selected by setting the IRS terminal to “0” or”1”.

The Internal resistor ratio selects 8 conditions of the feedback resistor ratio(1+Rb/Ra).The feed back

resistor ratio(1+Rb/Ra) changing 3-bit data into the Internal resistor ratio register.

IRS

0

Ra, Rb

External resistors

Internal resistors

1

Internal resistor ratio register:

(Reference)

(1+Rb/Ra)

D₂

D₁

D₀

0

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.4

0

1

0

1

0

1

0

1

0

1

0

1

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NJU6674

(3-4) Voltage Adjust Circuit

The boosted voltage of V_OUToutputs V₅for V_LCDdriving through the voltage adjust circuit.

This circuit is composed of high the V_RS, 64-level EVR and internal feedback resistor.

(a) Using Internal Resistor Ratio function (IRS=”1”)

The LCD driving volatge V₅is determined in accordance with the setting for the EVR and the

internal resistor ratio Instruction.

The output voltage of V₅adjusted by changing with in the V₅>V_OUT

The output voltage is caluculated by the following formula.

.

V₅=(1+Rb/Ra)V_EV=(1+(Rb/Ra))(n/162)V_REG

(a-1)

V

n

_REG: External Constant voltage (V_RS)

: EVR value

(EVR)

V_DD

V_EV

V_REG

V_RS

V₅

V_DD

Ra

Rb

Fig-3-a Voltage Adjust Circuit

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NJU6674

(b) Using external Ra and Rb resistors

In case that the external feedback resistors (Ra, Rb) are used by setting the IRS terminal to “0”,

these external resistors are required to be placed between the V_DDand V_Rand between the V_Rand

V₅terminals. The LCD driving voltage V₅is determined in accordance with the setting for the EVR

and the external resistor ratio.

The output voltage of V₅adjusted by changing the Ra and Rb within the V₅>V_OUT

The output voltage is caluculated by the following formula.

.

V₅=(1+(Rb’/Ra’))V_EV=(1+(Rb’/Ra’))(1-(n/162))V_REG(b-1)

(EVR)

V_EV

V_DD

V_REG

V_RS

V_DD

V₅

Ra’

VR

Rb’

Fig-3-b Voltage Adjust Circuit

< Designe example for R1 and R2 / Reference >

Condition : Ta=25°C, n=31, V_REG=-2.1V, EVR=1F_{H ,}

V₅=(1+(Rb/Ra))(n/162)V_REG

-7=(1+(Rb’/Ra’))(1-(31/162) (-2.1)

(b-2)

Determined by the current flown between V_DD-V₅/ 5uA.

Ra’+Rb’=1.4MΩ

(b-3)

Ra and Rb caluculated by above conditions and the formula of (b-2, b-3) to mentioned below;

Rb’/Ra’=3.12

Ra=340kΩ

Rb=1060kΩ

The adjustable V₅range and step voltage table shown below.

V₅

Min.

Typ.

-7.0 (32 Step)

52

Max.

UNIT

[V]

Adjustable Range

-8.6 (63 Step)

-5.3(0 Step)

Step Voltage

[mV]

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NJU6674

(3-5) LCD Driving Voltage Generation Circuits

The LCD driving bias voltage of V₁,V₂,V₃,V₄are generated by dividing the V₅voltage with the internal

bleeder resistance and is supplied to the LCD driving circuits after the impedence conversion by the

voltage follower.

The external capacitors to V₁to V₅for Bias voltage stabilization may be removed in use of small size

LCD panel. The equivalent load of LCD panel may be changed depending on display patterns. Therefore,

it require display quality check on various display patterns actually without external capacitors. If the

display quality is not so good, external capacitors should connects as show in Fig. 4. (If no need external

capacitors as result of experiment, the application patterns (wiring) should be prepared for recovery.)

Using the internal Power Supply

Using the external Power Supply

IRS

V_SS2

V_SS1

C_OUT

IRS

V_SS1

V_SS2

V_OUT

C3-

V_OUT

C3-

C1

C3

+

C1+

C1-

C1+

C1-

C2+

C2-

V₅

C2

C2+

C2-

R3

R2

R1

V₅

VR

V_DDor V_SS1

VR

V_DD

V₁

V_DD

+

C4

V_DD

V₁

+

C5

C6

C7

C8

V₂

V₃

V₄

External

Voltage

Generator

V₂

V₃

V₄

+

V₅

V_RS

V₅

V_SS1

V_RS

Fig.4

Reference set up value V_LCD=V_DD-V₅=5..0 to 9.0V

.

1 Short wiring or sealed wiring to the VR terminal is required due to

the high impedance of VR terminal.

2 Following connection of V_OUTis required when external power

supply using.

When V_SS>V₅, V_OUT=V₅

When V_SS≤V₅, V_OUT=V_SS

3 Bias capacitors are selected depending on the LCD panel.

The evaluation in various display patterns should be

experimented in the application

C_OUT

C1, C2, C3

C4 to C7

R₁

1.0µF

0.1 to 0.47 µF

264kΩ

R₂

211kΩ

R₃

925kΩ

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NJU6674

(4) MPU Interface

(4-1) Interface type selection

NJU6674 interfaces with MPU by 8-bit bi-directional data bus (D₇to D₀) or serial (SI:D₇). The 8 bit

parallel or serial interface is determined by a condition of the P/S terminal connecting to “H” or “L” level as

shown in Table 5. In case of the serial interface, status and RAM data read out operation is impossible.

Table 5

P/S

H

L

I/F type

Parallel

Serial

CS₁B

CS₂

A0

RDB

-

WRB SEL68

D₇

SI

D₆

SCL

D₅- D₀

Hi-Z

-

“Hi-Z” mark: Hi-impedance "-" mark: Fix to "H"or "L"

(4-2) Parallel Interface

The NJU6674 interfaces the 68- or 80-type MPU directly if the parallel interface (P/S=”H” is selected.

The 68-type or 80-type MPU is selected by connecting the SEL68 terminal to “H” or “L” as shown in

table 6.

Table 6

CS₁B

SEL68

Type

CS₂

A0

RDB

E

WRB

R/WB

WRB

D₇- D₀

H

L

68-type MPU

80-type MPU

CS₁B

RDB

(4-3) Discrimination of Data Bus Signal

The NJU6674 discriminates the mean of signal on the data bus by the combination of A0, E, R/WB, and

(RDB, WRB) signals as shown in Table 7.

Table 7

common

68 type

R/WB

80 type

Function

A0

H

L

RDB

WRB

H

L

H

L

H

L

H

L

H

L

Read Display Data

Write Display Data

Status Read

L

H

Write into the Register(Instruction)

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NJU6674

(4-4) Serial Interface.(P/S="L")

The serial interface of the NJU6674 consists of the 8-bit shift register and 3-bit counter. In case the

chip is selected (CS₁B=”L”, CS₂=”H”), the input to D₇(SI) and D₆(SCL) becomes available, and in case that

the chip isn’t selected, the shift register and the counter are reset to the initial condition.

The data input from the terminal(SI) is MSB first like as the order of D₇, D₆,------ D₀, by a serial interface,

it is entered into with rise edge of serial clock(SCL). The data converted into parallel data of 8-bit with the

rise edge of 8th serial clock and processed.

It discriminates display data or instructions by A0 input terminal. A0 is read with rise edge of (8 X n)th of

serial clock (SCL), it is recognized display data by A0=“H” and instruction by A0=“L” A0 input is read in the

rise edge of (8 X n)th of serial clock (SCL) after chip select and distinguished.

However,in case of RESB=“H” to “L” or CS₁B=“L” to “H” and CS₂=“H” to “L” with trasfered data does not

fill 8 bit, attention is necessary because it will processed as there was command input. Always, input the

data of (8 X n) style.

The SCL signal must be careful of the termination reflection by the wiring length and the external noise

and confirmation by the actual machine is recommended by it.

CS₁B, CS₂

SI

SCL

A0

D₄

D₆

D₅

3

D₇

1

D₆

D₁

7

D₀

8

D₇

9

2

4

10

Fig.5

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NJU6674

(4-5) Access to the Display Data RAM and Internal Register.

The NJU6674 transfers data to the MPU through the bus holder with the internal data bus.

In case of reading out the display data contents in the DD RAM, the data which was read in the first

data read cycle (= the dummy read ) is memorized in the bus holder. Then the data is read out to the

system bus from the bus holder in the next data read cycle. Also, In case that the MPU writes into DD

RAM, the data is temporarily stored in the bus holder and is then written into DD RAM by the next data

write cycle.

Therefore, the limitation of the access to NJU6674 from MPU side is not access time (t_ACC, t_DS) of

Display Data RAM and the cycle time becomes dominant. With this, speed-up of the data transfer with the

MPU becomes possible. In case of cycle time isn’t met, the MPU inserts NOP operation only and

becomes an equivalent to an execution of wait operation on the satisfy condition in MPU.

When setting an address, the data of the specified address isn’t output immediately by the read

operation after setting an address, and the data of the specified address is output at the 2nd data read

operation. Therefore, the dummy read is always necessary once after the address set and the write cycle.

(See Fig. 6)

The example of Read Modify Write operation is mentioned in (3)Instruction -l)The sequence of Inverse

Display.

ꢁ Write Operation

MPU

WRB

DATA

N+2

N+3

N

N+1

Internal

timing

Bus holder

WRB

N

N+1

N+2

N+3

ꢁ Read Operation

MPU

WRB

RDB

n

N

n+1

Data read n+1

DATA

Address set N

Data read n

Dummy read

WRB

RDB

Internal

timing

N

N+1

N+2

Column address

Bus holder

N

n

n+1

n+2

Fig.6

(4-6) Chip Select

CS₁B, CS₂is Chip Select terminal. In case of CS₁B="L" and CS₂="H". the interface with MPU is

available. In case of CS₁B=”H” or CS₂=”L”, the D₀to D₇are high impedance and A0, RDB, WRB, SI and

SCL inputs are ignored. If the serial interface is selected when CS₁B=”H” or CS₂=”L” the shift register and

counter are reset. However, the reset is always operated in any conditions of CS₁B, CS₂.

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NJU6674

ꢀ

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

RATINGS

UNIT

V

-0.3 to +7.0

-0.3 to +3.6(Used Tripler)

-7.0 to +0.3

Supply Voltage(1)

V_DD

Supply Voltage(2)

V_SS2

V

-3.6 to +0.3(Used Tripler)

Supply Voltage(3)

Supply Voltage(4)

V₅, V_OUT

V_DD-11.0 to V_DD+0.3

V

V₁,V₂,V₃,V₄

V₅to V_DD+0.3

Supply Voltage(5)

Input Voltage

V_RS

V_IN

-7.0 to +0.3

-0.3 to V_DD+0.3

V

Operating

Temperature

Strage temperature

T_opr

T_stg

-40 to +85

°C

-55 to +125

V_DD

V_SS

V_DD

V₅

Note 1) All voltage values are specified as V_SS1=0V.

Note 2) The relation of V_DD>V₁>V₂>V₃>V₄>V₅>V_OUT; V_DD>V_SS1>V_OUTmust be maintained.

In case of inputting external LCD driving voltage , the LCD drive voltage should start supplying to

NJU6674 at the mean time of turning on V_DDpower supply or after turned on V_DD.

In use of the voltage boost circuit, the condition that the supply voltage: 11.0V> V_DD-V_OUTis necessary.

Note 3) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed.

Using LSI within electrical characteristics is strongly recommended for normal operation.

Use beyond the erectric characteristics conditions will cause malfunction and poor reliability.

Note 4) Decoupling capacitor should be connected between V_DDand V_SS1due to the stabilized operation for

the voltage converter.

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NJU6674

ꢀ DC Electrical Characteristics

(V_DD=2.4V to 3.3V, V_SS=0V, Ta=-20 to 75°C)

NOTE

SYMBOL

UNIT

PARAMETER

CONDITIONS

MIN

TYP

MAX

Operating voltage (1)

Operating voltage (2)

Recommend

V_DD

V_SS

2.4

3.3

V_DD-2.4

V_DD-5.0

V

1

V_DD-3.3

V_DD-10.0

V_DD-0.4xV₅

V₅

0.8 x V_DD

V_SS

V₅

Operating Available

V

voltage(3)

Available

V₁,V₂V_LCD=V_DD-V₅

V₃,V₄

V_IHC

V_ILC

V_OHCD₀to D₇

V_OLC

I_LI

V_DD

V_DD-0.6xV₅

V_DD

0.2 x V_DD

V_DD

A0, D₀to D₇, RDB, WRB, RESB,

CS₁B, CS₂, P/S, SEL68 Terminal

“H” level input voltage

“L” level input voltage

“H” level output voltage

“L” level output voltage

V

I_OH=-0.5mA

I_OL= 0.5mA

0.8 x V_DD

V_SS

Terminal

0.2 x V_DD

1.0

All input terminals

-1.0

-3.0

Input Leagage Current

µA

kΩ

I_LOD₀to D₇terminals, Hi-Z state

3.0

Ta=25°C, V_LCD=8.0V

Driver On-resistance

Stand-by Current

Input Terminal

Capacitance

Oscillation Frequency

Reset Time

R_ON

3.0

4.5

5.0

2

During Power Save Mode

Ta=25°C

I_DDQ

C_IN

0.01

10.0

12.5

3

4

µA

pF

f_OSC

t_R

t_RW

10.2

1.0

10.0

14.8

kHz

µs

V_DD= 3.0V Ta =25°C

5

6

RESB terminal

Reset “L” level pulse Width

V_DD13-times boost

V_DD24-times boost

V_RS

2.4

V_DD-5.0

-10.0

3.3

2.5

V_DD-2.4

-9.5

V

Input voltage

7

V

Output voltage

On-resistance

V_OUT14-times boost, V_DD=2.5V

3-times boost,

V_DD=3.0V, C_OUT=1.0µF

R_TRI

1600

2600

Ω

Adjustment range LCD

driving voltage

Voltage Follower

Voltage boost operation off

V_OUT2

V_DD-10.0V

V_DD-5.0V

V

8

9

V₅

Voltage adjustment circuit “OFF” V_DD-10.0V

V_DD=3.0V, V_RS=V_DD-2.4V,

EVR=00_H,V_OUT=V_DD-10.0V

Int. resistor ratio

INTR

3.0

%

V₅=No load ;Ta =25°C

Power save mode

I_DDQ1

I_OUT1

0.01

51

5

85

µA

V_DD=3.0V, V_LCD=5V, No access

Com/Seg terminals non connect

Display Checkerd pattern

Operating Current

10

I_OUT2

12

20

µA

Note 1) Although the NJU6674 can operate in wide range of the operating voltage, it shall not be guaranteed in

a sudden voltage fluctuation during the access with MPU.

Note 2) R_ONis the resistance values in supplying 0.1V voltage-difference beteen power supply terminals

(V₁,V₂,V₃,V₄) and each output terminals (common/ segment). This is specified within the range of

Operating Voltage(2).

Note 3) Apply no access from MPU.

Note 4) Apply A0, D₀to D₇, RDB, WRB, CS₁B, CS₂, RESB, P/S, CL terminals.

Note 5) t_R( Reset Time ) refers to the reset completion time of the internal circuits from the rise edge of the

RESB signal.

Note 6) Apply minimum pulse width of the RESB signal. To reset, the ”L” pulse over t_RWshall be input.

Note 7) Apply to the V_DDwhen using 4-times boost.

Note 8) The voltage adjustment circuit controls V₅within the range of the voltage follower operating voltage.

Note 9) INTR : The calculation of (V_LCD(Ideal)*¹-(V_LCD(Real))/V_LCD(Ideal)) x100%

*¹V_LCD(Ideal)=Nx(1-63/162)x2.4 (N:Selected by the “Internal resistor ratio” )

Ver.2003-04-08

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NJU6674

Note10) Each operating current shall be defined as being measured in the following condition.

Power Control

Operating Condition

Voltage

External Voltage

Supply

(Input terminal)

Symbol

D₂

D₁

D₀

Voltage

converter

Voltage

Follower

regulator

I_DD1

I_DD2

1

0

1

0

1

0

Validity

Use(V_SS2)

Invalidity

Use(V_OUT, V₁to V₅)

V_DD

V_DDor V_SS

V_DD-3V

:I_DD1

1MΩ

500kΩ

1.6MΩ

VR

V₅

IR

CLS CL VR

V_DD

NJU6674

A

V_SS1

C1+ C1- C3- C₂+ C2-

V_OUT

V_SS2

3V

+

1.0µF

+

1.0µF

10kΩ

:I_DD2

V_DD

10kΩ

V_DD

VR

V_SS1V_SS2

V₅

V₄

V₂

V₃

V₁

CLS

V_OUT

CL

V_DD

NJU6674

C1- C2+

A

C1+

C3-

C2-

3V

-5V

Fig.7 MEASURMENT BLOCK DIAGRAM

Ver.2003-04-08

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NJU6674

ꢀ BUS TIMING CHARACTERISTICS

Read and Write characteristics (80 type MPU)

•

t_CYC8

A0, CS₁B, CS₂

WRB, RDB

t_r

t_f

t_AW8

t_AH8

t_CCL

t_CCH

t_DH8

t_DS8

D₀to D₇

(WRITE)

t_ACC8

t_OH8

D₀to D₇

(READ)

(V_DD=2.7V to 3.3V, Ta=-20 to 75°C)

Parameter

Address hold time

Terminal

t_AH8

Symbol

Condition

Min.

Max.

Unit

TYP

0

A0, CS₁B,

CS₂

0

Address set up time

System cycle time

t_AW8

t_CYC8

t_CCL(W)

t_CCL(R)

t_CCH

300

60

120

60

40

25

WRB,

RDB

Control “L” pulse width (Write)

Control “L” pulse width (Read)

Control “H” pulse width

Data set up time

t_DS8

t_DH8

ns

D₀to D₇

Data set up time

RD access time

t_ACC8

t_OH8

140

100

CL=100pF

10

Output disable time

CS₁B, CS₂,

WRB, RDB

Input signal rising, falling edge

t_r, t_f

15

A0, D₀to D₇

•

*:All timing based on 20% and 80% of V_DDvoltage level.

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NJU6674

Read and Write characteristics (68 type MPU)

t_CYC6

E

t_r

t_f

t_EWL

t_EWH

R/WB

t_AW6

t_AH6

A0, CS₁B, CS₂

t_DH6

t_DS6

D₀~D₇

(WRITE)

t_ACC6

t_OH6

D₀~D₇

(

READ)

(V_DD=2.7V to 3.3V, Ta=-20 to 75°C)

Parameter

Symbol

Terminal

Condition

Unit

MIN

TYP

MAX

Address hold time

t_AH6

t_AW6

t_CYC6

0

A0, CS₁B

CS₂, R/WB

Address set up time

System cycle time

0

E

300

120

60

WRITE

Enable “H” pulse

width (Read)

t_EWH

t_EWL

READ

WRITE

READ

60

Enable “L” pulse

width (Read)

ns

E

60

Data set up time

Data hold time

t_DS6

t_DH6

t_ACC6

t_OH6

40

25

D₀to D₇

RD access time

Output disable time

140

100

CL=100pF

10

E, R/WB,

A0, D₀to D₇

Input signal rising, falling edge

t_r, t_f

15

*:All timing based on 20% and 80% of V_DDvoltage level.

*:t_CYC6shows the cycle of theE signal in active CS₁B and CS₂.

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NJU6674

Write characteristics (Serial interface)

t_CSH

t_CSS

CS₁B, CS₂

t_SAS

t_SAH

A0

t_SCYC

t_SLW

t_SHW

SCL

t_r

t_f

t_SDS

t_SDH

SI

(V_DD=2.7V to 3.3V, Ta=-20 to 75°C)

Unit

Parameter

Serial clock cycle

Symbol

t_SCYC

Terminal

Condition

MIN

TYP

MAX

250

SCL

SCL “H” pulse width

SCL “L” pulse width

Address set up time

Address hold time

Data set up time

t_SHW

t_SLW

t_SAS

t_SAH

t_SDS

t_SDH

t_CSS

t_CSH

100

150

100

150

A0

SI

ns

Data hold time

CS-SCL time

CS₁B, CS₂

SCL, SI, A0

Input signal rising, falling edge

t_f, t_r

15

*:All timing based on 20% and 80% of V_DDvoltage level.

Ver.2003-04-08

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NJU6674

ꢀ LCD DRIVING WAVEFORM

37 38

0

1

2

3

4

0

1

2

3

4

5

37 38

V_DD

V_SS

FR

V_DD

V₁

V₂

V₃

V₄

V₅

C₀

C₁

C₂

C₃

V_DD

V₁

V₂

V₃

V₄

V₅

C₄

C₅

C₁

C₆

C₇

V_DD

V₁

V₂

V₃

V₄

V₅

C₈

C₉

C₂

C₁₀

C₁₁

C₁₂

C₁₃

V_DD

V₁

V₂

V₃

V₄

V₅

C₁₄

C₁₅

S₀

V_DD

V₁

V₂

V₃

V₄

V₅

S₁

V₅

V₄

V₃

V₂

V₁

V_DD

C₀~S₀

-V₁

-V₂

-V₃

-V₄

-V₅

V₅

V₄

V₃

V₂

V₁

C₀~S₁

V_DD

-V₁

-V₂

-V₃

-V₄

-V₅

Ver.2003-04-08

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NJU6674

ꢀ APPLICATION CIRCUIT

•

(1) Microprocessor Interface Example

The NJU6674 interfaces to 80 type or 68 type MPU directly.

And the serial interface also communicate with MPU.

* : C86 terminal must be fixed V_DDor V_SS.

ꢁ 80 Type MPU

V_CC

V_DD

A0

A1~A7

IORQ

SEL68

CS₁B

CS₂

Decoder

CPU

NJU6674

D₀~D₇

V_DD

RD

RDB

WR

RES

WRB

RESB

P/S

GND

V_SS

RESET

Decoder

RESET

ꢁ 68 Type MPU

V_DD

V_CC

V_DD

A0

A1~A15

VMA

SEL68

CS₁B

CS₂

CPU

NJU6674

D₀~D₇

V_DD

E

R/W

RES

E

R/WB

RESB

P/S

GND

V_SS

ꢁ Serial Interface

V_DD

V_CC

A0

SEL68

CS₁B

CS₂

A1~A7

Decoder

CPU

NJU6674

D₇(SI)

D₆(SCL)

Port 1

Port 2

P/S

RES

RESB

GND

V_SS

RESET

Ver.2003-04-08

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NJU6674

MEMO

[CAUTION]

The specifications on this databook are only

given for information , without any guarantee

as regards either mistakes or omissions. The

application circuits in this databook are

described only to show representative usages

of the product and not intended for the

guarantee or permission of any right including

the industrial rights.

Ver.2003-04-08

- 42 -


型号：	NJU6674CJ
厂家：	NEW JAPAN RADIO
描述：	Liquid Crystal Driver, 171-Segment, CMOS, 10.38 X 2.51MM, DIE-286 驱动接口集成电路
文件：	总42页 (文件大小：309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NJU6674CJ [NJRC]

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