NJU6676CL [NJRC]

Liquid Crystal Driver, 197-Segment, CMOS, 8.72 X 2.37 MM, DIE-276;


型号：	NJU6676CL
厂家：	NEW JAPAN RADIO
描述：	Liquid Crystal Driver, 197-Segment, CMOS, 8.72 X 2.37 MM, DIE-276 驱动器控制器 CD
文件：	总46页 (文件大小：738K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NJU6676

PRELIMINARY

64-Common X 132-Segment plus 1-Icon

Bit Map Type LCD Controller and Driver

■ GENERAL DESCRIPTION

■ PACKAGE

The NJU6676 is a bit map LCD driver to display

graphics or characters. It contains 8,580 bits display data

RAM, microprocessor interface circuits, instruction

decoder, 132-segment drivers, 64-common drivers and 1-

icon drivers.

The bit image display data is transferred to the display

data RAM by serial or 8-bit parallel interface.

65 x 132 dots graphics or 8-character 4-line by 16 x 16

dots character with icon are displayed by NJU6676 itself.

The wide operating voltage from 2.2 to 5.5V and low

operating current are useful for small size battery

operating items.

NJU6676CH

The build-in Electrical Variable Resistance is very

precision, furtheremore the rectangle outlook is very

applicable to COG or Slim TCP.

■ FEATURES

■ Direct Correspondence between Display Data RAM and LCD Pixel

■ Display Data RAM - 8,580 bits

■ 197 LCD Drivers - 65-common and 132-segment

■ Direct Microprocessor Interface for both of 68 and 80 type MPU

■ Serial Interface

■ Programmable Bias selection ; 1/7,1/9 bias

■ Useful Instruction Set

Display Data Read/Write, Display ON/OFF Cont, Static indicator, Display Start Line Set, Bias Select,

Inverse Display, Common Driver order Assignment, Power control set, Page Address Set,

Column Address Set,Status Read, All On/Off, ADC Select, Read Modify Write, Power Saving.

■ Power Supply Circuits for LCD Incorporated

Voltage Booster Circuits (4-time Maximum), Regulator, Voltage Follower x 4

■ Precision Electrical Variable Resistance (64-step)

■ Low Power Consumption 80uA(Typ.).

■ Operating Voltage (All the voltages are based on VDD=0V.)

- Rogic Operating Voltage

: -2.2V -5.5V

- Voltage Booster Operating Voltage : -2.5V

- LCD Driving Voltage

: -6.0V -18.0V

■ Rectangle outlook for COG

■ Package Outline : Bump-chip / TCP

■ C-MOS Technology

Ver.1.31

NJU6676

PRELIMINARY

■ PAD LOCATION

DUMMY4

S131

S130

DUMMY1

OSC1

OSC2

FRS

DOF

VSS

CS1

CS2

VDD

RES

VSS

VDD

D6(SCL)

D7(SI)

VDD

VSS

VSS2

VOUT

C3-

C1+

C1-

C2-

C2+

VSS

VDD

Chip Center : X=0um, Y=0um

Chip Size

:X=8.72mm,Y=2.37mm

Chip Thickness : 675um ± 30um

Bump Size

: 45um x 83um

Pad Pitch : 60um(Min.)

Bump Height : 15um(Typ.)

Bump Material : Au

VDD

M/S

CLS

VSS

C86

P/S

VDD

VSS

VDD

DUMMY2

DUMMY3

NJU6676

PRELIMINARY

n PAD COORDINATES

Chip Size 8.72 x 2.37mm(Chip Center X=0um, Y=0um)

PAD No. Terminal

X(um)

-4139

-3347

-3287

-3129

-2909

-2688

-2468

-2311

-2251

-2191

-2131

-2071

-2011

-1951

-1891

-1831

-1771

-1613

-1393

-1172

-952

-731

-511

-291

-70

155

215

275

335

395

455

515

575

635

695

755

815

875

935

995

Y(um)

-1025

PAD No. Terminal

X(um)

1655

1715

1775

1835

1895

1955

2015

2075

2135

2195

2255

2315

2375

2435

2495

2555

2615

2675

2810

2870

2930

3065

3125

3185

3245

4139

4200

Y(um)

-1025

-935

-875

-815

-755

-695

-635

-575

-515

-455

-395

-335

-275

-215

-155

-95

-35

DUMMY1

OSC1

OSC2

FRS

100

VDD

DOF

VSS

CS1

CS2

VDD

RES

VSS

VDD

M/S

CLS

VSS

C86

P/S

VDD

VSS

VDD

DUMMY2

C31

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

D6(SCL)

D7(SI)

VDD

VSS

VSS2

VOUT

C3^-

C1⁺

1055

1115

1175

1235

1295

1355

1415

1475

1535

1595

C1⁺

C1^-

145

205

265

325

385

445

C2^-

C2⁺

VSS

NJU6676

PRELIMINARY

PAD No. Terminal

X(um)

4200

4119

3933

3873

3813

3753

3693

3633

3573

3513

3453

3393

3333

3273

3213

3153

3093

3033

2973

2913

2853

2793

2733

2673

2613

2553

2493

2433

2373

2313

2253

2193

2133

2073

2013

1953

1893

1833

1773

1713

1653

1593

Y(um)

505

565

625

685

745

805

865

925

PAD No. Terminal

X(um)

1533

1473

1413

1353

1293

1233

1173

1113

1053

993

933

873

813

753

693

633

573

513

453

393

333

273

213

153

Y(um)

1025

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

S40

S41

S42

S43

S44

S45

S46

S47

S48

S49

S50

S51

S52

S53

S54

S55

S56

S57

S58

S59

S60

S61

S62

S63

S64

S65

S66

S67

S68

S69

S70

S71

S72

S73

S74

S75

S76

S77

S78

S79

S80

S81

S82

S83

S84

S85

S86

S87

S88

S89

COMM

DUMMY3

985

1025

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

-27

-87

-147

-207

-267

-327

-387

-447

-507

-567

-627

-687

-747

-807

-867

-927

-987

-1047

-1107

-1167

-1227

-1287

-1347

-1407

NJU6676

PRELIMINARY

PAD No. Terminal

X(um)

-1467

-1527

-1587

-1647

-1707

-1767

-1827

-1887

-1947

-2007

-2067

-2127

-2187

-2247

-2307

-2367

-2427

-2487

-2547

-2607

-2667

-2727

-2787

-2847

-2907

-2967

-3027

-3087

-3147

-3207

-3267

-3327

-3387

-3447

-3507

-3567

-3627

-3687

-3747

-3807

-3867

-3927

-4119

-4200

Y(um)

1025

985

PAD No. Terminal

X(um)

-4200

Y(um)

565

505

445

385

325

265

205

145

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

S90

S91

S92

S93

S94

S95

S96

S97

S98

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

C39

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

C50

C51

C52

C53

C54

C55

C56

C57

C58

C59

C60

C61

C62

C63

COMM

S99

-35

-95

S100

S101

S102

S103

S104

S105

S106

S107

S108

S109

S110

S111

S112

S113

S114

S115

S116

S117

S118

S119

S120

S121

S122

S123

S124

S125

S126

S127

S128

S129

S130

S131

DUMMY4

C32

-155

-215

-275

-335

-395

-455

-515

-575

-635

-695

-755

-815

-875

-935

C33

C34

C35

C36

C37

C38

925

865

805

745

685

625

NJU6676

PRELIMINARY

■ BLOCK DIAGRAM

C0 - - - - C31

C63 - - - - C32

S0 - - - - - - - - - - - - - S131

COMM

Vss

VDD

Common

Drivers

Segment Drivers

Common

Drivers

V1 to V5

Internal

Power

Circuits

Voltage

Followers

Shift

Common

Timing

Voltage

Regulator

Display Data Latch

Vout

C1+/C1-

C2+/C2-

C3-

Voltage

Converter

Display Data RAM

Vss2

65 X 132 = 8,580-bit

Colum Address Recoder

Colum Address Counter

M/S

FRS

Display

Timing

CLS

DOF

Colum Address Register

Multiplexer

OSC1

OSC2

Ocsailator

Bus Holder

Instruction

Decoder

Status

Busy Flag

Internal Bus Line

Reset

MPU Interface

P/S

RES

CS1 CS2

C86

D5 to D0

(SI)

(SCL)

NJU6676

PRELIMINARY

■ TERMINAL DESCRIPTION

Power Supply Peripheral

No.

Symbol

Description

11,17

26 29

51,52

65 67

73,75

8,14,

VDD

VDD=+3V

VSS

VSS=0V

3031,

32,49

50,70,74

33 36

53,54

55,56

57,58

59,60

61,62

VSS2

Reference voltage for voltage booster

LCD Driving Voltage Supplying Terminal. When the internal voltage booster

is not used, supply each level of LCD driving voltage from outside with

following relation.

VDD≥V1≥V2≥V3≥V4≥V5

When the internal power supply is on, the internal circuits generate and

supply following LCD bias voltage from V1 to V4 terminal.

Bias

1/7 Bias V5+6/7VLCD V5+5/7VLCD V5+2/7VLCD V5+1/7VLCD

1/9 Bias V5+8/9VLCD V5+7/9VLCD V5+2/9VLCD V5+1/9VLCD

(VLCD=VDD-V5)

LCD Driving Power Supply Peripheral

No.

Symbol

Description

41,42

43,44

47,48

45,46

39,40

C1+

C1-

C2+

C2-

C3-

Boosted capacitor connecting terminals used for voltage booster.

37,38

63,64

Vout

Voltage booster output terminal. Connect the boosted capacitor between

this terminal and VSS2.

Voltage adjust terminal. V5 level is adjusted by external bleeder resistance

connecting between VDD and V5 terminal.

ＭＰＵ Interface Peripheral

No.

Symbol

Description

18 25

(24,25)

D0 D7

(SCL,

SI)

P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.

P/S="L" : D7=Serial data input terminal. D6=Serial data clock signal input

terminal. Data from SI is loaded at the rising edge of SCL and

latched as the parallel data at 8th rising edge of SCL.

Connect to the Address bus of MPU. The data on the D0 to D7 is

distinguished between Display data and Instruction by status of A0.

Distin

Display Data

Instruction

RES

Reset terminal. When the RES terminal goes to “L”, the initialization is

performed.

Reset operation is executing during “L” state of RES.

Chip select terminal. Data Input/Output are available during CS1=”L” and

CS2=”H”.

CS1

CS2

NJU6676

PRELIMINARY

No.

Symbol

Description

RD signal of 80 type MPU input terminal.

Active "L" During this signal is "L" , D0 to D7 terminals are output. <In

(E)

case of 68 Type MPU>

Enable signal of 68 type MPU input terminal.

Active "H"

(R/W)

<In case of 80 Type MPU> Connect to the 80 type MPU WR signal. Actie

"L". The data on the data bus input syncronizing the rise edge of this

signal. <In case of 68 Type MPU>

The read/write control signal of 68

type MPU input terminal.

R/W

State

Read

Write

C86

P/S

MPU interface type selection terminal.

C86

State

68 Type

80 Type

Serial or parallel interface selection terminal.

Serial

Clock

P/S Chip Select Data/Command Data Read/Write

“H”

“L”

CS1, CS2

D0 D7

RD,WR

SI(D7) Write Only SCL(D6)

RAM data and status read operation do not work in mode of

the serial interface. In case of the serial interface (P/S="L"),RD and WR

must be fixed "H" or "L", and D0 to D5 are high impedance.

OSC1

OSC2

System clock input terminal for Maker testing.(This terminal should be

Open) For external clock operation, the clock shoud be input to OSC1

terminal.

CLS

Terminal to select whether or enable or disable the display clock internal

oscillator circuit.

CLS=”H” : Internal oscillator circuit is enabld

CLS=”L” : Internal oscillator circuit is disabled (requires external input)

When CLS=”L”, input the display clock through the CL terminal.

This terminal selects the master/slave operation for the NJU6676. Master

operation outputs the timing signals that are required for the LCD display,

while slave operation inputs the timing signals required for the LCD,

synchronizing the LCD system.

M/S

M/S = ”H” : Master operation

M/S = ”L” : Slave operation

The following is true depending on the M/S and CLS status:

Power Supply

M/S CLS OSC.

FRS

DOF

Circuit

“H” Available Available

“L” Not Avail. Available

Output Output Output Output

Input Output Output Output

“H”

“L”

Not Avail. Not Avail.

Input

Input Output Input

*:Don’t Care

NJU6676

PRELIMINARY

No.

Symbol

Description

Display clock input/output terminal.

The following is true depending on the M/S and CLS status.

M/S

“H”

“L”

CLS

“H”

“L”

Output

Input

*:Don’t Care

LCD alternating current signal I/O terminal.

M/S = ”H” : Output

M/S = ”L” : Input

LCD Display blanking control terminal.

M/S = ”H” : Display “On” = “H”, Display “Off” = “L”

M/S = ”L” : External control. Refer to the following table.

DOF

Command

Display On”

Display Off”

Off

FRS

The output terminal for the static drive.

This terminal is used in conjunction with the FR terminal.

LCD Drivers

No.

Symbol

Description

108

C31 C0 LCD driving signal output terminals.

-Segment output terminals : S0 S131

-Common output terminal : C0 C63

Segment output terminal

The following output voltages are selected by the combination of FR and

data in the RAM.

111

242

S0 S131

RAM

Data

Output Voltage

Normal Reverse

VDD

244

275

C32 C63 Common output terminal

The following output voltages are selected by the combination of FR and

status of common.

Scan

Output Voltage

Data

VDD

109,

276

COMM

COM output terminals for the indicator. Both terminals output the same

signal.

Leave these open if they are not used.

(Terminals 1,76,110,243 are Dummy Pad)

NJU6676

PRELIMINARY

Functional description

(1) Block circuits description

(1-1) Busy Flag (BF)

During internal operation, the LSI is being busy and can’t accept any instructions except “status

read”. The BF data is output through D7 terminal by the “status read” instruction.

When the cycle time (tcyc) mentioned in the “AC characteristics” is satisfied, the BF check isn’t

required after each instruction, so that MPU processing performance can be improved.

(1-2) Initial display line register

The initial display line register assigns a DDRAM line address, which corresponds, to COM0 by

“initial display line set” instruction. It is used for not only normal display but also vertical display

scrolling and page switching without changing the contents of the DDRAM.

However, the 65^thaddress for icon display can’t be assigned for initial display line address.

(1-3) Line counter

The line counter provides a DDRAM line address. It initializes its contents at the switching of frame

timing signal (FR), and also counts-up in synchronization with common timing signal.

(1-4) Columnaddress counter

The column address counter is an 8-bit preset counter which provides a DDRAM column address,

and it is independent of below-mentioned page address register.

It will increment (+1) the column address whenever “display data read” or “display data write”

instructions are issued. However, the counter will be locked when no-existing address above (84)H

are addressed. The count-lock will be able to be released by the “column address set” instruction

again. The counter can invert the correspondence between the column address and segment driver

direction by means of “ADC set” instruction.

(1-5) Page address register

The page address register provides a DDRAM page address.

The last page address “8” should be used for icon display because the only D0 is valid.

(1-6) Display data RAM (DDRAM)

The DDRAM contains 8,580-bit, and stores display data which is 1-to-1 correspondents to LCD

panel pixels.

When normal display mode, the display data “1” turns on and “0” turns off LCD pixels. When inverse

display mode, “1” turns off and “0” turns on.

NJU6676

PRELIMINARY

Fig.1 Display data RAM (DDRAM) Map

Page Address

Data

Display Pattern

Line

Addres

Common

Driver

(00)H

COM0

COM1

COM2

D3,D2,D1,D0

(0,0,0,0)

Page 0

COM3

COM4

COM5

COM6

COM7

Initial

n n

COM8

COM9

D3,D2,D1,D0

(0,0,0,1)

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

Page 1

n n

D3,D2,D1,D0

(0,0,1,0)

Page 2

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COMI

D3,D2,D1,D0

(0,1,1,1)

Page 7

Page 8

(1,0,0,0)

00 01 02 03 04 05 06

83 82 81 80 7F 7E 7D

82 83

Column

Address

ADC

“0”

“1”

For example the Initial

display is 08H.

01 00

130 131

Segment Drivers

Note) COMI is independent of the “Initial display line set” instruction and always corresponds to the 65^thline.

NJU6676

PRELIMINARY

(1-7) Common direction register

The common direction register specifies common driver’s scanning direction.

Common drivers

PAD No.

Pin name

108

275

244

C0 ------------------------------ C31

COM0 ------------------ COM31

COM63 ----------------- COM32

C63 ---------------------------- C32

COM63 ----------------- COM32

COM0 ------------------ COM31

(1-8) Reset circuit

The reset circuit initializes the LSI to the following status by using of the reset signal into the RES

terminal.

Reset status using the RES terminal:

1. LCD Driver Set off

2. Display off

3. Normal Display (Non-inverse display)

4. ADC select : Normal mode (D0=0)

5. Power control register clear

6. Serial interface register clear

7. LCD bias select

: 1/9 bias

8. Read modify write off

9. Static indicator off

10. Initial display line address

: (00)H

11. Column address

12. Page address

: (00)H

: (0) page

13. Common direction register

14. EVR mode off and EVR register

15. Test mode off

: Normal mode (D3=0)

: (20)H

16. Entire display off

: Normal mode

The RES terminal should be connected to MPU’s reset terminal, and the reset operation should be

executed at the same timing of the MPU reset.

As described in the “DC characteristics”, it is necessary to input 10us or over “L” level signal into the

RES terminal in order to carry out the reset operation. The LSI will return to normal operation after

about 1us from the rising edge of the rest signal.

In case of using external power supply for LCD driving voltage, the RES terminal is required to be

being “L” level when the external power supply is turned-on.

The “Reset” instruction in Table.4 can’t be substituted for the reset operation by using of the RES

terminal. It executes above-mentioned only 8 to 16 items.

(1-9) LCD display circuits

a) Common and segment drivers

LCD drivers consist of 64-common drivers, 132-segment divers and 1-icon-common driver.

As shown in Fig.7, LCD driving waveforms are generated by the combination of display data,

common timing signal and internal FR timing signal.

NJU6676

PRELIMINARY

b) Display data latch circuit

The display data latch circuit temporally stores 132-bit display data transferred from the DDRAM in

the synchronization with the common timing signal, and then it transfers these stored data to the

segment drivers.

“Display on/off”, “inverse display on/off” and “entire display on/off” instructions control only the

contents of this latch circuit, they can’t change the contents of the DDRAM.

In addition, the LCD display isn’t affected by the DDRAM accuses during its displaying because the

data read-out timing from this latch circuit to the segment drivers is independent of accessing timing

to the DDRAM.

c) Line counter and latch signal or latch Circuits

The clock line counter and latch signal to the latch circuits are generated from the internal display

clock (CL). The line address of display data RAM is renewed synchronizing with display clock (CL).

132bits display data are latched in display latch circuits synchronizing with display clock, and then

output to the LCD driving circuits. The display data transfer to the LCD driving circuits is executed

independently with RAM access by the MPU.

d) Display timing generator

The display timing generates the timing signal for the display system bay combination of the master

clock CL and driving signal FR ( refer to Fig.2 ) The frame signal FR and LCD alternative signal

generate LCD driving waveform on the two frame alternative driving method.

e) Common timing generation

The common timing is generated by display clock CL (refer to Fig.2)

Fig.2 Display Timing

64 63 1

COM0

COM1

RAM data

SEG n

Fig.2 Waveform of Display Timing

NJU6676

PRELIMINARY

f) Oscillator

This is the low power consumption CR oscillator which provides the display clock and voltage

converter-timing clock.

e) Internal power circuits

The internal power circuits are composed of x4 boost voltage converter, output voltage regulator

including 64-step EVR and voltage followers.

The optimum values of the external passive components for the internal power circuits, such as

capacitors for V1 to V5 terminals and feed back resistors for VR terminal, depend on LCD panel size.

Therefore, it is necessary to evaluate the actual LCD module with these external components in

order to determine the optimum values.

Each portion of the internal power circuits is controlled by “power control set” instruction as shown in

Table.1. In addition, the combination of power supply circuits is described in Table.2.

Table.1) Power control set

Bits

Portions

Status

Voltage converter

Voltage regulator

Voltage followers

1 :On

0: Off

Table.2) Powersupply combinations

Status

D2 D1 D0

Voltage

converter regulator

Voltage

followers

External

voltage

Capacito

terminals

Using all internal power circuits

Using voltage regulator and

Voltage followers

Off

Vss2

Vout,

Vss2

Use

Open

Using voltage followers

Using only external power supply

Off

V5, Vss2

V1 to V5

Open

Note1) Capacitor input terminals: C1+, C1-, C2+, C2-, C3-

Note2) Do not use other combinations except examples in Table.2.

Note3) Connect decoupling capacitors on V1 to V5 terminals whenever using the voltage followers.

NJU6676

PRELIMINARY

(2) Instruction set

The D7 to D0 data is distinguished as display data or instruction data by the combination of A0, RD

and WR signals.

Table.3 Instruction table

Instruction

Instruction code

Description

D7 D6

D3 D2

Display On/Off

0 :Off

1 :On

Initial display line set

D3 D2

Specify DDRAM line

address for COM0

Page address set

D3 D2

DDRAM page address

Column address set

Upper 4-bit

DDRAM column address

of upper 4-bits

Column address set

Lower 4-bit

D3 D2

DDRAM column address

of lower 4-bits

Status read

D7 D6

Read internal status

Write DDARM data

Display data write

Display data read

ADC select

D3 D2

Read DDRAM data

Select segment direction

Inverse display On/Off

0 : Normal display

1 : Inverse display on

0 : Normal display

1 : Entire display on

10 Entire display On/Off

11 LCD bias select

0 : 1/9 bias

1 : 1/7 bias

12 Read modify write

13 End

Increment column address

Release read modify write

Internal reset

14 Reset

15 Common direction select

Select common direction

16 Power control set

17 Driver On/Off

Set the status of internal

power circuits

0 : Driver Off

1 : Driver On

18 EVR mode set

EVR register set

Set EVR mode

D3 D2

Set EVR register

19 Static indicator On/Off

0 : Off

1 : On

Static indicator register

set

Set static indicator register

20 Power save mode On/Off

Dual commands of display

Off & entire display On

21 NOP

22 Test

Don’t use

NJU6676

PRELIMINARY

(3) Instruction description

3-1) Display On/Off

This instruction selects display turn-on or turn-off regardless of the contents of the DDRAM.

Display On or Off

0 :Off

1 :On

3-2) Initial display line set

This instruction specifies the DDRAM line address which corresponds to the COM0 position.

By means of repeating this instruction, the initial display line address will be dynamically changed; it

means smoothdisplay scrolling will be enabled.

Line address for COM0

3-3) Page address set

In order to access to the DDRAM for writing or reading display data, both “page address set” and

“column address set” instructions are required before accessing.

Page address

NJU6676

PRELIMINARY

3-4) Column address set

As above-mentioned, in order to access to the DDRAM for writing or reading display data, it is

necessary to execute both “page address set” and “column address set” before accessing. The 8-bit

column address data will be valid when both upper 4-bit and lower 4-bit data are set into the column

address register.

Once the column address is set, it will automatically increment (+1) whenever the DDRAM will be

accessed, so that the DDRAM will be able to be continuously accessed without “column address set”

instruction.

The column address will stop increment and the page address will not be changed when the last

address (83)His addressed.

Upper 4-bit

Lower 4-bit

Column address

130

131

3-5) Status read

This instruction reads out the internal status regarding “busy flag”, “ADC select”, “display on/off” and

“reset”.

BUSY

ADC

On/Off

RESET

BUSY : When D7 is “1”, the LSI is being busy and can’t accept any instructions.

ADC

: It shows the correspondence between the column address and segment drivers.

When D6 is “0”, the column address (131-n) corresponds to segment driver n.

When D6 is “1”, the column address (n) corresponds to segment driver n.

Please be careful that read out data isopposite of “ADC select” instruction data.

On/Off : It shows display on or off status.

When D5 is “0”, the LSI is in display-on status.

When D5 is “1”, the LSI is in display-off status.

Please be careful that read out data isopposite of “ADC select” instruction data.

RESET : It shows reset status.

When D4 is “0”, the LSI is in normal operation.

When D4 is “1”, the LSI is during reset operation.

NJU6676

PRELIMINARY

3-6) Display data write

This instruction writes display data into the selected column address on the DDRAM.

The column address automatically increments (+1) whenever the display data is written by this

instruction, so that this instruction can be continuously issued without “column address set”

instruction.

Write Data

3-7) Display data read

This instruction reads out the display data stored in the selected column address on the DDRAM.

The column address automatically increments (+1) whenever the display data is read out by this

instruction, so that this instruction can be continuously issued without “column address set”

instruction.

After the ”column address set” instruction, a dummy read will be required, please refer to the (5-4).

In case of using serial interface mode, this instruction can’t be used.

Read Data

3-8) ADC select

This instruction selects segment driver direction.

The correspondence between the column address and segment driver direction is shown in Fig.1.

Segment driver direction

Normal

Inverse

3-9) Inverse display On/Off

This instruction inverses the status of turn-on or turn-off of entire LCD pixels. It doesn’t change the

contents of the DDRAM.

Display status

Normal

Inverse

3-10) Entire display On/Off

This instruction turns on entire LCD pixels regardless the contents of the DDRAM. It doesn’t change

the contents of DDRAM.

Entire display on/off

Normal

Entire display on

NJU6676

PRELIMINARY

3-11) LCD bias set

This instruction selects LCD bias value.

LCD bias

1/9

1/7

3-12) Read modify write

This instruction controls column address increment.

By using of this instruction, the column address can’t increment when read operation but it can

increment when write operation. This status will be continued until the below-mentioned “end”

instruction will be issued.

This instruction can reduce the load of MPU, during the display data in specific DDRAM area is

repeatedly changed for cursor blink or others.

The sequence of cursor blink display

Page address set

Set address

for cursor line

Column address set

Read modify write

Start

“read

modify

Dummy read

Data read

Inverse data in MPU

Data write

Dummy read

Data read

Data write

Repeat

End

“read

End

modify

Finish?

Yes

NJU6676

PRELIMINARY

3-13) End

The “end” instruction cancels the read modify write mode and makes the column address return to

the initial value just before “read modify write” is started.

Return

Column

Address

N+1

N+2

N+3

N+m

Read modify write

End

3-14) Reset

This instruction reset the LSI to the following status, however it doesn’t change the contents of the

DDRAM. Please be careful that it can’t be substituted for the reset operation by using of the RES

terminal.

Reset status by “reset” instruction:

1. Read modify write off

2. Static indicator off

3. Initial display line address

4. Column address

: (00)H

5. Page address

6. Common direction register

: (0) page

: Normal mode (D3=0)

7. EVR mode off and EVR register : (20)H

8. Test mode off

3-15) Common driver direction select

This instruction selects common driver direction.

Please refer to (1-7) common driver direction for more detail.

Common driver direction

Normal

Inverse

NJU6676

PRELIMINARY

3-16) Power control set

This instruction controls the status of internal power circuits. Please refer to the (4) internal power

supply circuits for more detail.

Status

Voltage converter off

Voltage converter on

Voltage regulator off

Voltage regulator on

Voltage followers off

Voltage followers on

Note) The internal power supply must be Off when external power supply using.

* The wait time depends on the C3 to C7, COUT capacitors, and VDD and VLCD Voltage.

Therefore it requires the actual evaluation using the LCD module to get the correct time.

B.D

3-17) LCD Driver On/Off

This instruction controls LCD driving waveform output through the COM/SEG terminals.

Driver

Off

The NJU6676 contains low power LCD driving voltage generator circuit reducing own operating

current. Therefore , it requires the following sequence procedures at power on for power source

stabilized operation.

NJU6676

PRELIMINARY

LCD Driving power supply On/Off sequences

The following sequences required when the power supply is turned On/Off.

When the power supply is turned on again after the turn off (by the power save instruction), the power

save release sequence(3-22) is required.

Turn ON sequence

Turn OFF sequence

Output Assign. Register Set

Display OFF

Static Indicater Set

EVR Register Set

Entire Display OFF

Internal Power Supply OFF

External Power Supply OFF

Internal Power Supply ON

External Power Supply ON

Wait Time

LCD Driver ON

LCD Drivier OFF

3-18) EVR mode set

This instruction sets the LSI into the EVR mode, and it is always used by the combination with “EVR

The LSI can’t accept any instructions except the “EVR register set” during the EVR set mode. This

mode will be released after the “EVR register set” instruction.

3-19) EVR register set

This instruction sets 6-bit data into the EVR register to determine the output voltage “V5” of the

internal voltage regulator.

Minimum

：

;

：

Maximum

3-20) Static indicator on/off

This instruction selects static indicator turn-on or turn-off, and it is always used by the combination

with the “ static indicator register set”.

Static indicator

Off

NJU6676

PRELIMINARY

3-21) Static indicator register set

This instruction sets 2-bit data into the static indicator register.

Status

Off

On (Blink at 1.0 s intervals)

On (Blink at 0.5s intervals)

On (Turn on at all time)

3-22) Power save mode On/Off

This instruction sets the LSI into the power save mode by the combination of “display off” and “whole

display on” instructions for reducing operating current as well as static operation’s.

The internal status and the contents of the DDRAM will be remained just before the “power save

mode on/off” instruction. In addition, the DDRAM can be accessed during the power save mode.

There are two power save modes, sleep mode and standby mode.

During sleep mode:

All LCD system stops as follows,

1. Oscillator and internal power circuits stop.

2. All common and segment drivers output VDD level.

During standby mode:

The LCD system except the static indicator stops as follows,

1. Oscillator and internal power circuits stop.

2. All common and segment drivers output VDD level.

3. The only static indicator is operating.

Fig.5 The sequence of power save mode

Static indicator off

Static indicatoron

Power save on (Dual instructions)

Sleep mode

Standby mode

Power save off

Entire display off

Static indicator on

Release Sleep mode

Release Standby mode

NJU6676

PRELIMINARY

(4) Internal power circuits

(a)Voltage converter

The voltage converter generates maximum 4x boosted negative-voltage from the voltage between

VDD and Vss2. The boosted voltage is output from the VOUT terminal.

The internal oscillator is required to be operating when using this converter, because the divided

signal provided from the oscillator is used for the internal timing of this circuit.

The boosted voltage between VDD and Vout must not exceed 18.0V.

The voltage converter requires external capacitors for boosting as shown in Fig.7.

Fig.7 The capacitors connection for the voltage regulator:

4x boost

3x boost

2x boost

Vss2

Vout

C3-

Vout

C3-

Vout

C3-

C1+

C1-

C2-

C1-

C2-

C1-

C2-

C2+

VDD

Vss2

Vout= 2x (VDD-Vss2)

Vout= 3x (VDD-Vss2)

Vout= 4x (VDD-Vss2)

NJU6676

PRELIMINARY

(b)Contrast control using the voltage regulator

The voltage regulator determines the LCD driving voltage “V5” according to the Rb/Ra ratio and

VREG voltage. The equations to calculate V5 are as follows:

Fig.5 Voltage regulator circuit

Voltage regulator

VDD

VREG

VLCD

Vout

VLCD = VDD – V5

= (1+Rb/Ra) x VREG

---[1]

VREG= (n/162) x (VDD-Vss2) ---[2]

VLCD

Ra, Rb

VREG

: LCD driving voltage

: Feed back resistors

: Contrast control voltage

: Parameter decided instruction

(c)Contrast control voltage VREG

As the equation [2] shows, the VREG value depends on the parameter “n”. The “n” is selected a

value within 99 to 162 by using of “EVR register set” instruction as described in Table.8.

Table.8 The relationship between EVR register and VLCD level

VREG

(99/162) x (VDD-Vss2)

(100/162) x (VDD-Vss2)

(101/162) x (VDD-Vss2)

Minimum

100

101

160

161

162

(160/162) x (VDD-Vss2)

(161/162) x (VDD-Vss2)

(162/162) x (VDD-Vss2)

Maximum

NJU6676

PRELIMINARY

- VLCD setting example

We recommend the total value of Ra and Rb is between 1MW and 5MW. When using Ra=1MW,

Rb=4MW and VDD=3V, the VLCD is calculated as follows:

The minimum VLCD:

VLCD =(1+Rb/Ra) X VREG

=(1+4/1) X [(99/162) X 3.0]

=9.15V

The maximum VLCD:

VLCD =(1+Rb/Ra) X VREG

=(1+4/1) X [(162/162) X 3.0]

=15.0V

NJU6676

PRELIMINARY

(d) LCD Driving Voltage Generation Circuits

The LCD driving bias voltage of V1,V2,V3,V4 are generated internally by dividing the V5 voltage

with the internal bleeder resistance. And it is supplied to the LCD driving circuits after the

impedance conversion with voltage follower circuit.

As shown in below, Five capacitors are required to connect to each LCD driving voltage terminal for

voltage stabilizing. And the value of capacitors C4, C5, C6, C7, and C8 are determined depending

on the actual LCD panel display evaluation.

Using the internal Power Supply

Using the external Power Supply

VSS

C1-

VSS2

C1-

C1+

C3-

Cout

C2+

C2-

＊2

VOUT

NJU6676

＊1

VDD

External

Voltage

Generator

Reference set up value

VLCD=VDD-V5=9.0 to 10.5V

*1 Short wiring or sealed wiring to the VR terminal is

required due to the high impedance of VR terminal.

*2 Following connection of VOUT is required when external

power supply using.

1.0ｕF

0.1 0.47ｕF

2MΩ

500KΩ

2.5MΩ

COUT

C1/C2/C3

C4 C8

When VSS > V5 --- VOUT=V5

When VSS < V5 --- VOUT=VSS

NJU6676

PRELIMINARY

(5) MPU interface

(5-1) Interface type selection

NJU6676 interfaces with MPU by 8-bit bidirectional data bus (D7 to D0) or serial (SI:D7). The 8 bit

parallel or serial interface is determined by a condition of the P/S terminal connecting to "H" or "L"

level as shown in Table 4. In case of the serial interface, status and RAM data read out operation is

impossible.

Table4

P/S

Type

CS1

C86

SI(D7) SCL(D6) D0~D5

Parallel

Serial

CS1

C86

SCL

D0~D5

Hi-z

“-“ : They should be fixed to “H” or “L”.

(5-2) Parallel Interface

The NJU6676 interfaces to 68 or 80 type MPU directly when the parallel interface (P/S="H") is

selected. 68 type MPU or 80 is determined by the condition of C86 terminal connecting to "H" or "L"

as shown in table 5.

Table 5

C86

Type

CS1

R/W

D0~D7

68 type MPU

80 type MPU

(5-3) Discrimination of Data Bus Signal

The NJU6676 discriminates the mean of signal on the data bus by the combination of A0, E, R/W,

and (RD,WR) signals as shown in Table 6.

Table 6

Common

68 type

80 type

Function

R/W

Read Display Data

Write Display Data

Status Read

Write into the Register(Instruction)

NJU6676

PRELIMINARY

(5-4) Serial Interface.(P/S="L")

Serial interface circuits consist of 8 bits shift register and 3 bits counter. SI and SCL input are

activated when the chip select terminal CS1 set to "L"and P/S terminal set to "L". The 8 bits shift

input from SI terminal is MSB first like as the order of D7,D6,- - - - D0, and the data are entered into

the shift register synchronizing with the rise edge of the serial clock SCL. The data in the shift

display data or instruction of the serial input data is executed by the condition of A0 at the 8th serial

clock rise edge. A0="H" is display data and A0="L" is instruction. When RES terminal becomes "L"

or CS1 terminal becomes "H" before 8th serial clock rise edge, NJU6676 recognizes them as a

instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit. The time chart

for the serial interface is shown in Fig. 5. To avoid the noise trouble, the short wiring is required for

the SCL input.

Note) The read out function, such as the status or RAM data read out, is not supported in this serial

interface

CS1

CS2

SCL

Fig.5

NJU6676

PRELIMINARY

5-5) Access to the Display Data RAM and Internal Register.

The NJU6676 is operating as one of pipeline processor by the bus-holder connecting to the internal data bus to

adjust the operation frequency between MPU and the Display Data RAM or Internal Register.

For example, when the MPU reads out the data from the Display Data RAM, the read out data in the data read

cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the

next data read cycle. When the MPU writes the data into the Display Data RAM, the data is held in the bus-

holder, then it is written into the Display Data RAM by the next data write cycle.

Therefore high speed data transmission between MPU and NJU6676 is available because of it is not limited by

the tACC and tDS as display data RAM access time and is limited by the system cycle time (R) or (W).

If the cycle time is not be kept in the MPU operation, NOP should be inserted to the system instead of the

waiting operation.

The read out operation does not read out the data in the pointed address just after the address set operation.

And second read out operation can read out the data correctly from the pointed address.

Therefore, one dummy read operation is required after address setting or write cycle as shown in FIG. 6..

Write timing

MPU signal

Data

Bus holder

N+1

N+2

N+3

N+1

N+2

N+3

Internal signal

Read timing

MPU signal

Data

n +1

Address

set

Dummy

read

Data read

Internal signal

Column

address

N+1

N+2

Bus holder

n+1

Fig.6

NJU6676

PRELIMINARY

5-5) Chip select

CS1, CS2 are Chip Select terminals. In case of CS1="L" and CS2=”H”, the interface with MPU is

available. In case of CS1=”H” or CS2=”L”, the D0 to D7 are high impedance and A0, RD, WR,

D7(SI) and D6(SCL) inputs are ignored. If the serial interface is selected when CS1=”H” or CS2= ”L”,

the shift register and the counter are reset. However, the reset is always operated in any conditions

of CS1 and CS2.

NJU6676

PRELIMINARY

n ABSOLUTE MAXIMUMN RATINGS

Ta=25°C

Parameter

Symbol

Ratings

Unit

Supply voltage

VDD

Vss2

-0.3 to +7.0

-7.0 to+0.3

-6.0 to +0.3 (When using 3x voltage converter)

-4.5 to +0.3 (When using 4x voltage converter)

Supply voltage

Vout

-18.0 to +0.3

V1,V2

V3,V4

V5 to +0.3

Input voltage

Operating temperature

Storage temperature

Vin

Topr

Tstg

-0.3 to VDD+0.3

-30 to +80

°C

-55 to +100 (TCP)

-55 to +125 (Chip)

Note1) All voltages are relative to the Vss = 0V reference.

The relationship among the supply voltages should be maintained the following condition.

VDD>V0>V1>V2>V3>V4>V5;VDD>Vss>Vout

Note2) When using the external power supply for LCD driving, the external power should be turn on at

the same timing of VDD or after VDD.

Note3) The LSI should be operated inside of the absolute maximum ratings in order to prevent

excessive stress. Otherwise, the stresses beyond the absolute maximum ratings may

cause permanent damage to the LSI.

Note4) The decoupling capacitor between VDD terminal and Vss terminal is required in order to

stabilize the LSI operation.

NJU6676

PRELIMINARY

DC Electrical Characteristics

VDD=2.7V to 3.3V, Vss=0V, Ta=-30 to +80°C

Parameter

Power supply(1)

Symbol

VDD

Conditions

Recommend

Possible

Min.

Typ.

Max.

Unit

Note

2.7

3.3

2.2

5.5

Power supply(2)

Power supply(3)

Vss1

VDD-6.0

VDD-18

0.4xV5

0.8VDD

Vss

0.8VDD

Vss

-1.0

VDD-2.5

VDD-6

VDD

0.6xV5

VDD

0.2VDD

VDD

0.2VDD

1.0

VLCD=VDD-V5

V1,V2

V3,V4

VIHC1

VILC1

VOHC1

VOLC1

ILI

“H” level input voltage

“L” level input voltage

“H” level output voltage

“L” level output voltage

Input leakage current

Output leakage current

LCD on resistance

IOH=-0.5mA

IO=0.5mA

kΩ

ILO

RON1

-3.0

3.0

3.5

VLCD=14.0V,

Ta=25°C

2.0

RON2

CIN

FOSC

3.2

5.4

VLCD=8.0V, Ta=25°C

Ta=25°C

kΩ

KHz

Input pin capacitance

Oscillation frequency

Reset time

1.0

Using RES terminal

Reset pulse width

TRW

Internal power supply

Parameter

Input voltage

Symbol

VDD1

Conditions

VDD-Vss

Using 3x voltage converter

VDD-Vss

Min.

-6.0

Typ.

Max.

-2.5

Unit

Note

VDD2

Vout

RSTEP

Vout

-4.5

-18.0

-2.5

Using x4 voltage converter

Voltage converter

Output voltage

Voltage converter

Output on resustance

Volateg regulator

Operating voltage

Voltage follower

Operating voltagae

Operating current

C1 to C3, Cout=1.0uF

Using x4 booster

Voltage converter off

2500

3500

Ω

VDD

-18.0V

VDD

-18.0V

VDD

-6.0V

VDD

-6.0V

5.0

140

Voltage regulator off

IDDQ1

IDDQ2

IDD1

IDD2

IDD3

When sleep mode

When standby mode

VDD=3V, V5=-11V

Checker flag display

Without MPU access

All COM/SEG open

VDD=3V, Ta=25°C

0.01

3.0

IDD4

VREG

Reference Voltage

Note5) This parameter can’t be guaranteed for spike voltage during MPU access.

Note6) Apply to the resistance between each driver (COM, SEG) and power supply terminal (V1,V2,V3,V4)

when 0.1V voltage difference is supplied between these terminals.

Note7,8)Apply to the condition when internal power circuits aren’t used.

Note7) Apply to the condition when MPU doesn’t access to the LSI.

Note8) Apply to the condition when writing checker flag pattern to the DDRAM at the timing of tcyc.

Note9) Apply to A0, D7 to D0, RD, WR, CS, RES, C86 and P/S terminals.

Note10) Specified the time between the rising edge of the RES signal and completion of reset operation.

NJU6676

PRELIMINARY

Note11) specified the minimum pulse width of RES signal.

Note12) Apply to theVDD when using quadrupler.

Note13) LCD driving voltage can be adjusted within the voltage follower operating range.

Note14) Each value are specified in the following conditions:

Power Control

D2 D1 D0

Operating Condition

External

Voltage Supply

(Input Terminal)

Symbol

Voltage

converter

regulator

followers

Iout1

Iout2

Iout3

Iout4

Off

Use(VSS2)

Use(VOUT,VSS2)

Use(V5,VSS2)

Use(V1~V5)

Off

IDD 1,2,3,4 measurement circuits:

IDD1

VDD

Vss

C2-C1-

C1+

C3-

Vout

IDD2

VDD

C2+

C2- C1-

C1+

C3-

Vout

Vss

IDD3

VDD

Vss

C2+

C2- C1-

C1+

C3-

Vout

NJU6676

PRELIMINARY

IDD4

V1 V2 V3 V4

VR V1 V2 V3 V4 V5

VDD

Vss

C2+

C2- C1-

C1+

C3-

Vout

NJU6676

PRELIMINARY

BUS TIMING CHARACTERISTICS

Read and Write characteristics (80 type MPU)

tcyc8

A0,CS1,CS2

WR,RD

tAW8

tAH8

tCCL

tCCH

tDS8

tDH8

D7 to D0

Write

tACC8

tOH8

D7 to D0

Read

(Vss=0V, VDD=4.5 to 5.5V, Ta=-30 to 80°C)

Parameter

Terminal

Symbol

Condition

Min.

Max.

Unit

Address hold time

Address set up time

System cycle time

Control “H” pulse width (Read)

Control “H” pulse width (Write)

Control “L” pulse width (Read)

Control “L” pulse width (Write)

Data set up time

A0,CS1,

CS2

tAH8

tAW8

tcyc8

tCCHR

tCCHW

tCCLR

tCCLW

tDS8

166

WR,RD

Data hold time

RD access time

Output disable time

tDH8

tACC8

tOH8

D7 ~ D0

CL=100pF

CS1,CS2

RW,RD,A0,

D7 ~ D0

Input signal rising, falling edge

tr,tf

NJU6676

PRELIMINARY

(Vss=0V, VDD=2.7 to 4.5V, Ta=-30 to 80°C)

Parameter

Address hold time

Address set up time

Terminal

Symbol

Condition

Min.

Max.

Unit

A0,CS1,

CS2

tAH8

tAW8

tcyc8

tCCHR

tCCHW

tCCLR

tCCLW

tDS8

System cycle time

300

120

Control “H” pulse width (Read)

Control “H” pulse width (Write)

Control “L” pulse width (Read)

Control “L” pulse width (Write)

Data set up time

Data hold time

RD access time

Output disable time

WR,RD

tDH8

tACC8

tOH8

D7 ~ D0

140

100

CL=100pF

CS1,CS2

RW,RD,A0,

D7 ~ D0

Input signal rising, falling edge

tr,tf

(Vss=0V, VDD=2.2 to 2.7V, Ta=-30 to 80°C)

Parameter

Terminal

Symbol

Condition

Min.

Max.

Unit

Address hold time

Address set up time

System cycle time

Control “H” pulse width (Read)

Control “H” pulse width (Write)

Control “L” pulse width (Read)

Control “L” pulse width (Write)

Data set up time

A0,CS1,

CS2

tAH8

tAW8

tcyc8

tCCHR

tCCHW

tCCLR

tCCLW

tDS8

1000

120

240

120

WR,RD

Data hold time

RD access time

Output disable time

tDH8

tACC8

tOH8

D7 ~ D0

280

200

CL=100pF

CS1,CS2

RW,RD,A0,

D7 ~ D0

Input signal rising, falling edge

tr,tf

Note) Each timing is specified based on 0.2xVDD and 0.8xVDD.

NJU6676

PRELIMINARY

Read and Write characteristics (68 type MPU)

tcyc6

tAW6

tEW

R/W

tAH6

A0,CS1,CS2

tDS6

tDH6

tOH6

D7 to D0

Write

tACC6

D7 to D0

Read

(Vss=0V, VDD=4.5 to 5.5V, Ta=-30 to 80°C)

Parameter

Terminal

Symbol

Condition

Min.

Max.

Unit

Address hold time

Address set up time

System cycle time

Enable “H” pulse width (Read)

Enable “H” pulse width (Write)

Enable “L” pulse width (Read)

Enable “L” pulse width (Write)

Data set up time

tAH6

tAW6

tcyc6

tCCHR

tCCHW

tCCLR

tCCLW

tDS6

A0,CS1,

CS2

166

Data hold time

RD access time

Output disable time

tDH6

tACC6

tOH6

D7 ~ D0

CL=100pF

E,R/W,A0,

D7 ~ D0

Input signal rising, falling edge

tr,tf

NJU6676

PRELIMINARY

(Vss=0V, VDD=2.7 to 4.5V, Ta=-30 to 80°C)

Parameter

Address hold time

Address set up time

Terminal

Symbol

Condition

Min.

Max.

Unit

tAH6

tAW6

tcyc6

tCCHR

tCCHW

tCCLR

tCCLW

tDS6

A0,CS1,

CS2

System cycle time

300

120

Enable “H” pulse width (Read)

Enable “H” pulse width (Write)

Enable “L” pulse width (Read)

Enable “L” pulse width (Write)

Data set up time

Data hold time

RD access time

Output disable time

tDH6

tACC6

tOH6

D7 ~ D0

140

100

CL=100pF

E,R/W,A0,

D7 ~ D0

Input signal rising, falling edge

tr,tf

(Vss=0V, VDD=2.2 to 2.7V, Ta=-30 to 80°C)

Parameter

Terminal

Symbol

Condition

Min.

Max.

Unit

Address hold time

Address set up time

System cycle time

Enable “H” pulse width (Read)

Enable “H” pulse width (Write)

Enable “L” pulse width (Read)

Enable “L” pulse width (Write)

Data set up time

tAH6

tAW6

tcyc6

tCCHR

tCCHW

tCCLR

tCCLW

tDS6

A0,CS1,

CS2

1000

240

120

Data hold time

RD access time

Output disable time

tDH6

tACC6

tOH6

D7 ~ D0

280

200

CL=100pF

E,R/W,A0,

D7 ~ D0

Input signal rising, falling edge

tr,tf

Note) Each timing is specified based on 0.2xVDD and 0.8xVDD.

NJU6676

PRELIMINARY

Write characteristics (Serial interface)

tCSS

tCSH

CS1,CS2

tSAS

tSAH

tscyc

tSLW

SCL

tSHW

tSDH

(Vss=0V, VDD=4.5 to 5.5V, Ta=-30 to 80°C)

Parameter

Terminal

Symbol

Condition

Min.

Max.

Unit

Serial clock cycle

SCL “H” pulse width

SCL “L” pulse width

Address set up time

Address hold time

Data set up time

tscyc

tSHW

tSLW

tSAS

tSAH

tSDS

tSDH

tCSS

tCSH

200

100

SCL

Data hold time

CS-SCL time

CS1,CS2

SCL,A0,

CS1,CS2,SI

Rising, falling edge

tr,tf

NJU6676

PRELIMINARY

(Vss=0V, VDD=2.7 to 4.5V, Ta=-30 to 80°C)

Parameter

Serial clock cycle

SCL “H” pulse width

SCL “L” pulse width

Address set up time

Address hold time

Data set up time

Terminal

SCL

Symbol

Condition

Min.

Max.

Unit

tscyc

tSHW

tSLW

tSAS

tSAH

tSDS

tSDH

tCSS

tCSH

250

100

150

100

150

Data hold time

CS-SCL time

CS1,CS2

SCL,A0,

CS1,CS2,SI

Rising, falling edge

tr,tf

(Vss=0V, VDD=2.2 to 2.7V, Ta=-30 to 80°C)

Parameter

Terminal

SCL

Symbol

Condition

Min.

Max.

Unit

Serial clock cycle

SCL “H” pulse width

SCL “L” pulse width

Address set up time

Address hold time

Data set up time

tscyc

tSHW

tSLW

tSAS

tSAH

tSDS

tSDH

tCSS

tCSH

400

150

250

150

250

Data hold time

CS-SCL time

CS1,CS2

SCL,A0,

CS1,CS2,SI

Rising, falling edge

tr,tf

Note) Each timing is specified based on 0.2xVDD and 0.8xVDD.

NJU6676

PRELIMINARY

Display control timing characteristics

(OUT)

tDFR

(V_SS=0V, V_DD=4.5~5.5V, Ta=-30~80°C)

Terminal

Parameter

FR Delay Time

Symbol Condition

CL=50pF

Min.

Typ.

Max.

Unit

tDFR

(V_SS=0V, V_DD=2.7~4.5V, Ta=-30~80°C)

Terminal

Parameter

FR Delay Time

Symbol Condition

CL=50pF

Min.

Typ.

Max.

Unit

tDFR

(V_SS=0V, V_DD=2.2~2.7V, Ta=-30~80°C)

Terminal

Parameter

Symbol Condition

CL=50pF

Min.

Typ.

Max.

200

Unit

FR Delay Time

tDFR

Note) Each timing is specified based on 0.2xVDD and 0.8xVDD.

Note) The delay time is applied to the master operation only.

Reset input timing

tRW

RES

Internal circuit

During reset

status

End of reset

(V_SS=0V, V_DD=4.5~5.5V, Ta=-30~80°C)

Terminal

RES

Parameter

Reset Time

Reset ”L” Level Pulse

Width

Symbol Condition

Min.

Typ.

Max.

0.5

Unit

tRW

0.5

(V_SS=0V, V_DD=2.7~4.5V, Ta=-30~80°C)

Terminal

Parameter

Reset Time

Reset ”L” Level Pulse

Width

Symbol Condition

Min.

Typ.

Max.

1.0

Unit

RES

1.0

(V_SS=0V, V_DD=2.2~2.7V, Ta=-30~80°C)

Terminal

Parameter

Reset Time

Reset ”L” Level Pulse

Width

Symbol Condition

Min.

Typ.

Max.

1.5

Unit

RES

tRW

1.5

Note) Each timing is specified based on 0.2xVDD and 0.8xVDD.

NJU6676

PRELIMINARY

n LCD DRIVING WAVEFORM

64 65

VSS

V^DD

V¹

V²

COM⁰

COM1

COM²

COM³

COM

COM⁴

COM⁵

COM⁶

V⁴

V⁵

COM⁷

V^DD

V²

V³

COM¹

COM8

COM9

COM¹⁰

V⁵

COM

COM12

COM¹³

COM¹⁴

COM¹⁵

V²

V⁴

V⁵

COM

S S S S

E E E E

G G G G G

V^DD

V¹

V²

V³

SEG⁰

SEG¹

V⁵

V^DD

V¹

V⁴

V⁵

V⁴

V³

V¹

V^DD

-V¹

-V²

-V3

-V⁴

COM⁰-SEG0

-V

V³

V¹

COM⁰-SEG¹V^DD

-V1

-V²

-V

-V4

-V⁵

NJU6676

PRELIMINARY

nAPPLICATION CIRCUIT

- Microprocessor Interface Example

The NJU6676 interfaces to 80 type or 68 type MPU directly.

And the serial interface also communicates with MPU.

* : C86 terminal must be fixed VDD or VSS.

l 80 Type MPU

VDD

VCC

C86

A0 A7

Decoder

NJU6676

MPU

IORQ

D0 D7

D0~D7

P/S

RES

GND

VSS

RESET

l 68 Type MPU

VCC

VDD

C86

A0 A15

MPU

Decoder

NJU6676

VMA

D0 D7

R/W

RES

P/S

RES

GND

VSS

RESET

l Serial Interface

VDD

VCC

C86

A1 A7

NJU6676

Decoder

MPU

VDD

Port 1

Port 2

SCL

P/S

RES

GND

RES

VSS

RESET

NJU6676

PRELIMINARY

- 65 x 264 dots Driving Application Circuits Example

(Common and Segment Drivers Extension by using two of NJU6676)

LCD Panel : 65 x 264

SEG

COM

M/S

NJU6676

Master

NJU6676

Slave

DOF

[CAUTION]

The specifications on this databook are only

given for information , without any guarantee

as regards either mistakes or omissions. The

application circuits in this databook are

described only to show representative usages

of the product and not intended for the

guarantee or permission of any right including

the industrial rights.

NJU6676CL [NJRC]

相关型号：

NJU6676H

NJU6677

NJU6677ACH

NJU6677ACJ

NJU6677ACL

NJU6677ACL-G

NJU6677AH

NJU6677AT

NJU6677BCL

NJU6677BCL-G

NJU6677BT

NJU6677CL