NJU6655 [ETC]
64-common X 160-segment + 1-icon common Bitmap LCD Driver; 64普通X 160段+ 1图标常见的位图LCD驱动器
| 型号： | NJU6655 |
| 厂家： | 
ETC |
| 描述： | 64-common X 160-segment + 1-icon common Bitmap LCD Driver |
| 文件： | 总47页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU6655
Preliminary
64-common X 160-segment + 1-icon common
Bitmap LCD Driver
ꢀ GENERAL DESCRIPTION
ꢀ PACKAGE OUTLINE
The NJU6655 is a bitmap LCD driver to display graphics or
characters.
It contains 10,400 bits display data RAM, microprocessor
interface circuits, instruction decoder, 64-common and
160-segment + 1-icon-common drivers.
The bit image display data is transferred to the display data
RAM by serial or 8-bit parallel interface.
NJU6655CJ
65 x 160 dots graphics or 10-character 4-line by 16 x 16 dots
character with icon are displayed by NJU6655 itself.
The wide operating voltage from 2.4 to 5.5V and low operating
current are suitable for battery-powered applications.
The build-in Electrical Variable Resistance is very precision,
furthermore the rectangle outlook is very applicable to COG or
Slim TCP.
ꢀ FEATURES
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
Direct Correspondence between Display Data RAM and LCD Pixel
Display Data RAM - 10,400 bits
225 LCD Drivers - 64-common and 160-segment + 1-icon common
Direct Microprocessor Interface for both of 68 and 80 type MPU
Serial Interface (SI, SCL, A0, CS1b, CS2)
Programmable Bias selection : 1/5,1/7,1/9 bias
Useful Instruction Set
Display On/Off Cont, Initial Display Line Set, Page Address Set, Column Address Set, Status Read,
Display Data Read/Write, ADC Select, Inverse Display, Entire Display On/Off, Bias Select, Read Modify Write,
End, Reset, Common Direction Register Set, Power control set, Feedback Resistor Ratio Set,
EVR Mode Set, EVR Register Set, Static Indicator On/Off, Static Indicator Register Set, Power Save,
Power Save Reset, n-line Inverse Drive Register Set, n-line Inverse Drive Reset, Partial Select,
Internal Oscillation Circuit ON.
ꢁ
Power Supply Circuits for LCD Incorporated
Voltage Booster Circuits (4-time Maximum),
Voltage Adjust Circuits, Voltage Follower x 4
ꢁ
ꢁ
ꢁ
ꢁ
Voltage Regulator Incorporated
Precision Electrical Variable Resistance (64-step)
Low Power Consumption T.B.D.uA(Typ.).
Operating Voltage (All the voltages are based on VDD=0V.)
- Logic Operating Voltage
- Voltage Booster Operating Voltage
- LCD Driving Voltage
: -2.4V to -5.5V
: -2.4V to -6.0V
: -4.5V to -18.0V
ꢁ
ꢁ
ꢁ
Rectangle outlook for COG
Package Outline : Bump-chip
C-MOS Technology (Substrate : N)
Ver.2004-11-08
- 1 -
NJU6655
ꢀ PAD LOCATION
DUMMY19
DUMMY18
DUMMY17
S156
DUMMY1
DUMMY2
TEST1
SYNC
FRS
FR
S155
CL
DOFb
SYNC
VSS
CS1b
CS2
VDD
RESb
A0
VSS
WRb
RDb
VDD
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
VSS2
VOUT
VOUT
C3-
Y
C3-
C1+
C1+
C1-
C1-
C2-
C2-
X
C2+
C2+
VSS
VSS
VRS
VRS
DUMMY3
Chip Center
: X=0um, Y=0um
: X=8.88mm,Y=2.77mm
: 675um ± 30um
: 130um x 31um
: 50um(Min.)
Chip Size
DUMMY4
VDD
VDD
V1
V1
V2
V2
V3
V3
V4
Chip Thickness
Bump Size
Bump Pitch
Bump Height
Bump Material
: 17.5um(Typ.)
: Au
Voltage Boosting Polarity
V4
V5
V5
VR
: Negative Voltage (VDD common)
Substrate
: N
VDD
M/S
CLS
VSS
C86
P/S
VDD
TEST2
VSS
IRS
VDD
DUMMY5
DUMMY6
S4
S3
DUMMY16
DUMMY15
DUMMY14
Ver.2004-11-08
- 2 -
NJU6655
ꢀ PAD COORDINATES
Chip Size 8.88 x 2.77mm(Chip Center X=0um, Y=0um)
PAD No.
1
Terminal
DUMMY1
DUMMY2
TEST1
SYNC
FRS
FR
X= um
-4092
-4042
-3919
-3796
-3637
-3417
-3197
-2976
-2756
-2598
-2474
-2317
-2194
-2071
-1914
-1790
-1667
-1510
-1387
-1229
-1008
-788
-567
-347
-127
94
Y= um
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
PAD No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Terminal
X= um
1622
1672
1722
1772
1822
1872
1922
1972
2022
2072
2122
2172
2222
2272
2322
2372
2422
2472
2522
2572
2622
2672
2796
2953
3076
3199
3356
3480
3603
3726
3849
3972
4022
4072
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
Y= um
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1213
-1037
-987
C2+
2
C2+
3
VSS
4
VSS
5
VRS
6
VRS
7
CL
DUMMY3
DUMMY4
VDD
8
DOFb
SYNC
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
CS1b
CS2
V1
V1
VDD
V2
RESb
A0
V2
V3
VSS
V3
WRb
RDb
VDD
V4
V4
V5
D0
V5
D1
VR
D2
VDD
D3
M/S
D4
CLS
VSS
D5
D6(SCL)
D7(SI)
VDD
C86
314
P/S
472
VDD
VDD
522
TEST2
VSS
VDD
572
VDD
622
IRS
VDD
672
VDD
VSS
722
DUMMY5
DUMMY6
DUMMY7
DUMMY8
DUMMY9
DUMMY10
C31
VSS
772
VSS
822
VSS2
VSS2
VSS2
VSS2
VSS2
VOUT
VOUT
C3-
872
922
-937
972
-887
1022
1072
1122
1172
1222
1272
1322
1372
1422
1472
1522
1572
-837
C30
-787
C29
-737
C28
-687
C27
-637
C3-
C26
-587
C1+
C25
-537
C1+
C24
-487
C1-
C23
-437
C1-
C22
-387
C2-
C21
-337
C2-
C20
-287
Ver.2004-11-08
- 3 -
NJU6655
PAD No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Terminal
X= um
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4265
4115
4065
4015
3965
3915
3865
3815
3765
3715
3665
3615
3565
3515
3465
3415
3365
3315
3265
3215
3165
3115
3065
3015
Y= um
-237
-187
-137
-87
PAD No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Terminal
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
X= um
2965
2915
2865
2815
2765
2715
2665
2615
2565
2515
2465
2415
2365
2315
2265
2215
2165
2115
2065
2015
1965
1915
1865
1815
1765
1715
1665
1615
1565
1515
1465
1415
1365
1315
1265
1215
1165
1115
1065
1015
965
Y= um
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
C19
C18
C17
C16
C15
-37
C14
13
C13
63
C12
113
C11
163
C10
213
C9
263
C8
313
C7
363
C6
413
C5
463
C4
513
C3
563
C2
613
C1
663
C0
713
COMM
763
S0
813
S1
863
S2
913
DUMMY11
963
DUMMY12
1013
1063
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
DUMMY13
DUMMY14
DUMMY15
DUMMY16
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
915
865
815
765
715
665
615
565
515
Ver.2004-11-08
- 4 -
NJU6655
PAD No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Terminal
S73
X= um
465
Y= um
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
PAD No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Terminal
S123
X= um
-2035
-2085
-2135
-2185
-2235
-2285
-2335
-2385
-2435
-2485
-2535
-2585
-2635
-2685
-2735
-2785
-2835
-2885
-2935
-2985
-3035
-3085
-3135
-3185
-3235
-3285
-3335
-3385
-3435
-3485
-3535
-3585
-3635
-3685
-4015
-4065
-4115
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
Y= um
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1213
1063
1013
963
S74
415
S124
S75
365
S125
S76
315
S126
S77
265
S127
S78
215
S128
S79
165
S129
S80
115
S130
S81
65
S131
S82
15
S132
S83
-35
S133
S84
-85
S134
S85
-135
-185
-235
-285
-335
-385
-435
-485
-535
-585
-635
-685
-735
-785
-835
-885
-935
-985
-1035
-1085
-1135
-1185
-1235
-1285
-1335
-1385
-1435
-1485
-1535
-1585
-1635
-1685
-1735
-1785
-1835
-1885
-1935
-1985
S135
S86
S136
S87
S137
S88
S138
S89
S139
S90
S140
S91
S141
S92
S142
S93
S143
S94
S144
S95
S145
S96
S146
S97
S147
S98
S148
S99
S149
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S150
S151
S152
S153
S154
S155
S156
DUMMY17
DUMMY18
DUMMY19
DUMMY20
DUMMY21
DUMMY22
S157
913
S158
863
S159
813
C32
763
C33
713
C34
663
C35
613
C36
563
C37
513
C38
463
Ver.2004-11-08
- 5 -
NJU6655
PAD No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
Terminal
X= um
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
-4265
Y= um
413
C39
C40
363
C41
313
C42
263
C43
213
C44
163
C45
113
C46
63
C47
13
C48
-37
C49
-87
C50
-137
-187
-237
-287
-337
-387
-437
-487
-537
-587
-637
-687
-737
-787
-837
-887
-937
-987
-1037
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
COMM
DUMMY23
DUMMY24
DUMMY25
DUMMY26
Ver.2004-11-08
- 6 -
NJU6655
ꢀ BLOCK DIAGRAM
C31 - - - - C0
C32 - - - C63
S0 - - - - - - - - - - - - - S159
COMM
VSS
VDD
Segment
Drivers
Common
Drivers
5
Common
Drivers
V1 to V5
Internal
Voltage
Shift
Power
Shift
Followers
Common
Register
Circuits
Register
Timing
VR
VRS
IRS
Voltage
Regulator
Display Data Latch
VOUT
C1+/C1-
C2+/C2-
C3-
Voltage
Converter
Display Data RAM
VSS2
160 X 65 = 10,400-bit
Column Address Decoder 160
Column Address Counter 8bit
M/S
FR
Display
Timing
FRS
CL
CLS
SYNC
DOFb
Column Address Register 8bit
Multiplexer
Oscillator
Instruction
Decoder
Status
Bus Holder
Busy Flag
Internal Bus Line
Reset
MPU Interface
D7
D6
RESb
CS1b
CS2
A0
RDb
WRb
C86
P/S D0 to D5
(SI)
(SCL)
Ver.2004-11-08
- 7 -
NJU6655
ꢀ TERMINAL DISCRIPTION
No.
SYMBOL
I/O
FUNCTION
1,2,57,58, DUMMY1
Dummy terminals.
83 to 88,
to
These are open terminals electrically.
125 to 130, DUMMY26
285 to 290,
327 to 330
13,19,
VDD
VSS
Power Power supply terminal.
GND Ground terminal.
28 to 32
59,60,72,
78,82
10,16,
33 to 35
53,54,75,
80
36 to 40
55,56
VSS2
VRS
Power Reference voltage for voltage booster.
Power External reference voltage input terminal.
Normally open.
61,62
63,64
65,66
67,68
69,70
V1
V2
V3
V4
V5
Power LCD driving voltage supplying terminal.
When the internal voltage booster is not used, supply each level of LCD driving
voltage from outside with following relation.
V
DD≥V1≥V2≥V3≥V4≥V5≥VOUT
When the internal power supply is on, the internal circuits generate and supply
following LCD bias voltage from V1 to V4 terminal.
Bias
1/5 Bias
V1
V2
V3
V4
V5+4/5VLCD
V5+6/7VLCD
V5+8/9VLCD
V5+3/5VLCD
V5+5/7VLCD
V5+7/9VLCD
V5+2/5VLCD V5+1/5VLCD
V5+2/7VLCD V5+1/7VLCD
V5+2/9VLCD V5+1/9VLCD
1/7 Bias
1/9 Bias
(VLCD=VDD-V5)
45,46
47,48
51,52
49,50
43,44
41,42
C1+
C1-
O
Boosted capacitor connecting terminals used for voltage booster.
C2+
C2-
C3-
VOUT
O
I
Voltage booster output terminal.
Connect the boosted capacitor between this terminal and VSS2
Voltage adjustment terminal
.
71
VR
Connect external feedback resistor to control the LCD driving voltage V5. This
terminal is effective when IRS=”L”.
20 to 27
(26, 27)
D0 to D7
I/O
Data input/output terminals.
(SCL, SI)
P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.
P/S="L" : D7=Serial data input terminal. D6=Serial data clock signal input terminal.
D0 to D5 terminals are Hi-impedance.
Data from SI is loaded at the rising edge of SCL and latched as the parallel data at
8th rising edge of SCL. When CS1b="H", D0 to D7 terminals are Hi-impedance.
Data discrimination signal input terminal.
15
14
A0
I
I
Connect to the Address bus of MPU. The data on the D0 to D7 is distinguished between
Display data and Instruction by status of A0.
A0
Distinction
H
L
Display Data
Instruction
RESb
Reset terminal.
When the RESb terminal goes to “L”, the initialization is performed.
Reset operation is executing during “L” state of RESb.
Ver.2004-11-08
- 8 -
NJU6655
No.
SYMBOL
I/O
I
FUNCTION
11
12
18
CS1b
CS2
RDb
(E)
Chip select terminal.
Data Input/Output are available during CS1b=”L” and CS2=”H”.
<In case of 80 Type MPU>
I
RDb signal of 80 type MPU input terminal. Active "L"
During this signal is "L" , D0 to D7 terminals are output.
<In case of 68 Type MPU>
Enable signal of 68 type MPU input terminal. Active "H"
<In case of 80 Type MPU>
17
WRb
I
(R/W)
Connect to the 80 type MPU WRb signal. Active "L".
The data on the data bus input synchronizing the rise edge of this signal.
<In case of 68 Type MPU>
The read/write control signal of 68 type MPU input terminal.
R/W
State
H
Read
L
Write
76
77
C86
P/S
I
I
MPU interface type selection terminal.
This terminal must connect to VDD or VSS.
C86
State
H
L
68 Type
80 Type
Serial or parallel interface selection terminal.
Serial
Clock
-
P/S
Chip Select Data/Instruction
Data Read/Write
D0toD7 RDb,WRb
“H”
“L”
CS1b,CS2
CS1b,CS2
A0
A0
SI(D7)
-
SCL(D6)
In case of the serial interface (P/S="L")
RAM data and status read operation do not work in mode of the serial interface.
RDb and WRb must be fixed "H" or "L", and D0 to D5 are high impedance.
Terminal to select whether or enable or disable the display clock internal oscillator
circuit.
74
73
CLS
M/S
I
I
CLS=”H” : Internal oscillator circuit is enable
CLS=”L” : Internal oscillator circuit is disabled (requires external input)
When CLS=”L”, input the display clock through the CL terminal.
This terminal selects the master/slave operation for the NJU6655.
Master operation outputs the timing signals that are required for the LCD display, while
slave operation inputs the timing signals required for the LCD, synchronizing the LCD
system.
M/S = ”H” : Master operation
M/S = ”L” : Slave operation
The following is true depending on the M/S and CLS status:
Power
M/S CLS
OSC.
Supply
Circuit
CL
FR
FRS
DOFb
“H” Available Available Output Output Output Output
“L” Not Avail. Available Input Output Output Output
“H”
“L”
*
Not Avail. Not Avail. Input
Input Output Input
*:Don’t Care
7
CL
I/O
Display clock input/output terminal.
The following is true depending on the M/S and CLS status.
M/S
“H”
“L”
CLS
“H”
“L”
*
CL
Output
Input
Input
*:Don’t Care
Ver.2004-11-08
- 9 -
NJU6655
No.
SYMBOL
FR
I/O
I/O
FUNCTION
6
LCD alternating current signal I/O terminal.
M/S=”H” : Output
M/S=”L” : Input
4,9
8
SYNC
DOFb
I/O
I/O
LCD synchronizing current signal I/O terminal.
M/S=”H” : Output
M/S=”L” : Input
LCD Display blanking control terminal.
M/S=”H” : Output terminal. Display “On” = “H”, Display “Off” = “L”
M/S=”L” : Input terminal. External control. Refer to the following table.
DOFb
Instruction
H
On
Off
L
Off
Off
Display On
Display Off
81
5
IRS
I
Internal Feedback Resistor Select
IRS=“H” : Internal feedback
IRS=“L” : External feedback resistor
This setting is effective in the master operation. It is ineffective in the slave operation
but should be fixed to “H” or “L”.
FRS
O
O
The output terminal for the static drive.
This terminal is used in conjunction with the SYNC terminal.
LCD driving signal output terminals.
89 to 120
C31 to C0
-Common output terminals : C0 to C63
-Segment output terminals : S0 to S159
Common output terminals
The following output voltages are selected by the combination of alternating (FR)
signal and Common scanning data.
122 to 124, S0 to S159
131 to 284,
O
O
Scan Data
H
FR
Output Voltage
H
L
H
L
V5
VDD
V1
291 to 293
L
V4
294 to 325 C32 to C63
Segment output terminals
The following output voltages are selected by the combination of alternating (FR)
signal and display data in the RAM.
Output Voltage
RAM Data
FR
Normal
VDD
V5
Reverse
V2
H
L
H
L
H
L
V3
V2
VDD
V5
V3
121,326
COMM
TEST1
TEST2
O
O
I
COM output terminals for the indicator.
Both terminals output the same signal. Leave these open if they are not used.
3
Maker test only.
Normally open.
79
Maker test only.
This terminal must connect to VSS.
Ver.2004-11-08
- 10 -
NJU6655
ꢀ FUNCTIONAL DESCRIPTION
(1) Description for each blocks
(1-1) Busy Flag (BF)
During internal operation, the LSI is being busy and can’t accept any instructions except “status read”. The BF
data is output through D7 terminal by the “status read” instruction.
When the cycle time (tcyc) mentioned in the “AC characteristics” is satisfied, the BF check isn’t required after
each instruction, so that MPU processing performance can be improved.
(1-2) Initial display line register
The initial display line register assigns a DDRAM line address, which corresponds to COM0 by “initial display
line set” instruction. It is used for not only normal display but also vertical display scrolling and page switching
without changing the contents of the DDRAM.
However, the 65th address for icon display can’t be assigned for initial display line address.
(1-3) Line counter
The line counter provides a DDRAM line address. It initializes its contents at the switching of frame timing signal
(FR), and also counts-up in synchronization with common timing signal.
(1-4) Column address counter
The column address counter is an 8-bit preset counter, which provides a DDRAM column address, and it is
independent of below-mentioned page address register.
It will increment (+1) the column address whenever “display data read” or “display data write” instructions are
issued. However, the counter will be locked when no-existing address above A0H are addressed. The count-lock will
be able to be released by the “column address set” instruction again. The counter can invert the correspondence
between the column address and segment driver direction by means of “ADC set” instruction.
(1-5) Page address register
The page address register provides a DDRAM page address.
The last page address “8” should be used for icon display because the only D0 is valid.
(1-6) Display data RAM (DDRAM)
The DDRAM contains 10,400-bit, and stores display data, which are 1-to-1 correspondents to LCD panel pixels.
When normal display mode, the display data “1” turns on and “0” turns off LCD pixels. When inverse display
mode, “1” turns off and “0” turns on.
Ver.2004-11-08
- 11 -
NJU6655
Line
Common
Driver
Data
Page Address
Display Pattern
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
C56
C57
C58
C59
C60
C61
C62
C63
C0
C1
C2
C3
C4
00H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
D3,D2,D1,D0
(0,0,0,0)
PAGE 0
D3,D2,D1,D0
(0,0,0,1)
PAGE 1
PAGE 2
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
12
13
14
15
16
17
18
19
1A
D3,D2,D1,D0
(0,0,1,0)
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
C46
C47
C48
C49
C50
C51
C52
C53
36
D6
D7
D0
D1
D2
D3
D4
D6
D7
D0
37
38
39
3A
3B
3C
3D
3E
3F
D3,D2,D1,D0
(0,1,1,1)
PAGE 7
PAGE 8
C54
C55
COMM*
(1,0,0,0)
D0="0" 00 01 02 03 04 05 06
D0="1" 9F 9E 9D 9C 9B 9A 99
9E 9F
01 00
Column
ADC
Address
For example the Initial
display is 08H.
Segment Drivers
0
1
2
3
4
5
6
- - - - - - - - - - - - - - - -
158 159
Fig.1 Display data RAM (DDRAM) Map
* : COMM is independent of the “Initial display line set” instruction and always corresponds to the 65th line.
Ver.2004-11-08
- 12 -
NJU6655
(1-7) Common direction register
The common direction register is selected by the "Partial Select" and "Common Direction Register Set"
instructions as shown in Table 1. When using the partial display function, the COM0 - COM15 and COM48
-
COM63 terminals cannot be used.
Table 1. Common direction
Partial
Select
Common
Direction
Register Set
D3
Common drivers
D0
PADNo. 114
Pin name C0
83
309
278
C32
COM32
COM31
278
C32
COM32
COM31
C31
COM31
COM32
83
C63
0
0
0
1
COM0
COM63
PADNo. 98
Pin name C16
COM16
COM47
COM63
COM0
293
C31
C47
1
1
0
1
COM31
COM32
COM47
COM16
(1-8) Reset circuit
The reset circuit initializes the LSI to the following status by using of the reset signal into the RESb terminal.
-Reset status using the RESb terminal:
1. Display off
2. Normal display (Non-inverse display)
3. ADC select : Normal mode (D0="0")
4. Power control register clear : D2,D1,D0=”0,0,0”
5. Serial interface register clear
6. LCD bias select : D1,D0=”0,0”(1/9 bias)
7. Power save reset
8. Entire display off
: Normal mode
9. Internal oscillation circuit stop
10.Partial select : D0=”0”(1/65 duty)
11.Static indicator off
Static indicator register : D1,D2=”0,0”
12.Read modify write off
13.Initial display line address : 00H
14.Column address
15.Page address
: 00H
: 0 page
16.Common direction register : D3=”0”(Normal)
17.Feedback resistors ratio : D2,D1,D0=”0,0,0”
18.EVR mode off and EVR register: D5,D4,D3,D2,D1,D0=”1,0,0,0,0,0”
19.n-line inverse drive register : D3,D2,D1,D0=”0,0,0,0”(n-line inverse reset)
20.Test mode reset (Test mode 1 and Test mode 2)
The RES terminal should be connected to MPU’s reset terminal, and the reset operation should be executed at the
same timing of the MPU reset. As described in the “BUS TIMING CHARACTERISTICS”, it is necessary to input
1.5us(min.) or over “L” level signal into the RES terminal in order to carry out the reset operation. The LSI will
return to normal operation after about 1.5us(max.) from the rising edge of the reset signal.
The reset operation by RESb="L" initializes each register setting as above reset status, but the internal oscillation
circuit and output terminals (D0 to D7) are not affected.
The reset operation is necessary to avoid malfunctions.
Note 1) The “Reset” instruction in Table.4 can’t be substituted for the reset operation by using of the RES terminal. It
executes above-mentioned only 11 to 20 items.
Note 2) The reset terminal is susceptible to external noise, so design PCB layout in consideration for the noise.
Note 3) In case of using external power supply for LCD driving voltage, the RESb terminal is required to be being “L”
level when the external power supply is turned-on.
Ver.2004-11-08
- 13 -
NJU6655
(1-9) LCD driving circuits
(a) Common and segment drivers
LCD drivers consist of 64-common drivers, 160-segment divers and 1-icon-common driver.
As shown in “■ LCD driving waveform”, LCD driving waveforms are generated by the combination of display data,
common timing signal and internal FR timing signal.
(b) Display data latch circuit
The display data latch circuit temporally stores 160-bit display data transferred from the DDRAM in the synchronization
with the common timing signal, and then it transfers these stored data to the segment drivers.
“Display on/off”, “inverse display on/off” and “entire display on/off” instructions control only the contents of this latch
circuit, they can’t change the contents of the DDRAM.
In addition, the LCD display isn’t affected by the DDRAM accuses during its displaying because the data read-out
timing from this latch circuit to the segment drivers is independent of accessing timing to the DDRAM.
(c) Line counter and latch signal or latch Circuits
The clock line counter and latch signal to the latch circuits are generated from the internal display clock (CL). The line
address of display data RAM is renewed synchronizing with display clock (CL).
160bits display data are latched in display latch circuits synchronizing with display clock, and then output to the LCD
driving circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by the
MPU.
(d) Display timing generator
The display timing generates the timing signal for the display system by combination of the master clock CL and driving
signal FR ( refer to Fig.2 ) The frame signal FR and LCD alternative signal generate LCD driving waveform on the
2-frame alternative driving method or the n-line inverse driving method.
Ver.2004-11-08
- 14 -
NJU6655
(e) Common timing generation
The common timing is generated by display clock CL (refer to Fig.2)
64 65
1
2
3
4
5
6
7
8
62 63 64 65
1
2
3
4
5
CL
FR
VDD
V1
C0
C1
V4
V5
VDD
V1
V4
V5
RAM DATA
Sn
VDD
V2
V3
V5
Fig.2-1 2-frame alternating drive mode
64 65
1
2
3
4
5
6
7
8
62 63 64 65
1
2
3
4
5
CL
FR
VDD
V1
C0
C1
V4
V5
VDD
V1
V4
V5
RAM DATA
Sn
VDD
V2
V3
V5
Fig.2-2 n-line inverse drive mode (n=7, line inverting register sets to 6)
Ver.2004-11-08
- 15 -
NJU6655
(f) Oscillator
This is the low power consumption CR oscillator which provides the display clock and voltage converter timing clock.
(g) Internal power circuits
The internal power circuits are composed of x4 boost voltage converter, output voltage regulator including 64-step EVR
and voltage followers.
The optimum values of the external passive components for the internal power circuits, such as capacitors for V1 to V5
terminals and feed back resistors for VR terminal, depend on LCD panel size. Therefore, it is necessary to evaluate the
actual LCD module with these external components in order to determine the optimum values.
Each portion of the internal power circuits is controlled by “power control set” instruction as shown in Table.2. In
addition, the combination of power supply circuits is described in Table.3.
Table.2 Power control set
Status
Portions
“1”
ON
ON
ON
“0”
D2
D1
D0
Voltage converter
Voltage regulator
Voltage followers
OFF
OFF
OFF
Table.3 Power supply combinations
Status
Voltage
Voltage
Voltage
External
voltage
VSS2
Capacitor
terminals
D2 D1 D0
converter
regulator
ON
followers
ON
Use
1) Using all internal power circuits
2) Using voltage regulator and Voltage
followers
3) Using voltage followers
4) Using only external power supply
1
0
1
1
1
1
ON
Open
OFF
ON
ON
VOUT,VSS2
Open
Open
0
0
0
0
1
0
OFF
OFF
OFF
OFF
ON
OFF
VOUT,V5,VSS2
VOUT,V1~V5
* Capacitor input terminals: C1+, C1-, C2+, C2-, C3-
* Do not use other combinations except examples in Table.3.
The internal LCD power supply is designed to drive small LCD panels such as cellular phones. Thus, if the IC is used to
drive a large panel, make sure whether it works with the internal power supply or needs an external power supply.
The selections of external components for the LCD bias circuit, the voltage booster and the feedback loop depend on
panel sizes, so make sure what are the best values in the particular application.
Ver.2004-11-08
- 16 -
NJU6655
○Power Supply applications
Power Control Instruction
D2 : Boost Circuit
D1 : Voltage Regulator
D0 : Voltage Follower
(1) Internal power supply Example.
All of the Internal Booster, Voltage Regulator,
Voltage Follower using
(2) Only VOUT Supply from outside Example.
Internal Voltage Regulator,
Voltage Follower using.
(D2,D1,D0) = (0,1,1)
(D2,D1,D0) = (1,1,1)
V
V
V
V
V
DD
1
V
V
V
V
V
DD
1
+
+
+
+
+
+
+
+
+
+
+
C1-
C1+
C3-
C2+
C2-
+
+
2
2
3
3
4
4
V
V
V
5
V
V
V
5
OUT
OUT
SS2
V
SS2
V
DD
VR
V
5
DD
VR
V
5
(3) VOUT and V5 Supply from outside Example.
Internal Voltage Follower using.
(D2,D1,D0) = (0,0,1)
(4) External Power Supply Example.
All of V1 to V5 and VOUT supply from outside
(D2,D1,D0) = (0,0,0)
V
V
V
V
V
DD
1
V
V
V
V
V
DD
1
+
+
+
+
2
2
3
3
4
4
V
V
V
5
V
V
V
5
OUT
SS2
OUT
SS2
: These switches should be open during the power save mode.
Note) : When using the voltage follower circuit, external resistors may be necessary to stabilize V1,V2,V3 and V4
voltages.
Ver.2004-11-08
- 17 -
NJU6655
(2) Instruction set
The NJU6655 distinguishes the signal on the data bus D0 to D7 as an Instruction by combination of A0 , RDb and
WRb(R/W). The decode of the instruction and execution performs with only high speed Internal timing without
relation to the external clock. Therefore no busy flag check required normally. In case of serial interface, the data
input as MSB(D7) first serially. The Table. 4-1,4-2 shows the instruction codes of the NJU6655.
Table. 4-1 Instruction table
(*: Don’t Care)
Instruction code
Instruction
Description
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
(a)
(b)
(c)
(d)
Display On/Off
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0/1 LCD Display On/Off
D0=0:Off D0=1:On
Initial Display Line Set
Page Address Set
1
0
0
0
Line Address
Determine the Display Line of RAM to
COM0
Set the page of DD RAM to the Page
Address Register
Set the Upper order 4 bits Column
Address to the Register
Set the Lower order 4 bits Column
Address to the Register
1
0
0
1
1
0
Page Address
Column Address Set
Upper Order
Upper Order 4bits
Column Address Set
Lower Order 4bits
Column Address
Lower Order
Column Address
(e)
(f)
Status Read
0
1
0
1
1
0
Status
0
0
0
0
Read out the internal Status
Write Display Data
Write Data
Write the data into the Display Data
RAM
(g)
(h)
(i)
Read Display Data
ADC Select
1
0
0
0
0
1
1
1
1
0
0
0
Read Data
Read the data from the Display Data
RAM
0/1 Set the DD RAM vs Segment
D0=0 :Normal D0= 1:Inverse
0/1 Inverse the On and Off Display
D0=0 :Normal D0= 1:Inverse
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
0
1
0
Normal or Inverse of
On/Off Set
Whole Display Turns On
D0=0: Normal D0=1: Whole Disp. On
Select the Bias
Increment the Column Address Register
when writing but no-change when
reading
(j)
0/1
Whole Display On/Off
(k)
(l)
LCD Bias Select
Read Modify Write
0
0
1
1
0
0
1
1
0
1
0
1
1
0
0
0
0
0
Bias
0
1
0
0
(m)
End
0
1
0
1
1
1
0
1
1
Release from the Read Modify write
Mode
(n)
(o)
Reset
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
*
1
*
0
*
Initialize the Internal Circuits
Common Direction Select
0/1
Set the scanning order of common
drivers to the Register
D3=0 : Normal, D3=1 : Inverse
(p)
(q)
Power Control Set
Feedback Resistor Ratio Set
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
0
Operating Mode Set the status of internal power circuits
Resistor Ratio
Set the status of internal resistors ratio
(Rb/Ra)
Ver.2004-11-08
- 18 -
NJU6655
Table. 4-2 Instruction table
(*: Don’t Care)
Instruction code
Instruction
Description
A0 RDb WRb D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
(r)
EVR Mode Set
0
0
1
1
0
0
1
*
Set EVR mode
EVR Register Set
*
Setting Data
Set the V5 output level to the EVR
register
(s)
(t)
Static Indicator On/Off
Static Indicator Register Set
Pawer Save
0
0
0
1
1
1
0
0
0
1
*
1
0
*
0
1
*
1
0
*
0
1
*
1
1
*
0
0
0/1 D =0 : Off, D =1 : On
0 0
Mode
0
Set static indicator register
0/1 D =0 : Standby mode
0
D =1 : Sleep mode
0
(u)
(v)
Pawer Save Reset
n-line Inverse Drive Register
Set
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
0
0
1
Release from the Pawer Save Mode
Set the number of inverse drive line
Number of Inverse
Lines
(w)
(x)
n-line Inverse Drive Reset
Partial Select
0
0
1
1
0
0
1
1
1
0
1
1
0
0
0
0
1
0
0
1
0
Release the line inverse drive
0/1 D =0 : Off (1/65 Duty)
0
D =1 : On (1/33 Duty)
0
(y)
(z)
Internal Oscillation Circuit
On
NOP
0
0
1
1
0
0
1
1
0
1
1
1
0
0
1
0
0
0
1
1
1
1
Start the operation of the Internal
Oscillation circuit
Ver.2004-11-08
- 19 -
NJU6655
(2-1) Explanation of Instruction Code
(a) Display On/Off
This instruction selects display turn-on or turn-off regardless of the contents of the DDRAM.
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
D
0
1
0
1
D
0: Display Off
1: Display On
(b) Initial Display Line Set
This instruction specifies the DDRAM line address which corresponds to the COM0 position.
By means of repeating this instruction, the initial display line address will be dynamically changed; it means smooth
display scrolling will be enabled.
A0 RDb WRb D7
D6
1
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
0
1
0
0
A5
0
0
:
A4
0
0
:
A3
0
0
:
A2
A1
A0
0
1
:
Line Address (HEX)
0
0
:
0
0
:
00
01
:
:
:
:
:
:
:
:
1
1
1
1
1
1
3F
(c) Page Address Set
In order to access to the DDRAM for writing or reading display data, both “page address set” and “column address set”
instructions are required before accessing.
The last page address “8” should be used for icon display because the only D0 is valid.
A0 RDb WRb D7
D6
0
D5
1
D4
1
D3
A3
D2
A2
D1
A1
D0
A0
0
1
0
1
A3
0
0
:
A2
A1
0
0
:
A0
Page
0
0
:
0
1
:
0
1
:
:
:
:
:
:
1
0
0
0
8
Ver.2004-11-08
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NJU6655
(d) Column Address Set
As above-mentioned, in order to access to the DDRAM for writing or reading display data, it is necessary to execute
both “page address set” and “column address set” before accessing. The 8-bit column address data will be valid when
both upper 4-bit and lower 4-bit data are set into the column address register.
Once the column address is set, it will automatically increment (+1) whenever the DDRAM will be accessed, so that the
DDRAM will be able to be continuously accessed without “column address set” instruction.
The column address will stop increment and the page address will not be changed when the last address 9FH is
addressed.
A0 RDb WRb D7
D6
0
D5
0
D4
1
D3
A7
D2
A6
D1
A5
D0
0
1
0
0
A4 Upper 4-bit
0
1
0
0
0
0
0
A3
A2
A1
A0 Lower 4-bit
A7
0
0
:
A6
0
0
:
A5
0
0
:
A4
0
0
:
A3
0
0
:
A2
0
0
:
A1
0
0
:
A0
0
1
:
Column Address (HEX)
00
01
:
:
:
:
:
:
:
:
:
:
1
0
0
1
1
1
1
1
9F
(e) Status Read
This instruction reads out the internal status regarding “busy flag”, “ADC select”, “display on/off” and “reset”.
A0 RDb WRb D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
0
0
1
BUSY ADC ON/OFF RESET
BUSY
ADC
: When D7 is “1”, the LSI is being busy and can’t accept any instructions.
: It shows the correspondence between the column address and segment drivers.
When D6 is “0”, the column address (159-n) corresponds to segment driver n.
When D6 is “1”, the column address (n)
corresponds to segment driver n.
Please be careful that read out data is opposite of “ADC select” instruction data.
ON/OFF
RESET
: It shows display on or off status.
When D5 is “0”, the LSI is in display-on status.
When D5 is “1”, the LSI is in display-off status.
Please be careful that read out data is opposite of “Display On/Off” instruction data.
: It shows reset status.
When D4 is “0”, the LSI is in normal operation.
When D4 is “1”, the LSI is during reset operation.
(f) Display Data Write
This instruction writes display data into the selected column address on the DDRAM.
The column address automatically increments (+1) whenever the display data is written by this instruction, so that this
instruction can be continuously issued without “column address set” instruction.
A0 RDb WRb D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
Write Data
Ver.2004-11-08
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NJU6655
(g) Display Data Read
This instruction reads out the display data stored in the selected column address on the DDRAM.
The column address automatically increments (+1) whenever the display data is read out by this instruction, so that this
instruction can be continuously issued without “column address set” instruction.
After the ”column address set” instruction, a dummy read will be required, please refer to the (4-4).
In case of using serial interface mode, this instruction can’t be used.
A0 RDb WRb D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
Read Data
(h) ADC Select
This instruction selects segment driver direction.
The correspondence between the column address and segment driver direction is shown in Fig.1.
This function reduces the restrictions on the IC position of an LCD module.
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
D
0
1
0
1
D
0: Clockwise Output (Normal)
Segment Driver S0 to S159
1: Counterclockwise Output (Inverse) Segment Driver S159 to S0
(i) Inverse Display On/Off
This instruction inverses the status of turn-on or turn-off of entire LCD pixels. It doesn’t change the contents of the
DDRAM.
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
0
D2
1
D1
1
D0
D
0
1
0
1
D
0: Normal
1: Inverse
RAM data "1" correspond to "On"
RAM data "0" correspond to "On"
(j) Whole Display On/Off
This instruction turns on entire LCD pixels regardless the contents of the DDRAM. It doesn’t change the contents of
DDRAM.
This instruction should be performed prior to the "Inverse display On/Off" instruction.
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
0
D2
1
D1
0
D0
D
0
1
0
1
D
0: Normal Display
1: Whole Display Turns On
(Whole Display Off)
(Whole Display On)
(k) Bias Select
This instruction selects LCD bias value.
A0 RDb WRb D7
D6
0
D5
0
D4
1
D3
0
D2
0
D1
A1
D0
A0
0
1
0
1
A1
A0
0
LCD Bias
1/9
0
0
1
1
1
1/7
0
1
1/5
Prohibited*
* : Because it may malfunction-operate, do not set (D1,D0) = (1,1).
Ver.2004-11-08
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NJU6655
(l) Read Modify Write
This instruction controls column address increment.
By using of this instruction, the column address can’t increment when read operation but it can increment when write
operation. This status will be continued until the below-mentioned “end” instruction will be issued.
This instruction can reduce the load of MPU, during the display data in specific DDRAM area is repeatedly changed for
cursor blink or others.
A0 RDb WRb D7
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
0
1
0
1
Note) In this "Read Modify Write" mode, out of display data "Read" / "Write", any instructions except "Column Address
Set" can be executed.
- The Sequence of Cursor Blink Display
Page Address Set
Set to the Start Address of Cursor
Display
Column Address Set
Read Modify Write
Data Read
Start the Read Modify Write
The data is ignored
Column Counter doesn’t increase
Data inverse by MPU
Column Counter increase
Data Write
Column Counter doesn’t increase
Column Counter doesn’t increase
Column Counter increase
Data Write
Column Counter doesn’t increase
Column Counter doesn’t increase
Column Counter increase
Data Write
Repeating
End the Read Modify Write
No
Finish?
Yes
Ver.2004-11-08
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NJU6655
(m) End
The “end” instruction cancels the read modify write mode and makes the column address return to the initial value just
before “read modify write” is started.
A0 RDb WRb D7
D6
1
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
0
1
0
1
Return
End
Column
Address
N
N+1
N+2
N+3
- - - -
N+m
N
Read modify write
(n) Reset
This instruction reset the LSI to the following status, however it doesn’t change the contents of the DDRAM. Please be
careful that it can’t be substituted for the reset operation by using of the RESb terminal.
Reset status by “reset” instruction:
1: Static indicator register
2: Read modify write off
3: Initial display line address
4: Column address
: D1,D0 = “0,0”
: 00H
: 00H
5: Page address
: 0 page
6: Common direction register
7: Feedback resistors ratio
8: EVR mode off and EVR register
9: n-line inverse drive register
: D3=”0”(Normal mode)
: D2,D1,D0 = “0,0,0”
: D5,D4,D3,D2,D1,D0 = “1,0,0,0,0,0”
: D3,D2,D1,D0 = “0,0,0,0”
10: Test mode reset (Test mode 1 and Test mode 2)
The DD RAM is not affected of this initialization.
A0 RDb WRb D7
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
0
0
1
0
1
(o) Common Driver Direction Select
This instruction selects common driver direction.
Please refer to (1-7) common driver direction for more detail.
A0 RDb WRb D7
D6
1
D5
0
D4
0
D3
D3
D2
*
D1
*
D0
*
0
1
0
1
(*: Don’t Care)
D3
0: Normal
1: Inverse
Common driver direction (C0 to C63) or (C16 to C47)
Common driver direction (C63 to C0) or (C47 to C16)
Ver.2004-11-08
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NJU6655
(p) Power Control Set
This instruction controls the status of internal power circuits. Please refer to the (1-9) LCD Driving Circuits (g) internal
power circuits for more detail.
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
1
D2
A2
D1
A1
D0
A0
0
1
0
0
A2
A1
A0
0: Voltage Converter Off
1: Voltage Converter On
0: Voltage Regulator Off
1: Voltage Regulator On
0: Voltage Followers Off
1: Voltage Followers On
Note) The internal power supply must be Off when external power supply using.
* The wait time depends on the C4 to C8, COUT capacitors, and VDD and VLCD Voltage.
Therefore it requires the actual evaluation using the LCD module to get the correct time.
(q) Feedback Resistor Ratio Set
This instruction is used to determine the internal feedback resistor ratio.
Please refer to the (3-2) Voltage Adjust Circuits for more detail.
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
0
D2
A2
D1
A1
D0
A0
0
1
0
0
Internal resistor ratio
VLCD
A2
A1
A1
1+(Rb/Ra)
4.5
1+(Rb/Ra)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Minimum
5.0
:
5.5
:
6.0
:
6.5
:
7.0
:
7.6
:
8.1
Maximum
Ver.2004-11-08
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NJU6655
(r) EVR Set
1) EVR mode set
This instruction sets the LSI into the EVR mode, and it is always used by the combination with “EVR register set”. The
LSI can’t accept any instructions except the “EVR register set” during the EVR set mode. This mode will be released
after the “EVR register set” instruction.
A0
0
RDb WRb D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
1
0
1
2) EVR Register Set
This instruction sets 6-bit data into the EVR register to determine the output voltage “V5” of the internal voltage
regulator.
A0 RDb WRb D7
D6
*
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
D0
0
1
0
*
A0 (*: Don’t Care)
A5
0
0
:
A4
0
0
:
A3
0
0
:
A2
A1
A0
0
1
:
VLCD
0
0
:
0
0
:
Minimum
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
Maximum
(s) Static Indicator
1) Static Indicator On/Off
This instruction selects static indicator turn-on or turn-off, and it is always used by the combination with the “ static
indicator register set”.
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
1
D2
1
D1
0
D0
D
0
1
0
1
D
0: Static Indicator Off
1: Static Indicator On
2) Static Indicator Register Set
A0 RDb WRb D7
D6
*
D5
*
D4
*
D3
*
D2
*
D1
A1
D0
0
1
0
*
A0 (*: Don’t Care)
A1
A0
0
Indicator display Status
Off
On (Blink at 1.0s intervals)
On (Blink at 0.5s intervals)
On (Turn on at all time)
0
0
1
1
1
0
1
Ver.2004-11-08
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NJU6655
(t) Power Save
This instruction sets the LSI into the power save mode. This instruction is reducing operating current as well as static
operations.
The internal status and the contents of the DDRAM will be remained just before the “Power save” instruction. In
addition, the DDRAM can be accessed during the power save mode.
There are two power save modes, sleep mode and standby mode.
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
1
D2
0
D1
0
D0
D
0
1
0
1
D
0: Standby Mode
1: Sleep Mode
<Sleep Mode>
All functions are halted so that its operating current is reduced as low as standby current.
All LCD system stops as follows,
1) Oscillator and internal power circuits stop.
2) All common and segment drivers output VDD level.
<Standby Mode>
A part of functions are halted. The only static drive system as the indicator operates.
The LCD system except the static indicator stops as follows,
1) Internal power circuits stop. (Oscillator is operating.)
2) LCD driving is stopped. All common and segment drivers output VDD level.
3) The only static indicator is working.
(u) Pawer Save Reset
This instruction releases the power save mode.
A0 RDb WRb D7
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
1
0
1
0
1
Ver.2004-11-08
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NJU6655
(v) n-line Inverse Drive Register Set
This instruction specifies the number of n-line. Please refer to the (1-9)LCD Driving Circuits (e)Common timing
generation Fig.2-1, Fig.2-2 for more detail.
A0 RDb WRb D7
D6
0
D5
1
D4
1
D3
A3
D2
A2
D1
A1
D0
A0
0
1
0
0
A3
0
0
0
:
1
1
A2
0
0
0
:
1
1
A1
A0
0
1
0
:
0
1
Inverse Lines
0
0
1
:
-(*)
2
(*) 2-frame alternating drive
mode.
3
:
15
16
1
1
(w) n-line Inverse Drive Reset
This instruction releases n-line inversion, but does not change the contents of the n-line register.
A0 RDb WRb D7
D6
1
D5
1
D4
0
D3
0
D2
1
D1
0
D0
0
0
1
0
1
(x) Patial Select
This instruction starts the partial mode operation.
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
0
D2
0
D1
1
D0
D
0
1
0
1
D
0: 1/65 Duty (Partial Select Off)
1: 1/33 Duty (Partial Select On)
Display structure by Partial Select On / Off
Partial Select On
Partial Select Off
(1/65 Duty)
(1/33 Duty)
COM0~COM7
COM8~COM15
COM16~COM23
COM24~COM31
COM32~COM39
COM40~COM47
COM48~COM55
COM56~COM63
COMM
COM0~COM7
COM8~COM15
COM16~COM23
COM24~COM31
COM32~COM39
COM40~COM47
COM48~COM55
COM56~COM63
COMM
64com+1
32com+1
160seg
160seg
Active Display-block
Ver.2004-11-08
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NJU6655
(y) Internal Oscillation Circuit On
This setting is effective when M/S=”1” and CLS=”1”.
A0 RDb WRb D7
D6
0
D5
1
D4
0
D3
1
D2
0
D1
1
D0
1
0
1
0
1
(z)NOP
Non Operation.
A0 RDb WRb D7
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
1
0
1
0
1
Ver.2004-11-08
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NJU6655
(3) Internal power circuits
(3-1) Voltage converter
The voltage converter generates maximum 4x boosted negative-voltage from the voltage between VDD and VSS2. The
boosted voltage is output from the VOUT terminal.
The internal oscillator is required to be operating when using this converter, because the divided signal provided from
the oscillator is used for the internal timing of this circuit.
The boosted voltage between VDD and VOUT must not exceed 18.0V.
The voltage converter requires external capacitors for boosting as shown in below.
ꢁ
The boosted voltage and VDD, VSS2
VDD=+3V
V
V
V
V
SS2=0V
OUT=-3V
OUT=-6V
OUT=-9V
2x boost
3x boost
3x boost
4x boost
ꢁ
Example for connecting the capacitors
4x boost
2x boost
VSS2
C1-
VSS2
C1-
VSS2
C1-
C1+
C3-
C2+
C1+
+
+
+
C1+
+
+
+
+
+
C3-
C2+
C3-
C2+
C2-
C2-
C2-
VOUT
VOUT
VOUT
Ver.2004-11-08
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NJU6655
(3-2) Voltage Adjust Circuits
The voltage adjust circuits is composed of the reference voltage circuit, 64-step E.V.R. and feedback resistors. The adjust
circuits produces the LCD driving voltage V5 on the V5 terminal, using the VOUT voltage supplied from the internal
booster.
(a) Using Internal Feedback Resistors
LCD contrast can be fine-tuned by adjusting the V5 voltage through setting the internal feedback resistors and the E.V.R.
And the V5 voltage is calculated from the foemula (1), where |V5| < |VOUT|.
VLCD = VDD-V5
- - - - - (1)
= (1+(Rb/Ra)) x VCON
[VCON = (EVR) x (VREG)]
= (1+(Rb/Ra)) x (EVR) x VREG [EVR = (n+99) / 162]
VLCD : LCD Driving Voltage VCON : Contrast Control Voltage
VREG : Reference Voltage
VDD
Ra,Rb : Feedback Resistors
n
: E.V.R. Setting Value
VCON
(VREG x EVR)
Internal Ra
VLCD
+
-
V5
VOUT
Internal Rb
Fig.3-1 Voltage adjust circuits (Using internal feedback resistors)
The VREG is the regulated voltage with temperature coefficient, as follows.
Temperature
Coefficient
Internal Power Supply 0.05[%/°C] (Typ.)
VREG
2.11[V] (Typ.)
The V5 is adjusted in 64-step by setting 6-bit data into the E.V.R. register, as follows.
E.V.R. Register
E.V.R. Value
(99/162)
(100/162)
(101/162)
:
VLCD
00H
01H
02H
:
(0,0,0,0,0,0)
Minimum
(0,0,0,0,0,1)
:
(0,0,0,0,1,0)
:
:
:
:
:
:
:
:
:
:
:
3DH
3EH
3FH
(1,1,1,1,0,1)
(1,1,1,1,1,0)
(1,1,1,1,1,1)
(160/162)
(161/162)
(162/162)
:
:
Maximum
Ver.2004-11-08
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NJU6655
The ratio of the Ra and Rb (Ra/Rb) is selected out of 8 options by the "Feedback Resistor set" instruction.
The Register of Feedback Resistor
1+(Rb/Ra)
4.5
VLCD
00H
01H
02H
03H
04H
05H
06H
07H
(0,0,0)
(0,0,1)
(0,1,0)
(0,1,1)
(1,0,0)
(1,0,1)
(1,1,0)
(1,1,1)
Minimum
5.0
:
5.5
:
6.0
:
6.5
:
7.0
:
7.6
:
8.1
Maximum
* : The resistance of the feedback resistors has a certain amount of error. If it may impact on the LCD contrast external
feedback resistors should be considered.
(b) Using External Feedback Resistors
When IRS="L", the V5 voltage can be adjusted by the external feedback resistors. And the E.V.R. function is applied in
combination, and fine-tunes the LCD contrast through software. The V5 voltage is calculated from the formula (2), where
|V5| < |VOUT|.
VLCD = VDD-V5
- - - - - (2)
= (1+(Rb/Ra)) x VCON
[VCON = (EVR) x (VREG)]
= (1+(Rb/Ra)) x (EVR) x VREG [EVR = (n+99) / 162]
VLCD : LCD Driving Voltage VCON : Contrast Control Voltage
VREG : Reference Voltage
VDD
Ra,Rb : Feedback Resistors
n
: E.V.R. Setting Value
VCON
(VREG x EVR)
External Ra
VLCD
VR
+
-
V5
VOUT
External Rb
Fig.3-2 Voltage adjust circuits (Using external feedback resistors)
* : When using either the internal feedback resistors or E.V.R. or both, the LCD voltage generator and the buffer
amplifiers must be activated.
* : The VR terminal is only used for the external feedback resistors. This must be open when using the internal
feedback resistors.
Ver.2004-11-08
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NJU6655
<Design example for the adjustable range / Reference> Using external resistors(Not using variable resistor), VLCD=7V
Power supply
VDD=3.0V, VSS=0V
E.V.R. register = (D5,D4,D3,D2,D1,D0) : (1,0,0,0,0)
By formula (2)
VLCD = VDD-V5
= (1+(Rb/Ra)) x (EVR) x VREG
7[V] = (1+(Rb/Ra)) x (130/162) x 2.1
Rb/Ra = 3.15
- - - - - (3)
In case of the current value sets 5uA, which flows to Ra and Rb
Ra+Rb = 1.4MΩ
By formula (3), (4)
Ra+3.15Ra= 1.4MΩ
- - - - - (4)
- - - - - (5)
Ra
= 337kΩ
Therefore,
Rb
= 1.4MΩ - 337kΩ
= 1063kΩ
- - - - - (6)
The adjustable range and the step voltage are calculated as follows in the formula (2).
- In case of setting 00H in the E.V.R. register,
VLCD =(1+(Rb/Ra)) x (EVR) x VREG
=(1+3.15) x [(99/162) x 2.1]
=5.33V
- In case of setting 3FH in the E.V.R. register,
VLCD =(1+(Rb/Ra)) x (EVR) x VREG
=(1+3.15) x [(162/162) x 2.1]
=8.72V
(min.) 00H
(max.) 3FH
VLCD Adjustable Range 5.33 ---------------------------------------- 8.72[V]
VLCD Step Voltage
54
[mV] *: In case of VDD=3V
Ver.2004-11-08
- 33 -
NJU6655
(3-3) LCD Driving Voltage Generation Circuits
The LCD driving bias voltage of V1,V2,V3,V4 are generated internally by dividing the VLCD (VLCD=VDD-V5) voltage
with the internal bleeder resistance. And it is supplied to the LCD driving circuits after the impedance conversion with
voltage follower circuit.
As shown in Fig 4, Five capacitors are required to connect to each LCD driving voltage terminal for voltage stabilizing.
And the value of capacitors C4, C5, C6, C7, and C8 are determined depending on the actual LCD panel display evaluation.
Using the internal Power Supply
Using the external Power Supply
VSS
VSS
VSS2
C1-
C1-
C1+
C1
C3
C1+
+
+
+
C3-
C2+
C3-
C2+
COUT
C2
C2-
C2-
*2
VOUT
VOUT
R3
NJU6655
NJU6655
V5
V5
(1)
*1
VR
VR
R2
R1
VDD
VDD
+
C4
V1
V2
V1
V2
+
+
+
+
C5
C6
C7
C8
External
Voltage
Generator
V3
V4
V3
V4
V5
V5
Fig.4 LCD Driving Voltage Generation Circuits
Reference set up value
LCD=VDD-V5=7.0 to 10.5V
V
*1 Short wiring or sealed wiring to the VR terminal is required due to
the high impedance of VR terminal.
*2 Following connection of VOUT is required when external power
supply using.
~1.0uF
~1.0uF
COUT
C1~C3, C8
C4~C7
R1
(1): When VSS > V5 --- VOUT=V5
0.1 ~ 0.47uF
225kΩ
(2): When VSS < V5 --- VOUT=VSS
R2
112kΩ
R3
1.063MΩ
Ver.2004-11-08
- 34 -
NJU6655
(4) MPU interface
(4-1) Interface type selection
NJU6655 interfaces with MPU by 8-bit bidirectional data bus (D7 to D0) or serial (SI:D7). The 8 bit parallel or serial
interface is determined by a condition of the P/S terminal connecting to "H" or "L" level as shown in Table 5. In case
of the serial interface, status and RAM data read out operation is impossible.
Table.5 Relation between P/S terminal and each I/O terminal
P/S
H
L
Type
Parallel
Serial
CS1b
CS1b
CS1b
A0
A0
A0
RDb
RDb
-
WRb
WRb
-
C86
C86
-
SI(D7) SCL(D6
)
D0 ~ D5
D0 ~ D5
Hi-Z
D7
D6
SCL
SI
“Hi-Z” : Hi-impedance “-“ : They should be fixed to “H” or “L”.
Parallel Interface
The NJU6655 interfaces to 68 or 80 type MPU directly when the parallel interface (P/S="H") is selected. 68 type MPU
or 80 is determined by the condition of C86 terminal connecting to "H" or "L" as shown in Table 6.
Table.6 Relation between C86 terminal and each I/O terminal
C86
H
L
Type
CS1b
CS1b
CS1b
A0
A0
A0
RDb
E
RDb
WRb
R/W
WRb
D0 ~ D7
D0 ~ D7
D0 ~ D7
68 type MPU
80 type MPU
(4-2) Discrimination of Data Bus Signal
The NJU6655 discriminates the mean of signal on the data bus by the combination of A0, E, R/W, and (RDb,WRb)
signals as shown in Table 7.
Table.7 Relation between A0 terminal and 68/80 type terminal
Common
68 type
80 type
Function
A0
H
H
L
R/W
H
RDb
WRb
H
L
H
L
Read Display Data
Write Display Data
Status Read
L
L
H
H
L
L
L
H
Write into the Register(Instruction)
Ver.2004-11-08
- 35 -
NJU6655
(4-3) Serial Interface (P/S="L")
Serial interface circuits consist of 8 bits shift register and 3 bits counter. SI and SCL input are activated when the chip
select terminal CS1b set to "L", CS2 set to "H"and P/S terminal set to "L". The 8 bits shift register and 3 bits counter are
reset to the initial condition when the chip is not selected.
The data input from SI terminal is MSB first like as the order of D7,D6,- - - - D0, and the data are entered into the shift
register synchronizing with the rise edge of the serial clock SCL. The data in the shift register are converted to parallel
data at the 8th serial clock rise edge input.
Discrimination of the display data or instruction of the serial input data is executed by the condition of A0 at the 8th
serial clock rise edge. A0="H" is display data and A0="L" is instruction. When RESb terminal becomes "L" or CS1b
terminal becomes "H" (CS2 terminal becomes "L") before 8th serial clock rise edge, NJU6655 recognizes them as a
instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit.
The time chart for the serial interface is shown in Fig. 5. To avoid the noise trouble, the short wiring is required for the
SCL input.
Note) The read out function, such as the status or RAM data read out, is not supported in this serial interface.
CS1
CS2
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
SCL
A0
1
2
3
4
5
6
7
8
9
10
Fig.5 Signal chart of serial interface
Ver.2004-11-08
- 36 -
NJU6655
(4-4) Access to the Display Data RAM and Internal Register
The NJU6655 is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus to adjust
the operation frequency between MPU and the Display Data RAM or Internal Register.
For example, when the MPU reads out the data from the Display Data RAM, the read out data in the data read cycle
(dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the next data read
cycle. When the MPU writes the data into the Display Data RAM, the data is held in the bus-holder, then it is written
into the Display Data RAM by the next data write cycle.
Therefore high speed data transmission between MPU and NJU6655 is available because of it is not limited by the tACC
and tDS as display data RAM access time and is limited by the system cycle time (R) or (W).
If the cycle time is not be kept in the MPU operation, NOP should be inserted to the system instead of the waiting
operation.
The read out operation does not read out the data in the pointed address just after the address set operation. And second
read out operation can read out the data correctly from the pointed address.
Therefore, one dummy read operation is required after address setting or write cycle as shown in Fig. 6.
The example of Read Modify Write operation is mentioned in (2-1) Instruction (l)The sequence of inverse display.
ꢁ
Write Operation
CPU
WRb
DATA
N+1
N+2
N+3
Internal
Timing
WRb
N+1
N+2
N+3
ꢁ
Read Operation
CPU
WRb
RDb
DATA
N
N
Dummy read
n
Data read n
n+1
Data read n+1
Address Set N
Internal
Timing
WRb
RDb
Column
address
N
N+1
N+2
n+1
n+2
Fig.6 Relation between display data write/read and internal timing
(4-5) Chip select
CS1b, CS2 are Chip Select terminals. In case of CS1b="L" and CS2=”H”, the interface with MPU is available. In case
of CS1b=”H” or CS2=”L”, the D0 to D7 are high impedance and A0, RDb, WRb, D7(SI) and D6(SCL) inputs are ignored.
If the serial interface is selected when CS1b=”H” or CS2=”L”, the shift register and the counter are reset. However, the
reset is always operated in any conditions of CS1b and CS2.
Ver.2004-11-08
- 37 -
NJU6655
ꢀ ABSOLUTE MAXIMUMN RATINGS
(Ta=25°C)
UNIT
V
PARAMETER
SYMBOL
RATINGS
Supply Voltage (1)
Supply Voltage (2)
VDD
Vss
-0.3 to +7.0
2
-7.0 to +0.3
-6.0 to +0.3
-4.5 to +0.3
-18.0 to +0.3
V
(
(
When using 3x voltage converter
When using 4x voltage converter
Supply Voltage (3)
Supply Voltage (4)
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
)
)
V
5
1
,VOUT
V
V
V
,V
2
,V3
,V
4
V5 to +0.3
VIN
VOUT
Topr
-0.3 to VDD + 0.3
-0.3 to VDD + 0.3
-30 to +80
V
V
°C
°C
(TCP) Tstg
(Chip)
-55 to +100
-55 to +125
VDD
VDD
VSS
V
SS2, V1 to V4
V5
Note 1) VSS2, V1 to V5, VOUT voltage values are specified as VDD = 0V.
Note 2) The relation of VDD>V1>V2>V3>V4>V5>VOUT ; VDD>VSS>VOUT must be maintained.
In case of inputting external LCD driving voltage, LCD drive voltage should start supplying to NJU6655 at the
mean time of turning on VDD power supply or after turned on VDD
.
In use of the voltage boost circuit, the condition that the supply voltage : 18V >VDD-VOUT is necessary.
Note 3) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI
within electrical characteristics is strongly recommended for normal operation. Use beyond the electric
characteristics conditions will cause malfunction and poor reliability.
Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for the voltage
converter.
Ver.2004-11-08
- 38 -
NJU6655
ꢀ DC Electrical Characteristics
(VDD=2.4 to 3.6V, VSS=0V, Ta= -30 to 80°C)
NOTE
SYMBOL
VDD
PARAMETER
CONDITIONS
Recommend→
Possible→
MIN
2.4
TYP
MAX UNIT
Power Supply (1)
-
3.6
5.5
V
V
V
V
5
2.4
-
Power Supply (2)
Power Supply (3)
VSS2 VDD common
-6.0
-18
0.4V5
V5
-
-2.4
-4.5
VDD
0.6V5
VDD
0.2VDD
VDD
0.2VDD
1.0
V5
VDD common
-
V1,V2 VDD common
-
V3,V4
VIHC1
VILC1
-
“H” Level Input Voltage
“L” Level Input Voltage
“H” Level Output Voltage
“L” Level Output Voltage
Leakage Current
0.8VDD
VSS
0.8VDD
VSS
-1.0
-3.0
-
-
V
V
-
-
VOHC1
VOLC1
ILI
IOH=-0.5mA
IOL= 0.5mA
All input terminals
D0 to D7 terminals, Hi-Z state
V
-
V
-
uA
uA
kΩ
kΩ
uA
uA
pF
kHz
ILO
-
3.0
Driver On-resistance
RON1 Ta=25°C V5=-14.0V
2.0
3.2
0.01
0.01
5
3.5
6
7
RON2
ISSQ
I5Q
V5=-8.0V
-
5.4
Stand-by Current
-
5
Output Leakage Current
Input Terminal Capacitance
V5=-18.0V (VDD common)
Ta=25°C
-
15
CIN
-
8
Oscillation Frequency
Display Clock Frequency
fOSC VDD=3V,Ta=25°C
17.0
20.8
24.6
fCL
External input
4.25
5.20
6.15
kHz
Input Voltage
VSS2
VDD common, 3-times boost
VDD common, 4-times boost
-6.0
-4.5
-
-
-2.4
-2.4
-
V
V
Output Voltage
On-resistance
VOUT VDD common
-18.0
-
RQUAD 4-times boost, C1-C3, COUT=1uF
VDD=3V, VSS=VSS2
2.5
3.5
kΩ
Adjustment Range
LCD Driving Voltage
Voltage Follower
Operating Voltage
Operating current
VOUT2 Voltage boost operation off
External power supply
-18.0
-18.0
-
-
-6.0
-4.5
5.0
10
8
9
V
V5
Voltage adjustment circuit off
External power supply
V
IDDQ1 Power save mode
(Sleep mode)
0.01
4
uA
IDDQ2 Power save mode
(Standby mode)
IDD1
IDD2
VDD=3V, V5=-11V
130
20
200
50
uA
All COM/SEG open, Without MPU
access, Checker flag display
Reference Voltage
Temperature
VREF Ta=25°C
TC VDD=3V
2.04
2.15
-0.05
2.26
V
%/°C
Coefficient
Note 5) Although the NJU6655 can operate in wide range of the operating voltage, it shall not be guaranteed in a
sudden voltage fluctuation during the access with MPU.
Note 6) RON is the resistance values in supplying 0.1V voltage-difference between power supply terminals
(V1,V2,V3,V4) and each output terminals (common / segment). This is specified within the range of Operating
Voltage (2).
Note 7) Apply to A0, D7 to D0, RDb, WRb, CS1b, CS2, RESb, C86 and P/S terminals.
Note 8) The voltage adjustment circuit controls V5 within the range of the voltage follower operating voltage.
Note 9) Each operating current shall be defined as being measured in the following condition.
Ver.2004-11-08
- 39 -
NJU6655
Power Control
Operating Condition
Voltage regulator
External
Symbol
Voltage Supply
(Input Terminal)
D2
D1
D0
Voltage converter
Voltage
followers
IDD1
IDD2
1
1
0
1
0
On
Off
On
Off
On
Off
Use(VSS2
)
0
Use(VOUT,V1 V5)
IDD 1,2 measurement circuits:
:IDD1
VDD
VR
V5
NJU6655
A
VSS C1+ C1- C2+ C2-
C3-
VOUT
+
+
+
+
V1 V2 V3 V4
:IDD2
V1 V2 V3 V4 V5
VR
VDD
NJU6655
A
VSS C1+ C1- C2+ C2-
C3-
VOUT
Ver.2004-11-08
- 40 -
NJU6655
ꢀ BUS TIMING CHARACTERISTICS
- Read and Write characteristics (80 type MPU)
CS2=H
A0
tCYC8
(1)CS1b
*
(2)WRb,RDb
tAW8
tAH8
tCCL
(1)WRb,RDb
*
tCCH
(2)CS1b
tDS8
tDH8
tr
D0 to D7
(Write)
tf
tACC8
tOH8
D0 to D7
(Read)
(VSS=0V, VDD=2.4 to 3.6V, Ta=-40 to 85°C)
SYMBOL CONDITION
PARAMETER
TERMINAL
MIN
0
MAX
UNIT
ns
ns
Address Hold Time
A0,CS1b
t
t
AH8
AW8
CYC8
CCLW
CCLR
CCHW
CCHR
DS8
DH8
ACC8
OH8
-
-
CS2
Address Set Up Time
System Cycle Time
0
t
800
120
240
120
120
80
-
ns
Control “L” Pulse Width (WRb)
Control “L” Pulse Width (RDb)
Control “H” Pulse Width (WRb)
Control “H” Pulse Width (RDb)
Data Set Up Time
t
-
ns
WRb
RDb
t
-
ns
t
-
-
ns
t
ns
t
-
ns
Data Hold Time
t
30
-
ns
D0 to D7
RDb Access Time
t
-
280
200
ns
CL=100pF
Output Disable Time
t
10
ns
CS1b,CS2,
WRb,RDb,
A0,D0 to D7
Input Signal Rising, Falling Edge
tr, tf
15
ns
Note 10) Each timing is specified based on 0.2xVDD and 0.8xVDD
.
* : (1) Accessed by WRb and RDb signal when CS1b="L". (2) Accessed by CS1b signal when WRb and RDb ="L".
Ver.2004-11-08
- 41 -
NJU6655
- Read and Write characteristics (68 type MPU)
tCYC6
CS2=H
tEWL
(1)E
*
*
(2)CS1b
tAW6
tEWH
(1)CS1b
(2)E
tr
tf
tAH6
A0,R/W
tDS6
tDH6
D0 to D7
(Write)
tOH6
tACC6
D0 to D7
(Read)
(VSS=0V, VDD=2.4 to 3.6V, Ta=-40 to 85°C)
SYMBOL CONDITION
PARAMETER
TERMINAL
MIN
0
MAX
UNIT
ns
Address Hold Time
A0,CS1b
t
t
AH6
AW6
CYC6
EWHR
EWHW
EWLR
-
CS2
Address Set Up Time
System Cycle Time
0
-
ns
t
800
240
120
120
120
80
-
ns
Enable “H” Pulse Width (Read)
Enable “H” Pulse Width (Write)
Enable “L” Pulse Width (Read)
Enable “L” Pulse Width (Write)
Data Set Up Time
t
-
ns
E(RDb)
t
-
ns
t
-
-
ns
t
EWLW
ns
t
DS6
DH6
ACC6
OH6
-
ns
Data Hold Time
t
30
-
ns
D0 to D7
E(RDb),
RDb Access Time
t
-
280
200
ns
CL=100pF
Output Disable Time
t
10
ns
Input Signal Rising, Falling Edge R/W(WRb),
A0,D0 to D7
tr, tf
15
ns
Note 11) Each timing is specified based on 0.2xVDD and 0.8xVDD
.
* : (1) Accessed by WRb and RDb signal when CS1b="L". (2) Accessed by CS1b signal when WRb and RDb ="L".
Ver.2004-11-08
- 42 -
NJU6655
- Write characteristics (Serial interface)
CS2=H
CS1b
tCSS
tCSH
tSAS
tSAH
A0
tSCYC
tSLW
tSHW
SCL
tSDS
tSDH
SI
tf
tr
(VSS=0V, VDD=2.4 to 3.6V, Ta=-40 to 85°C)
SYMBOL CONDITION
PARAMETER
Serial Clock Cycle
SCL “H” Pulse Width
SCL “L” Pulse Width
Address Set Up Time
Address Hold Time
Data Set Up Time
Data Hold Time
TERMINAL
SCL(D6)
MIN
400
150
150
250
250
150
150
250
250
MAX
UNIT
ns
t
SCYC
SHW
SLW
SAS
SAH
SDS
SDH
CSS
CSH
-
-
-
-
-
-
-
-
-
t
ns
t
ns
t
ns
A0
t
ns
t
ns
SI(D7)
t
t
ns
t
ns
CS1b-SCL Time
CS1b,CS2
ns
SCL(D6),A0,
CS1b,CS2,
SI(D7)
Input Signal Rising, Falling Edge
tr,, tf
15
ns
Note 12) Each timing is specified based on 0.2xVDD and 0.8xVDD
.
Ver.2004-11-08
- 43 -
NJU6655
- Display control timing characteristics
CL
(OUT)
tDFR
FR
tDSNC
SYNC
(VSS=0V, VDD=2.4 to 3.6V, Ta=-40 to 85°C)
TERMINAL SYMBOL CONDITION
PARAMETER
FR Delay Time
SYNC Delay Time
MIN
TYP
50
MAX
200
200
UNIT
ns
ns
FR
t
DFR
DSNC
CL=50pF
CL=50pF
-
-
SYNC
t
50
Note 13) Each timing is specified based on 0.2xVDD and 0.8xVDD
(The delay time is applied to the master operation only.)
.
- Reset input timing
tRW
RESb
tR
During reset
End of reset
Internal
(VSS=0V, VDD=2.4 to 3.6V, Ta=-40 to 85°C)
TERMINAL SYMBOL CONDITION
PARAMETER
Reset Time
Reset ”L” Level Pulse
Width
MIN
-
TYP
-
MAX
1.5
UNIT
us
t
R
RESb
t
RW
1.5
-
-
us
Note 14) Each timing is specified based on 0.2xVDD and 0.8xVDD
.
Ver.2004-11-08
- 44 -
NJU6655
ꢀ LCD DRIVING WAVEFORM
64 65
0
1
2
3
4
0
1
2
3
4
5
64 65
V
VSDSD
FR
VDD
V
COM
COM0
COM1
COM2
COM3
COM4
COM5
V1
V2
V3
COM
0
1
V4
5
COM6
7
V
VDD
V1
V2
V3
COM
COM
COM8
COM
COM9
COM10
COM11
COM12
COM13
COM145
V4
5
VDD
V
V1
V2
V3
2
S S S S
E
E
G
1
E E E
V4
5
0
2
3
4
VDD
V1
V2
V3
V
SEG
0
V4
5
VDD
V
V1
V2
V3
SEG
1
V4
5
V
V5
V4
V3
V2
VD1 D
-V
COM0-SEG0
-V1
-V2
-V3
-V4
5
V
V5
V4
V3
V2
VD1 D
-V
COM0-SEG1
-V1
-V2
-V3
-V4
5
Ver.2004-11-08
- 45 -
NJU6655
ꢀ APPLICATION CIRCUIT
(1) Microprocessor Interface Example
The NJU6655 interfaces to 80 type or 68 type MPU directly. And the serial interface also communicate with MPU.
* : C86 terminal must be fixed VDD or VSS.
ꢁ
80 Type MPU
VDD
VCC
A0
A0
C86
P/S
A1~A7
IORQ
CS1b
CS2
Decoder
NJU6655
C P U
D0~D7
RD
D0~D7
RDb
WR
WRb
RES
RESb
GND
VSS
RESET
ꢁ
68 Type MPU
VCC
VDD
A0
A0
C86
P/S
A1~A15
VMA
CS1b
CS2
Decoder
NJU6655
C P U
D0~D7
E
D0~D7
E
R/W
R/W
RES
RESb
GND
VSS
RESET
ꢁ
Serial Interface
VDD
VCC
A0
A0
C86
A1~A7
CS1b
CS2
VDD
OR GND
NJU6655
Decoder
C P U
SI
Port 1
Port 2
RES
SCL
P/S
RESb
VSS
GND
RESET
Ver.2004-11-08
- 46 -
NJU6655
(2) 65 x 320 dots Driving Application Circuits Example
(Common and Segment Drivers Extension by using two of NJU6655)
LCD Panel : 65 x 320
SEG
SEG
M/S
M/S
CL
COM
COM
CL
NJU6655
NJU6655
Slave
FR
FR
SYNC
DOFb
SYNC
DOFb
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2004-11-08
- 47 -
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