NJU6673CH [NJRC]
Liquid Crystal Driver, 125-Segment, CMOS, BUMP, DIE-212;
| 型号： | NJU6673CH |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Liquid Crystal Driver, 125-Segment, CMOS, BUMP, DIE-212 驱动 接口集成电路 |
| 文件： | 总38页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU6673
PRELIMINARY
25-common x 100-segment
BITMAP LCD DRIVER
ꢀ GENERAL DESCRIPTION
ꢀ PACKAGE OUTLINE
The NJU6673 is a 25-common x 100-segment bit map
LCD driver to display graphics or characters.
It contains 2,500 bits display data RAM, microprocessor
interface circuits, instruction decoder, and common and
segment drivers.
An image data from MPU through the serial or 8-bit
parallel interface are stored into the 2,500 bits internal
displayed on the LCD panel through the commons and
segments drivers.
NJU6673CL
The NJU6673 displays 25 x 100 dots graphics or
7-character 2-line by 12 x 13 dots character.
The NJU6673 contains a built-in OSC circuit for
reducing external components.
And it features an
electrical variable resistor. As result, it reduces the
operating current.
The operating voltage from 2.4V to 5.5V and low
operating current are suitable for small size battery
operation items.
ꢀ FEATURES
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
Direct Correspondence of Display Data RAM to LCD Pixel
Display Data RAM
LCD Drivers
2,500 bits
25-common and 100-segment
Selectable Duty and Bias Ratio ; 1/25 Duty 1/6 Bias or 1/15 Duty 1/5 Bias
Direct connection to 8-bit Microprocessor interface for both of 68 and 80 type MPU
Serial Interface (SI, SCL, A0, CS)
Useful instruction set
Display ON/OFF, Display Start Line Set, Page Address Set, Column Address Set, Status Read,
Write Display Data, Read Display Data, Normal or Inverse ON/OFF Set, Static Drive ON/Normal Display,
EVR Register Set, Read Modify Write, End, Reset, Internal Power Supply ON/OFF, Driver Output ON/OFF,
Power Save and ADC select.
ꢁ
Power Supply Circuits for LCD;
Available attractive operation for small LCD panel without external capacitors for bias stabilization.
Booster Circuits(3 times maximum, Voltage boosting polarity : Negative (VDD Common)),
Regulator, Voltage Follower(x 4)
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
Precision Electrical Variable Resistance (16 Steps)
Low Power Consumption
Operating Voltage
LCD Driving Voltage
Package Outline
2.4V to 5.5V
6.0V to 10V
COF / TCP / Bumped Chip
C-MOS Technology (Substrate : N)
01/04/19
- 1 -
NJU6673
ꢀ PAD LOCATION
ALI_A2
ALI_B1
DUMMY15
S0
DUMMY12
DUMMY11
V1
S1
V1
V1
V2
V2
V2
V3
V3
V3
V4
V4
V4
V5
V5
V5
VR
VR
VR
DUMMY10
VDD
VDD
VDD
VOUT
VOUT
VOUT
C2-
C2-
C2-
C2+
C2+
C2+
C1-
X
C1-
C1-
C1+
C1+
C1+
DUMMY9
DUMMY8
VSS
VSS
Y
VSS
DUMMY7
D7
D6
D5
D4
D3
D2
D1
D0
DUMMY6
DUMMY5
DUMMY4
DUMMY3
CDIR
DUTY
RD
WR
A0
CS
OSC
T1
T2
VSS
VSS
VSS
SEL68
P/S
VDD
VDD
VDD
S98
S99
RES
DUMMY2
DUMMY1
DUMMY16
ALI_B2
Chip Center
Chip Size
Chip Thickness
Bump Size
Pad Pitch
Bump Height
Bump Material
: X=0µm, Y=0µm
: X=7.54mm, Y=2.09mm
: 625µm±30µm
: 78.16µm x 48.10µm
: 70µm(Min.)
: 15µm(Typ.)
: Au
Voltage boosting polarity : Negative Voltage(VDD Common)
Substrate : N
- 2 -
NJU6673
ꢀ TERMINAL DESCRIPTION
Chip Size 7.54x2.09mm(Chip Center X=0µm, Y=0µm)
PAD No.
1
Terminal
DUMMY1
DUMMY2
RES
VDD
VDD
VDD
P/S
SEL68
VSS
VSS
VSS
T2
T1
OSC1
CS
A0
PAD No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Terminal
VOUT
VOUT
VOUT
X= µm
-3536
-3466
-3396
-3326
-3256
-3186
-3116
-3046
-2976
-2906
-2836
-2766
-2696
-2626
-2556
-2486
-2416
-2346
-2276
-2206
-2136
-2066
-1996
-1926
-1715
-1435
-1155
-875
-595
-315
-35
245
455
525
595
665
735
805
875
945
Y= µm
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
X= µm
1715
1786
1856
1926
1996
2066
2136
2206
2276
2346
2416
2486
2556
2626
2696
2766
2836
2906
2976
3046
3116
3186
3256
3326
3396
3466
3536
3616
3616
3616
3616
3616
3616
3616
3616
3616
3616
3616
3616
3616
3616
3616
3616
3616
3616
3616
3536
3466
3396
3326
Y= µm
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-891
-745
-675
-605
-535
-465
-395
-325
-255
-185
-115
-45
2
3
4
5
6
7
8
9
VDD
VDD
VDD
DUMMY10
VR
VR
VR
V5
V5
V5
V4
V4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V4
V3
WR
V3
V3
V2
V2
V2
V1
V1
V1
RD
DUTY
CDIR
DUMMY3
DUMMY4
DUMMY5
DUMMY6
D0
D1
D2
D3
D4
DUMMY11
DUMMY12
ALI_A2
DUMMY13
D5
DUMMY14
D6(SCL)
D7(SI)
DUMMY7
VSS
C0
C1
C2
C3
C4
C5
C6
C7
C8
VSS
VSS
DUMMY8
DUMMY9
C1+
C1+
C9
25
95
166
236
306
376
873
891
C1+
1015
1085
1155
1225
1295
1365
1435
1505
1575
1645
C10
C11
C12
C13
C14
ALI_B1
DUMMY15
S0
C1-
C1-
C1-
C2+
C2+
C2+
C2-
891
891
891
C2-
S1
S2
C2-
- 3 -
NJU6673
PAD No.
101
102
103
104
105
106
107
108
109
110
111
Terminal
PAD No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Terminal
S53
X= µm
3256
3186
3116
3046
2976
2906
2836
2766
2696
2626
2556
2486
2416
2346
2276
2206
2136
2066
1996
1926
1856
1786
1715
1645
1575
1505
1435
1365
1295
1225
1155
1085
1015
945
875
805
735
665
595
525
455
385
315
245
175
105
35
-35
-105
-175
Y= µm
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
X= µm
-245
-315
-385
-455
-525
-595
-665
-735
Y= µm
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
873
25
S3
S4
S5
S6
S7
S8
S9
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
-805
-875
-945
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
-1015
-1085
-1155
-1225
-1295
-1365
-1435
-1505
-1575
-1645
-1715
-1786
-1856
-1926
-1996
-2066
-2136
-2206
-2276
-2346
-2416
-2486
-2556
-2626
-2696
-2766
-2836
-2906
-2976
-3046
-3116
-3186
-3256
-3326
-3396
-3466
-3536
-3616
-3616
DUMMY16
ALI_B2
C24
- 4 -
NJU6673
PAD No.
201
202
203
204
205
206
207
208
209
210
211
Terminal
C23
X= µm
-3616
-3616
-3616
-3616
-3616
-3616
-3616
-3616
-3616
-3616
-3616
-3616
Y= µm
-45
C22
C21
C20
C19
C18
C17
C16
C15
-115
-185
-255
-325
-395
-465
-535
-605
-675
-745
-891
DUMMY17
DUMMY18
ALI_A1
212
• Alignment marks
110.34µm
70.38µm
70.38µm
70.38µm
ALI_B1, ALI_B2
ALI_A1, ALI_A2
Note) Alignment Marks are not contains window.
- 5 -
NJU6673
ꢀ BLOCK DIAGRAM
C0
C14 S0
S99 C24
C15
Vss
VDD
COM
Driver
SEG
Driver
COM
Driver
CDIR
V1 to V5
5
C1+
COM, SEG
Timing
Generator
Shift
Register
Shift
Register
C1-
C2+
C2-
Display Data Latch 100
T1
T2
Display Data RAM
100 x 25 bit
VR
Column Address Decoder
DUTY
OSC
Display
Timing
Generator
Column Address Counter 8bit
Column Address Register 8bit
OSC.
Multiplexer
Status
Instruction
Decoder
BF
Bus Holder
Internal Bus
Reset
RES
CPU interface
WR
SEL68
CS A0 RD
D0 to D5
P/S
D6(SCL)
D7(SI)
- 6 -
NJU6673
ꢀ TERMINAL DESCRIPTION
No.
Symbol
I/O
Function
1,
2,
21-
24,
33,
37,
38,
57,
76,
77,
79,
80,
97,
198,
210,
211
4,5,6
9-11,
34-36
73-75
70-72
67-69
64-66
61-63
DUMMY1
DUMMY2
DUMMY3 -
DUMMY6
DUMMY7
DUMMY8
DUMMY9
DUMMY10
DUMMY11
DUMMY12
DUMMY13
DUMMY14
DUMMY15
DUMMY16
DUMMY17
DUMMY18
VDD
Dummy Terminal.
These are open terminals electrically.
Power Power supply terminal. (+2.4 to +5.5V)
GND Ground terminal. (0V)
VSS
V1
V2
V3
V4
V5
LCD Driving Voltage Supplying Terminals.
In case of external power supply operation without internal power supply
operation, each level of LCD driving voltage is supplied from outside
fitting with following relation.
VDD≥V1≥V2≥V3≥V4≥V5≥VOUT
In case of internal power supply, LCD driving voltages V1 to V4
depending on the bias selection are supplied as shown in follows;
Power
Duty
Bias
V1
V2
V3
V4
1/15 Duty 1/5 Bias V5+4/5 VLCD V5+3/5 VLCD V5+2/5 VLCD V5+1/5 VLCD
1/25 Duty 1/6 Bias V5+5/6 VLCD V5+4/6 VLCD V5+2/6 VLCD V5+1/6 VLCD
VLCD=VDD-V5
39-41
42-44
45-47
48-50
C1+
C1-
C2+
C2-
O
Condenser connecting terminals for internal Voltage Booster.
Boosting time is selected by each connected condenser.
In case of 3-time boost operation, connect the condenser between C1+
and C1-, C2+ and C2-.
In case of 2-time boost operation, connect the condenser between C2+
and C2-, connect C2+ to C1+, and C1- should be open.
Boosted voltage output terminal. Connects the capacitor between VOUT
terminal and VSS.
VLCD voltage adjustment terminal. The gain of VLCD setup circuit for V5
level is adjusted by external resistor.
51-53
58-60
VOUT
VR
O
I
13
12
T1,
T2
I
LCD bias voltage control terminals.
Voltage
T1
T2
Voltage adjustor
V/F circuit
booster circuit
L
H
H
H/L
L
H
Available
Not available
Not available
Available
Available
Not available
Available
Available
Available
25
26
27
28
29
30
31
32
D0
D1
D2
D3
D4
I/O
Data input / output terminals.
In parallel interface Mode (P/S=”H”)
I/O terminals of 8-bit bus.
In Serial interface Mode(P/S=”L”)
D7:Input terminal of serial data (SI).
D6:Input terminal of serial data clock (SCL).
D5 to D0 terminals are High impedance.
D5
D6(SCL)
D7(SI)
When CS=”H” , D0 to D7 terminals are high-impedance.
- 7 -
NJU6673
No.
16
Symbol
A0
I/O
I
Function
Data discremination signal input terminal. The signal from MPU
discreminates transmitted data between Display data and Instruction.
A0
H
L
Discremination
Display Data
Instruction
3
I
I
Reset terminal.
Reset operation is executing during “L” state of RES.
RES
CS
15
Chip select signal input terminal.
Data Input/Output are available during CS ="L".
18
I
RD (E)
RD(80 type) or E(68 type) signal input terminal.
<In 80 type MPU mode>(SEL68=”L”)
RD signal from 80 type MPU input terminal. Active”L”.
D0 to D7 terminals are output during ”L” level.
<In 68 type MPU mode>(SEL68=”H”)
Enable signal from 68 type MPU input terminal. Active "H"
WR (80 type) or R/W(68 type) signal input terminal.
<In 80 Type MPU mode>(SEL68=”L”)
17
I
WR(R/W)
WR signal from 80 type MPU input . Active "L".
The data transmitted during WR=”L” are fetched at the rising edge of
WR.
<In 68 Type MPU mode>
R/w signal from 68 type MPU input terminal.
R/W
H
L
State
Read
Write
8
7
SEL68
P/S
I
I
MPU interface type selection terminal.
This terminal must connect to VDD or VSS
SEL68
State
H
L
68 type
80 type
Parallel or Serial interface selection signal input terminal.
Chip Data
Select /Command
P/S Inter face
Data Read/Write Serial CLK
“H”
“L”
A0
A0
D0-D7
SI(D7)
-
Parallel
Serial
CS
CS
RD, WR
-
SCL(D6)
In case of the serial interface (P/S="L")
RAM data and status read operation do not work in mode of the serial
interface. RD and WR terminals must fix to "H" or "L".
D0 to D5 terminals are high impedance.
14
OSC
O
Maker Testing Clock output terminal.
The terminal is recommended to open.
- 8 -
NJU6673
No.
81-95
Symbol
C0-C14
I/O
O
Function
LCD driving signal output terminals.
ꢁ
ꢁ
Common output terminals
Segment output terminals
• Common Output Terminal
:C0 to C24
:S0 to S99
Following output voltages is selected by the combination of
alternating(FR) signal and Common scanning data.
Scan data
FR
H
L
H
L
Output Voltage
98-197
S0-S99
O
O
V5
VDD
V1
H
L
V4
• Segment output terminal
Following output voltages is selected by the combination of
alternating(FR) signal and display data in the DD RAM.
200-209
C24-C15
Output Voltage
RAM data
FR
Normal
VDD
V5
Reverse
V2
H
L
H
L
H
L
V3
V2
V3
VDD
V5
19
20
DUTY
CDIR
I
I
Duty and Bias selection terminal.
DUTY
H
L
Duty
1/15
1/25
Bias
1/5
1/6
Common Driver Assignment selection terminal.
CDIR
Common Output terminals
H
L
Reverse (C24→C0)
Normal (C0→C24)
- 9 -
NJU6673
ꢀ FUNCTIONAL DESCRIPTION
(1) Description for each blocks
(1-1) Busy Flag (BF)
The Busy Flag (BF) is set to logical “1” in busy of internal execution by an instruction, and any
instruction excepting for the “Status Read” is disable at this time. Busy Flag is outputted through D7
terminal by “Status Read” instruction. Although another instructions should be inputted after check of
Busy Flag, no need to check Busy flag if the system cycle time (tCYC) as shown in ꢀ AC
CHARACTERISTICS is secured completely.
(1-2) Display Start Line Register
The Display Start Line Register is a register to set a display data RAM address corresponding to the
COM0 display line (the top line normally) for the vertical scroll on the LCD, Page address change and so
forth. The Display Start Line Address set instruction sets the 8-bit display start address into this register.
(1-3) Line Counter
Line Counter is reset when the internal FR signal is switched and outputs the line address of the display
data RAM by count up operation synchronizing with common cycle of NJU6673.
(1-4) Column Address Counter
Column Address Counter is the 8-bit preset-able counter to point the column address of the display data
RAM (DD RAM) as shown in Fig. 1. The counter is incremented automatically after the display data
read/write instructions execution. When the Column address counter reaches to the maximum existing
address by the increment operations, the count up operation (increment) is frozen. However, when new
address is set to the column address counter again, it restarts the count up operation from a set address.
The operation of Column Address Counter is independent against Page Address Register.
By the address inverse instruction (ADC select) as shown in Fig. 1, Column Address Decoder reverses
the correspondence between Column address and Segment output of display data RAM.
(1-5) Page Address Register
Page Address Register assigns the page address of the display data RAM as shown in Fig. 1. In case
of accessing from the MPU with changing the page address, Page Address Set instruction is required.
(1-6) Display Data RAM
The Display data RAM (DD RAM) is the bit map RAM consisting of 2,500 bits to store the display data
corresponding to the LCD pixel on LCD panel.
In Normal Display : “1” Turn-On Display, “0”=Turn-Off Display
In Reveres Display: “1” Turn-Off Display, “0”=Turn-On Display
DD RAM output 100 bits parallel data addressed by line address counter then the data latched in the
display data latch. Asynchronous data access to the DD RAM is available due to the access to the DD
RAM from the MPU and latch to the display data latch operation are done independently.
(1-7) Common Driver Assignment
The scanning order can be assigned by set Common Driver Assignment selection terminal as shown on
Table 1.
Table 1 Common Driver Order Assignment
COM Outputs Terminals
PAD No. 81
Pin name C0
95
C14
200
C24
209
C15
COM Driver Assignment
selection terminal
“L”
“H”
COM0
COM24
COM14
COM10
COM24
COM0
COM10
COM14
The duty ratio setting and output assignment register are so controlled to operate independently that
duty ratio setting required to corresponding duty ratio for output assignment.
- 10 -
NJU6673
Page
Address
Line
Address
COM output
example 1
Data
Display Pattern
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D0=0
D0=1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
C17
C18
C19
C20
C21
C22
C23
C24
C0
C1
C2
C3
C4
D1, D0
(0, 0)
Page 0
COM
output
example 2
C0
C1
C2
C3
C4
C5
C6
C7
C8
D1, D0
(0, 1)
Page 1
C5
C6
C7
C8
C9
C9
C10
C11
C12
C13
C14
C15
C16
C10
C11
C12
C13
C14
D1, D0
(1, 0)
Page 2
Page 3
D1, D0(1, 1)
Column
Address(ADC)
00 01 02 03 04 05
63 62 61 60 5F 5E
62 63
01 00
Segment output
S0 S1 S2 S3 S4 S5
S98 S99
COM output example1 : 1/25Duty, set Display Start Line 08H
COM output example2 : 1/15Duty, set Display Start Line 08H
Fig.1 Correspondence with Display Data RAM Address
- 11 -
NJU6673
(1-8) Reset Circuit
Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level.
• Initialization
1. Display Off
2. Normal Display (Non-inverse display)
3. ADC Select : Normal (ADC Instruction D0=”0”)
4. Read Modify Write Mode Off
5. Voltage Booster off, Voltage Regulator off, Voltage follower off
6. Clear the serial interface register
7. Driver Output Off
8. Set the Display Start Line Register to 00H
9. Set the Column Address Counter to 00H
10. Set the Page Address Register to page “0”
11. Set the EVR register to 00H
The RES terminal connects to the reset terminal of the MPU synchronization with the MPU initialization
as shown in “the MPU interface” in the Application Circuit section. The “L” level input signal as reset
signal must keep the period over than 10µs as shown in DC Characteristics. The NJU6673 takes 1µs for
the reset operation after the rising edge of the RES signal.
The reset operation by RES =”L” initializes each resister setting as above reset status, but the internal
oscillation circuit and output terminals (D0 to D7) are not affected.
To avoid the lock-up, the reset operation by the RES terminal must be required every time when power
terns on. The reset operation by the reset instruction, function 8 to 11 operations mentioned above is
performed.
The RES terminal must be keep “L” level when the power terns on in not use of the built-in LCD power
supply circuit for no affect to the internal execution.
(1-9) LCD Driving
(a)LCD Driving Circuits
LCD driver is 125 sets of multiplexer consisting of 100 segments and 25 commons drivers to output
LCD driving voltage. The common driver outputs the common scan signals formed with the shift register.
The segment driver outputs the segment driving signal determined by a combination of display data in the
DD RAM, common timing, FR signal, and alternating signal for LCD. The output wave forms of
segment/common are shown in ꢀ LCD DRIVING WAVEFORM.
(b)Display Data Latch Circuits
Display Data Latch Circuit latches the 100 bits display data outputted from the DD RAM addressed by
the Line address counter to LCD driver at every common signal cycle temporarily. The original data in
the DD RAM is not changed because of the Normal/Reverse display, Display On/Off, Static drive On/Off
instruction processes only stored data in this Display Data Latch Circuit.
(c) Line Counter and Latch signal of Latch Circuits
The count clock to Line Counter and the latch clock to Display Data Latch Circuit are formed using the
internal display clock (CL). The display data of 100 bits from Display Data RAM pointed by the line
address synchronizing with the internal display clock are latched into the Display Data Latch Circuit and
are outputted to LCD driving circuits.
The display data read out operation from DD RAM to the LCD Driver Circuit is completely independent
operation with an access to the display data RAM from MPU.
- 12 -
NJU6673
(d)Display Timing Generaton Circuit
The display timing generation circuit generates the internal timing of the display system by the master
clock and the internal FR signal. As for it, the internal FR signal and the LCD alternating signal generate
the wave form of 2-frame alternating drive wave form or the n-line inverse drive method for the LCD
Driving circuit.
(e)Common Timing Generation
The Common Timing Generator generates the common timing signal from the display clock (CL).
24 25 1
2
3
4
5 6 7 8
23 24 25 1
2
3
4
5 6
7
CL
FR
VDD
V1
C0
C1
V4
V5
VDD
V1
V4
V5
RAM
DATA
VDD
V2
Sn
V3
V5
Fig. .2
(f) Oscillation Circuit
The Oscillation Circuit is a low power type CR oscillator using an internal resistor and capacitor. The
oscillator output is using for the display timing clock and for the voltage booster circuit. And the display
clock(CL) is generated from this oscillator output frequency by dividing.
Table 2 The relation between duty and divide
Duty
1/15
1/10
1/25
1/6
Divide
- 13 -
NJU6673
(g)Power Supply Circuit
The internal power supply circuit generates the voltage for driving LCD. It consists of voltage booster
circuits (3-Time maximum), voltage regulator circuits, and voltage followers.
The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off
Instruction. When the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits,
regulator circuits, voltage follower circuits are turned off. In this time, the bias voltage of V1, V2, V3, V4, V5
and VOUT for the LCD should be supplied from outside, terminals C1+, C1-, C2+, C2- and VR should be
open. The status of internal power supply is selected by T1 and T2 terminals. Furthermore the external
power supply operates with some of internal power supply function.
Table3 The Relation Between Power Supply Circuit And T1, T2 Terminal
Voltage
Booster
ON
OFF
OFF
Ext.Power
Supply
-
VOUT
V5, VOUT
C1+, C1-,
C2+, C2-
T1
T2
Voltage Adj. Buffer(V/F)
VR Term.
Open
L
H
H
L/H
L
H
ON
ON
ON
ON
ON
Open
Open
OFF
When (T1, T2)=(H, L), C1+, C1-, C2+, C2- terminals for voltage booster circuits are open because the
voltage booster circuits doesn't operate. Therefore LCD driving voltage to the VOUT terminal should be
supplied from outside.
When (T1, T2)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage
booster circuits and Voltage adjust circuits do not operate.
The internal power supply Circuits is designed specially for a small-size LCD like as normal cellular
phone size LCD panel. When NJU6673 apply to the large size LCD panel application (large capacitive
load), external power supply is required to keep good display condition.
The external capacitors to V1 to V5 for Bias voltage stabilization may be removed in use of small size
LCD panel. The equivalent load of LCD panel may be changed depending on display patterns. Therefore,
it require display quality check on various display patterns actually without external capacitors. If the
display quality is not so good, external capacitors should connects as show in (3-4)LCD Driving Voltage
Generation Circuits -Fig. 4. (If no need external capacitors as result of experiment, the application
patterns (wiring) should be prepared for recovery.)
- 14 -
NJU6673
! Power Supply applications
(1) Internal power supply example.
All of the Internal Booster, Voltage Regulator,
Voltage Follower using.
(2) Only VOUT Supply from outside Example.
Internal Voltage Regulator,
Voltage Follower using
Internal power supply ON (instruction)
(T1, T2)=(L, L)
Internal power supply ON (Instruction)
(T1, T2)=(H, L)
T1
T2
VDD
VDD
T1
T2
+
+
+
+
+
V1
C1+
C1-
+
+
+
+
+
+
+
V1
V2
V3
V4
V5
V2
V3
V4
V5
C2+
C2-
+
VOUT
VSS
VOUT
VSS
VDD
V5
VR
VDD
V5
VR
(3) VOUT and V5 supply from outside Example.
Internal Voltage Follower using.
Internal power supply (Instruction)
(T1, T2)=(H, H)
(4) External Power Supply Example.
All of V1 to V5 and VOUT supply from outside
Internal power supply (Instruction)
(T1, T2)=(H, H)
T1
T2
VDD
VDD
T1
T2
+
+
+
+
V1
V2
V1
V1
V3
V3
V4
V5
V3
V5
VOUT
VSS
VOUT
VSS
: These switches should be open during the power save mode.
- 15 -
NJU6673
(2) Instruction
The NJU6673 distinguishes the signal on the data bus D0 to D7 as an Instruction by combination of A0 , RD
and WR(R/W). The decode of the instruction and execution performs with only high speed Internal timing
without relation to the external clock. Therefore no busy flag check required normally. In case of serial
interface, the data input as MSB(D7) first serially. The Table. 4 shows the instruction codes of the NJU6673.
Table 4 Instruction Code
(*:Don't Care)
Code
Instruction
Description
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
LCD Display ON/OFF
D0=0:OFF D0=1:ON
Determine the Display Line of
RAM to COM 0
Set the page of DD RAM to the
Page Address Register
Set the Higher order 3 bits
Column Address to the Reg.
Set the Lower order 4 bits
Column Address to the Reg.
Read out the internal Status
Display ON/OFF
Display Start
(a)
(b)
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
1
*
0
1
1
1
0/1
Start address
Line Set
Page
(c) Page Address Set
1
0
0
1
1
0
*
*
Address
Column Address Set
High Order 3bits
Column Address Set
Lower Order 4bits
High Order
Column
0
(d)
Lower Order
Column Add
(e) Status Read
Status
0
0
0
0
Write the data into the Display
Data RAM
Read the data from the Display
Data RAM
Inverse the ON and OFF
Display
(f) Write Display Data
(g) Read Display Data
Write Data
Read Data
Normal or Inverse of
ON/OFF Set
Static Drive ON
(h)
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0/1
0/1
Whole Display Turns ON
D0=0: Normal D0=1: Whole Disp. ON
(i)
/Normal Display
Set the V5 output level to the
EVR register
(j) EVR Register Set
0
Setting Data
Increment the Column Address
Register when writing but
no-change when reading
Release from the Read Modify
write Mode
(k) Read Modify Write
0
1
0
1
1
1
0
0
0
0
0
(l) End
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
1
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
1
0
1
1
0
1
0
Initialize the Internal Circuits
(m) Reset
0
Internal Power
(n)
0:Int. Power Supply OFF
1:Int. Power Supply ON
D0=0: LCD Driver Outputs OFF
D0=1: LCD Driver Outputs ON
0/1
0/1
Supply ON/OFF
Driver Outputs
ON/OFF
(o)
Set the Power Save Mode
(LCD Display OFF + Whole
Display Turns ON)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
1
0
0
1
Power Save
(q)
(Complex command)
Set the DD RAM vs Segment
D0=0 :Normal D0= 1:Inverse
(p) ADC Select
0
1
0
1
0
1
0
0
0
0
0/1
- 16 -
NJU6673
(2-1) Explanation of Instruction Code
(a)Display On/Off
It executes the On/Off control of the whole display without relation to the DD RAM or any internal
conditions.
A0
0
RD
1
WR
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
D
D
0: Display Off
1: Display On
(b)Display Start Line
It sets the DD RAM line address corresponding to the COM0 terminal (normally assigned to the top
display line). In this instruction execution, the display area is automatically set by the lines that correspond
to the display duty ratio to the upward direction of the line address. Changing the line address by this
instruction performs smooth scrolling to a vertical direction. In this time, the DD RAM data are unchanged.
A0
0
RD
1
WR
0
D7
0
D6
1
D5
*
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
A4
0
0
A3
0
0
A2
0
0
:
A1
0
0
A0
0
1
Line Address(HEX)
00
01
:
:
:
1
1
0
0
0
18
(c) Page Address Set
When MPU accesses to the DD RAM, a page address is set by page Address Set instruction before
writing the data (Note:the change of page address is not affected to the display).
A0
0
RD
1
WR
0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
A1
D0
A0
*:Don’t Care
A1
0
0
1
1
A0
0
1
0
1
Page
0
1
2
3
- 17 -
NJU6673
(d)Column Address
When MPU accesses to the DD RAM, row address set by Page Address Set instruction is required with
the column address before writing the data. The column address set requires twice address set which are
higher order 3 bits address set and lower order 4 bits. When the MPU accesses to the DDRAM
continuously, the column address increments automatically from the set address after each data access.
Therefore, the MPU can transmit only the Data continuously without setting the column address at every
transmission time. The increment of the column address is stopped at the maximum column address plus
1 limited by each display mode. When the column address count up is stopped, the row address is not
changed.
A0
0
RD
1
WR
0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
A6
D1
A5
D0
A4
Higher Order
Lower Order
0
1
0
0
0
0
0
A3
A2
A1
A0
A6
0
0
A5
0
0
A4
0
0
A 3
0
0
:
A2
0
0
A1
0
0
A0
0
1
Column Address (HEX)
00
01
:
:
:
1
1
0
0
0
1
1
63
(e)Status Read
This instruction reads out the internal status of "BUSY", "ADC", "ON/OFF" and "RESET" as follows.
A0
0
RD
0
WR
1
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
BUSY ADC ON/OFF RESET
BUSY:BUSY=1 indicate the operating or the Reset cycle.
The instruction can be input after the BUSY status change to "0".
ADC : Indicate the output correspondence of column (segment) address and segment driver.
0: Counterclockwise Output
1: Clockwise Output
(Inverse)
(Normal)
Note) The data “0=Inverse” and “1=Normal” of ADC status is inverted with the ADC select
Instruction of "1=Inverse" and "0=Normal".
ON/OFF: Indicate the whole display On/Off status.
0: Whole Display "On”
1: Whole Display "Off"
Note) The data "0=On" and "1=Off" of Display On/Off status is inverted with the Display
On/Off instruction data of "1=On" and "0=Off".
RESET :Indicate the initializing by RES signal or reset instruction.
0: Not Reset status
1: In the Reset status
(f) Write Display Data
It writes the data on the data bus into the DD RAM column address increments automatically after data
writing, therefore, the MPU can write the data into the DD RAM continuosly without the address setting at
every writing time once the starting address is set.
A0
1
RD
1
WR
0
D7
D6
D5
D4
D3
D2
D1
D0
Write Data
- 18 -
NJU6673
(g)Read Display Data
This instruction reads out the 8-bit data from DD RAM addressed by the column and the page
address.The column address automatically increments after the 8-bit read out, therefore, the MPU can
read the data from the DD RAM continuously without the address setting at every reading time once the
starting address is set. Note that the dummy read is required just after setting the column address
(see”(4-4)Access to the DD RAM and the Internal Register”). In the serial interface mode, the display data
is unable to read out.
A0
1
RD
0
WR
1
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
(h)Normal or Inverse On/Off Set
It changes the display condition of normal or reverse for entire display area. The execution of this
instruction does not change the display data in the DD RAM.
A0
0
RD
1
WR
0
D7
1
D6
0
D5
1
D4
0
D3
0
D2
1
D1
1
D0
D
D
0: Normal
1: Inverse
RAM data “1” correspond to “On”
RAM data “0” correspond to “On”
(i) Static Drive
This instruction turns all the pixels ON regardless the data stored in the DD RAM. In this time, the data
in DD RAM are remained and unchanged. This instruction is executed prior to the “Normal or Inverse
On/Off Set” instruction.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
0
D
D
0: Normal Display
1: Whole Display turns On
(j) EVR Register Set
It controls the voltage regulator circuit of the internal LCD power supply to adjust the LCD display
contrast by changing the LCD driving voltage “V5”. By data setting into the EVR register, the LCD driving
voltage “V5” selects out of 16 steps of regulated voltage. The voltage adjustable range of “D5” is fixed by
the external resistors. For details, refer the section”(3-2) Voltage Adjust Circuits”.
A0
0
RD
1
WR
0
D7
1
D6
0
D5
0
D4
0
D3
A3
D2
A2
D1
A1
D0
A0
A3
0
A2
0
A1
0
A0
0
VLCD
Low
:
:
:
:
1
1
1
1
High
VLCD=VDD-V5
When EVR doesn't use, set the EVR register to (0,0,0,0).
- 19 -
NJU6673
(k) Read Modify Write
This instruction sets the Read Modify Write controlling the page address increment. In this mode, the
Column Address only increments when execute the display data “Write instruction; but no change when
the display data “Read “ Instruction. This status is continued until the End instruction execution. When the
End instruction is executed, the Column Address goes back to the start address before the execution of
this “Read Modify Write” instruction. This function reduces the load of MPU for repeating display data
change of the fixed area (ex. cursor blink)
A0
0
RD
1
WR
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
Note) In this “Read Modify Write” mode, out of display data “Read”/”Write”, any instructions except “Column
Address Set” can be executed.
ꢁ
The Example of Read Modify Write Sequence
Page Address Set
Set to the Start
Address of Curs or
Display
Column Address Set
Start to the
Read Modify Write
Read Modify Write
Dummy Read
The data is ignored
Column Counter doesn’t increase
Data Read
Column Counter
doesn’t increase
Data Write
Data inverse by MPU
Column Counter increase
Column Counter doesn’t increase
Dummy Read
Data Read
Column Counter doesn’t increase
Column Counter increase
Data Write
Column Counter doesn’t increase
Dummy Read
Data Read
Column Counter doesn’t increase
Column Counter increase
Data Write
End
End the Read Modify Write
No
Finish?
Yes
- 20 -
NJU6673
(l) End
This instruction releases the Read Modify Write mode and the column address back to the address
where the read modify write mode setting.
A0
0
RD
1
WR
0
D7
1
D6
1
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
Return
Column Address
(m) Reset
N
N+1
N+2
N+3
N+m
N
Read Modify write set
End
This instruction executes the following initialization. The reset by the reset signal input to the RES
terminal (hardware reset) is required when power turns on. This reset instruction does not use instead of
this hardware reset when power turns on.
Initialization
1) Set the Display Start Line Register to 00H.
2) Set the Column Address Counter to 00H.
3) Set the page Page Address Register to page “0”.
4) Set the EVR Register to 0H.
The DD RAM is not affected of this initialization.
A0
0
RD
1
WR
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
0
(n)Internal Power Supply ON/OFF
This instruction control ON and OFF for the internal Voltage Converter, Voltage Regulator and Voltage
Follower circuits. For the Booster circuits operation, the oscillation circuits must be in operation.
A0
0
RD
1
WR
0
D7
0
D6
0
D5
1
D4
0
D3
0
D2
1
D1
0
D0
D
D
0: Internal Power Supply Off
1: Internal Power Supply On
The internal Power Supply must be Off when external power supply using.
*1 The set up period of internal power supply On depends on the step up capacitors, voltage stabilizer
capacitors, VDD and VLCD. Therefore it requires the actual evaluation using the LCD module to get the
correct time.(Refer to the (3-4) Fig.4)
- 21 -
NJU6673
(o)Driver Outputs ON/OFF
This instruction controlls ON/OFF of the LCD Driver Outputs.
A0
0
RD
1
WR
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
0
D1
1
D0
D
D
0: LCD driving waveform output Off
1: LCD driving waveform output On
The NJU6673 implements low power LCD driving voltage generator circuit and requires the following
Power supply ON/OFF sequence.
ꢁ
LCD Driving power supply ON/OFF sequences
The sequences below are required when the power supply turns ON/OFF.For the power supply turning on
operation after the power-save mode, refer the “power save release sequence” mentioned after.
Turn ON sequence
Turn OFF sequence
Display OFF
E.V.R. Register set
Whole Display ON
Internal Power Supply ON
or
External Power supply ON
Internal Power Supply OFF
or
External Power supply OFF
(Wait Time) *1
Driving Outputs ON
NJU6673 Power OFF
*1 : The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5
External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time
correctly, test by using the actual LCD module.
- 22 -
NJU6673
(p)Power Save(complex command)
When Static Drive ON at the Display OFF status(inverse order also same), the internal circuits goes to
the Power Save Mode and the operating current is dramatically reduced, almost same as the standby
current. The internal status in the Power Save Mode is shown as follows;
1: The Oscillation Circuits and the Internal Power Supply Circuits stop the operation.
2: LCD driving is stopped. Segment and Common drivers output VDD level voltage.
3: The display data and the internal operating condition are remained and kept as just before enter the
Power Save Mode.
4: All the LCD driving bias voltage(V1 to V5) is fixed to the VDD level.
The power save and its release perform according to the following sequences.
! Power Save Sequence
! Power Save Release Sequence
(Static Drive ON)
Display OFF
Normal Display
Display ON
Static Drive ON
Driver Outputs OFF
(Wait Time)
Driver Outputs ON
The NJU6673 constantly spends the current without the execution of the Driver Outputs OFF instruction.
The LCD drive waveform is not output until the Driver Outputs ON instruction is executed.
*1 : In the Power Save sequence, the Power Save Mode starts after the Static Drive ON bcommand is
executed.
*2 : In the Power Save Release sequence, the Power Save Mode releases just after the Static Drive OFF
instruction execution. The Display ON instruction is allowed to execute at any time after the Static Drive
OFF instruction is completed.
*3 : The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5 ,
External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time
correctry, test by using the actual LCD module.
*4 : LCD driving waveform is output after the exection of the Driver Outputs ON instruction execution.
*5 : In case of the external power supply operation, the external power supply should be turned off before
the Power Save Mode and connected to the VDD for fixing the voltage of VOUT terminal. In this time, VOUT
terminal also should be made codition like as disconection to the lowest voltage of the system.
(q)ADC Select
This instruction determines the correspondence of Column in the DD RAM with the Segment Driver
Outputs. Segment Driver Outout order is inverse when this instruction executes, therefore, the placement
the NJU6673 against the LCD panel becomes easy.
A0
0
RD
1
WR
0
D7
1
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0/1
D
0: Clokwise Output(Normal)
1: Counterclockwise Output(Inverse)
- 23 -
NJU6673
(3) Internal Power Supply
(3-1) Voltage tripler
The 3-time voltage booster circuit outputs the negative Voltage(VDD Common) boosted 3 times of
VDD-VSS from the VOUT terminal with connecting the five capacitors between C1+ and C1-, C2+ and C2-, and
SS and VOUT. In case of the 2-time voltage booster operation, connect the two capacitor between C2+ and
V
C2-, VSS and VOUT, then connect the C1+ and C2+ terminals. Voltage Booster circuits requires the clock
signals from internal oscillation circuit or the external clock signal. therefore, the internal oscillation
circuits or the external clock supplier must be operating when the voltage booster is in operation.
The boosted voltage of VDD-VOUT must be 10V or less.
The boost voltage and the capacitor connection are shown below.
ꢁ
The boosted voltage and VDD, VSS
VDD=+3V
VSS=0V
V
OUT=-3V
OUT=-6V
V
2 time voltage
3 time voltage
(3-2) Voltage Adjust Circuits
The boosted voltage of VOUT outputs V5 for LCD driving through the voltage adjust circuits. The output
voltage of V5 is adjusted by Ra and Rb within the range of |V5| < |VOUT|.
The output is calculated by the following formula(1).
VLCD = VDD-V5 = (1+Rb/Ra)VREG
(1)
The VREG voltage is a reference voltage generated by the built-in bleeder registance. VREG is adjustable
by EVR functions (see section 3-3).
For minor adjustment of V5, it is recommended that the Ra and Rb is composed of R2 as variable
resistor and R1 and R3 as fixed resistors, constant should be connected to VDD terminal,VR and V5 ,as
shown below.
VDD
VREG
Ra
R1
+
VR
V5
-
R2
VOUT
R3
Rb
Fig-3 Voltage Adjust Circuit
<Design example for R1, R2 and R3 / Reference>
-
R1+R2+R3=3.1MΩ
(Determined by the current flown between VDD- V5)
-
Variable voltage range by the R2. -3.2V to -6.3V (VLCD= VDD- V5=6.2V to 9.3V)
(Determined by the LCD electrical characteristics)
-
-
VREG=3V(In case of EVR=(F)H)
- R1, R2 and R3 are calculated by above conditions and the formula of (1) to mentioned below;
R1=1.0MΩ,
R2=0.5MΩ,
R3=1.6MΩ
Note) V5 voltage is generated referencing with VREG voltage beased on the supply voltage (VDD and VSS) as
shown in above figure. Therefore, VLCD (VDD-V5) is affected including the gain (Rb/Ra) by the fluctuation
of VREG voltage based on the supply voltage. The power supply voltage should be stabilized for V5 stable
operation.
- 24 -
NJU6673
(3-3) Contrast Adjustment by the EVR function
The EVR selects the VREG voltage out of the following 16 conditions by setting 4-bit data into the EVR
register. With the EVR function, VREG is controlled, and the LCD display contrast is adjusted. The EVR
controls the voltage of VREG by instruction and changes the voltage of V5.
A step with EVR is set like table shown below.
EVR register
(0, 0, 0, 0)
V
REG [V]
VLCD
Low
:
:
0H
1H
2H
:
(135/150)(VDD-VSS)
(136/150)(VDD-VSS)
(137/150)(VDD-VSS)
:
(0, 0, 0, 1)
(0, 0, 1, 0)
:
:
:
:
:
:
:
EH
FH
(1, 1, 1, 0)
(1, 1, 1, 1)
(149/150)(VDD-VSS)
(150/150)(VDD-VSS)
High
*
In use of the EVR function, the voltage adjustment circuit must turn on by the power supply instruction.
ꢁ
Adjustable range of the LCD driving voltage by EVR function
The adjustable range is decided by the power supply voltage VDD and the ratio of external resistors Ra and
Rb.
[ Design example for the adjustable range / Reference ]
- Condition VDD =3.0V, VSS=0V
Ra=1MΩ, Rb=1MΩ ( Ra:Rb=1:1 )
The adjustable range and the step voltage are calculated as follows in the above condition.
In case of setting 00H in the EVR register,
VLCD
= ((Ra+Rb)/Ra) VREG
= (2/1)[(135/150)3.0]
= 5.4V
In case of setting 0FH in the EVR register,
VLCD
= ((Ra+Rb)/Ra) VREG
= (2/1)[(150/150)3.0]
= 6.0V
(min.)0H
5.4
(max.)FH
6.0 [V]
[mV]
Adjustable Range
Step Voltage
40
- 25 -
NJU6673
(3-4) LCD Driving Voltage Generation Circuits
The LCD driving bias voltage of V1,V2,V3,V4 are generated by dividing the V5 voltage with the internal
bleeder resistance and is supplied to the LCD driving circuits after the impedence conversion by the
voltage follower.
The external capacitors to V1 to V5 for Bias voltage stabilization may be removed in use of small size
LCD panel. The equivalent load of LCD panel may be changed depending on display patterns. Therefore,
it require display quality check on various display patterns actually without external capacitors. If the
display quality is not so good, external capacitors should connects as show in Fig. 4. (If no need external
capacitors as result of experiment, the application patterns (wiring) should be prepared for recovery.)
Using the internal Power Supply
Using the external Power Supply
VSS
VSS
C1+
C1+
+
+
C1-
C1
C2+
+
C1-
C2+
COUT
C2-
C2-
C2
∗2
VOUT
V
OUT
R3
V5
NJU6673
V5
NJU6673
∗1
VR
VR
R2
R1
VDD
VDD
C3
+
+
+
V1
V2
V3
V1
V2
C4
C5
External
Voltage
V3
Generator
C6
C7
+
+
V4
V5
V4
V5
Fig.4
Reference set up value VLCD=VDD- V5=6.2-9.3V
COUT
C1, C2
C3-C7
R1
to 1.0µF
to 1.0µF
0.1 to 0.47 µF
1MΩ
∗1 Short wiring or sealed wiring to the VR terminal is required due to
the high impedance of VR terminal.
∗2 Following connection of VOUT is required when external power
supply using.
When VSS＞V5、VOUT＝V5
When VSS≤V5、VOUT＝VSS
R2
500kΩ
1.6MΩ
R3
- 26 -
NJU6673
(4) MPU Interface
(4-1) Interface type selection
Two MPU interface types are available in the NJU6673: by 1) 8-bit bi-directional data bus (D7 to D0), 2)
serial data input (SI:D7). The interface type (the 8 bit parallel or serial interface) is determined by the
condition of the P/S terminals connecting to “H” or “L” level as shown in Table 5. In case of the serial
interface, neither the status read-out nor the RAM data read-out operation is allowed..
Table 5
P/S
H
I/F type
Parallel
Serial
CS
CS
CS
A0
A0
A0
RD
RD
-
WR
WR
-
SEL68
SEL68
-
D7
D7
SI
D6
D6
D5-D0
D5-D0
Hi-Z
L
SCL
Parallel Interface
The NJU6673 interfaces the 68- or 80-type MPU directly if the parallel interface (P/S=”H” is selected.
The 68-type or 80-type MPU is selected by connecting the SEL68 terminal to “H” or “L” as shown in
table 6.
Table 6
CS
RD
WR
SEL68
Type
A0
A0
A0
D7-D0
D7-D0
D7-D0
CS
CS
H
L
68 type MPU
80 type MPU
E
R/W
WR
RD
(4-2) Discrimination of Data Bus Signal
The NJU6673 discriminates the mean of signal on the data bus by the combination of A0, E, R/W, and
(RD, WR) signals as shown in Table 7.
Table 7
common
68 type
R/W
H
80 type
Function
A0
H
H
L
RD
WR
H
L
H
L
Read Display Data
Write Display Data
Status Read
L
H
L
H
L
L
H
L
Write into the Register(Instruction)
- 27 -
NJU6673
(4-3) Serial Interface.(P/S="L")
The serial interface of the NJU6673 consists of the 8-bit shift register and 3-bit counter. In case the
chip is selected (CS=L), the input to D7(SI) and D6(SCL) becomes available, and in case that the chip isn’t
selected, the shift register and the counter are reset to the initial condition.
The data input from the terminal(SI) is MSB first like as the order of D7, D6,------ D0, by a serial interface,
it is entered into with rise edge of serial clock(SCL). The data converted into parallel data of 8-bit with the
rise edge of 8th serial clock and processed.
It discriminates display data or instructions by A0 input terminal. A0 is read with rise edge of (8 X n)th of
serial clock (SCL), it is recognized display data by A0=“H” and instruction by A0=“L” A0 input is read in the
rise edge of (8 X n)th of serial clock (SCL) after chip select and distinguished.
However,in case of RES=“H” to “L” or CS=“L” to “H” with trasfered data does not fill 8 bit, attention is
necessary because it will processed as there was command input. Always, input the data of (8 X n) style.
The SCL signal must be careful of the termination reflection by the wiring length and the external noise
and confirmation by the actual machine is recommended by it.
CS
SI
D4
D6
D5
3
D7
1
D6
D1
7
D0
8
D7
9
SCL
A0
2
4
10
Fig.5
- 28 -
NJU6673
(4-4) Access to the Display Data RAM and Internal Register.
The NJU6673 transfers data to the MPU through the bus holder with the internal data bus.
In case of reading out the display data contents in the DD RAM, the data which was read in the first
data read cycle (= the dummy read ) is memorized in the bus holder. Then the data is read out to the
system bus from the bus holder in the next data read cycle. Also, In case that the MPU writes into DD
RAM, the data is temporarily stored in the bus holder and is then written into DD RAM by the next data
write cycle.
Therefore, the limitation of the access to NJU6673 from MPU side is not access time (tACC,tDS) of
Display Data RAM and the cycle time becomes dominant. With this, speed-up of the data transfer with the
MPU becomes possible. In case of cycle time isn’t met, the MPU inserts NOP operation only and
becomes an equivalent to an execution of wait operation on the satisfy condition in MPU.
When setting an address, the data of the specified address isn’t output immediately by the read
operation after setting an address, and the data of the specified address is output at the 2nd data read
operation. Therefore, the dummy read is always necessary once after the address set and the write cycle.
(See Fig. 6)
The example of Read Modify Write operation is mentioned in (2-1)Instruction -k)The sequence of
Inverse Display.
ꢁ
Write Operation
WR
MPU
N+2
N+3
N
N+1
DATA
I/O Buffer
WR
N
N+1
N+2
N+3
Internal
timing
ꢁ
Read Operation
MPU
WR
RD
N
N
ｎ
ｎ+1
DATA
Address set N Dummy Read Data Read n Data Read n+1
WR
RD
N
N+1
N+2
Column Address
I/O Buffer
Internal
timing
N
ｎ
ｎ+1
ｎ+2
Fig.6
(4-5) Chip Select
CS is Chip Select terminal. In case of CS="L". the interface with MPU is available. In case of CS=”H”,
the D0 to D7 are high impedance and A0, RD, WR, SI and SCL inputs are ignored. If the serial interface is
selected when CS=”H” the shift register and counter are reset. However, the reset is always operated in
any conditions of CS.
- 29 -
NJU6673
ꢀ ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATINGS
-0.3 - +7.0
-0.3 -+3.6(Used Tripler)
VDD-11.0 - VDD+0.3
UNIT
V
Supply Voltage(1)
VDD
Supply Voltage(2)
Supply Voltage(3)
V5
V1,V2,V3,V4
VIN
V
V
V
V5-VDD+0.3
-0.3-VDD+0.3
Input Voltage
Operating
Temperature
Topr
Tstg
-30-+80
°C
°C
Strage temperature
-55-+125
VDD
VSS
VDD
V5
Note 1) All voltage values are specified as VSS=0V.
Note 2) The relation of VDD>V1>V2>V3>V4>V5>VOUT; VDD>VSS>VOUT must be maintained.
In case of inputting external LCD driving voltage , the LCD drive voltage should start supplying to
NJU6673 at the mean time of turning on VDD power supply or after turned on VDD
.
In use of the voltage boost circuit, the condition that the supply voltage: 11.0V> VDD -VOUT is necessary.
Note 3) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed.
Using LSI within electrical characteristics is strongly recommended for normal operation.
Use beyond the erectric characteristics conditions will cause malfunction and poor reliability.
Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for
the voltage converter.
- 30 -
NJU6673
ꢀ ELECTRICAL CHARACTERISTICS
(VDD=2.4V-3.6V, VSS=0V, Ta=-20 to 75°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT NOTE
Recommend
Available
Recommend
Available
Available
Available
Operating
voltage(1)
2.4
2.4
VDD-10.0
VDD-10.0
VDD-0.6VLCD
V5
3.0
3.6
5.5
VDD-5.0
VDD
V
V
1
V5
Operating
voltage(2)
V1,V2
V3,V4
VDD
VDD-0.4VLCD
VDD
VLCD=VDD-V5
0.8VDD
VSS
0.8VDD
VSS
-1.0
-3.0
High Level VIHC
Low Level VILC
High Level VOHC
Low Level VOLC
ILI
Input
Voltage
Output
Voltage
A0, D0-D7, RD, WR, RES, CS
P/S, SEL68, DUTY, CDIR Terminal
V
V
0.2VDD
VDD
0.2VDD
1.0
IOH=-0.5mA
D0-D7
Terminal
IOL= 0.5mA
All input terminals
D0 to D7 terminals, Hi-Z state
Input Leagage Current
µA
IL0
3.0
Driver On-resistance
RON
IDDQ
CIN
3.0
T.B.D
10
4.5
2
4
3
Ta=25°C, VLCD=8.0V
During Power Save Mode
Ta=25°C
kΩ
µA
pF
Stand-by Current
Input Terminal
Capacitance
T.B.D
Oscillation Frequency fOSC
T.B.D
1.0
T.B.D
T.B.D
kHz
VDD= 3.0V Ta =25°C
RES terminal
Reset Time
Reset “L”
tR
5
6
µs
tRW
10
µs
level pulse Width
VDD1
VDD2
2.4
2.4
-6.6
5.5
3.3
-5.5
Input voltage
V
V
Ω
3-times boost
7
Output voltage
On-resistance
VOUT1 3-times boost,VDD=3.0V
3-times boost,
VDD=3.0V, COUT=1.0µF
RTRI
T.B.D
T.B.D
Adjustment range
LCD driving oltage
Voltage Follower
Voltage Regulator
f
VOUT2 Voltage boost operation off
VDD-10.0V
VDD-5.0V
V
8
9
V5
VREG%
Voltage adjustment circuit “OFF” VDD-10.0V
VDD-5.0V
T.B.D
V
%
VDD=3.0V; Ta =25°C
VDD=3.0V, VLCD=8V,
Display Checkerd pattern
IOUT1
IOUT2
T.B.D
T.B.D
T.B.D
T.B.D
µA
µA
Operating Current
Note 1) Although the NJU6673 can operate in wide range of the operating voltage, it shall not be guaranteed in
a sudden voltage fluctuation during the access with MPU.
Note 2) RON is the resistance values in supplying 0.1V voltage-difference beteen power supply terminals
(V1,V2,V3,V4) and each output terminals (common/ segment). This is specified within the range of
Operating Voltage(2).
Note 3) Apply A0, D0 to D7,RD,WR,CS,RES,SEL68,P/S,T1,T2,DUTY,CDIR terminals.
Note 4) Apply no access from MPU.
Note 5) tR ( Reset Time ) refers to the reset completion time of the internal circuits from the rise edge of the RES
signal.
Note 6) Apply minimum pulse width of the RES signal. To reset, the ”L” pulse over tRW shall be input. .
Note 7) Apply to the VDD when using 3-times boost.
Note 8) The voltage adjustment circuit controls V5 within the range of the voltage follower operating voltage.
- 31 -
NJU6673
Note 9) Each operating current shall be defined as being measured in the following condition.
External Voltage
Oprating Condition
Voltage
Status
Supply
SYMBOL
Voltage
booster
Voltage
Follower
T1
T2
(Input terminal)
adjustment
IOUT1
IOUT2
L
H
L/H
H
Unuse
Use (VOUT,V5)
Validity
Invalidity
Validity
Invalidity
Validity
Invalidity
LCD output terminal Open.
Display on, Display checered pattern, No access from MPU
Set VLCD=8V
Internal Oscillator : Validity
MEASUREMENT BLOCK DIAGRAM
: IOUT1
500kΩ
1MΩ
1.6MΩ
VR
V5
VDD
T1
T2
NJU6673
A
VSS C1+
C1-
C2+ C2-
VOUT
+
+
+
1µF
1µF
1µF
: IOUT2
-5V
10kΩ 10kΩ 10kΩ 10kΩ 10kΩ
VDD V1
V2
V3
V4
V5 VOUT
VDD
T1
T2
NJU6673
A
VSS C1+
C1-
C2+ C2-
- 32 -
NJU6673
ꢀ BUS TIMING CHARACTERISTICS
• Read/Write operation sequence(80 type MPU)
tCYC8
A0
tr
tf
tAW8
tAH8
tCCL
WR, RD
(CS)
tCCH
tDH8
tDS8
D0-D7
(Write)
tACC8
tOH8
D0-D7
(Read)
(VDD=2.4V-3.6V, Ta=-20 to 75°C)
UNIT
PARAMETER
SYMBOL SIGNAL CONDITION
MIN
32
TYP
MAX
Address Hold Time
Address Setup Time
System Cycle Time
tAH8
tAW8
tCYC8
tCCL(W)
tCCL(R)
tCCH
A0, CS
32
560
75
WR, RD
WR, "L"
Control
250
RD, "L"
"H"
Pulse Width
275
150
44
ns
Data Setup Time
Data Hold Time
tDS8
tDH8
DD-D7
tACC8
175
44
RD Access Time
Output Disable Time
CL=100pF
tOH8
tr, tf
0
CS,WR,RD
Rise Time, Fall Time
15
Note 1) All timing based on 20% and 80% of VDD voltage level.
- 33 -
NJU6673
Read/Write operation sequence(68 type MPU)
tCYC6
E
tr
tf
tEWL
tEWH
R/W
tAW6
tAH6
A0, CS
tDH6
tDS6
D0-D7
(Write)
tACC6
tOH6
D0-D7
(Read)
(VDD=2.4V-3.6V, Ta=-20 to 75°C)
PARAMETER
Address Hold Time
Address Setup Time
SYMBOL SIGNAL CONDITION
MIN
32
TYP
MAX UNIT
A0,CS
R/W
tAH6
tAW6
tCYC6
32
E
E
560
250
62
System Cycle Time
READ
WRITE
Enable
Pulse Width
tEWH
ns
Data Setup Time
Data Hold Time
Access Time
Output Disable Time
Rise Time, Fall Time
tDS6
150
50
tDH6
tACC6
tOH6
D0-D7
tr, tf
175
56
CL=100pF
0
E
15
Note 1) All timing based on 20% and 80% of VDD voltage level.
Note 2) tCYC6 shows the cycle of the E signal in active CS.
- 34 -
NJU6673
Write operation sequence(Serial Interface)
tCSH
tCSS
CS
tSAS
tSAH
A0
tSCYC1
tSLW
tSHW
SCL
SI
tr
tf
tSDS
tSDH
(VDD=2.4V-3.6V, Ta=-20 to 75°C)
PARAMETER
SYMBOL SIGNAL CONDITION
MIN
TYP
MAX UNIT
Serial Clock cycle
tSCYC
1000
SCL
SCL "H" Pulse width
SCL "L" Pulse width
Address Setup Time
Address Hold Time
Data Setup Time
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
tf, tr
300
300
250
400
250
100
60
A0
SI
ns
Data Hold Time
CS-SCL Time
CS
800
Rise time, Fall Time
SCL
15
Note 1) All timing are based on 20% and 80% of VDD voltage level.
- 35 -
NJU6673
ꢀ LCD DRIVING WAVERORM
VDD
VSS
FR
VDD
V1
V2
V3
V4
V5
C0
C0
C1
C2
C3
VDD
V1
V2
V3
V4
V5
C4
C5
C1
C6
C7
VDD
V1
V2
V3
V4
V5
C8
C9
C2
S0
C10
C11
C12
C13
VDD
V1
V2
V3
V4
V5
C14
C15
VDD
V1
V2
V3
V4
V5
S1
V5
V4
V3
V2
V1
VDD
C0-S0
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
C0-S1
VDD
-V1
-V2
-V3
-V4
-V5
- 36 -
NJU6673
ꢀ APPLICATION CIRCUIT
Microprocessor Interface Example
The NJU6673 is connectable to 80-type MPU or 68-type. In use of Serial Interface, it is possible to be controlled
by the signal line with the more small being.
*:SEL68 terminal shall be connected to VDD or VSS.
ꢁ
80 type MPU
VCC
VDD
A0
A0
A1-A7
IORQ
SEL68
CS
Decoder
MPU
NJU6673
D0-D7
D0-D7
VDD
RD
RD
WR
RES
WR
RES
P/S
GND
VSS
RESET
ꢁ
68 type MPU
VDD
VCC
VDD
A0
A0
A1-A15
VMA
SEL68
CS
Decoder
MPU
NJU6673
D0-D7
D0-D7
VDD
E
E
R/W
RES
R/W
RES
P/S
GND
VSS
RESE
ꢁ
Serial Interface
VDD
VCC
A0
A0
SEL68
CS
A1-A7
Decoder
MPU
NJU6673
D7(SI)
D6(SCL)
Port 1
Port 2
P/S
RES
RES
GND
VSS
RESE
- 37 -
NJU6673
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 38 -
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