MP3908DK [MPS]
Switching Controller, Current-mode, 300kHz Switching Freq-Max, PDSO10, MO-817BA, MSOP-10;
| 型号： | MP3908DK |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Switching Controller, Current-mode, 300kHz Switching Freq-Max, PDSO10, MO-817BA, MSOP-10 开关 光电二极管 |
| 文件： | 总11页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP3908
Current Mode PWM Controller
with Synchronous Secondary Gate Drive
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP3908 is a flexible current-mode PWM
•
•
•
•
•
•
•
•
•
•
•
•
•
Programmable Dead-Time
Synchronous Secondary Gate Drive
Current Mode Control
10V MOSFET Gate Drivers
Drives >10A MOSFETs
Soft-Start
Cycle-by-Cycle Current Limiting
Slope Current Compensation
Lossless Current Sense (VISENSE<28V)
50µA Shutdown Current
270uA typical Operating Current
250KHz Constant Frequency Operation
Applicable to Boost, SEPIC, Flyback and
Forward Topologies
controller
optimized
for
power-supply
applications. The MP3908 features resistor-
programmable dead-time control to optimize
efficiency for a broad number of different
configurations, and a synchronous secondary
gate drive. The MOSFET drivers are capable
of driving >10A MOSFETs. It has an operational
current of typically 270µA and can accommodate
off-line, Telecom and non-isolated applications.
Under-voltage
lockout,
soft-start,
slope
compensation and peak current limiting are all
included. In a boost application, with an output
voltage of less than 28V, the current sense pin
can connect directly to the drain of the external
switch. This eliminates the requirement for an
additional current sensing element and its
associated efficiency loss.
•
Available in a 10-Pin MSOP Package
APPLICATIONS
•
•
•
•
•
PoE PD Power Supplies
TV CCFL Power Generation
Telecom Isolated Power
Brick Modules
While designed for boost applications, the MP3908
can also be used for other topologies including
Forward, Flyback and Sepic. The 10V gate driver
compliance minimizes the power loss of the external
MOSFET while allowing the use of a wide variety of
standard threshold devices. An externally
programmable delay following the turn off of the
synchronous rectifier allows the incorporation of
secondary side synchronous rectifier
Off-line Controller
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
The MP3908 is available in space saving 10-pin
MSOP package.
TYPICAL APPLICATION
Efficiency vs.
Output Current
8
95
VCC
T1
7
5
2
1
GND
DELAY
ADJ
90
85
80
75
70
65
60
MP3908
9
EN
MAIN
6
ISENSE
SYNC
FB
10
CSS
COMP
4
3
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
MP3908 Rev.0.9
8/29/2008
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1
MP3908 – HIGH EFFICIENCY BOOST CONTROLLER
PACKAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS (1)
VCC.............................................–0.3V to +10V
VCC Maximum Current ............................ 30mA
ISENSE .......................................–0.3V to +28V
FB ..............................................–0.3V to +1.3V
COMP............................................–0.3V to +3V
CSS, ENABLE...............................–0.3V to +5V
Junction Temperature...............................125°C
Lead Temperature....................................260°C
Storage Temperature ..............–65°C to +150°C
TOP VIEW
1
2
3
4
5
10
9
8
7
6
Recommended Operating Conditions (2)
VCC Current................................. 1mA to 25mA
Operating Temperature .............–40°C to +85°C
Thermal Resistance (3)
MSOP10................................150..... 65... °C/W
θJA
θJC
Part Number*
MP3908DK
Package
MSOP10
Temperature
–40°C to +85°C
For Tape & Reel, add suffix –Z (eg. MP3908DK–Z)
For RoHS compliant packaging, add suffix –LF (eg.
MP3908DK–LF–Z)
*
Notes:
1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its
operating conditions.
3) Measured on approximately 1” square of 1 oz copper.
ELECTRICAL CHARACTERISTICS
VCC = 10V, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Internal Divider (IQ)
Min
Typ
4.5
1
Max
4.7
Units
V
V
VCC Undervoltage Lockout
VCC On/Off Voltage Hysteresis
Shutdown Current
IS
EN/SS = 0V, VIN = 9V
Output not switching, VFB
1V, VCC = 9V
50
µA
=
Quiescent Current (Operation)
IQ
270
16
320
µA
Ω
Main Gate Driver Impedance
(Sourcing)
Main Gate Driver Impedance
(Sinking)
Synchronous Gate Driver
Impedance (Sourcing)
Synchronous Gate Driver
Impedance (Sinking)
Delay after Synchronous Gate
VCC = 9V, VGATE = 5V
VCC = 9V, IGATE = 5mA
VCC = 9V, VSYNCGATE = 5V
VCC = 9V, IGATE = 5mA
5.0
16
Ω
Ω
5.0
50
Ω
ns
RDELAY=100kΩ
FB connected to VCOMP/RUN.
V
Error Amplifier Transconductance
0.26
0.38
0.46
mA/V
Force ±10µA to VCOMP/RUN
.
Maximum Comp Current
Error Amplifier Translator Gain (4)
Switching Frequency
Thermal Shutdown
Maximum Duty Cycle
Minimum On Time
ISENSE Limit
Sourcing and Sinking
40
0.32
260
150
81
µA
V/V
KHz
°C
%
ns
mV
V
nA
AET
fS
0.28
220
0.36
300
76
86
tON
200
190
0.794 0.818
50
165
215
0.847
FB Voltage
FB Bias Current
VFB
IFB
Current flowing out of part
Note:
4) Guaranteed by design.
MP3908 Rev.0.9
8/29/2008
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2
MP3908 – HIGH EFFICIENCY BOOST CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC = 10V, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
50
1.25
50
Max
Units
ISENSE Bias Current
Enable On Threshold
Enable Hysteresis
Soft Start Current
ISENSE Current flowing out of part
nA
V
mV
VEN
VEN
ISS
High-to-Low
1.15
1.35
4
µA
PIN FUNCTIONS
Pin #
Name
Description
Capacitor Soft Start. A charging current of 5µA is enabled when the ENABLE pin is
taken above 1.2V. The rise time of the capacitor allows output current soft start. Full
output current is allowed when the voltage is above 2.7V.
1
CSS
This pin serves two functions. Below 0.6V, the part is in sleep mood, drawing 10µA
(typ). The second threshold of 1.2V can be used as a precise under-voltage lock out
(UVLO) and enables full operation..
2
ENABLE
3
4
COMP
FB
Compensation.
Feedback forces this pin voltage to the 0.8V internal reference potential. Do not allow
this pin to rise above 1.2V in the application.
External resistor determines delay between the Synchronous Gate Drive pin going low
to the Main Gate drive going high.
5
6
RDELAY
ISENSE
Current Sense. Do not connect this pin directly to the drain of the external MOSFET if
the voltage swing exceeds 27V in the particular application. During normal operation,
this pin will sense the voltage across the external MOSFET or sense resistor if one is
used, limiting the peak inductor current on a cycle-by-cycle basis.
7
8
9
GND
VCC
Ground.
Input Supply. Decouple this pin as close as possible to the GND pin.
MAIN GATE This pin drives the external MAIN MOSFET device.
This pin drives the external SYNCHRONOUS MOSFET device. The Sync Gate is
SYNC GATE
10
disabled at the end of switching period if Main Gate is not turned on the next cycle.
MP3908 Rev.0.9
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MP3908 – HIGH EFFICIENCY BOOST CONTROLLER
OPERATION
RDLY
RDELAY
V
IN
V
CC
V
OUT
CSS
Slope
Compensation
Internal
Bias
Enable
Oscillator
--
+
9.9V
1.2V
Vref = 0.8V
ENABLE
Delay
Turn
MAIN
Off
Q
Q
S
R
EA
+
--
FB
Driver
+
--
ITRP
Gates
Off
Rsense
PGND
IMAX
Clamp
COMP
ISENSE
V
CC
Q
S
R
EA Translator
Rdson
SYNC
sensing
SGND
Optional Filter
Figure 1—Functional Block Diagram
The MP3908 uses a constant frequency, peak
current mode architecture to regulate the
feedback voltage. The operation of the MP3908
can be understood with the block diagram of
Figure 1.
When the voltage at the ISENSE node rises
above the voltage set by the COMP/RUN pin,
the external main FET is turned off and the
synchronous FET, if used, is turned on. The
inductor current then flows to the output
capacitor through the Schottky diode. The
inductor current is controlled by the
COMP/RUN voltage, which itself is controlled
by the output voltage. The peak inductor current
is internally limited by the IMAX clamp voltage
that limits the voltage applied to the ITRP
comparator input.
At the beginning of each cycle the main
external N-Channel MOSFET is turned on,
forcing the current in the inductor to increase.
The current through the FET can either be
sensed through a sensing resistor or across the
external FET directly. This voltage is then
compared to
a
voltage related to the
COMP/RUN node voltage. The voltage at the
COMP/RUN pin is an amplified voltage of the
difference between the 0.8V reference and the
feedback node voltage.
Thus the output voltage controls the inductor
current to satisfy the load. This current mode
architecture improves transient response and
control loop stability over a voltage mode
architecture.
MP3908 Rev. 0.9
8/29/2008
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MP3908 – HIGH EFFICIENCY BOOST CONTROLLER
APPLICATION INFORMATION
Selecting the Inductor and Current Sensing
Resistor
COMPONENT SELECTION
Setting the Output Voltage
The inductor is required to transfer the energy
between the input source and the output
capacitors. A larger value inductor results in
less ripple current that results in lower peak
inductor current, and therefore reduces the
stress on the power MOSFET. However, the
larger value inductor has a larger physical size,
higher series resistance, and/or lower
saturation current.
Set the output voltage by selecting the resistive
voltage divider ratio. If we use 10kꢀ for the low-
side resistor (R2) of the voltage divider, we can
determine the high-side resistor (R1) by the
equation:
R2× (VOUT − VREF
)
R1 =
VREF
Where VOUT is the output voltage.
A good rule of thumb is to allow the
peak-to-peak ripple current to be approximately
30-50% of the maximum input current. Make
sure that the peak inductor current is below
80% of the IC’s maximum current limit at the
operating duty cycle to prevent loss of
regulation. Make sure that the inductor does not
saturate under the worst-case load transient
and startup conditions. The required inductance
value can be calculated by :
For R2=10kꢀ, VOUT=25V and VREF=0.8V, then
R1=301kꢀ.
An external resistor tied from the RDELAY pin to
ground programs an internal time delay circuit
that sets a delay from the turn off of the
synchronous MOSFET drive pin output to the
turn on of the main MOSFET drive pin output.
This delay is adjustable to program the required
time interval required by the circuitry to turn off
the synchronous MOSFET from the time that
the Synchronous output drive signal goes low.
This path may include active devices as well as
an isolating transformer used to electrically
isolate the secondary side output. Efficiency
losses can be quite significant if an overlap
occurs between the main and synchronous
switching MOSFETs if the delay is not carefully
determined and accounted for. The RDELAY pin
has an internal resistance of approximately
50kOhms that should be added to any external
resistance used to approximate the delay
interval. Shorting the pin directly to ground will
result in approximately 30nSec delay as a result
of this internal resistance. A graph is provided
in the applications section of this data sheet to
illustrate the typical delay time generated
versus the resistor value selected
VIN(MIN) × (VOUT - VIN(MIN)
VOUT × fSW × ∆I
)
L =
VOUT ×ILOAD
(MAX)
IIN(MAX)
=
VIN(MIN) ×η
∆I =
30% − 50% IIN(MAX)
)
Where ILOAD (MAX) is the maximum load current,
∆I is the peak-to-peak inductor ripple current
and η is the efficiency. For a typical design,
boost converter efficiency can reach 85%~95%.
For VIN (MIN)=10V, VOUT=25V, ILOAD (MAX)=2A, the
ripple percentage being 30%, η=95% and
fSW=330kHz, then L=10µH. In this case, use a
8.8µH inductor (i.e. Sumida CDRH127/LDNP-
100MC).
The switch current is usually used for the peak
current mode control. In order to avoid hitting
the current limit, the voltage across the sensing
resistor RSENSE should be less than 80% of the
worst case current limit voltage, 200mV.
0.8 × 0.2
IL(PEAK)
RSENSE
=
Where IL (PEAK) is the peak value of the inductor
current.
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MP3908 – HIGH EFFICIENCY BOOST CONTROLLER
For IL (PEAK)=5.3A, RSENSE=30mꢀ.
Selecting the Output Capacitor
Typically, a boost converter has significant output
voltage ripple because the current through the
output diode is discontinuous. During the diode off
state, all of the load current is supplied by the output
capacitor.
In cases where the RDS(ON) of the power
MOSFET is used as the sensing resistor, be
sure that the RDS(ON) is lower than the value
calculated above, 30mꢀ
Another factor to take into consideration is the
Low ESR capacitors are preferred to keep the
temperature coefficient of the MOSFET RDS(ON)
As the temperature increases, the RDS(ON) also
increases.. Device vendors will usually provide
an RDS(ON) vs. temperature curve and the
temperature coefficient in the datasheet.
Generally, the MOSFET on resistance will
double from 25°C to 125°C.
.
output voltage ripple to a minimum. The
characteristics of the output capacitor also affect the
stability of the regulation control system. Ceramic,
tantalum or low ESR electrolytic capacitors are
recommended. In the case of ceramic capacitors,
the impedance of the capacitor at the switching
frequency is dominated by the capacitance, and so
the output voltage ripple is mostly independent of
the ESR. The output voltage ripple is estimated to
be:
Selecting the Input Capacitor
An input capacitor (C1) is required to supply the
AC ripple current to the inductor, while limiting
noise at the input source. A low ESR capacitor
is required to keep the noise to the IC at a
minimum. Ceramic capacitors are preferred, but
tantalum or low-ESR electrolytic capacitors may
also suffice.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VIN
1-
×ILOAD
VOUT
VRIPPLE
≈
C2× fSW
Where VRIPPLE is the output ripple voltage, VIN
and VOUT are the DC input and output voltages
respectively, ILOAD is the load current, fSW is the
switching frequency and C2 is the output
capacitor.
The capacitance can be calculated as:
∆I
C1 ≈
8 × ∆VIN(RIPPLE) × fSW
Where ∆I is the peak-to-peak inductor ripple
current and ∆VIN(RIPPLE) is the input voltage
ripple. When using ceramic capacitors, take into
account the vendor specified voltage and
temperature coefficients for the particular
dielectric being used.
In the case of tantalum or low-ESR electrolytic
capacitors, the ESR dominates the impedance
at the switching frequency. Therefore, the
output ripple is calculated as:
ILOAD ×RESR × VOUT
VRIPPLE(pk _pk)
≈
VIN
For example, 2.2uF capacitance is sufficient to
achieve less then 1% input voltage ripple.
Meanwhile, it requires an adequate ripple current
rating. Use a capacitor with RMS current rating
greater than the inductor ripple current (see
Selecting the Inductor to determine the inductor
ripple current).
where RESR is the equivalent series resistance
of the output capacitors.
For the application shown in page 1, use
ceramic capacitor as an example. For
VIN(MIN)=10V, VOUT=25V, ILOAD(MAX)=2A, and
VRIPPLE=1% of the output voltage, the
capacitance C2=14.5µF. Please note that the
In addition, a smaller high quality ceramic
0.1µF~1µF capacitor may be placed to absorb the
high frequency noise. If using this technique, it is
recommended that the larger capacitor be a
tantalum or electrolytic type.
ceramic
capacitance
could
dramatically
decrease as the voltage across the capacitor
increases. As a result, larger capacitance is
recommended. In this example, place four
4.7µF ceramic capacitors in parallel. The
voltage rating is also chosen as 50V.
In the meantime, the RMS current rating of the
output capacitor needs to be sufficient to handle
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MP3908 – HIGH EFFICIENCY BOOST CONTROLLER
VOUT − VIN(MIN)
the large ripple current. The RMS current is
given by:
DMAX
≈
VOUT
V
2
2 − 2×ILOAD ×I
)
×
+ILOAD
IN
The current rating of the MOSFET should be
greater than 1.5 times IRMS,
IRIPPLE(RMS)
≈
(
I
IN(MAX)
IN(MAX)
VOUT
2
The on resistance of the MOSFET determines
the conduction loss, which is given by:
IRIPPLE(RMS) ≈ D(1−D)×I
< 0.5×I
INMAX
I
NMAX
For
IIN(MAX)=5.3A, ILOAD=2A, VIN=12V and
2
Pcond = IRMS × RDS(on) × k
VOUT=25V, IRIPPLE(RMS)=2.64A. Make sure that
the output capacitor can handle such an RMS
current.
Where k is the temperature coefficient of the
MOSFET. If the RDS(ON) of the MOSFET is used
as the current sensing resistor, make sure the
voltage drop across the device does not exceed
the current limit value of 190mV.
In addition, a smaller high quality ceramic
0.1µF~1uF capacitor needs to be placed at the
output to absorb the high frequency noise
during the commutation between the power
MOSFET and the output diode. Basically, the
high frequency noise is caused by the parasitic
inductance of the trace and the parasitic
capacitors of devices. The ceramic capacitor
should be placed as close as possible to the
power MOSFET and output diode in order to
minimize the parasitic inductance and maximize
the absorption.
The switching loss is related to QGD and QGS1
which determine the commutation time. QGS1 is
the charge between the threshold voltage and
the plateau voltage when a driver charges the
gate, which can be read in the chart of VGS vs.
QG of the MOSFET datasheet. QGD is the
charge during the plateau voltage. These two
parameters are needed to estimate the turn on
and turn off loss.
Selecting the Power MOSFET
QGS1 × RG
PSW
=
× VDS × IIN × fSW
× VDS × IIN × fSW
+
The MP3908 is capable of driving a wide variety
of N-Channel power MOSFETS. The critical
parameters of selection of a MOSFET are:
VDR − VTH
QGD × RG
VDR − VPLT
1. Maximum drain to source voltage, VDS(MAX)
2. Maximum current, ID(MAX)
Where VTH is the threshold voltage, VPLT is the
plateau voltage, RG is the gate resistance, VDS
is the drain-source voltage. Please note that the
switching loss is the most difficult part in the
loss estimation. The formula above provides a
simple physical expression. If more accurate
estimation is required, the expressions will be
much more complex.
3. On-resistance, RDS(ON)
4. Gate source charge QGS and gate drain
charge QGD
5. Total gate charge, QG
Ideally, the off-state voltage across the
MOSFET is equal to the output voltage.
Considering the voltage spike when it turns off,
VDS(MAX) should be greater than 1.5 times of the
output voltage.
For extended knowledge of the power loss
estimation, readers should refer to the book
“Power MOSFET Theory and Applications”
written by Duncan A. Grant and John Gowar.
The maximum current through the power
MOSFET happens when the input voltage is
minimum and the output power is maximum.
The maximum RMS current through the
MOSFET is given by
The total gate charge, QG, is used to calculate
the gate drive loss. The expression is
PDR = QG × VDR × fSW
where VDR is the drive voltage.
IRMS(MAX) = IIN(MAX) × DMAX
For the application in page 1, a FDS6630 or
equivalent MOSFET is chosen. Read from the
datasheet: RDS(ON)=28mꢀ, k = 0.5, QGD=0.9nC,
Where:
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MP3908 – HIGH EFFICIENCY BOOST CONTROLLER
QGS1=1nC, VTH=1.7V, VPLT=3V and QG=5nC @
10V. The MP3908 has its gate driving resistance of
around 20ꢀ at VDR=10V and VGATE = 5V.
Where RLOAD is the load resistance.
The DC mid-band loop gain is:
0.5× GEA × VIN ×RLOAD × VREF ×R3× AET
Based on the loss calculation above, the
conduction loss is around 0.629W. The
switching loss is around 0.171W, and the gate
drive loss is 0.015W.
AVDC =
VOUT2 ×RSENSE
where VREF is the voltage reference, 0.8V. AET is
the gain of error amplifier translator and GEA is
the error amplifier transconductance.
Selecting the Output Diode
The output rectifier diode supplies current to the
inductor when the MOSFET is off. To reduce
losses due to diode forward voltage and
recovery time, use a Schottky diode. The diode
should be rated for a reverse voltage greater
than the output voltage used. Considering the
voltage spike during the commutation period,
the voltage rating of the diode should be set as
1.5 times the output voltage. For high output
voltages (150V or above), a Schottky diode
might not be practical. A high-speed ultra-fast
recovery silicon rectifier is recommended.
The ESR zero in this example locates at very
high frequency. Therefore, it is not taken into
design consideration.
There is also a right-half-plane zero (fRHPZ) that
exists in continuous conduction mode (inductor
current does not drop to zero on each cycle)
step-up converters. The frequency of the right
half plane zero is:
VIN2 × RLOAD
fRHPZ
=
2
2× π×L× VOUT
Observation of the boost converter circuit
shows that the average current through the
diode is the average load current, and the peak
current through the diode is the peak current
through the inductor. The average current rating
must be greater than 1.5 times of the maximum
load current, and the peak current rating must
be greater than the peak inductor current.
The right-half-plane zero increases the gain and
reduces the phase simultaneously, which
results in smaller phase margin and gain
margin. The worst case happens at the
condition of minimum input voltage and
maximum output power.
In order to achieve system stability, fz1 is placed
close to fP1 to cancel the pole. R3 is adjusted to
change the voltage gain. Make sure the
bandwidth is about 1/10 of the lower one of the
ESR zero and the right-half-plane zero.
For the application in page 1, a Vishay SS16
Schottky diode or equivalent part is chosen.
Boost Converter: Compensation Design
The output of the transconductance error
amplifier (COMP) is used to compensate the
regulation control system. The system uses two
poles and one zero to stabilize the control loop.
The poles are fP1, which is set by the output
capacitor (C2) and load resistance and fP2,
which starts from origin. The zero (fZ1) is set by
the compensation capacitor (C3) and the
compensation resistor (R3). These parameters
are determined by the equations:
1
1
=
π × C2×RLOAD
2× π × C3×R3
2
VOUT × 2× π× C2× fc ×RSENSE
R3 =
GEA × VREF ×VIN × AET
Based on these equations, R3 and C3 can be
solved.
For the application in page 1, fp1 = 1.35KHz,
ESR zero is much higher than the switching
frequency and fRHPZ=45.8KHz. Set fz1 to
3.18KHz and make the crossover frequency
8.5kHz, then R3=5kꢀ and C3=10nF. Choose
5kꢀ and 10nF.
1
fP1
=
=
π × C2×RLOAD
1
fZ1
2 × π × C3×R3
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MP3908 – HIGH EFFICIENCY BOOST CONTROLLER
In cases where the ESR zero is in a relatively
low frequency region and results in insufficient
gain margin, an optional capacitor (C5) (shown
in flat page) should be added. Then a pole,
formed by C5 and R3, should be placed at the
ESR zero to cancel the adverse effect.
Layout Consideration
High frequency switching regulators require
very careful layout for stable operation and low
noise. Keep the high current path as short as
possible between the MOSFET drain, output
diode, output capacitor and GND pin for
minimal noise and ringing. The VCC capacitor
must be placed close to the VCC pin for best
decoupling. All feedback components must be
kept close to the FB pin to prevent noise
injection on the FB pin trace. The ground return
of the input and output capacitors should be
tied closed to the GND pin. See the MP3908
demo board layout for reference.
1
C5 =
2× π×R3 ×
fESRz
MP3908 Rev.0.9
8/29/2008
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2008 MPS. All Rights Reserved.
9
MP3908 – HIGH EFFICIENCY BOOST CONTROLLER
TYPICAL APPLICATION CIRCUITS
D6
1
2
4
SYNC
R18, 5
R34, 330
D5
3
T2
36V to 72V
VIN
D7
R19
3k
5
5V@5A
VOUT
15V
R10
30k
R9
30k
R6
51k
R8
30k
Q5
Np1
3
R32
0
10, 11, 12
+
VCC
Q8
NS
7, 8, 9
R23
GND
D4
2
Np2
1
VCC 1.5k
11V
D1
R20
10
C7
R35
1k
R2
300k
PGND
EN
R11
200V
8
4.7uF
499k
R21
976
VCC
D3
7
T1 8:1:4
5
GND
DELAY
D2
R12, 5
R24
NS
9
6
Q2
Si7450
R4
82.5k
MP3908
U2
PC817B
R13, 1k
R31 NS
Q1
R17
200
2
1
R1
1k
EN
ISENSE
C16
R26
C8
330pF
10nF
R16
0.05
R3
20k
33.2k
C17
470pF
C15
33nF
10
VCC
R28
10k
SYNC
CSS
R29
NS
2N7002
COMP FB
D8
NS
R25
10k
R14
4
3
0
Q3
NS
Q6
2N3904
R5
R30
100k
C4
NS
SYNC
10k
R7
910k
Q7
C5
TLV431/1.24V
Q4
NS
R33
10nF
R27
10k
0
R15
470k
R22
204
C18
1000pF/2000V
Figure 2—MP3908 Isolated Synchronous Flyback Application
MP3908 Rev.0.9
8/29/2008
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2008 MPS. All Rights Reserved.
10
MP3908 – HIGH EFFICIENCY BOOST CONTROLLER
PACKAGE INFORMATION
MSOP10
0.114(2.90)
0.122(3.10)
6
10
0.187(4.75)
0.199(5.05)
0.114(2.90)
0.122(3.10)
PIN 1 ID
(NOTE 5)
5
1
0.007(0.18)
0.011(0.28)
0.0197(0.50)BSC
BOTTOM VIEW
TOP VIEW
GAUGE PLANE
0.010(0.25)
0.030(0.75)
0.037(0.95)
0.043(1.10)MAX
SEATING PLANE
0.002(0.05)
0.004(0.10)
0.008(0.20)
0.016(0.40)
0.026(0.65)
0o-6o
0.006(0.15)
FRONT VIEW
SIDE VIEW
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS
IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
0.181(4.60)
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) PIN 1 IDENTIFICATION HAS THE HALF OR FULL CIRCLE OPTION.
6) DRAWING MEETS JEDEC MO-817, VARIATION BA.
7) DRAWING IS NOT TO SCALE.
0.040(1.00)
0.012(0.30)
0.0197(0.50)BSC
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP3908 Rev. 0.9
8/29/2008
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2008 MPS. All Rights Reserved.
11
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