MP3910 [MPS]
Peak Current Mode. Boost PWM Controller with Programmable Frequency, External Soft Start, and Light Load Operation.;
| 型号： | MP3910 |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Peak Current Mode. Boost PWM Controller with Programmable Frequency, External Soft Start, and Light Load Operation. |
| 文件： | 总23页 (文件大小：673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP3910
Peak Current Mode
Boost PWM Controller with Programmable Frequency,
External Soft Start, and Light Load Operation
The Future of Analog IC Technology
DESCRIPTION
FEATURES
5V to 35V Supply Voltage Range(1)
1A 12V MOSFET Gate Driver
External Soft-Start
The MP3910 is a Peak Current Mode PWM
controller that can drive an external MOSFET
capable of handling more than 10A current. It
has a typical operational current of 288µA and
can accommodate flyback, boost for non-
isolated and isolated applications.
Pulse Skipping Operation with Light Load
Programmable
(30kHz-to-400kHz)
Switching
Frequency
Current mode control provides inherently simple
loop compensation and cycle-by-cycle current
limit. Under-voltage lockout, soft-start, internal
regulated supply and slope compensation are
all provided to minimize the external component
count.
Frequency Synchronizable from 80kHz-to-
400kHz
Cycle-by-Cycle Current Limit
Over Voltage Protection
Short Circuit Protection
Over Temperature Protection
Available in an MSOP10 Package
While designed for Flyback applications, the
MP3910 can also be used for other topologies
including Boost, Forward and Sepic. The 1A
gate driver minimizes the power loss of the
external MOSFET while allowing the use of a
wide variety of standard threshold devices.
Additionally, MP3910 has pulse skipping mode
function that improves the efficiency with light
load or no load. It also provides hiccup
protection for OLP, OVP and SCP condition.
APPLICATIONS
Telecom Isolated Power Supplies
Brick Modules
Off-line Controller
General Step Up Applications
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc..
The MP3910 is available in MSOP10 package.
Notes:
1) Refer to “Operation/Internal VCC Regulation” section for <7V
input voltage application.
TYPICAL APPLICATION
DOUT
VIN
CIN
VOUT
COUT
8
RFB
Q1
VIN
9
VCC
10
7
GATE
CVCC
ISENSE
RMODE
RSENSE
MP3910
EN/SYNC
5
2
1
4
EN
GND
FB
ROVH
DFB
RT
SS
COMP
6
3
RT
ROVL
CSS
MP3910 Rev. 1.11
11/6/2014
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
1
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
ORDERING INFORMATION
Part Number*
MP3910GK
Package
MSOP10
Top Marking
M3910
* For Tape & Reel, add suffix –Z (e.g. MP3910GK–Z);
PACKAGE REFERENCE
TOP VIEW
GND
RT
1
2
3
4
5
GATE
VCC
10
9
COMP
FB
VIN
8
7
6
ISENSE
EN/SYNC
SS
ABSOLUTE MAXIMUM RATINGS (2)
VIN to GND.....................................-0.3V to 40V
VCC, GATE to GND.......................–0.3V to 15V
All Other Pins...................................–0.3V to 6V
EN Pin Sink Current.............................. 0.5mA(6)
Thermal Resistance (5)
MSOP10................................150..... 65... °C/W
θJA
θJC
Notes:
2) Exceeding these ratings may damage the device.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
(3)
Continuous Power Dissipation (TA = +25°C)
........................................................... 0.83W
Maximum Operating Frequency............. 500kHz
Storage Temperature............... -55°C to +150°C
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (4)
Supply Voltage VIN ..............................7V to 35V
Supply Voltage with VIN and VCC connected
......................................................5V to 13V
EN Pin Sink Current.................. 0mA to 0.4mA(5)
Operating Junction Temp. (TJ). -40°C to +125°C
6) Refer to “Enable/SYNC Control” section.
MP3910 Rev. 1.11
11/6/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
2
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
ELECTRICAL CHARACTERISTICS
VIN = 18V, TJ = -40°C to 125°C (typical value are tested at 25°C), unless otherwise noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
Input Supply Management
VCC UVLO Threshold
VCC UVLO Hysteresis
Shut Down Current
Quiescent Current
VCC Regulation Voltage
Driving Signal
VUVLO
VUVLO_HYS
Rising edge
3.9
4.17 4.44
350
1
V
mV
μA
μA
V
IS
IQ
VCC
VEN=0V
VFB=1.5V
VCC Load=0mA to 10mA
288
523
10.8
11.8 12.8
Gate Driver Impedance
(Sourcing)
Gate Driver Impedance
(Sinking)
IGATE=-20mA
IGATE=20mA
4.1
2
Ω
Ω
Error Amplifier
Error Amplifier
VFB is +-50mV from FB threshold
1.26V, VCOMP=1.5V
GEA
0.56
75
mA/V
μA
Transconductance
Maximum Amplifier Output
Current
Sourcing and sinking
ISENSE=0V, VFB =1V
ISENSE=1V, Floating COMP
COMP High Voltage
2.4
V
Current Sense
Current Comparator
TLEB
214
ns
Leading Edge Blanking (9)
ISENSE Limit
SCP Limit(7)
Vlimit
VSCP
163
185
350
206
mV
mV
TJ=25°C
Current Sense Amplifier
Gain
ISENSE Bias Current
PWM
GSENSE
ISENSE
∆VCOMP/∆VISENSE
2.7
V/V
0.01 0.15
μA
TJ=25°C
Pulse skipping mode operation
threshold, V(comp)
RT=6.81k
VCOMP(Skipping Mode) (7)
0.95
V
308
25
337
30
214
95
363
35
400
kHz
kHz
ns
Switching Frequency
FSW
RT =80.6k
Minimum ON Time
Maximum Duty Cycle
Soft-start (8)
TON-MIN
DMAX
93
%
RT=6.81k
Charge Current
ISS
54
μA
μA
Over Load Detection
Discharge Current
Discharge Current During
Protection
17.8
1.66
3.65
3.27
μA
V
Charged Threshold Voltage
Over Load Shutdown
Threshold Voltage
Protection Reset Threshold
Voltage
V
0.2
V
MP3910 Rev. 1.11
11/6/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
3
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 18V, TJ= -40°C to 125°C (typical value are tested at 25°C), unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
Voltage Feedback Management
Mode Detection Voltage(7)
Mode Detection Current(7)
Mode Detection Time(7)
185
55
50
mV
μA
μs
V
V
μA
V
1.222 1.237
1.211 1.237
0.01
1.391 1.438
14.4
1.252
1.258
0.15
TJ=25°C
TJ=-40°C to 125°C
VFB=1.237V, TJ= 25°C
FB Reference Voltage
VFB
FB Bias Current
IFB
VOVP
OVP Reference Level
COMP Pull up Resistor
COMP Pull up Voltage(7)
Enable Control
1.479
kꢀ
V
3.6
Enable Rising Threshold
Enable Hysteresis
Enable Turn-off Delay
Enable Input Current
Thermal Protection
Thermal Shutdown(7)
Thermal Hysteresis(7)
Notes:
VEN-RISING
VEN-HYS
TTD-OFF
IEN
1.463 1.628
1.793
5
V
mV
μs
TJ=25°C
VEN=3V
540
20
2.5
μA
TSD
160
20
ºC
ºC
7) Guaranteed by engineering sample characterization.
8) Refer to “soft-start section” for detail function of discharge current and threshold voltage.
9) Same as Minimum On Time.
MP3910 Rev. 1.11
11/6/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
4
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
PIN FUNCTIONS
Pin #
Name
Description
1
GND
Power ground pin which is gate driver return.
Switching frequency set pin. Connect a resistor from this pin to GND to set the
switching frequency (30kHz~400kHz).
2
3
RT
COMP
Feedback pin for isolated solution. Error amplifier output pin for un-isolated solution.
Feedback and OVP monitor pin with respective internal reference voltage for un-
isolated solution. OVP monitor pin for isolated solution. Connected to GND if not used
in isolated solution.
4
5
6
FB
On/off control Input. Internally connected to GND with 1Mꢀ resistor. Apply an external
EN/SYNC clock higher than RT set frequency to the EN pin can synchronize the switching
frequency.
Soft-start pin. Connect one capacitor between this pin and GND to control the duration
of COMP voltage rising. It determines both the soft-start current, and hiccup protection
delay.
SS
Current Sense and application mode (isolated/un-isolated) setting pin. At start-up, this
pin will output one current signal and sense the voltage for mode setting detection.
7
ISENSE During normal operation, this pin will sense the voltage across sense resistor for
current mode control, as well as cycle-by-cycle current limit, over load and short circuit
protection.
8
9
VIN
Input supply. Connect a bypass capacitor from this pin to GND
Internal 12V regulator output. Connect a capacitor between this pin to GND to bypass
the internal regulator.
VCC
10
GATE
This pin drives the external N-channel power MOSFET device.
MP3910 Rev. 1.11
11/6/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
5
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL CHARACTERISTICS
VIN = 18V, TA = 25°C, unless otherwise noted.
MP3910 Rev. 1.11
11/6/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
6
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL CHARACTERISTICS (continued)
VIN = 18V, TA = 25°C, unless otherwise noted.
MP3910 Rev. 1.11
11/6/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
7
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 48V, VOUT = 12V, FSW=250kHz, TA = 25°C, unless otherwise noted.
Efficiency vs.
Efficiency vs.
Load Current,
Load Regulation vs.
Load Current
Load Current
Flyback
VOUT=24V, F =300kHz, Boost
S
0.10
0.05
100
98
96
94
92
90
88
86
84
82
80
100
95
90
85
80
75
70
65
60
VIN=20V
VIN=36V
VIN=12V
VIN=72V
VIN=48V
VIN=72V
0.00
VIN=48V
-0.05
-0.10
VIN=36V
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
LOAD CURRENT(A)
LOAD CURRENT(A)
LOAD CURRENT(A)
Line Regulation vs.
Input Voltage
Gain and Phase vs.
Frequency
IOUT=2.5A
60
180
140
100
60
0.10
0.05
40
20
I
OUT=0A
20
0
0.00
IOUT=1A
-20
-20
-40
-60
-60
-0.05
-0.10
-100
-140
-180
IOUT=2.5A
35 40 45 50 55 60 65 70 75
INPUT VOLTAGE(V)
1000
10000
100000
FREQUENCY (Hz)
MP3910 Rev. 1.11
11/6/2014
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8
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 48V, VOUT = 12V, FSW=250kHz, TA = 25°C, unless otherwise noted.
MP3910 Rev. 1.11
11/6/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
9
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 48V, VOUT = 12V, FSW=250kHz, TA = 25°C, unless otherwise noted.
MP3910 Rev. 1.11
11/6/2014
www.MonolithicPower.com
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© 2014 MPS. All Rights Reserved.
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
FUNCTION BLOCK DIAGRAM
VIN
VIN
VIN
VCC
Enable
Control
Regulator
EN/SYNC
UVLO
VOUT
Clock
Oscillator and
Slope
Compensation
Slope Comp
RT
-
GATE
GND
PWM
Logic
Driver
Burst mode
3.6V
+
PWM
R
MODE
Comparator
OL/OV/SC
Protection
Rsense
OCP
0.7V
3R
COMP
MODE
Detection
7R
3.65V
Current Sense
ISENSE
+
Gain
Amplifier
54
A
Soft-start
-
SS
OCP
0.185V
+
-
50us
timer
OLP Timer
Protection
1.66
A
17.8 A
VOUT
FB
EA Out
+
-
SCP
1.237V
+
-
0.35V
Q
EA
Error Amplifier
3.27V
+
-
OLP
OL/OV/SC
Protection
R
S
OVP
+
OVP
-
1.438V
0.2V
+
-
Restart
Figure 1: Functional Block Diagram
MP3910 Rev. 1.11
11/6/2014
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11
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
OPERATION
When the Enable is high, the capacitor at VCC
pin is charged through the VIN pin. VCC has its
own UVLO protection. This UVLO’s rising
threshold is 4.17V with a hysteresis of 350mV.
When the voltage at VCC pin crosses the VCC
UVLO, the controller is enabled and all the
internal circuitry is powered by VCC source. As
the capacitor is charged, VCC voltage
increases until reaching 12V regulated voltage
if the VIN voltage is high enough.
The MP3910 uses a programmable frequency,
peak current mode architecture to regulate the
feedback voltage. The operation of the MP3910
can be understood with the block diagram of
Figure 1.
PWM Operation
At the beginning of each cycle the external N-
channel MOSFET is turned on, forcing the
current in the inductor to increase. The current
through the FET can be sensed and when the
sum voltage of amplified ISENSE signal and
slope signal rises above the voltage set by the
COMP pin, the external FET is turned off. The
inductor current then flows to the output
capacitor through the schottky diode. The
inductor current is controlled by the COMP
voltage, which itself is controlled by the output
voltage. Thus the output voltage controls the
inductor current to satisfy the load. This current
mode architecture improves transient response
and control loop stability over voltage mode
architecture.
When input voltage is lower than 12V, VCC
voltage will be lower than Vin and 12V due to
LDO drop. For normal startup, the input voltage
should be higher than 7V. If Vcc and Vin is
connected together, MP3910 can start-up from
5V but the max input voltage shouldn’t be
higher than 13 V. Vcc voltage can not be higher
than Vin voltage if both Vin and Vcc are
powered by external source because there is
one diode from Vcc to Vin.
Feedback Loop Setting
To be coincident for different design in isolated
and un-isolated application, MP3910 can
feedback the output signal through either of FB
pin or COMP pin by different setting on ISENSE
pin.
Pulse Skipping Mode
At light load condition, the MP3910 goes into
pulse skipping mode to improve light load
efficiency. Pulse skipping decision is based on
its internal COMP voltage. If COMP is lower
than the internal sleep threshold with typical
0.95V, a PAUSE command is generated to
block the turn-on clock pulse so the power
MOSFET is turned off immediately, saving gate
driving and switching losses. This PAUSE
command also puts the whole chip into sleep
mode, consuming very low quiescent current to
further improve the light load efficiency. The
gate driver output remains low until COMP
voltage is higher than the sleep threshold, then
PAUSE signal is reset so the chip is back into
normal PWM operation.
For un-isolated application such as boost mode,
MP3910 integrates one error amplifier which
can amplify the output error signal from FB pin,
COMP pin needs one RC network for
compensation. For isolated application such as
fly-back mode, the feedback signal from opto-
coupler has been amplified by secondary
circuitry, directly connect the signal to COMP
pin will make loop compensation much easier
by eliminating the primary side amplifier.
The different feedback loop can be set by
different ISENSE pin connection. At the
beginning of part enabled, ISENSE pin will
output 50us current pulse with typical value of
55uA, as showed in Figure2, if the reflected
voltage on ISENSE pin is higher than 185mV,
MP3910 will disable the internal error amplifier
between FB and COMP pins and pull up COMP
Internal VCC Regulator
MP3910 operates with supply voltage from 7V
to 35V. An internal regulator is applied to
regulate the power at VCC pin for supplying the
internal circuitry of the controller, including the
gate driver. The regulator has a nominal output
voltage of 12V at VCC pin and must be
bypassed with no less than 1μF capacitor.
MP3910 Rev. 1.11
11/6/2014
www.MonolithicPower.com
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12
MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
pin to 3.6V source with 14.4kꢀ resistor, the
external resistor from the RT pin to ground. The
value of RT can be estimated from:
feedback signal can be connected to COMP pin
directly. If the detection voltage is lower than
185mV, MP3910 will enable the internal error
amplifier but turn off the pull up resistor. Then
COMP pin is just one output pin of error
amplifier and the feedback signal should be
connected to FB pin.
2.35103
RT
fSW
RT is in kꢀ and fSW is in kHz.
The frequency setting resistor value shouldn’t
be too large for noise immunity consideration. It
is recommended to set the frequency within
30kHz to 400kHz.
VIN
55µA
Enable/SYNC Control
EN/SYNC is a digital control pin that turns
MP3910 on and off. Drive EN high to turn on
the controller; drive it low to turn it off. An
internal 1Mꢀ resistor from EN/SYNC to GND
allows EN/SYNC to be floated to shut down the
chip.
50µs
GATE
Start up
+
-
High / Low
I SENSE
0.185V
R MODE
R SENSE
V SENSE
= 55µA x(RMODE+R SENSE)
For external clock synchronization, connect a
clock with a frequency higher than RT set
frequency and between 80kHz to 400kHz, the
internal clock rising edge will synchronize with
the external clock rising edge. Select an
external clock pulse signal with low level width
less than 10μs, or else MP3910 may treat it as
EN power off.
Figure 2: Feedback Mode Setting
Generally, it is recommended to place one
resistor with 5Kohm~10Kohm between ISENSE
pin and current sense resistor for the feedback
mode through directly COMP pin, and connect
ISENSE pin to current sense resistor directly for
feedback mode through FB pin.
EN/SYNC pin can not be connected to voltage
higher than 6V, when voltage source is higher
than 6V, a pull up resistor is recommend. For
resistor pull up condition, an internal zener
diode clamps the voltage at EN/SYNC pin. The
maximum pull-up current for the internal clamp
zener (assuming clamped at 6V) should be less
than 0.4mA. Typically 100k pull up resistor is
recommended. There is no problem if the clamp
voltage is distributed at higher than 6V if pull up
current is less than 0.4mA.
Soft-Start
MP3910 uses one external capacitor on SS pin
to control COMP voltage rising for soft-start.
When the chip starts, the capacitor on SS pin is
charged by one 54uA current source at a slow
pace set by the capacitance. When the SS
voltage is lower than the external COMP
voltage, SS overrides the COMP signal so the
PWM comparator uses SS instead of COMP as
the PWM turn off reference. When SS is higher
than COMP voltage, COMP gains the control
back and the soft start finishes. The soft-start
can reduce voltage stresses and surge currents
during start up, also prevent the converter
output voltage from overshooting during startup.
Soft start occurs during the start up time and
protection recovery time after OLP, SCP and
OVP. During normal condition, the SS voltage
is clamped at 3.65V.
Current Sense and Over Current Protection
The MP3910 is peak current mode controller.
The current through the external FET can be
sensed through a sensing resistor used in
series with the source terminal of FET. The
sensed voltage on ISENSE pin is then amplified
and fed to the high speed current comparator
for the current mode control purpose. The
current comparator takes this sensed voltage
(plus slope compensation) as one of its inputs,
then compares the power switch current with
the COMP voltage. When the amplified current
Programmable Oscillator
The MP3910 oscillating frequency is set by an
MP3910 Rev. 1.11
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
signal is higher than the COMP voltage, the
comparator output is low, turning off the power
MOSFET.
When the output is shorted to the ground, the
part works in OCP mode and current is limited
cycle-by-cycle, the part may run into OLP
protection.
If the voltage on the ISENSE pin exceeds the
current-limit threshold voltage with typical value
of 185mV, MP3910 will turn off the GATE
output for that cycle, until the internal oscillator
starts the next cycle, and sense current again.
MP3910 limits the current of MOSFET cycle-by-
cycle.
But if the peak current cannot be limited by
185mV ISENSE voltage in every cycle due to
leading edge blanking (LEB) time, the current
may run out of control and transformer may run
into saturation. If the monitored ISENSE voltage
reaches 0.35V, the part will turn off the GATE
out and run into hiccup mode by discharge SS
capacitor with 1.66uA current. It will also re-
start up if SS voltage is discharged to 0.2V.
Over Load Protection (OLP)
The peak current is limited cycle-by-cycle, if the
load continues increasing after triggering OCP
protection, the output voltage will decrease and
the peak current will trigger OCP every cycle.
MP3910 set the over load detection by continue
monitoring the ISENSE pin voltage.
In case the short circuit is removed, the output
voltage will recover only after the next new
restart cycle.
For boost converter, it has no method to limit
current from the input to the output in the
condition of output short circuit. If protection
from this type condition is desired, it is
necessary to add some secondary protection
circuit.
Once the SS voltage is charged to 3.65V after
start up, the OLP protection is enabled. If an
OCP signal is detected, the soft-start charging
current is disabled and one over current
discharge source is enabled, the SS voltage
drops with the rate of 17.8uA current. At the
same time, one 50us one-shot timer is activated
and it remains active for 50µs after the OCP
condition stops. The 17.8uA discharge source
cannot be turn off until the one-shot timer
becomes inactive. If the OCP disappears before
at least 50us prior than the SS capacitor
discharging to 3.27V, MP3910 will run back to
normal work condition and the SS capacitor will
be re-charged to 3.65V with 54uA rate. If the
SS capacitor is discharged to 3.27V, MP3910
will register it as over load condition and turn off
the gate output until next re-start cycle. At the
same time, 17.8uA discharge current is
disabled and the 1.66uA over load discharge
source is enabled. After the SS voltage is
discharged to 0.2V, MP3910 will re-start up with
new soft-start cycle. This is hiccup mode
protection.
Over Voltage Protection
For isolated-flyback application, the positive
plateau of auxiliary winding voltage is
proportional to the output voltage, MP3910
features the over voltage protection by using
the auxiliary winding voltage instead of directly
monitoring the output voltage. The auxiliary
voltage can be monitored by FB pin through
resistor divider, once the voltage is higher than
OVP reference voltage, MP3910 turns off the
GATE output and discharge SS voltage with
1.66uA current until SS voltage is lower than
0.2V, then the part will initial one new re-start
cycle.
To avoid the mis-trigger due to the oscillation of
the leakage inductance and the parasitic
capacitance, the OVP sampling has a TOVPS
blanking with 500ns typical value. For some
oscillation condition, one external filter is
necessary to work together with the 500ns LEB
time.
The OLP detection function is disabled after the
SS voltage is discharged to be lower than
3.27V and it will be re-enabled after SS voltage
is re-charged to 3.65V. So the OLP only occurs
after the soft-start is completed.
For un-isolated solution, the DC output voltage
is applied to FB pin and it can easily detect the
OVP condition.
Short Circuit Protection
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
Thermal Shutdown
Thermal shutdown is implemented to prevent the
chip from thermally running away. When the
silicon die temperature is higher than its upper
threshold, it shuts down the whole chip. When
the temperature is lower than its lower threshold,
thermal shutdown is gone so the chip is enabled
again with a new start-cycle.
MP3910 Rev. 1.11
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
APPLICATION INFORMATION
The output capacitor’s characteristics also
affect system stability. For best results, use
COMPONENT SELECTION
MP3910 can be used for topologies including
Flyback, Boost and Sepic. Refer to figure 5 and
below introduction for typical external
component selection of boost converter.
ceramic, tantalum, or low-ESR electrolytic
capacitors. For ceramic capacitors, the
capacitance dominates the impedance at the
switching frequency, and so the output voltage
ripple is mostly independent of the ESR. The
output voltage ripple is estimated as:
Setting the Output Voltage
Set the output voltage by selecting the resistive
voltage divider ratio. If we use 10kꢀ for the low-
side resistor (RFBL) of the voltage divider, we
can determine the high-side resistor (RFBH) by
the equation:
V
IN
1
VOUT
VOUT ILOAD
COUT F
SW
Where ∆VOUT is the output ripple voltage, VIN
and VOUT are the DC input and output voltage,
respectively, ILOAD is the load current, FSW is the
switching frequency, and COUT is the value of
the output capacitor.
RFBL (VOUT VREF
)
RFBH
VREF
Where VOUT is the output voltage
For RFBL=10kꢀ, VOUT=24V and VREF=1.237V,
then RFBH=182kꢀ.
For tantalum or low-ESR electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency, so the output ripple is
estimated as:
Selecting the Soft-start Capacitor
MP3910 ramps external capacitor voltage on
SS pin to control COMP voltage, which
determines inductor peak current. The SS pin
voltage can be calculated by blew equation:
V
IN
1
VOUT
ILOAD RESR VOUT
VOUT ILOAD
COUT F
V
SW
IN
54A
Css
Vss
Tss
Where RESR is the equivalent series resistance
of the output capacitors. Choose an output
capacitor that satisfies the output ripple and
load transient requirements of the design.
When OLP, SCP, OVP occurs, the SS acts as a
timer. Once the protection occurs, the 1.66uA
current discharges SS cap for hiccup protection.
Selecting the Inductor and Current Sensing
Resistor
Selecting the Input Capacitor
An input capacitor is required to supply the AC
ripple current to the inductor, while limiting
noise at the input source. A low ESR capacitor
is required to keep the noise to the IC at a
minimum. Ceramic capacitors are preferred, but
tantalum or low-ESR electrolytic capacitors may
also suffice. When using tantalum or electrolytic
capacitors, a small high quality ceramic
capacitor, i.e. 0.1uF, should be place close to
IC. The capacitance for boost input can be
calculated as:
The inductor is required to transfer the energy
between the input source and the output
capacitors. A larger value inductor results in
less ripple current that results in lower peak
inductor current, and therefore reduces the
stress on the power MOSFET. However, the
larger value inductor has a larger physical size,
higher series resistance, and lower saturation
current.
A good rule of thumb is to allow the peak-to-
peak ripple current to be approximately 30-50%
of the maximum input current. Make sure that
the peak inductor current is below 80% of the
IC’s maximum current limit at the operating duty
cycle to prevent loss of regulation. Make sure
that the inductor does not saturate under the
worst-case load transient and startup conditions.
The required inductance value can be
calculated by:
I
CIN
8 V FSW
IN
Where ΔI is the peak-to-peak inductor ripple
current and ΔVIN is the input voltage ripple.
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage. For best results, use low-ESR
capacitors to minimize the output voltage ripple.
MP3910 Rev. 1.11
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
Where K is the on-resistance temperature
coefficient of the MOSFET. So it is smaller, it is
better.
V (VOUT V )
VOUT FSW I
IN
IN
L
VOUT ILOAD
I
IN
V
The switching loss is related to QGD and QGS1
which determine the commutation time. QGS1 is
the charge between the threshold voltage and
the plateau voltage when a driver charges the
gate, which can be read in the chart of VGS vs.
QG of the MOSFET datasheet. QGD is the charge
during the plateau voltage. These two
parameters are needed to estimate the turn on
and turn off loss.
IN
I (30% 50%)I
IN
Where ILOAD is the load current, ΔI is the peak-
to-peak inductor ripple current and η is the
efficiency. For a typical design, boost converter
efficiency can reach 85%~95%.
The switch current is usually used for the peak
current mode control. In order to avoid hitting
the current limit, the voltage across the sensing
resistor RSENSE should be less than 80% of the
worst case current limit voltage, 185mV.
0.80.185
QGS1 R
VDR VTH
QGD RG
VDR VPLT
P
G VDS I F
VDS I F
IN SW
SW
IN
SW
Where VTH is the threshold voltage, VPLT is the
plateau voltage, RG is the gate resistance, VDS
is the drain-source voltage. Please note that the
switching loss is the most difficult part in the
loss estimation. The formula above provides a
simple physical expression.
RSENSE
IL(PEAK)
Where IL(PEAK) is the peak value of the inductor
current.
Selecting the Power MOSFET
The MP3910 is capable of driving a wide variety
of N-Channel power MOSFETS. The critical
parameters of selecting a MOSFET are:
On the other hand, small QG will cause fast turn
on/off speed which determines the spike and
kick.
1. Maximum drain to source voltage, VDS(MAX)
2. Maximum current, ID(MAX)
3. On-resistance, RDS(ON)
4. Gate source charge QGS and gate drain
charge QGD
The turn on threshold voltage VTH is also
important. GATE pin is powered by VCC power,
so the VTH must be lower than VCC voltage. For
worst case, VCC voltage is at the 3.55V falling
UVLO, so the MOSFET VTH should be much
lower than this voltage to get enough driving
capability.
5. Total gate charge, QG
6. Turn on threshold VTH
Ideally, the off-state voltage across the
MOSFET is equal to boost output voltage.
Considering the voltage spike when it turns off,
VDS(MAX) should be greater than 1.5 times of the
output voltage.
Selecting the Diode
The boost output rectifier diode supplies current
to the inductor when the MOSFET is off. Use a
Schottky diode to reduce losses due to the
diode forward voltage and recovery time. The
diode should be rated for a reverse voltage
greater than the expected output voltage. The
average current rating must exceed the
maximum expected load current, and the peak
current rating must exceed the peak inductor
current.
The maximum current through the power
MOSFET happens when the input voltage is
minimum and the output power is maximum.
The maximum RMS current through the
MOSFET is given by:
VOUT V
IN
IRMS I
IN
VOUT
Boost Converter Compensation Design
The output of the transconductance error
amplifier (COMP) is used to compensate the
regulation control system. The system uses two
poles and one zero to stabilize the control loop.
The poles are FP1, which is set by the output
capacitor (COUT) and load resistance, and FP2
The current rating of the MOSFET should be
greater than 1.5 times IRMS,
The on resistance of the MOSFET determines
the conduction loss, which is given by:
P
IR2MS RDS(ON) K
LOSS
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
which starts from origin. The zero (FZ1) is set by
the compensation capacitor (CCOMP) and the
compensation resistor (RCOMP). These
should be added between COMP pin and GND.
Then a pole, formed by CPOLE and RCOMP
should be placed at the ESR zero to cancel the
,
parameters are determined by the equations:
1
adverse effect.
1
CPOLE
F
P1
2 RCOMP F
2 COUT RLOAD
ESRZ
1
PCB Layout Guide
FZ1
2 CCOMP RCOMP
High frequency switching regulators require
very careful layout for stable operation and low
noise. For boost topology layout:
Where RLOAD is the load resistance.
The DC mid-band loop gain is:
1. Keep the high current path as short as
possible between the MOSFET drain,
output diode, output capacitor and current
sense resistor for minimal noise and ringing.
0.5GEA V RLOAD VREF RCOMP
IN
AVDC
VO2UT RSENSE GSENSE
Where VREF is the voltage reference, 1.237V.
GSENSE is the current sense amplifier gain and
GEA is the error amplifier transconductance.
2. The VCC capacitor must be placed close to
the VCC pin for best decoupling.
The ESR zero in this example locates at very
high frequency. Therefore, it is not taken into
design consideration.
3. All feedback components must be kept
close to the FB pin to prevent noise injection
on the FB pin trace.
There is also a right-half-plane zero (FRHPZ) that
exists in continuous conduction mode (inductor
current does not drop to zero on each cycle)
step-up converters. The frequency of the right
half plane zero is:
4. The ground return of the input and output
capacitors should be tied to the GND pin
with single point connection.
Refer to Figure 3 for boost layout, which is
referenced to schematic in Figure 5
V2 RLOAD
IN
F
RHPZ
2 L VO2UT
D1
The right-half-plane zero increases the gain and
reduces the phase simultaneously, which
results in smaller phase margin and gain
margin. The worst case happens at the
condition of minimum input voltage and
maximum output power.
SW
L1
Q1
COUT
Vo
GND
CVCC
RSENSE
REN
In order to achieve system stability, Fz1 is
placed close to FP1 to cancel the pole. RCOMP is
adjusted to change the voltage gain. Make sure
the bandwidth FC is about 1/10 of the lower one
of the ESR zero and the right-half-plane zero.
CIN
CSS
MP3910
CIN2
RT
1
1
2 COUT RLOAD 2 CCOMP RCOMP
VO2UT 2 COUT FC RSENSE GSENSE
RFBH
Vin
GND
CCOMP
RCOMPRFBL
RCOMP
GEA VREF V
IN
Top Layer
Based on these equations, RCOMP and CCOMP
can be solved.
In cases where the ESR zero is in a relatively
low frequency region and results in insufficient
gain margin, an optional capacitor (CPOLE
)
MP3910 Rev. 1.11
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
For flyback topology PCB layout:
1. Keep the input loop as short as possible
between input cap, transformer, MOSFET,
current sense resistor and GND plane for
minimal noise and ringing.
2. Keep the output loop between rectifier diode,
output cap and transformer as short as
possible.
3. The clamp loop circuit between DSN, CSN
and transformer should be as small as
possible
4. The VCC capacitor must be placed close to
the VCC pin for best decoupling.
5. The feedback trace should be far away from
noise source such as drain of power FET.
Bottom Layer
6. Use single point connection between power
GND and signal GND.
Figure 3: Boost PCB Layout
Refer to figure 4 for flyback layout, which is
referenced to schematic on page 1. For more
detail information, refer to flyback EVB
datasheet.
Vin
T1
CIN RSN
CSN
DOUT
DSN
GND
RSENSE
GND
Vout
COUT
Q1
Design Example
CVCC
U1
RT
Below is a design example following the
application guidelines for the specifications:
1
10
9
2
3
4
5
8
RMODE
7
6
DFB
ROVL
ROVH
CSS
Table 1: Boost Design Example
CIN2
U2
VIN
VOUT
fSW
10-20V
24V
300kHz
RFB
Top Layer
The detailed application schematic is shown in
Figure 8. And there is another design example
for fly-back application in Figure 6.
Input
GND
Output
GND
Table 2: Fly-back Design Example
VIN
VOUT
fSW
36-72V
12V
250kHz
The typical performance and circuit waveforms
of flyback have been shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
Evaluation Board Datasheets.
Bottom Layer
Figure 4: Fly-back PCB Layout
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
Figure 5: Boost Design and Layout Reference Schematic
MP3910 Rev. 1.11
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL APPLICATION CIRCUITS
Figure 6: Typical Fly-back Converter Application Schematic
Figure 7: Typical Sepic Converter Application Schematic
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL APPLICATION CIRCUITS (continued)
L1
24V@2A
10-20V
D2
0.47uH
L2
1
1
10uH
SS5P4
Vin
Vout
C1
10uF
C8
10uF
C9
10uF
C10
10uF
C4
R1
GND
453k
GND
GND
GND
1uF
GND
5
C7
4.7uF
1
1
EN/SYNC
GND
GATE
GND
R2
100k
EN
U1
1
6
2
10
7
Q1
SIR462
MP3910
SS
GND
D1
GND
GND
C2
R8 4.7R
0.22uF
RT
ISENSE
R3
8.06k
GND
R9
0.025
GND
R5
GND
R4
7.5K
180K
R6
10k
C5
15nF
GND
GND
Figure 8: Typical Boost Converter Application Schematic-High Input Voltage Condition
L1
24V@1A
5-10V
D2
0.47uH
L2
1
1
10uH
SS5P4
Vin
Vout
C1
10uF
C9
10uF
C10
10uF
C4
R1
GND
160k
GND
GND
1uF
GND
5
C7
4.7uF
1
1
EN/SYNC
GND
GATE
GND
R2
100k
EN
U1
1
6
2
10
7
Q1
SIR462
MP3910
SS
GND
D1
GND
GND
C2
R8 4.7R
0.22uF
RT
ISENSE
R3
8.06k
GND
R9
0.02
GND
R5
GND
R4
4.99K
180K
R6
10k
C5
22nF
GND
GND
Figure 9: Typical Boost Converter Application Schematic-Low Input Voltage Condition
MP3910 Rev. 1.11
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MP3910 –PEAK CURRENT MODE BOOST CONTROLLER
PACKAGE INFORMATION
MSOP10
0.114(2.90)
0.122(3.10)
6
10
0.187(4.75)
0.199(5.05)
0.114(2.90)
0.122(3.10)
PIN 1 ID
(NOTE 5)
5
1
0.007(0.18)
0.011(0.28)
0.0197(0.50)BSC
BOTTOM VIEW
TOP VIEW
GAUGE PLANE
0.010(0.25)
0.030(0.75)
0.037(0.95)
0.043(1.10)MAX
SEATING PLANE
0.002(0.05)
0.004(0.10)
0.008(0.20)
0.016(0.40)
0.026(0.65)
0o-6o
0.006(0.15)
FRONT VIEW
SIDE VIEW
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS
IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
0.181(4.60)
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) PIN 1 IDENTIFICATION HAS THE HALF OR FULL CIRCLE OPTION.
6) DRAWING MEETS JEDEC MO-817, VARIATION BA.
7) DRAWING IS NOT TO SCALE.
0.040(1.00)
0.012(0.30)
0.0197(0.50)BSC
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP3910 Rev. 1.11
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23
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