MP3910AGS [MPS]
Peak Current Mode Boost PWM Controller with Programmable Frequency, External Soft Start Light Load Operation, and SOIC8 Package;
| 型号： | MP3910AGS |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Peak Current Mode Boost PWM Controller with Programmable Frequency, External Soft Start Light Load Operation, and SOIC8 Package |
| 文件： | 总21页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP3910A
Peak Current Mode Boost PWM Controller
with Programmable Frequency, External Soft Start
Light Load Operation, and SOIC8 Package
The Future of Analog IC Technology
DESCRIPTION
FEATURES
9V to 14V Supply Voltage Range
1A MOSFET Gate Driver
External Soft-Start
The MP3910A is a Peak Current Mode PWM
controller that can drive an external MOSFET
capable of handling more than 10A current. It
has a typical operational current of 400µA and
can accommodate flyback, boost for non-
isolated and isolated applications.
Pulse Skipping Operation with Light Load
Programmable
Switching
Frequency
(30kHz-to-400kHz)
Cycle-by-Cycle Current Limit
Over Voltage Protection
Short Circuit Protection
Over Temperature Protection
Available in SOIC8 Package
Current mode control provides inherently simple
loop compensation and cycle-by-cycle current
limit. Under-voltage lockout, soft-start and slope
compensation are all provided to minimize the
external component count.
While designed for Flyback applications, the
MP3910A can also be used for other topologies
including Boost, Forward and Sepic. The 1A
gate driver minimizes the power loss of the
external MOSFET while allowing the use of a
wide variety of standard threshold devices.
Additionally, MP3910A has pulse skipping
mode function that improves the efficiency with
light load or no load. It also provides hiccup
protection for OLP, OVP and SCP condition.
APPLICATIONS
Telecom Isolated Power Supplies
Brick Modules
Off-line Controller
General Step Up Applications
PoE Powered Devices
All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For
MPS green status, please visit MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
The MP3910A is available in SOIC8 package.
TYPICAL APPLICATION
MP3910A Rev. 1.11
2/14/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
1
MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP3910AGS
SOIC-8
See Below
* For Tape & Reel, add suffix –Z (e.g. MP3910AGS–Z);
TOP MARKING
MP3910A: product code of MP3910AGS;
LLLLLLLL: lot number;
MPS: MPS prefix;
Y: year code;
WW: week code:
PACKAGE REFERENCE
MP3910A Rev. 1.11
2/14/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
2
MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
ABSOLUTE MAXIMUM RATINGS (1)
VCC, GATE to GND.......................–0.3V to 16V
All Other Pins...................................–0.3V to 6V
Thermal Resistance (4)
SOIC-8....................................90...... 45... °C/W
θJA
θJC
Notes:
(2)
Continuous Power Dissipation (TA = +25°C)
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
........................................................... 1.38W
Maximum Operating Frequency............. 500kHz
Storage Temperature............... -55°C to +150°C
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Recommended Operating Conditions (3)
Supply Voltage VCC .............................9V to 14V
Operating Junction Temp. (TJ). -40°C to +125°C
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MP3910A Rev. 1.11
2/14/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
3
MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
ELECTRICAL CHARACTERISTICS
VCC = 12V, TJ = -40°C to125°C (typical values are tested at 25°C), unless otherwise noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
Input Supply Management
VCC UVLO Threshold
VCC UVLO Hysteresis
Quiescent Current
Driving Signal
VUVLO
VUVLO HYS
IQ
Rising edge
VFB=1.35V
7.4
8
650
400
8.7
V
mV
μA
520
Gate Driver Impedance
(Sourcing)
Gate Driver Impedance
(Sinking)
I
GATE=-20mA
4.1
2
Ω
Ω
IGATE=20mA
Error Amplifier
Error Amplifier
VFB is +-50mV from FB Reference,
VCOMP=1.5V
GEA
0.56
75
mA/V
μA
Transconductance
Maximum Amplifier Output
Current
Sourcing or Sinking
I
SENSE=0V, VFB =1V
COMP High Voltage
2.4
V
ISENSE=1V, Floating COMP
Current Sense
Current Comparator
TLEB
214
398
206
ns
Leading Edge Blanking (7)
ISENSE Limit
SCP Limit(5)
Vlimit
VSCP
TJ=25°C
163
185
350
mV
mV
Current Sense Amplifier
Gain
GSENSE
∆VCOMP/∆VISENSE
2.7
V/V
ISENSE Bias Current
PWM
ISENSE
0.01 0.15
μA
TJ=25°C
Pulse skipping mode operation
threshold, V(comp)
RT=6.81k
VCOMP (Skipping Mode) (5)
0.95
V
308
25
337
30
214
95
363
35
398
kHz
kHz
ns
Switching Frequency
FSW
RT =80.6k
Minimum ON Time
Maximum Duty Cycle
Soft-start (6)
TON-MIN
DMAX
93
%
RT=6.81k
Charge Current
ISS
54
μA
μA
Over Load Detection
Discharge Current
Discharge Current During
Protection
17.8
1.66
3.65
2.9
μA
V
Charged Threshold Voltage
Over Load Shutdown
Threshold Voltage
Protection Reset Threshold
Voltage
V
0.2
V
MP3910A Rev. 1.11
2/14/2017
www.MonolithicPower.com
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC = 12V, TJ= -40°C to125°C(typical at a temperature range of 25°C), unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
Voltage Feedback Management
Mode Detection Voltage(5)
185
55
mV
Mode Detection Current(5)
Mode Detection Time(5)
μA
180
μs
1.222 1.237
1.211 1.237
0.01
1.391 1.438
14.4
1.252
1.258
0.15
V
V
μA
V
TJ=25°C
TJ=-40°C to 125°C
VFB=1.237V, TJ= 25°C
FB Reference Voltage
VFB
FB Bias Current
OVP Reference Level
COMP Pull up Resistor
IFB
VOVP
1.479
kꢀ
COMP Pull up Voltage(5)
3.6
V
Thermal Protection
Thermal Shutdown(5)
TSD
160
20
ºC
ºC
Thermal Hysteresis(5)
Notes:
5) Guaranteed by engineering sample characterization.
6) Refer to “soft-start section” for detail function of discharge current and threshold voltage.
7) It is same as Minimum on Time.
MP3910A Rev. 1.11
2/14/2017
www.MonolithicPower.com
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5
MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
PIN FUNCTIONS
Pin #
Name
Description
1
GND
Power ground pin which is gate driver return.
Switching frequency set pin. Connect a resistor from this pin to GND to set the
switching frequency (30kHz~400kHz).
2
3
RT
COMP
Feedback pin for isolated solution. Error amplifier output pin for un-isolated solution.
Feedback and OVP monitor pin with respective internal reference voltage for un-
isolated solution. OVP monitor pin for isolated solution. Connected to GND if not used
in isolated solution.
4
5
FB
SS
Soft-start pin. Connect one capacitor between this pin and GND to control the duration
of COMP voltage rising. It determines both the soft-start current, and hiccup protection
delay.
Current Sense and application mode (isolated/un-isolated) setting pin. At start-up, this
pin will output one current signal and sense the voltage for mode setting detection.
6
ISENSE During normal operation, this pin will sense the voltage across sense resistor for
current mode control, as well as cycle-by-cycle current limit, over load and short circuit
protection.
IC Input supply. Connect a bypass capacitor from this pin to GND. VCC voltage should
be lower than 14V in application.
7
8
VCC
GATE
This pin drives the external N-channel power MOSFET device.
MP3910A Rev. 1.11
2/14/2017
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL CHARACTERISTICS
VCC = 12V, TA = 25°C, unless otherwise noted.
MP3910A Rev. 1.11
2/14/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
7
MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 48V, VOUT = 12V, FSW=250kHz, Fly-back Mode, TA = 25°C, unless otherwise noted.
MP3910A Rev. 1.11
2/14/2017
www.MonolithicPower.com
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 48V, VOUT = 12V, FSW=250kHz, Fly-back Mode, TA = 25°C, unless otherwise noted.
Steady State
IOUT=0A
Steady State
IOUT=2.5A
Startup Through V
IOUT=0A
IN
V
/AC
V
/AC
OUT
OUT
50mV/div.
50mV/div.
V
OUT
5V/div.
V
V
IN
IN
50V/div.
50V/div.
V
IN
20V/div.
V
V
SW
SW
V
SW
50V/div.
50V/div.
100V/div.
I
I
I
TRANS-PRI
1A/div.
TRANS-PRI
5 A/div.
TRANS-PRI
5A/div.
Startup Through V
IOUT=2.5A
Shutdown Through V
IOUT=0.01A
Shutdown Through V
IN
IOUT=2.5A
IN
IN
V
V
V
OUT
OUT
OUT
5V/div.
5V/div.
5V/div.
V
V
V
IN
IN
IN
20V/div.
20V/div.
20V/div.
V
V
V
SW
SW
SW
100V/div.
50V/div.
50V/div.
I
I
L
L
I
500mA/div.
2A/div.
TRANS-PRI
5A/div.
SCP Recovery
IOUT=short->0A
SCP Entry
IOUT=0A->short
V
/AC
OUT
50mV/div.
V
V
OUT
OUT
5V/div.
5V/div.
V
V
IN
IN
50V/div.
50V/div.
V
V
SW
SW
100V/div.
100V/div.
I
OUT
2A/div.
I
I
TRANS-PRI
TRANS-PRI
5A/div.
5A/div.
MP3910A Rev. 1.11
2/14/2017
www.MonolithicPower.com
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9
MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
FUNCTION BLOCK DIAGRAM
VIN
VCC
Clock
UVLO
VOUT
Oscillator and
RT
Slope
Slope Comp
Compensation
-
GATE
GND
PWM
Logic
Driver
Burst mode
3.6V
+
PWM
R
MODE
Comparator
OL/OV/SC
Protection
Rsense
OCP
0.7V
3R
COMP
MODE
Detection
7R
3.65V
Current Sense
ISENSE
+
Gain
Amplifier
54uA
Soft-start
-
SS
OCP
0.185V
+
-
50us
timer
OLP Timer
17.8uA
Protection
1.66uA
VOUT
EA Out
+
-
SCP
1.237V
+
-
0.35V
Q
EA
FB
Error Amplifier
2.9V
+
-
OLP
OL/OV/SC
Protection
R
S
OVP
+
-
OVP
1.438V
0.2V
+
-
Restart
Figure 1: Functional Block Diagram
MP3910A Rev. 1.11
2/14/2017
www.MonolithicPower.com
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
OPERATION
voltage clamp circuit is needed to regulate VCC
voltage in appropriate range.
The MP3910A uses a programmable frequency,
peak current mode architecture to regulate the
feedback voltage. The operation of the
MP3910A can be understood with the block
diagram of Figure 1.
Feedback Loop Setting
To be coincident for different design in isolated
and un-isolated application, MP3910A can
feedback the output signal through either of FB
pin or COMP pin by different setting on ISENSE
pin.
PWM Operation
At the beginning of each cycle the external N-
channel MOSFET is turned on, forcing the
current in the inductor to increase. The current
through the FET can be sensed and when the
sum voltage of amplified ISENSE signal and
slope signal rises above the voltage set by the
COMP pin, the external FET is turned off. The
inductor current then flows to the output
capacitor through the schottky diode. The
inductor current is controlled by the COMP
voltage, which itself is controlled by the output
voltage. Thus the output voltage controls the
inductor current to satisfy the load. This current
mode architecture improves transient response
and control loop stability over voltage mode
architecture.
For un-isolated application such as boost mode,
MP3910A integrates one error amplifier which
can amplify the output error signal from FB pin,
COMP pin needs one RC network for
compensation. For isolated application such as
fly-back mode, the feedback signal from opto-
coupler has been amplified by secondary
circuitry, directly connect the signal to COMP
pin will make loop compensation much easier
by eliminating the primary side amplifier.
The different feedback loop can be set by
different ISENSE pin connection. At the
beginning of part enabled, ISENSE pin will
output 180us current pulse with typical value of
55uA, as showed in Figure 2, if the reflected
voltage on ISENSE pin is higher than 185mV,
MP3910A will disable the internal error amplifier
between FB and COMP pins and pull up COMP
pin to 3.6V source with 14.4kꢀ resistor, the
feedback signal can be connected to COMP pin
directly. If the detected voltage is lower than
185mV, MP3910A will enable the internal error
amplifier but turn off the pull up resistor. Then
COMP pin is just one output pin of error
amplifier and the feedback signal should be
connected to FB pin.
Pulse Skipping Mode
At light load condition, the MP3910A goes into
pulse skipping mode to improve light load
efficiency. Pulse skipping decision is based on
its internal COMP voltage. If COMP is lower
than the internal sleep threshold with typical
0.95V, a PAUSE command is generated to
block the turn-on clock pulse so the power
MOSFET is turned off immediately, saving gate
driving and switching losses. This PAUSE
command also puts the whole chip into sleep
mode, consuming very low quiescent current to
further improve the light load efficiency. The
gate driver output remains low until COMP
voltage is higher than the sleep threshold, then
PAUSE signal is reset so the chip is back into
normal PWM operation.
VCC Power Supply
MP3910A operates with supply voltage from 9V
to 14V on VCC pin. VCC UVLO’s rising
threshold is 8V with a hysteresis of 650mV.
When the voltage at VCC pin crosses the VCC
UVLO, the controller is enabled and all the
internal circuitry is powered by VCC source.
VCC voltage should be lower than 14V. For
high input voltage application, one external
Figure 2: Feedback Mode Setting
MP3910A Rev. 1.11
2/14/2017
www.MonolithicPower.com
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11
MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
Generally, it is recommended to place one
signal is higher than the COMP voltage, the
comparator output is low, turning off the power
MOSFET.
resistor with 5Kohm~10Kohm between ISENSE
pin and current sense resistor for the feedback
mode through COMP pin, and connect ISENSE
pin to current sense resistor directly for
feedback mode through FB pin.
If the voltage on the ISENSE pin exceeds the
current-limit threshold voltage with typical value
of 185mV, MP3910A will turn off the GATE
output for that cycle, until the internal oscillator
starts the next cycle, and sense current again.
MP3910A limits the current of MOSFET cycle-
by-cycle.
Soft-Start
MP3910A uses one external capacitor on SS
pin to control COMP voltage rising for soft-start.
When the chip starts, the capacitor on SS pin is
charged by one 54uA current source at a slow
pace set by the capacitance. When the SS
voltage is lower than the external COMP
voltage, SS overrides the COMP signal so the
PWM comparator uses SS instead of COMP as
the PWM turn off reference. When SS is higher
than COMP voltage, COMP gains the control
back and the soft start finishes. The soft-start
can reduce voltage stresses and surge currents
during start up, also prevent the converter
output voltage from overshooting during startup.
Soft start occurs during the start up time and
protection recovery time after OLP, SCP and
OVP. During normal condition, the SS voltage
is clamped at 3.65V.
Over Load Protection (OLP)
The peak current is limited cycle-by-cycle, if the
load continues increasing after triggering OCP
protection, the output voltage will decrease and
the peak current will trigger OCP every cycle.
MP3910A set the over load detection by
continue monitoring the ISENSE pin voltage.
Once the SS voltage is charged to 3.65V after
start up, the OLP protection is enabled. If an
OCP signal is detected, the soft-start charging
current is disabled and one over current
discharge source is enabled, the SS voltage
drops with the rate of 17.8uA current. At the
same time, one 50us one-shot timer is activated
and it remains active for 50µs after the OCP
condition stops. The 17.8uA discharge source
cannot be turn off until the one-shot timer
becomes inactive. If the OCP disappears before
at least 50us prior than the SS capacitor
discharging to 2.9V, MP3910A will run back to
normal work condition and the SS capacitor will
be re-charged to 3.65V with 54uA rate. If the
SS capacitor is discharged to 2.9V, MP3910A
will register it as over load condition and turn off
the gate output until next re-start cycle. At the
same time, 17.8uA discharge current is
disabled and the 1.66uA over load discharge
source is enabled. After the SS voltage is
discharged to 0.2V, MP3910A will re-start up
with new soft-start cycle. This is hiccup mode
protection.
Programmable Oscillator
The MP3910A oscillating frequency is set by an
external resistor from the RT pin to ground. The
value of RT can be estimated from:
2.35103
RT
fSW
RT is in kꢀ and fSW is in kHz.
The frequency setting resistor value shouldn’t
be too large for noise immunity consideration. It
is recommended to set the frequency within
30kHz to 400kHz.
Current Sense and Over Current Protection
The MP3910A is peak current mode controller.
The current through the external FET can be
sensed through a sensing resistor used in
series with the source terminal of FET. The
sensed voltage on ISENSE pin is then amplified
and fed to the high speed current comparator
for the current mode control purpose. The
current comparator takes this sensed voltage
(plus slope compensation) as one of its inputs,
then compares the power switch current with
the COMP voltage. When the amplified current
The OLP detection function is disabled after the
SS voltage is discharged to be lower than 2.9V
and it will be re-enabled after SS voltage is re-
charged to 3.65V. So the OLP only occurs after
the soft-start is completed.
MP3910A Rev. 1.11
2/14/2017
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
the auxiliary winding voltage instead of directly
monitoring the output voltage. The auxiliary
Short Circuit Protection
When the output is shorted to the ground, the
part works in OCP mode and current is limited
cycle-by-cycle, the part may run into OLP
protection.
voltage can be monitored by FB pin through
resistor divider, once the voltage is higher than
OVP reference voltage, MP3910A turns off the
GATE output and discharge SS voltage with
1.66uA current until SS voltage is lower than
0.2V, then the part will initial one new re-start
cycle.
But if the peak current cannot be limited by
185mV ISENSE voltage in every cycle due to
leading edge blanking (LEB) time, the current
may run out of control and transformer may run
into saturation. If the monitored ISENSE voltage
reaches 0.35V, the part will turn off the GATE
out and run into hiccup mode by discharge SS
capacitor with 1.66uA current. It will also re-
start up if SS voltage is discharged to 0.2V.
To avoid the mis-trigger due to the oscillation of
the leakage inductance and the parasitic
capacitance, the OVP sampling has a TOVPS
blanking with 500ns typical value. For some
oscillation condition, one external filter is
necessary to work together with the 500ns LEB
time.
In case the short circuit is removed, the output
voltage will recover only after the next new
restart cycle.
For un-isolated solution, the DC output voltage
is applied to FB pin and it can easily detect the
OVP condition.
For boost converter, it has no method to limit
current from the input to the output in the
condition of output short circuit. If protection
from this type condition is desired, it is
necessary to add some secondary protection
circuit.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from thermally running away. When the
silicon die temperature is higher than its upper
threshold, it shuts down the whole chip. When
the temperature is lower than its low threshold,
thermal shutdown is gone so the chip is
enabled again with a new start-cycle.
Over Voltage Protection
For isolated-flyback application, the positive
plateau of auxiliary winding voltage is
proportional to the output voltage, MP3910A
features the over voltage protection by using
MP3910A Rev. 1.11
2/14/2017
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13
MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
APPLICATION INFORMATION
COMPONENT SELECTION
The output capacitor’s characteristics also
MP3910A can be used for topologies including
Flyback, Boost and Sepic. Refer to figure 5 and
below introduction for typical external
component selection of boost converter.
affect system stability. For best results, use
ceramic, tantalum, or low-ESR electrolytic
capacitors. For ceramic capacitors, the
capacitance dominates the impedance at the
switching frequency, and so the output voltage
ripple is mostly independent of the ESR. The
output voltage ripple is estimated as:
Setting the Output Voltage
Set the output voltage by selecting the resistive
voltage divider ratio. If we use 10kꢀ for the low-
side resistor (RFBL) of the voltage divider, we
can determine the high-side resistor (RFBH) by
the equation:
V
IN
1
VOUT
VOUT ILOAD
COUT FSW
RFBL (VOUT VREF
)
Where ∆VOUT is the output ripple voltage, VIN
and VOUT are the DC input and output voltage,
respectively, ILOAD is the load current, FSW is the
switching frequency, and COUT is the value of
the output capacitor.
RFBH
VREF
Where VOUT is the output voltage
For RFBL=10kꢀ, VOUT=24V and VREF=1.237V,
then RFBH=182kꢀ.
For tantalum or low-ESR electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency, so the output ripple is
estimated as:
Selecting the Soft-start Capacitor
MP3910A ramps external capacitor voltage on
SS pin to control COMP voltage, which
determines inductor peak current. The SS pin
voltage can be estimated from below equation:
V
IN
1
VOUT
ILOAD RESR VOUT
54A
Css
VOUT ILOAD
Vss
Tss
COUT F
V
SW
IN
Where RESR is the equivalent series resistance
of the output capacitors. Choose an output
capacitor that satisfies the output ripple and
load transient requirements of the design.
When OLP, SCP, OVP occurs, the SS acts as a
timer. Once the protection occurs, the 1.66uA
current discharges SS cap for hiccup protection.
Selecting the Input Capacitor
Selecting the Inductor and Current Sensing
Resistor
An input capacitor is required to supply the AC
ripple current to the inductor, while limiting
noise at the input source. A low ESR capacitor
is required to keep the noise to the IC at a
minimum. Ceramic capacitors are preferred, but
tantalum or low-ESR electrolytic capacitors may
also suffice. When using tantalum or electrolytic
The inductor is required to transfer the energy
between the input source and the output
capacitors. A larger value inductor results in
less ripple current that results in lower peak
inductor current, and therefore reduces the
stress on the power MOSFET. However, the
larger value inductor has a larger physical size,
higher series resistance, and lower saturation
current.
capacitors,
a
small high quality ceramic
capacitor, i.e. 1uF, should be place close to IC.
The capacitance for boost input can be
calculated as:
I
A good rule of thumb is to allow the peak-to-
peak ripple current to be approximately 30-50%
of the maximum input current. Make sure that
the peak inductor current is below 80% of the
IC’s maximum current limit at the operating duty
cycle to prevent loss of regulation. Make sure
that the inductor does not saturate under the
worst-case load transient and startup
CIN
8 V F
IN
SW
Where ꢁI is the peak-to-peak inductor ripple
current and ꢁVIN is the input voltage ripple.
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage. For best results, use low-ESR
capacitors to minimize the output voltage ripple.
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
conditions. The required inductance value can
be calculated by:
The on resistance of the MOSFET determines
the conduction loss, which is given by:
P
IR2MS RDS(ON) K
V (VOUT V )
VOUT FSW I
IN
IN
LOSS
L
Where K is the on-resistance temperature
coefficient of the MOSFET. So it is smaller, it is
better.
VOUT ILOAD
I
IN
V
IN
I (30% 50%)I
The switching loss is related to QGD and QGS1
which determine the commutation time. QGS1 is
the charge between the threshold voltage and
the plateau voltage when a driver charges the
gate, which can be read in the chart of VGS vs.
QG of the MOSFET datasheet. QGD is the charge
during the plateau voltage. These two
parameters are needed to estimate the turn on
and turn off loss.
IN
Where ILOAD is the load current, ꢁI is the peak-
to-peak inductor ripple current and η is the
efficiency. For a typical design, boost converter
efficiency can reach 85%~95%.
The switch current is usually used for the peak
current mode control. In order to avoid hitting
the current limit, the voltage across the sensing
resistor RSENSE should be less than 80% of the
worst case current limit voltage, 185mV.
0.8 0.185
QGS1 R
VDR VTH
QGD RG
VDR VPLT
P
G VDS I F
VDS I F
IN SW
SW
IN
SW
RSENSE
IL(PEAK)
Where VTH is the threshold voltage, VPLT is the
plateau voltage, RG is the gate resistance, VDS
is the drain-source voltage. Please note that the
switching loss is the most difficult part in the
loss estimation. The formula above provides a
simple physical expression.
Where IL(PEAK) is the peak value of the inductor
current.
Selecting the Power MOSFET
The MP3910A is capable of driving a wide
variety of N-Channel power MOSFETS. The
critical parameters of selecting a MOSFET are:
On the other hand, small QG will cause fast turn
on/off speed which determines the spike and
kick.
1. Maximum drain to source voltage, VDS(MAX)
2. Maximum current, ID(MAX)
3. On-resistance, RDS(ON)
Selecting the Diode
The boost output rectifier diode supplies current
to the inductor when the MOSFET is off. Use a
Schottky diode to reduce losses due to the
diode forward voltage and recovery time. The
diode should be rated for a reverse voltage
greater than the expected output voltage. The
average current rating must exceed the
maximum expected load current, and the peak
current rating must exceed the peak inductor
current.
4. Gate source charge QGS and gate drain
charge QGD
5. Total gate charge, QG
Ideally, the off-state voltage across the
MOSFET is equal to boost output voltage.
Considering the voltage spike when it turns off,
VDS(MAX) should be greater than 1.5 times of the
output voltage.
The maximum current through the power
MOSFET happens when the input voltage is
minimum and the output power is maximum.
The maximum RMS current through the
MOSFET is given by:
Boost Converter Compensation Design
The output of the transconductance error
amplifier (COMP) is used to compensate the
regulation control system. The system uses two
poles and one zero to stabilize the control loop.
The poles are FP1, which is set by the output
capacitor (COUT) and load resistance, and FP2
which starts from origin. The zero (FZ1) is set by
the compensation capacitor (CCOMP) and the
VOUT V
IN
IRMS I
IN
VOUT
The current rating of the MOSFET should be
greater than 1.5 times IRMS,
compensation
resistor
(RCOMP).
These
parameters are determined by the equations:
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
1
1
CPOLE
F
P1
2 RCOMP F
2 COUT RLOAD
1
ESRZ
PCB Layout Guide
FZ1
2 CCOMP RCOMP
High frequency switching regulators require
very careful layout for stable operation and low
noise. For boost topology layout:
Where RLOAD is the load resistance.
The DC mid-band loop gain is:
1. Keep the high current path as short as
possible between the MOSFET drain,
output diode, output capacitor and current
sense resistor for minimal noise and ringing.
0.5GEA V RLOAD VREF RCOMP
IN
AVDC
VO2UT RSENSE GSENSE
Where VREF is the voltage reference, 1.237V.
GSENSE is the current sense amplifier gain and
GEA is the error amplifier transconductance.
2. The VCC capacitor must be placed close to
the VCC pin for best decoupling.
The ESR zero in this example locates at very
high frequency. Therefore, it is not taken into
design consideration.
3. All feedback components must be kept
close to the FB pin to prevent noise injection
on the FB pin trace.
There is also a right-half-plane zero (FRHPZ) that
exists in continuous conduction mode (inductor
current does not drop to zero on each cycle)
step-up converters. The frequency of the right
half plane zero is:
4. The ground return of the input and output
capacitors should be tied to the GND pin
with single point connection.
Refer to Figure 3 for boost layout, which is
referenced to schematic in Figure 5
V2 RLOAD
IN
F
RHPZ
2 L VO2UT
DOUT
SW
The right-half-plane zero increases the gain and
reduces the phase simultaneously, which
results in smaller phase margin and gain
margin. The worst case happens at the
condition of minimum input voltage and
maximum output power.
Q1
L1
Cout
Rsense
Css
CIN
In order to achieve system stability, Fz1 is
placed close to FP1 to cancel the pole. RCOMP is
adjusted to change the voltage gain. Make sure
the bandwidth FC is about 1/10 of the lower one
of the ESR zero and the right-half-plane zero.
CIN2
RT
1
1
RFBH
Vin
GND
CCOMP
2 COUT RLOAD 2 CCOMP RCOMP
VO2UT 2 COUT FC RSENSE GSENSE
RCOMP RFBL
Top Layer
RCOMP
GEA VREF V
IN
Based on these equations, RCOMP and CCOMP
can be solved.
In cases where the ESR zero is in a relatively
low frequency region and results in insufficient
gain margin, an optional capacitor (CPOLE
should be added between COMP pin and GND.
Then a pole, formed by CPOLE and RCOMP
)
,
should be placed at the ESR zero to cancel the
adverse effect.
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
RSN CSN
Vin
T1
CIN
DSN
DOUT
COUT
GND
RSENSE
GND
Vout
Q1
RT
1
2
3
4
8
7
6
5
U1
RMODE
DFB
RFB
CSS
U2
ROVL
ROVH
Top Layer
Bottom Layer
Figure 3: Boost PCB Layout
For flyback topology PCB layout:
1. Keep the input loop as short as possible
between input cap, transformer, MOSFET,
current sense resistor and GND plane for
minimal noise and ringing.
Bottom Layer
Figure 4: Fly-back PCB Layout
Design Example
2. Keep the output loop between rectifier diode,
output cap and transformer as short as
possible.
Below is a design example following the
application guidelines for the specifications:
Table 1: Boost Design Example
3. The clamp loop circuit between DSN, CSN
and transformer should be as small as
possible
VIN
VOUT
fSW
9-14V
24V
300kHz
4. The VCC capacitor must be placed close to
the VCC pin for best decoupling.
The detailed application schematic is shown in
Figure 6. And there is another design example
for fly-back application in Figure 7.
5. The feedback trace should be far away from
noise source such as drain of power FET.
Table 2: Fly-back Design Example
6. Use single point connection between power
GND and signal GND.
VIN
VOUT
fSW
36-72V
12V
250kHz
Refer to Figure 4 for flyback layout, which is
referenced to schematic on page 1 (excluding
the snubber). For more detail information, refer
to flyback EVB datasheet.
The typical performance and circuit waveforms
of flyback have been shown in the Typical
Performance Characteristics section.
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
Vin
Vout
L1
DOUT
CIN
COUT
GND
CIN2
GND
GND
U1
GND
SS
Q1
GATE
MP3910A
CSS
RT
GND
ISENSE
RT
RSENSE
GND
GND
RCOMP
CCOMP
CPOLE
RFBH
RFBL
GND
GND
Figure 5: Boost Design Reference Schematic
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
TYPICAL APPLICATION CIRCUITS
Figure 6: Typical Boost Converter Application Schematic
36V-72V
12V@2.5A
L1
C9
0.1uF
Vin
R7
R8
C1B C1C
2.2uF
D1
C1A
2.2uF
R13
2k
R12
499k
30k
30k
2.2uF
PDS560
0.47uH
Vout
C2C C2D
0.1uF
Q2
PGND
C2A
C2B
22uF
PGND
D3
10V
D4
200V
C11
1nF
470uF
R9
10
22uF
PGND
T1
AGND
AGND
AGND
AGND
AGND
GND
GND
PGND
R10
910K
Q1
D6
D5
C3
D2
Si7450
R17
4.7k
Vaux
Vaux
VCC
GATE
4.7uF
R5
4.99
U2A
C8
R1
U1
C7
R16
76.8k
470pF
PGND
SS
ISENSE
MP3910A
R11
1k
220pF
4.99k
R6A
0.05
R6B
C5
C6
0.1uF
R18
0.22uF
0.1
RT
FB
Q3
TL431
49.9k
R15
90k
PGND
PGND
R3
9.31k
R2
R14
10k
20k
PGND
1000p/2000V
C10
PGND
AGND
AGND
PGND
U2B
PC817B
PGND
Figure 7: Typical Fly-back Converter Application Schematic
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
Figure 8: Typical Sepic Converter Application Schematic
L1
75V@1.2A
Vout
45-55V
D1
33uH
74435573300
PDS5100
Vin
R7
0ꢀ
R4
100k
C1C
C1A
C1B
C2A
C2B
C2C
2.2uF 2.2uF
100V
Q2
STN715
2.2uF
100V
100V
D3
2.2uF 2.2uF 100V
100uF
100V 100V
12V
GND
GND
GND
GND
GND
GND
GND
Q1
VCC
GATE
GND
SIR878A
C3
10uF
U1
GND
GND
SS
ISENSE
R6
MP3910A
C5
0.22uF
0.02
C6
R1
604K
RT
FB
NC
GND
R3
GND
8.06k
R2
10k
GND
GND
C7
R4
150k
39pF
C4
3.3nF
GND
GND
Figure 9: High-voltage Input Boost Application Schematic
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MP3910A –PEAK CURRENT MODE BOOST CONTROLLER
PACKAGE INFORMATION
SOIC-8
0.189(4.80)
0.197(5.00)
0.050(1.27)
0.024(0.61)
0.063(1.60)
8
5
0.150(3.80)
0.157(4.00)
0.228(5.80)
0.244(6.20)
0.213(5.40)
PIN 1 ID
1
4
TOP VIEW
RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.0075(0.19)
0.0098(0.25)
0.013(0.33)
0.020(0.51)
SEE DETAIL "A"
0.050(1.27)
BSC
SIDE VIEW
FRONT VIEW
0.010(0.25)
0.020(0.50)
x 45o
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
GAUGE PLANE
0.010(0.25) BSC
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
0.016(0.41)
0.050(1.27)
0o-8o
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA.
6) DRAWING IS NOT TO SCALE.
DETAIL "A"
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP3910A Rev. 1.11
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