MP3900DS-LF [MPS]
Switching Controller, Current-mode, 390kHz Switching Freq-Max, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8;
| 型号： | MP3900DS-LF |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Switching Controller, Current-mode, 390kHz Switching Freq-Max, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8 开关 光电二极管 |
| 文件： | 总13页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP3900
High Efficiency
Boost Controller
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP3900 is a boost controller that drives an
external MOSFET capable of handling 10A
current. It has an operational current of typically
180µA and can accommodate off-line, Telecom
•
•
•
•
•
•
•
•
•
•
•
Current Mode Control
10V MOSFET Gate Driver
Undervoltage Lockout
Internal Soft-Start
and
non-isolated
applications.
Internal
Cycle-by-Cycle Current Limiting
Slope Current Compensation
Lossless Current Sense (VISENSE<30V)
10µA Shutdown Current
undervoltage lockout, slope compensation and
peak current limiting are all provided to
minimize the external component count. In a
boost application, with an output voltage of less
than 30V, the current sense pin can connect
directly to the drain of the external switch. This
eliminates the requirement for an additional
current sensing element and its associated
efficiency loss.
180µA Quiescent Current
330KHz Constant Frequency Operation
Applicable to Boost, SEPIC, Flyback and
Forward Topologies
Available in an 8-Pin MSOP/SOIC
Packages
•
While designed for boost applications, the
MP3900 can also be used for other topologies
including Forward, Flyback and Sepic. The 10V
gate driver voltage minimizes the power loss of
the external MOSFET while allowing the use of
a wide variety of standard threshold devices.
APPLICATIONS
•
•
•
•
TV CCFL Power Generation
Telecom Isolated Power
Brick Modules
Off-line Controller
The MP3900 is available in 8-pin MSOP and
SOIC packages.
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
TYPICAL APPLICATION
V
=12V
IN
Efficiency
VIN =13V, VOUT =25V
7
98
V
OUT
VCC
25V/2A
97
96
5
D1
ISENSE
V
=25V
OUT
FDS6630A
MP3900
8
95
94
93
GATE
1
4
PGND
SGND
FB
COMP/RUN
2
3
92
91
C3
10nF
0
0.5 1.0 1.5 2.0 2.5 3.0
Current (A)
MP3900 Rev. 1.0
12/17/2013
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1
MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
ORDERING INFORMATION
Part Number*
MP3900DK
MP3900DS
Package
Top Marking
3900D
Temperature
MSOP8
SOIC8
–40°C to +85°C
MP3900DS
* For Tape & Reel, add suffix –Z (e.g. MP3900DK–Z). For RoHS compliant packaging, add suffix –LF (e.g.
MP3900DK–LF–Z)
PACKAGE REFERENCE
TOP VIEW
PGND
COMP/RUN
FB
1
2
3
4
8
7
6
5
GATE
VCC
NC
SGND
ISENSE
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
MSOP8..................................150..... 65... °C/W
SOIC8.....................................90...... 45... °C/W
θJA
θJC
VCC .............................................–0.3V to +12V
VCC Maximum Current............................. 30mA
ISENSE........................................–0.3V to +30V
FB .................................................–0.3V to +5V
COMP/RUN ...................................–0.3V to +3V
Continuous Power Dissipation (TA = +25°C) (2)
MSOP8 .................................................... 0.67W
SOIC8........................................................ 1.1W
Junction Temperature...............................125°C
Lead Temperature ....................................260°C
Storage Temperature.............. –65°C to +150°C
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (3)
VCC Current .................................1mA to 25mA
Operating Temperature............. –40°C to +85°C
MP3900 Rev. 1.0
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MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
ELECTRICAL CHARACTERISTICS
VCC = 10V, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max Units
VCC Undervoltage Lockout
(VCC UVLO Turn_On Threshold)
Internal Divider (IQ)
8.6
8.9
9.2
V
V
VCC On/Off Voltage Hysteresis
(VCC UVLO Turn_On/Off Hysteresis)
2.0
2.3
COMP Run Threshold
Shutdown Current
0.120 0.160 0.200
V
IS
COMP/RUN = 0V, VIN = 8V
8
20
µA
Output not switching, VFB
1V, VCC = 9V
=
Quiescent Current (Operation)
IQ
180
280
µA
Gate Driver Impedance (Sourcing)
Gate Driver Impedance (Sinking)
VCC = 10V, VGATE = 5V
VCC = 10V, IGATE = 5mA
16
Ω
Ω
4.0
6.0
V
FB connected to VCOMP/RUN.
Error Amplifier Transconductance
0.26
0.36
0.46 mA/V
Force ±10µA to VCOMP/RUN
.
Maximum Comp Current
EA Translator Gain (5)
Switching Frequency
Thermal Shutdown (5)
Maximum Duty Cycle
Minimum On Time
ISENSE Limit
Sourcing and Sinking
40
0.32
330
150
80
µA
AET
fS
0.28
270
0.36
390
V/V
KHz
°C
77
83
%
tON
110
200
150
225
ns
175
mV
V
FB Voltage
VFB
IFB
0.790 0.816 0.840
FB Bias Current
ISENSE Bias Current (5)
Current flowing out of part
50
50
nA
nA
ISENSE Current flowing out of part
Note:
5) Guaranteed by design.
MP3900 Rev. 1.0
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MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
TYPICAL PERFORMANCE CHARACTERISITCS
VIN = 12V, C1 = 4.7µF, C2 = 4x4.7µF, L = 10µH and TA = +25°C, unless otherwise noted.
Efficiency
VIN =13V, VOUT =25V
Load Regulation vs.
Output Current
98
1.00
0.50
97
96
V
=25V
OUT
95
94
93
0.00
-0.50
-1.00
V =12V
IN
92
91
V
=25V
OUT
0
0.5 1.0 1.5 2.0 2.5 3.0
0
0.5
1.0
1.5
2.0
2.5
Current (A)
Current (A)
Switching Waveform
Load Transient Response
No Load Waveform
V
= 12V, V
OUT
= 25V, I = 2A,
V
= 12V, V
OUT
= 25V, I = 1A to 2.5A
V
= 12V, V = 25V, I = 0A
OUT O
IN
O
IN
O
IN
f
= 322.1kHz
SW
V
OUT
V
Ripple
500mV/div.
OUT,
Ripple
1V/div.
V
OUT
500mV/div.
V
DS
10V/div.
COMP
500mV/div.
V
SW
20V/div.
I inductor
2A/div.
I inductor
2A/div.
I inductor
1A/div.
20ms/div.
Shut Down with Input Voltage
Shut Down with COMP
V
= 12V, V
OUT
= 25V, I = 2A
V
= 12V, V = 25V, I = 2A
OUT O
IN
O
IN
V
V
OUT
OUT
10V/div.
10V/div.
V
IN
10V/div.
V
SW
20V/div.
I inductor
5A/div.
I inductor
5A/div.
1ms/div.
MP3900 Rev. 1.0
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MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
PIN FUNCTIONS
Pin #
Name
Description
1
PGND
Power Ground Pin which is gate driver return.
Enable and Compensation. An internal 0.5µA current charges the pin components
2
COMP/RUN above the 0.14V Run threshold to turn on the part. Below this threshold, the part is shut
down, drawing typically 3µA from VCC.
Feedback forces this pin voltage to the 0.8V internal reference potential. Do not allow
3
4
FB
this pin to rise above 1.2V in the application. If this pin is higher than 1.3V, the IC will go
into test mode and turn off the gate driver.
Signal Ground. The SGND and PGND pins should be tied together and returned directly
to the ground connection side of the output capacitor.
SGND
Current Sense. An internal clamp will limit this pin voltage to typically 36V. Do not
connect this pin directly to the drain of the external MOSFET if the voltage swing
exceeds 30V in the particular application. During normal operation, this pin will sense
the voltage across the external MOSFET or sense resistor if one is used, limiting the
peak inductor current on a cycle-by-cycle basis.
5
ISENSE
6
7
8
NC
No Connect.
VCC
GATE
Input Supply. Decouple this pin as close as possible to the SGND pin.
This pin drives the external power MOSFET device.
MP3900 Rev. 1.0
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MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
OPERATION
V
IN
V
CC
Slope
Compensation
Internal
Bias
Enable
Oscillator
V
OUT
Vref = 0.8V
Turn
Off
GATE
Q
Q
S
R
EA
FB
+
--
Driver
+
--
ITRP
Gates
Off
Rsense
PGND
IMAX
Clamp
COMP/RUN
ISENSE
EA Translator
SGND
Rdson
sensing
Optional Filter
Figure 1—Functional Block Diagram
The MP3900 uses a constant frequency, peak
current mode architecture to regulate the
feedback voltage. The operation of the MP3900
can be understood with the block diagram of
Figure 1.
When the voltage at the ISENSE node rises
above the voltage set by the COMP/RUN pin,
the external FET is turned off. The inductor
current then flows to the output capacitor
through the Schottky diode. The inductor
current is controlled by the COMP/RUN voltage,
which itself is controlled by the output voltage.
The peak inductor current is internally limited by
the IMAX clamp voltage that limits the voltage
applied to the ITRP comparator input.
At the beginning of each cycle the external
N-Channel MOSFET is turned on, forcing the
current in the inductor to increase. The current
through the FET can either be sensed through
a sensing resistor or across the external FET
directly. This voltage is then compared to a
voltage related to the COMP/RUN node voltage.
The voltage at the COMP/RUN pin is an
amplified voltage of the difference between the
0.8V reference and the feedback node voltage.
Thus the output voltage controls the inductor
current to satisfy the load. This current mode
architecture improves transient response and
control loop stability over a voltage mode
architecture.
MP3900 Rev. 1.0
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MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
APPLICATION INFORMATION
For VIN(MIN)=10V, VOUT=25V, ILOAD(MAX)=2A, the
ripple percentage being 30%, η=95% and
fSW=330kHz, then L=10µH. In this case, use a
8.8µH inductor (i.e. Sumida CDRH127/LDNP-
100MC).
COMPONENT SELECTION
Setting the Output Voltage
Set the output voltage by selecting the resistive
voltage divider ratio. If we use 10kꢀ for the low-
side resistor (R2) of the voltage divider, we can
determine the high-side resistor (R1) by the
equation:
The switch current is usually used for the peak
current mode control. In order to avoid hitting
the current limit, the voltage across the sensing
resistor RSENSE should be less than 80% of the
worst case current limit voltage, 200mV.
R2× (VOUT − VREF
)
R1 =
VREF
Where VOUT is the output voltage.
0.8 × 0.2
IL(PEAK)
RSENSE
=
For R2=10kꢀ, VOUT=25V and VREF=0.8V, then
R1=301kꢀ.
Where IL(PEAK) is the peak value of the inductor
current.
Selecting the Inductor and Current Sensing
Resistor
For IL(PEAK)=5.3A, RSENSE=30mꢀ.
The inductor is required to transfer the energy
between the input source and the output
capacitors. A larger value inductor results in
less ripple current that results in lower peak
inductor current, and therefore reduces the
stress on the power MOSFET. However, the
larger value inductor has a larger physical size,
higher series resistance, and/or lower
saturation current.
In cases where the RDS(ON) of the power
MOSFET is used as the sensing resistor, be
sure that the RDS(ON) is lower than the value
calculated above, 30mꢀ
Another factor to take into consideration is the
temperature coefficient of the MOSFET RDS(ON)
.
As the temperature increases, the RDS(ON) also
increases.. Device vendors will usually provide
an RDS(ON) vs. temperature curve and the
temperature coefficient in the datasheet.
Generally, the MOSFET on resistance will
double from 25°C to 125°C.
A good rule of thumb is to allow the
peak-to-peak ripple current to be approximately
30-50% of the maximum input current. Make
sure that the peak inductor current is below
80% of the IC’s maximum current limit at the
operating duty cycle to prevent loss of
regulation. Make sure that the inductor does not
saturate under the worst-case load transient
and startup conditions. The required inductance
value can be calculated by :
Selecting the Input Capacitor
An input capacitor (C1) is required to supply the
AC ripple current to the inductor, while limiting
noise at the input source. A low ESR capacitor
is required to keep the noise to the IC at a
minimum. Ceramic capacitors are preferred, but
tantalum or low-ESR electrolytic capacitors may
also suffice.
VIN(MIN) × (VOUT - VIN(MIN)
VOUT × fSW × ΔI
)
L =
The capacitance can be calculated as:
VOUT ×ILOAD
(MAX)
IIN(MAX)
=
ΔI
VIN(MIN) ×η
C1 ≈
8 × ΔVIN(RIPPLE) × fSW
ΔI =
(
30% − 50% IIN(MAX)
)
Where ΔI is the peak-to-peak inductor ripple
current and ΔVIN(RIPPLE) is the input voltage
ripple. When using ceramic capacitors, take into
account the vendor specified voltage and
temperature coefficients for the particular
dielectric being used.
Where ILOAD(MAX) is the maximum load current,
ΔI is the peak-to-peak inductor ripple current
and η is the efficiency. For a typical design,
boost converter efficiency can reach 85%~95%.
MP3900 Rev. 1.0
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MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
For example, 2.2uF capacitance is sufficient to
achieve less then 1% input voltage ripple.
Meanwhile, it requires an adequate ripple
current rating. Use a capacitor with RMS
current rating greater than the inductor ripple
current (see Selecting the Inductor to determine
the inductor ripple current).
For the application shown in page 1, use
ceramic capacitor as an example. For
V
V
IN(MIN)=10V, VOUT=25V, ILOAD(MAX)=2A, and
RIPPLE=1% of the output voltage, the
capacitance C2=14.5µF. Please note that the
ceramic capacitance could dramatically
decrease as the voltage across the capacitor
increases. As a result, larger capacitance is
recommended. In this example, place four
4.7µF ceramic capacitors in parallel. The
voltage rating is also chosen as 50V.
In addition, a smaller high quality ceramic
0.1μF~1µF capacitor may be placed to absorb
the high frequency noise. If using this technique,
it is recommended that the larger capacitor be a
tantalum or electrolytic type.
In the meantime, the RMS current rating of the
output capacitor needs to be sufficient to handle
the large ripple current. The RMS current is
given by:
Selecting the Output Capacitor
Typically, a boost converter has significant
output voltage ripple because the current
through the output diode is discontinuous.
During the diode off state, all of the load current
is supplied by the output capacitor.
V
2
IN
IRIPPLE(RMS)
≈
I
2 − 2×ILOAD ×I
)
×
+ILOAD
IN(MAX)
IN(MAX)
VOUT
2
IRIPPLE(RMS) ≈ D(1−D)×I
< 0.5×I
INMAX
I
Low ESR capacitors are preferred to keep the
output voltage ripple to a minimum. The
characteristics of the output capacitor also
affect the stability of the regulation control
system. Ceramic, tantalum or low ESR
electrolytic capacitors are recommended. In the
case of ceramic capacitors, the impedance of
the capacitor at the switching frequency is
dominated by the capacitance, and so the
output voltage ripple is mostly independent of
the ESR. The output voltage ripple is estimated
to be:
NMAX
For
IIN(MAX)=5.3A, ILOAD=2A, VIN=12V and
VOUT=25V, IRIPPLE(RMS)=2.64A. Make sure that
the output capacitor can handle such an RMS
current.
In addition, a smaller high quality ceramic
0.1μF~1uF capacitor needs to be placed at the
output to absorb the high frequency noise
during the commutation between the power
MOSFET and the output diode. Basically, the
high frequency noise is caused by the parasitic
inductance of the trace and the parasitic
capacitors of devices. The ceramic capacitor
should be placed as close as possible to the
power MOSFET and output diode in order to
minimize the parasitic inductance and maximize
the absorption.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VIN
1-
×ILOAD
VOUT
VRIPPLE
≈
C2× fSW
Where VRIPPLE is the output ripple voltage, VIN
and VOUT are the DC input and output voltages
respectively, ILOAD is the load current, fSW is the
switching frequency and C2 is the output
capacitor.
Selecting the Power MOSFET
The MP3900 is capable of driving a wide variety
of N-Channel power MOSFETS. The critical
parameters of selection of a MOSFET are:
In the case of tantalum or low-ESR electrolytic
capacitors, the ESR dominates the impedance
at the switching frequency. Therefore, the
output ripple is calculated as:
1. Maximum drain to source voltage, VDS(MAX)
2. Maximum current, ID(MAX)
3. On-resistance, RDS(ON)
ILOAD ×RESR × VOUT
VRIPPLE(pk _pk)
≈
4. Gate source charge QGS and gate drain
charge QGD
VIN
Where RESR is the equivalent series resistance
of the output capacitors.
5. Total gate charge, QG
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MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
Ideally, the off-state voltage across the
MOSFET is equal to the output voltage.
Considering the voltage spike when it turns off,
VDS(MAX) should be greater than 1.5 times of the
output voltage.
estimation is required, the expressions will be
much more complex.
For extended knowledge of the power loss
estimation, readers should refer to the book
“Power MOSFET Theory and Applications”
written by Duncan A. Grant and John Gowar.
The maximum current through the power
MOSFET happens when the input voltage is
minimum and the output power is maximum.
The maximum RMS current through the
MOSFET is given by
The total gate charge, QG, is used to calculate
the gate drive loss. The expression is
PDR = QG × VDR × fSW
where VDR is the drive voltage.
IRMS(MAX) = IIN(MAX) × DMAX
For the application in page 1, a FDS6630 or
equivalent MOSFET is chosen. Read from the
datasheet: RDS(ON)=28mꢀ, k = 0.5, QGD=0.9nC,
Where:
VOUT − VIN(MIN)
DMAX
≈
QGS1=1nC, VTH=1.7V, VPLT=3V and QG=5nC @
VOUT
10V. The MP3900 has its gate driving resistance of
around 20ꢀ at VDR=10V and VGATE = 5V.
The current rating of the MOSFET should be
greater than 1.5 times IRMS,
Based on the loss calculation above, the
conduction loss is around 0.629W. The
switching loss is around 0.171W, and the gate
drive loss is 0.015W.
The on resistance of the MOSFET determines
the conduction loss, which is given by:
2
Pcond = IRMS × RDS(on) × k
Selecting the Output Diode
Where k is the temperature coefficient of the
MOSFET. If the RDS(ON) of the MOSFET is used
as the current sensing resistor, make sure the
voltage drop across the device does not exceed
the current limit value of 190mV.
The output rectifier diode supplies current to the
inductor when the MOSFET is off. To reduce
losses due to diode forward voltage and
recovery time, use a Schottky diode. The diode
should be rated for a reverse voltage greater
than the output voltage used. Considering the
voltage spike during the commutation period,
the voltage rating of the diode should be set as
1.5 times the output voltage. For high output
voltages (150V or above), a Schottky diode
might not be practical. A high-speed ultra-fast
recovery silicon rectifier is recommended.
The switching loss is related to QGD and QGS1
which determine the commutation time. QGS1 is
the charge between the threshold voltage and
the plateau voltage when a driver charges the
gate, which can be read in the chart of VGS vs.
QG of the MOSFET datasheet. QGD is the
charge during the plateau voltage. These two
parameters are needed to estimate the turn on
and turn off loss.
Observation of the boost converter circuit
shows that the average current through the
diode is the average load current, and the peak
current through the diode is the peak current
through the inductor. The average current rating
must be greater than 1.5 times of the maximum
load current, and the peak current rating must
be greater than the peak inductor current.
QGS1 × RG
PSW
=
× VDS × IIN × fSW
× VDS × IIN × fSW
+
VDR − VTH
QGD × RG
VDR − VPLT
Where VTH is the threshold voltage, VPLT is the
plateau voltage, RG is the gate resistance, VDS
is the drain-source voltage. Please note that the
switching loss is the most difficult part in the
loss estimation. The formula above provides a
simple physical expression. If more accurate
For the application in page 1, a Vishay SS16
Schottky diode or equivalent part is chosen.
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MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
Boost Converter: Compensation Design
The output of the transconductance error
amplifier (COMP) is used to compensate the
regulation control system. The system uses two
poles and one zero to stabilize the control loop.
The poles are fP1, which is set by the output
capacitor (C2) and load resistance and fP2,
which starts from origin. The zero (fZ1) is set by
the compensation capacitor (C3) and the
compensation resistor (R3). These parameters
are determined by the equations:
The right-half-plane zero increases the gain and
reduces the phase simultaneously, which
results in smaller phase margin and gain
margin. The worst case happens at the
condition of minimum input voltage and
maximum output power.
In order to achieve system stability, fz1 is placed
close to fP1 to cancel the pole. R3 is adjusted to
change the voltage gain. Make sure the
bandwidth is about 1/10 of the lower one of the
ESR zero and the right-half-plane zero.
1
1
1
fP1
=
=
=
π × C2×RLOAD
π × C2×RLOAD
2× π × C3×R3
1
2
fZ1
VOUT × 2× π× C2× fc ×RSENSE
2 × π × C3×R3
R3 =
GEA × VREF ×VIN × AET
Where RLOAD is the load resistance.
The DC mid-band loop gain is:
Based on these equations, R3 and C3 can be
solved.
0.5× GEA × VIN ×RLOAD × VREF ×R3× AET
For the application in page 1, fp1 = 1.35KHz,
ESR zero is much higher than the switching
frequency and fRHPZ=45.8KHz. Set fz1 to
3.18KHz and make the crossover frequency
8.5kHz, then R3=5kꢀ and C3=10nF. Choose
5kꢀ and 10nF.
AVDC
=
VOUT2 ×RSENSE
where VREF is the voltage reference, 0.8V. AET is
the gain of error amplifier translator and GEA is
the error amplifier transconductance.
The ESR zero in this example locates at very
high frequency. Therefore, it is not taken into
design consideration.
In cases where the ESR zero is in a relatively
low frequency region and results in insufficient
gain margin, an optional capacitor (C5) (shown
in Figure 2) should be added. Then a pole,
formed by C5 and R3, should be placed at the
ESR zero to cancel the adverse effect.
There is also a right-half-plane zero (fRHPZ) that
exists in continuous conduction mode (inductor
current does not drop to zero on each cycle)
step-up converters. The frequency of the right
half plane zero is:
1
C5 =
2× π×R3 ×
fESRz
VIN2 × RLOAD
fRHPZ
=
2
Layout Consideration
2× π×L× VOUT
High frequency switching regulators require
very careful layout for stable operation and low
noise. Keep the high current path as short as
possible between the MOSFET drain, output
diode, output capacitor and GND pin for
minimal noise and ringing. The VCC capacitor
must be placed close to the VCC pin for best
decoupling. All feedback components must be
kept close to the FB pin to prevent noise
injection on the FB pin trace. The ground return
of the input and output capacitors should be
tied closed to the GND pin. See the MP3900
demo board layout for reference.
MP3900 Rev. 1.0
12/17/2013
www.MonolithicPower.com
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10
MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
TYPICAL APPLICATION CIRCUIT
V
=12V
IN
7
V
OUT
25V/2A
VCC
5
D1
ISENSE
FDS6630A
MP3900
8
1
GATE
4
PGND
SGND
COMP/RUN
FB
2
3
C3
10nF
C5
Figure 2—MP3900 for Boost Controller Application
MP3900 Rev. 1.0
12/17/2013
www.MonolithicPower.com
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© 2013 MPS. All Rights Reserved.
11
MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
PACKAGE INFORMATION
MSOP8
0.114(2.90)
0.122(3.10)
5
8
0.187(4.75)
0.199(5.05)
0.114(2.90)
0.122(3.10)
PIN 1 ID
(NOTE 5)
4
1
0.010(0.25)
0.014(0.35)
0.0256(0.65)BSC
BOTTOM VIEW
TOP VIEW
GAUGE PLANE
0.010(0.25)
0.030(0.75)
0.037(0.95)
0.043(1.10)MAX
SEATING PLANE
0.002(0.05)
0.004(0.10)
0.008(0.20)
0.016(0.40)
0.026(0.65)
0o-6o
0.006(0.15)
FRONT VIEW
SIDE VIEW
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS
IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
0.181(4.60)
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) PIN 1 IDENTIFICATION HAS HALF OR FULL CIRCLE OPTION.
6) DRAWING MEETS JEDEC MO-187, VARIATION AA.
7) DRAWING IS NOT TO SCALE.
0.040(1.00)
0.016(0.40)
0.0256(0.65)BSC
RECOMMENDED LAND PATTERN
MP3900 Rev. 0.92
12/17/2013
www.MonolithicPower.com
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© 2013 MPS. All Rights Reserved.
12
MP3900 – HIGH EFFICIENCY BOOST CONTROLLER
SOIC8
0.189(4.80)
0.197(5.00)
0.050(1.27)
0.024(0.61)
8
5
0.063(1.60)
0.150(3.80)
0.157(4.00)
0.228(5.80)
0.244(6.20)
0.213(5.40)
PIN 1 ID
1
4
TOP VIEW
RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.0075(0.19)
0.0098(0.25)
0.013(0.33)
0.020(0.51)
SEE DETAIL "A"
0.050(1.27)
BSC
SIDE VIEW
FRONT VIEW
0.010(0.25)
0.020(0.50)
x 45o
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
GAUGE PLANE
0.010(0.25) BSC
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
0.016(0.41)
0.050(1.27)
0o-8o
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA.
6) DRAWING IS NOT TO SCALE.
DETAIL "A"
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP3900 Rev. 1.0
12/17/2013
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
13
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