DSP56F807 [MOTOROLA]
56F807 16-bit Hybrid Processor; 56F807 16位混合处理器
| 型号： | DSP56F807 |
| 厂家： | 
MOTOROLA |
| 描述： | 56F807 16-bit Hybrid Processor |
| 文件： | 总52页 (文件大小：1094K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
DSP56F807/D
Rev. 12.0, 02/2004
56F807
Technical Data
56F807 16-bit Hybrid Processor
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•
Up to 40 MIPS at 80MHz core frequency
•
Up to 64K × 16- bit words each of external
Program and Data memory
DSP and MCU functionality in a unified,
C-efficient architecture
•
•
•
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Two 6 channel PWM Modules
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•
Hardware DO and REP loops
Four 4 channel, 12-bit ADCs
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
Two Quadrature Decoders
CAN 2.0 B Module
Two Serial Communication Interfaces (SCIs)
Serial Peripheral Interface (SPI)
Up to four General Purpose Quad Timers
JTAG/OnCETM port for debugging
14 Dedicated and 18 Shared GPIO lines
160-pin LQFP or 160 MAPBGA Packages
•
•
•
•
•
60K × 16-bit words Program Flash
2K × 16-bit words Program RAM
8K × 16-bit words Data Flash
4K × 16-bit words Data RAM
2K × 16-bit words Boot Flash
6
6
PWM Outputs
PWMA
PWMB
RSTO
EXTBOOT
IRQB
Current Sense Inputs
Fault Inputs
3
4
RESET
IRQA
VPP VCAPC
2
V
V
V
V
SSA
DD
SS
DDA
6
PWM Outputs
8
10*
3
3
Current Sense Inputs
Fault Inputs
3
4
4
4
JTAG/
OnCE
Port
Digital Reg
Analog Reg
A/D1
A/D2
ADCA
Low Voltage
Supervisor
VREF
A/D1
A/D2
ADCB
4
4
VREF2
Interrupt
Controller
Data ALU
Address
Generation
Unit
Bit
Manipulation
Unit
Program Controller
and
Hardware Looping Unit
Quadrature
Decoder 0
/Quad Timer
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
4
Quadrature
Decoder 1
/Quad Timer B
Program Memory
61440 x 16 Flash
2048 x 16 SRAM
PAB
PLL
CLKO
4
2
•
PDB
16-Bit
56800
Core
•
•
Quad Timer C
XTAL
Boot Flash
2048 x 16 Flash
Clock Gen
Quad Timer D
/ Alt Func
EXTAL
XDB2
4
2
CGDB
Data Memory
8192 x 16 Flash
4096 x 16 SRAM
CAN 2.0A/B
•
•
•
•
XAB1
SCI0
or
GPIO
XAB2
•
INTERRUPT
CONTROLS
IPBB
CONTROLS
16
2
2
A[00:05]
SCI1
or
GPIO
External
Address Bus
Switch
16
6
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
COP/
Watchdog
COP RESET
External
Bus
Interface
Unit
10
16
External
Data Bus
Switch
MODULE CONTROLS
Applica-
tion-Specific
Memory &
Peripherals
SPI
or
GPIO
D[00:15]
IPBus Bridge
(IPBB)
ADDRESS BUS [8:0]
DATA BUS [15:0]
PS Select
DS Select
WR Enable
RD Enable
4
Bus
Control
Dedicated
GPIO
14
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. 56F807 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
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Freescale Semiconductor, Inc.
Part 1 Overview
1.1 56F807 Features
1.1.1
Digital Signal Processing Core
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
Memory
•
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
— 60K × 16-bit words of Program Flash
•
— 2K × 16-bit words of Program RAM
— 8K × 16-bit words of Data Flash
— 4K × 16-bit words of Data RAM
— 2K × 16-bit words of Boot Flash
•
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K × 16 bits of Data memory
— As much as 64K × 16 bits of Program memory
1.1.3
Peripheral Circuits for 56F807
•
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and
four Fault inputs, fault tolerant design with dead time insertion, supports both center- and
edge-aligned modes
•
•
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions
with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized
Two Quadrature Decoders each with four inputs or two additional Quad Timers
2
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56F807 Description
•
Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D
with four pins
•
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•
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CAN 2.0 B Module with 2-pin port for transmit and receive
Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)
Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)
Computer-Operating Properly (COP) Watchdog timer
Two dedicated external interrupt pins
14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins
External reset input pin for hardware reset
External reset output pin for system reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller
core clock
1.1.4
Energy Information
•
•
•
•
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
1.2 56F807 Description
The 56F807 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single chip,
the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals
to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F807 is well-suited for many applications. The 56F807 includes many peripherals that
are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The
instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F807 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F807 also provides two external
dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each
programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It
also supports program execution from external memory.
56F807 Technical Data
3
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A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
software routines that can be used to program the main Program and Data Flash memory areas. Both
Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words.
The Boot Flash memory can also be either bulk or page erased.
A key application-specific feature of the 56F807 is the inclusion of two Pulse Width Modulator (PWM)
modules. These modules each incorporate three complementary, individually programmable PWM signal
outputs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM
outputs) to enhance motor control functionality. Complementary operation permits programmable dead
time insertion, distortion correction via current sensing by software, and separate top and bottom output
polarity control. The up-counter value is programmable to support a continuously variable PWM frequency.
Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The
device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC
(Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper
motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output
drive capability to directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature
for key parameters is also included. A patented PWM waveform distortion correction circuit is also
provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be
programmable from 1 to 16. The PWM modules provide a reference output to synchronize the
analog-to-digital converters.
The 56F807 incorporates two separate Quadrature Decoders capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of
these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. A
Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller, and
14 dedicated GPIO lines are also included on the 56F807.
1.3 State of the Art Development Environment
TM
•
Processor Expert (PE) provides a Rapid Application Design (RAD) tool that combines
easy-to-use component-based software application creation with an expert knowledge system.
•
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system
cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a
complete, scalable tools solution for easy, fast, and efficient development.
4
56F807 Technical Data
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Product Documentation
1.4 Product Documentation
The four documents listed in Table 1 are required for a complete description and proper design with the 56F807.
Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola
Literature Distribution Centers, or online at http://www.motorola.com/semiconductors
.
Table 1. 56F807 Chip Documentation
Topic
Description
Order Number
DSP56800
Family Manual
Detailed description of the 56800 family architecture,
and 16-bit core processor and the instruction set
DSP56800FM/D
DSP56F801/803/805/807
User’s Manual
Detailed description of memory, peripherals, and
interfaces of the 56F801, 56F803, 56F805, and
56F807
DSP56F801-7UM/D
56F807
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
DSP56F807/D
56F807
Product Brief
Summary description and block diagram of the 56F807
core, memory, peripherals and interfaces
DSP56F807PB/D
DSP56F807E/D
DSP56F807
Errata
Details any chip issues that might be present
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
“deasserted”
Examples:
A high true (active high) signal is high or a low true (active low) signal is low.
A high true (active high) signal is low or a low true (active low) signal is high.
Voltage1
Signal/Symbol
Logic State
True
Signal State
Asserted
PIN
PIN
PIN
PIN
VIL/VOL
False
Deasserted
Asserted
VIH/VOH
VIH/VOH
VIL/VOL
True
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56F807 Technical Data
5
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Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F807 are organized into functional groups, as shown in Table 2 and
as illustrated in Figure 2. In Table 3 through Table 19, each table row describes the signal or signals
present on a pin.
Table 2. Functional Group Pin Allocations
Number of
Pins
Detailed
Description
Functional Group
Power (VDD or VDDA
)
11
13
4
Table 3
Table 4
Table 5
Ground (VSS or VSSA
)
Supply Capacitors & VPP
PLL and Clock
3
Table 6
Table 7
Address Bus1
16
Data Bus
16
4
Table 8
Table 9
Bus Control
Interrupt and Program Control
Dedicated General Purpose Input/Output
Pulse Width Modulator (PWM) Ports
5
Table 10
Table 11
Table 12
Table 13
14
26
4
Serial Peripheral Interface (SPI) Port1
Quadrature Decoder Ports2
8
4
Table 14
Table 15
Serial Communications Interface (SCI) Ports1
CAN Port
2
20
6
Table 16
Table 17
Table 18
Table 19
Analog to Digital Converter (ADC) Ports
Quad Timer Module Ports
JTAG/On-Chip Emulation (OnCE)
6
1. Alternately, GPIO pins
2. Alternately, Quad Timer pins
6
56F807 Technical Data
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Introduction
V
DD
8
Power Port
Ground Port
Power Port
Ground Port
GPIOB0–7
GPIOD0–5
Dedicated
GPIO
8
6
V
SS
10*
3
V
DDA
V
SSA
3
PWMA0-5
ISA0-2
6
3
4
PWMA
Port
VCAPC
Other
Supply
Ports
2
2
FAULTA0-3
V
PP
PWMB0-5
ISB0-2
6
3
4
EXTAL
XTAL
PLL
and
Clock
1
1
1
PWMB
Port
56F807
FAULTB0-3
CLKO
SCLK (GPIOE4)
MOSI (GPIOE5)
MISO (GPIOE6)
SS (GPIOE7)
1
1
1
1
A0-A5
A6-7 (GPIOE2-E3)
A8-15 (GPIOA0-A7)
6
2
8
External
Address Bus or
GPIO
SPI Port
or GPIO
External
Data Bus
D0–D15
16
TXD0 (GPIOE0)
RXD0 (GPIOE1)
1
1
SCI0 Port
or GPIO
PS
DS
1
1
1
1
External
Bus Control
SCI1 Port
or GPI0
TXD1 (GPIOD6)
RXD1 (GPIOD7)
1
1
RD
WR
ADCA
Port
ANA0-7
VREF
8
2
8
PHASEA0 (TA0)
PHASEB0 (TA1)
INDEX0 (TA2)
HOME0 (TA3)
PHASEA1 (TB0)
PHASEB1 (TB1)
INDEX1 (TB2)
HOME1 (TB3)
TCK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Quadrature
Decoder or
Quad Timer A
ADCB
Port
ANB0-7
MSCAN_RX
MSCAN_TX
1
1
CAN
Quadrature
Decoder1 or
Quad Timer B
Quad
Timers
C & D
TC0-1
TD0-3
2
4
TMS
IRQA
1
1
1
1
1
TDI
IRQB
JTAG/OnCE
Port
Interrupt/
Program
Control
TDO
RESET
RSTO
TRST
EXTBOOT
DE
*includes TCS pin which is reserved for factory use and is tied to VSS
1
Figure 2. 56F807 Signals Identified by Functional Group
1. Alternate pin functionality is shown in parenthesis.
56F807 Technical Data
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2.2 Power and Ground Signals
Table 3. Power Inputs
No. of Pins
Signal Name
VDD
Signal Description
8
Power—These pins provide power to the internal structures of the chip, and
should all be attached to VDD.
3
VDDA
Analog Power—These pins is a dedicated power pin for the analog portion
of the chip and should be connected to a low noise 3.3V supply.
Table 4. Grounds
No. of Pins
Signal Name
VSS
Signal Description
9
GND—These pins provide grounding for the internal structures of the chip and
should all be attached to VSS.
3
1
VSSA
TCS
Analog Ground—This pin supplies an analog ground.
TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for
normal use. In block diagrams, this pin is considered an additional VSS.
Table 5. Supply Capacitors and VPP
No. of
Pins
Signal
Name
Signal
Type
State During
Signal Description
Reset
2
VCAPC
Supply
Supply
VCAPC—Connect each pin to a 2.2uF or greater bypass
capacitor in order to bypass the core logic voltage regulator
(required for proper chip operation). For more information, please
refer to Section 5.2
2
VPP
Input
Input
VPP—This pin should be left unconnected as an open circuit for
normal functionality.
2.3 Clock and Phase Locked Loop Signals
Table 6. PLL and Clock
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
EXTAL
Input
Input
External Crystal Oscillator Input—This input should be
connected to an 8MHz external crystal or ceramic resonator.
For more information, please refer to Section 3.5.
1
XTAL
Input/
Output
Chip-driven
Crystal Oscillator Output—This output should be connected
to an 8MHz external crystal or ceramic resonator. For more
information, please refer to Section 3.5.
This pin can also be connected to an external clock source. For
more information, please refer to Section 3.5.2.
8
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Address, Data, and Bus Control Signals
Table 6. PLL and Clock (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Signal Description
Reset
1
CLKO
Output
Chip-driven
Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
Table 7. Address Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
2
A0–A5
A6–A7
Output
Output
Tri-stated
Tri-stated
Input
Address Bus—A0–A5 specify the address for external
Program or Data memory accesses.
Address Bus—A6–A7 specify the address for external
Program or Data memory accesses.
GPIOE2-
GPIOE3
Input/O
utput
Port E GPIO—These two General Purpose I/O (GPIO) pins
can individually be programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15
Output
Tri-stated
Input
Address Bus—A8–A15 specify the address for external
Program or Data memory accesses.
GPIOA0-
GPIOA7
Input/O
utput
Port A GPIO—These eight General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
Table 8. Data Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
16
D0–D15
Input/O
utput
Tri-stated
Data Bus— D0–D15 specify the data for external program or
data memory accesses. D0–D15 are tri-stated when the external
bus is inactive. Internal pullups may be active.
56F807 Technical Data
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Table 9. Bus Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Signal Description
Reset
1
1
1
PS
DS
WR
Output
Output
Output
Tri-stated
Tri-stated
Tri-stated
Program Memory Select—PS is asserted low for external program
memory access.
Data Memory Select—DS is asserted low for external data
memory access.
Write Enable—WR is asserted during external memory write
cycles. When WR is asserted low, pins D0–D15 become outputs
and the device puts data on the bus. When WR is deasserted high,
the external data is latched inside the external device. When WR is
asserted, it qualifies the A0–A15, PS, and DS pins. WR can be
connected directly to the WE pin of a Static RAM.
1
RD
Output
Tri-stated
Read Enable—RD is asserted during external memory read cycles.
When RD is asserted low, pins D0–D15 become inputs and an
external device is enabled onto the device’s data bus. When RD is
deasserted high, the external data is latched inside the device.
When RD is asserted, it qualifies the A0–A15, PS, and DS pins. RD
can be connected directly to the OE pin of a Static RAM or ROM.
2.5 Interrupt and Program Control Signals
Table 10. Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
1
1
IRQA
IRQB
RSTO
Input
(Schmitt)
Input
Input
External Interrupt Request A—The IRQA input is a
synchronized external interrupt request that indicates that an
external device is requesting service. It can be programmed to
be level-sensitive or negative-edge-triggered.
Input
(Schmitt)
External Interrupt Request B—The IRQB input is an external
interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive
or negative-edge-triggered.
Output
Output
Reset Output—This output reflects the internal reset state of
the chip.
10
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GPIO Signals
Table 10. Interrupt and Program Control Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
RESET
Input
(Schmitt)
Input
Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and
placed in the Reset state. A Schmitt trigger input is used for
noise immunity. When the RESET pin is deasserted, the initial
chip operating mode is latched from the EXTBOOT pin. The
internal reset signal will be deasserted synchronous with the
internal clocks, after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should
be asserted together. The only exception occurs in a
debugging environment when a hardware device reset is
required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST.
1
EXTBOOT
Input
Input
External Boot—This input is tied to VDD to force device to boot
(Schmitt)
from off-chip memory. Otherwise, it is tied to VSS.
2.6 GPIO Signals
Table 11. Dedicated General Purpose Input/Output (GPIO) Signals
No.of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
8
6
GPIOB0-G
PIOB7
Input
or
Output
Input
Port B GPIO—These eight pins are dedicated General
Purpose I/O (GPIO) pins that can individually be programmed
as input or output pins.
After reset, the default state is GPIO input.
GPIOD0-G
PIOD5
Input
or
Input
Port D GPIO—These six pins are dedicated GPIO pins that
can individually be programmed as an input or output pins.
Output
After reset, the default state is GPIO input.
2.7 Pulse Width Modulator (PWM) Signals
Table 12. Pulse Width Modulator (PWMA and PWMB) Signals
No.of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
3
PWMA0-5
ISA0-2
Output
Tri- stated
Input
PWMA0-5— Six PWMA output pins.
Input
(Schmitt)
ISA0-2— These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMA.
4
6
FAULTA0-3
PWMB0-5
Input
(Schmitt)
Input
FAULTA0-3— These Fault input pins are used for disabling
selected PWMA outputs in cases where fault conditions
originate off-chip.
Output
Tri- stated
PWMB0-5— Six PWMB output pins.
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Table 12. Pulse Width Modulator (PWMA and PWMB) Signals (Continued)
No.of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
3
ISB0-2
Input
(Schmitt)
Input
ISB0-2— These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMB.
4
FAULTB0-3
Input
(Schmitt)
Input
FAULTB0-3— These four Fault input pins are used for
disabling selected PWMB outputs in cases where fault
conditions originate off-chip.
2.8 Serial Peripheral Interface (SPI) Signals
Table 13. Serial Peripheral Interface (SPI) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
MISO
Input/
Output
Input
Input
Input
Input
SPI Master In/Slave Out (MISO)—This serial data pin is an
input to a master device and an output from a slave device. The
MISO line of a slave device is placed in the high-impedance
state if the slave device is not selected.
GPIOE6 Input/Outp
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
ut
After reset, the default state is MISO.
1
MOSI
Input/
Output
SPI Master Out/Slave In (MOSI)—This serial data pin is an
output from a master device and an input to a slave device. The
master device places data on the MOSI line a half-cycle before
the clock edge that the slave device uses to latch the data.
GPIOE5 Input/Outp
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
ut
can individually be programmed as input or output pin.
After reset, the default state is MOSI.
1
SCLK
Input/Outp
ut
Input
Input
SPI Serial Clock—In master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves
as the data clock input.
GPIOE4 Input/Outp
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
ut
can individually be programmed as input or output pin.
After reset, the default state is SCLK.
1
SS
Input
Input
Input
SPI Slave Select—In master mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the
slave.
GPIOE7 Input/Outp
ut
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
After reset, the default state is SS.
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Quadrature Decoder Signals
2.9 Quadrature Decoder Signals
Table 14. Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
1
1
1
1
1
1
1
PHASEA0
TA0
Input
Input/Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Phase A—Quadrature Decoder #0 PHASEA input
TA0—Timer A Channel 0
PHASEB0
TA1
Phase B—Quadrature Decoder #0 PHASEB input
TA1—Timer A Channel 1
Input/Output
Input
INDEX0
TA2
Index—Quadrature Decoder #0 INDEX input
TA2—Timer A Channel 2
Input/Output
Input
HOME0
TA3
Home—Quadrature Decoder #0 HOME input
TA3—Timer A Channel 3
Input/Output
Input
PHASEA1
TB0
Phase A—Quadrature Decoder #1 PHASEA input
TB0—Timer B Channel 0
Input/Output
Input
PHASEB1
TB1
Phase B—Quadrature Decoder #1 PHASEB input
TB1—Timer B Channel 1
Input/Output
Input
INDEX1
TB2
Index—Quadrature Decoder #1 INDEX input
TB2—Timer B Channel 2
Input/Output
Input
HOME1
TB3
Home—Quadrature Decoder #1 HOME input
TB3—Timer B Channel 3
Input/Output
2.10 Serial Communications Interface (SCI) Signals
Table 15. Serial Communications Interface (SCI0 and SCI1) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TXD0
Output
Input
Input
Transmit Data (TXD0)—transmit data output
GPIOE0
Input/Outp
ut
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.
After reset, the default state is SCI output.
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Table 15. Serial Communications Interface (SCI0 and SCI1) Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
1
1
RXD0
Input
Input
Input
Receive Data (RXD0)— receive data input
GPIOE1
Input/Outp
ut
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.
After reset, the default state is SCI input.
TXD1
Output
Input
Input
Transmit Data (TXD1)—transmit data output
GPIOD6
Input/Outp
ut
Port D GPIO—This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.
After reset, the default state is SCI output.
RXD1
Input
Input
Input
Receive Data (RXD1)— receive data input
GPIOD7
Input/Outp
ut
Port D GPIO—This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.
After reset, the default state is SCI input.
2.11 CAN Signals
Table 16. CAN Module Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
1
MSCAN_ RX
MSCAN_ TX
Input
(Schmitt)
Input
MSCAN Receive Data—MSCAN input. This pin has
an internal pull-up resistor.
Output
Output
MSCAN Transmit Data—MSCAN output. CAN output
is open-drain output and pull-up resistor is needed.
2.12 Analog-to-Digital Converter (ADC) Signals
Table 17. Analog to Digital Converter Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
4
4
2
ANA0-3
ANA4-7
VREF
Input
Input
Input
Input
Input
Input
ANA0-3—Analog inputs to ADCA channel 1
ANA4-7—Analog inputs to ADCA channel 2
VREF—Analog reference voltage for ADC. Must be set to
VDDA-0.3V for optimal performance.
4
4
ANB0-3
ANB4-7
Input
Input
Input
Input
ANB0-3—Analog inputs to ADCB, channel 1
ANB4-7—Analog inputs to ADCB, channel 2
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Quad Timer Module Signals
2.13 Quad Timer Module Signals
Table 18. Quad Timer Module Signals
No. of
Pins
Signal
Name
State During
Signal Type
Signal Description
Reset
2
4
TC0-1
TD0-3
Input/Output
Input/Output
Input
Input
TC0-1—Timer C Channels 0 and 1
TD0-3—Timer D Channels 0, 1, 2, and 3
2.14 JTAG/OnCE
Table 19. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
1
1
1
TCK
TMS
TDI
Input
(Schmitt)
Input, pulled Test Clock Input—This input pin provides a gated clock to
low internally synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
Input
(Schmitt)
Input, pulled Test Mode Select Input—This input pin is used to sequence the
high internally JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Input
(Schmitt)
Input, pulled Test Data Input—This input pin provides a serial input data
high internally stream to the JTAG/OnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
TDO
Output
Tri-stated
Test Data Output—This tri-statable output pin provides a serial
output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
1
1
TRST
Input
(Schmitt)
Input, pulled Test Reset—As an input, a low signal on this pin provides a
high internally reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted at power-up and
whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware device reset is
required and it is necessary not to reset the OnCE/JTAG module.
In this case, assert RESET, but do not assert TRST.
DE
Output
Output
Debug Event—DE provides a low pulse on recognized debug
events.
Part 3 Specifications
3.1 General Characteristics
The 56F807 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such sytems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
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Absolute maximum ratings given in Table 20 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F807 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate voltage level.
Table 20. Absolute Maximum Ratings
Characteristic
Symbol
VDD
VIN
Min
Max
Unit
V
Supply voltage
VSS – 0.3
VSS – 0.3
VSSA– 0.3
VSSA– 0.3
—
VSS + 4.0
VSS + 5.5V
VDDA+ 0.3
VSSA+ 3.0
10
All other input voltages, excluding Analog inputs
Analog inputs, ANA0-7 and VREF
V
VIN
V
Analog inputs EXTAL and XTAL
VIN
V
Current drain per pin excluding VDD, VSS, PWM
outputs, TCS, VPP, VDDA, VSSA
I
mA
Table 21. Recommended Operating Conditions
Characteristic
Supply voltage, digital
Symbol
VDD
Min
3.0
3.0
2.7
–40
Typ
3.3
3.3
–
Max
3.6
Unit
V
V
Supply Voltage, analog
VDDA
VREF
TA
3.6
ADC reference voltage
VDDA
85
V
Ambient operating temperature
–
°C
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General Characteristics
6
Table 22. Thermal Characteristics
Value
Characteristic
Comments
Symbol
Unit
Notes
160-pin
LQFP
160
MBGA
Junction to ambient
RθJA
38.5
63.4
°C/W
2
Natural convection
Junction to ambient (@1m/sec)
RθJMA
35.4
33
60.3
49.9
°C/W
°C/W
2
Junction to ambient
Natural convection
Four layer
board (2s2p)
RθJMA
(2s2p)
1,2
Junction to ambient (@1m/sec) Four layer
board (2s2p)
RθJMA
31.5
46.8
°C/W
1,2
Junction to case
RθJC
ΨJT
8.6
0.8
8.1
0.6
°C/W
°C/W
W
3
Junction to center of case
I/O pin power dissipation
Power dissipation
4, 5
P I/O
P D
User Determined
P D = (IDD x VDD + P I/O
(TJ - TA) /θJA
)
W
Junction to center of case
PDMAX
°C
Notes:
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2. Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the
JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was
also simulated on a thermal test board with two internal planes (2s2p where “s” is the number of
signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name for
Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.
3. Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured
values using the cold plate technique with the cold plate temperature used as the “case” temperature.
The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This
is the correct thermal metric to use to calculate thermal performance when the package is being used
with a heat sink.
4. Thermal Characterization Parameter, Psi-JT (ΨJT ), is the “resistance” from junction to reference
point thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to
estimate junction temperature in steady state customer environments.
5. Junction temperature is a function of on-chip power dissipation, package thermal resistance,
mounting site (board) temperature, ambient temperature, air flow, power dissipation of other
components on the board, and board thermal resistance.
6. See Section 5.1 from more details on thermal design considerations.
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3.2 DC Electrical Characteristics
Table 23. DC Electrical Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Input high voltage (XTAL/EXTAL)
Symbol
VIHC
VILC
VIHS
VILS
VIH
Min
2.25
0
Typ
—
—
—
—
—
—
—
Max
2.75
0.5
5.5
0.8
5.5
0.8
1
Unit
V
Input low voltage (XTAL/EXTAL)
V
Input high voltage (Schmitt trigger inputs)1
2.2
-0.3
2.0
-0.3
-1
V
Input low voltage (Schmitt trigger inputs)1
Input high voltage (all other digital inputs)
V
V
Input low voltage (all other digital inputs)
VIL
V
Input current high (pullup/pulldown resistors disabled,
IIH
µA
VIN=VDD
)
Input current low (pullup/pulldown resistors disabled,
VIN=VSS
IIL
-1
—
1
µA
)
Input current high (with pullup resistor, VIN=VDD
Input current low (with pullup resistor, VIN=VSS
Input current high (with pulldown resistor, VIN=VDD
)
IIHPU
IILPU
IIHPD
IILPD
RPU, RPD
IOZL
-1
-210
20
—
—
—
—
30
—
—
—
1
-50
180
1
µA
µA
µA
µA
KΩ
µA
µA
µA
)
)
Input current low (with pulldown resistor, VIN=VSS
Nominal pullup or pulldown resistor value
Output tri-state current low
)
-1
-10
-10
-15
10
10
15
Output tri-state current high
IOZH
2
IIHA
Input current high (analog inputs, VIN=VDDA
)
3
IILA
-15
—
15
µA
Input current low (analog inputs, VIN=VSSA
Output High Voltage (at IOH)
Output Low Voltage (at IOL)
Output source current
)
VOH
VOL
IOH
VDD – 0.7
—
—
—
—
—
—
—
0.4
—
—
—
—
V
—
4
V
mA
mA
mA
mA
Output source current
IOL
4
PWM pin output source current3
PWM pin output sink current4
IOHP
IOLP
10
16
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DC Electrical Characteristics
Table 23. DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
CIN
Min
—
Typ
8
Max
—
Unit
pF
Input capacitance
Output capacitance
VDD supply current
COUT
—
12
—
pF
5
IDDT
Run 6
—
—
195
170
220
200
mA
mA
Wait7
Stop
—
115
2.7
145
3.0
mA
V
Low Voltage Interrupt, external power supply8
Low Voltage Interrupt, internal power supply9
Power on Reset10
VEIO
VEIC
2.4
2.0
—
2.2
1.7
2.4
2.0
V
V
VPOR
1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, ISA0-2, FAULTA0-3, ISB0-2, FAULTB0-3,
TCK, TRST, TMS, TDI, and MSCAN_RX
2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3. PWM pin output source current measured with 50% duty cycle.
4. PWM pin output sink current measured with 50% duty cycle.
5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA
)
6. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
configured as inputs; measured with all modules enabled.
7. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no
DC loads; less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly
affects wait IDD; measured with PLL enabled.
8. This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same
potential as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is
guaranteed under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the
VEIO interrupt is generated).
9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage
is regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt
will not be generated unless the external power supply drops below the minimum specified value (3.0V).
10. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power
is ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up
rate is. The internally regulated voltage is typically 100mV less than VDD during ramp-up until 2.5V is reached, at which
time it self-regulates.
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250
200
150
100
50
IDD Analog
IDD Total
IDD Digital
0
10
20
60
70
50
30
80
40
Freq. (MHz)
Figure 3. Maximum Run IDD vs. Frequency (see Note 6. in Table 16)
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics
table. In Figure 4 the levels of VIH and VIL for an input signal are shown.
Low
VIL
High
VIH
90%
50%
10%
Input Signal
Midpoint1
Fall Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Rise Time
Figure 4. Input Signal Measurement References
Figure 5 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state.
Tri-stated, when a bus or signal is placed in a high impedance state.
Data Valid state, when a signal level has reached V or V
OL
OH.
•
Data Invalid state, when a signal level is in transition between V and V
OL
OH.
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Flash Memory Characteristics
Data2 Valid
Data2
Data1 Valid
Data1
Data3 Valid
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 5. Signal States
3.4 Flash Memory Characteristics
Table 24. Flash Memory Truth Table
XE1
YE2
SE3
OE4
PROG5
ERASE6
MAS17
NVSTR8
Mode
Standby
Read
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
H
H
H
H
Word Program
Page Erase
Mass Erase
L
H
H
H
H
H
L
1. X address enable, all rows are disabled when XE=0
2. Y address enable, YMUX is disabled when YE=0
3. Sense amplifier enable
4. Output enable, tri-state Flash data out bus when OE=0
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle
Table 25. IFREN Truth Table
Mode
IFREN=1
IFREN=0
Read
Read information block
Program information block
Erase information block
Erase both block
Read main memory block
Program main memory block
Erase main memory block
Erase main memory block
Word program
Page erase
Mass erase
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Table 26. Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Program time
Symbol
Min
20
Typ
Max
Unit
us
Figure
Figure 6
Figure 7
Figure 8
–
–
–
–
–
–
Tprog*
Erase time
20
–
–
ms
Terase*
Mass erase time
100
10,000
10
ms
Tme*
ECYC
Endurance1
20,000
30
cycles
years
Data Retention1 @ 5000 cycles
DRET
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set
up time
–
5
–
us
Figure 6,
Figure 7, Figure 8
Tnvs*
NVSTR hold time
–
–
–
–
5
100
10
1
–
–
–
–
us
us
us
us
Figure 6, Figure 7
Figure 8
Tnvh*
Tnvh1*
Tpgs*
Trcv*
NVSTR hold time (mass erase)
NVSTR to program set up time
Recovery time
Figure 6
Figure 6,
Figure 7, Figure 8
Cumulative program
HV period2
–
3
–
ms
Figure 6
Thv
Program hold time3
–
–
–
–
–
–
–
–
–
Figure 6
Figure 6
Figure 6
Tpgh
Tads
Tadh
Address/data set up time3
Address/data hold time3
1. One cycle is equal to an erase program and read.
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot
be programmed twice before next erase.
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
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Flash Memory Characteristics
IFREN
XADR
XE
Tadh
YADR
YE
DIN
Tads
PROG
NVSTR
Tnvs
Tprog
Tpgh
Tpgs
Tnvh
Trcv
Thv
Figure 6. Flash Program Cycle
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IFREN
XADR
XE
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Tnvh
Trcv
Terase
Figure 7. Flash Erase Cycle
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1
Trcv
Tme
Figure 8. Flash Mass Erase Cycle
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External Clock Operation
3.5 External Clock Operation
The 56F807 system clock can be derived from an external crystal or an external system clock signal. To
generate a reference frequency using the internal oscillator, a reference crystal must be connected between
the EXTAL and XTAL pins.
3.5.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 28. In Figure 9 a recommended crystal
oscillator circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal, since
crystal parameters determine the component values required to provide maximum stability and reliable
start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and
XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x oscillator
circuitry is designed to have no external load capacitors present. As shown in Figure 10 no external load
capacitors should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF as
a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:
CL1 * CL2
CL1 + CL2
12 * 12
12 + 12
CL =
+ Cs =
+ 3 = 6 + 3 = 9pF
This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.
Recommended External Crystal
Parameters:
EXTAL XTAL
Rz
fc
Rz = 1 to 3 MΩ
fc = 8MHz (optimized for 8MHz)
Figure 9. Connecting to a Crystal Oscillator
3.5.2
Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. In Figure 10, a typical ceramic resonator circuit is shown.
Refer to supplier’s recommendations when selecting a ceramic resonator and associated components. The
resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The
internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in
Figure 9 no external load capacitors should be used.
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Recommended Ceramic Resonator
EXTAL XTAL
Parameters:
Rz = 1 to 3 MΩ
Rz
fc = 8MHz (optimized for 8MHz)
fc
Figure 10. Connecting a Ceramic Resonator
Note: Motorola recommends only two terminal ceramic resonators vs. three terminal
resonators (which contain an internal bypass capacitor to ground).
3.5.3
External Clock Source
The recommended method of connecting an external clock is given in Figure 11. The external clock
source is connected to XTAL and the EXTAL pin is grounded.
56F807
XTAL
EXTAL
VSS
External
Clock
Figure 11. Connecting an External Clock Signal
5
Table 27. External Clock Operation Timing Requirements
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Symbol
fosc
Min
0
Typ
—
Max
80
Unit
MHz
ns
Frequency of operation (external clock driver)1
Clock Pulse Width2, 3
tPW
6.25
—
—
1. See Figure 11 for details on using the recommended connection of an external clock driver.
2. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
3. Parameters listed are guaranteed by design.
VIH
External
Clock
90%
50%
10%
90%
50%
10%
VIL
tPW
tPW
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 12. External Clock Timing
26
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External Bus Asynchronous Timing
3.5.4
Phase Locked Loop Timing
Table 28. PLL Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Symbol
fosc
Min
4
Typ
8
Max
10
Unit
MHz
MHz
ms
External reference crystal frequency for the PLL1
PLL output frequency2
fout/2
tplls
40
—
—
—
110
10
PLL stabilization time3 0o to +85oC
PLL stabilization time3 -40o to 0oC
1
tplls
100
200
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.2.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter
in the User Manual. ZCLK = fop
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
3.6 External Bus Asynchronous Timing
1,2
Table 29. External Bus Asynchronous Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Unit
Min
Max
Address Valid to WR Asserted
tAWR
tWR
6.5
—
ns
WR Width Asserted
Wait states = 0
Wait states > 0
7.5
(T*WS)+7.5
—
—
ns
ns
WR Asserted to D0–D15 Out Valid
tWRD
tDOH
tDOS
—
T + 4.2
—
ns
ns
Data Out Hold Time from WR Deasserted
4.8
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
2.2
(T*WS)+6.4
—
—
ns
ns
RD Deasserted to Address Not Valid
tRDA
0
—
—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
18.7
(T*WS) + 18.7
ns
ns
Input Data Hold to RD Deasserted
tDRD
tRD
0
—
ns
RD Assertion Width
Wait states = 0
Wait states > 0
19
—
—
ns
ns
(T*WS)+19
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1,2
Table 29. External Bus Asynchronous Timing
(Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Unit
Min
Max
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD
—
—
1
ns
ns
(T*WS)+1
Address Valid to RD Asserted
tARDA
tRDD
-4.4
—
ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
—
—
2.4
ns
ns
(T*WS) + 2.4
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
WR Deasserted to WR Asserted
RD Deasserted to WR Asserted
tWRRD
tRDRD
tWRWR
tRDWR
6.8
0
—
—
—
—
ns
ns
ns
ns
14.1
12.8
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
A0–A15,
PS, DS
tARDD
(See Note)
tRDA
tARDA
tRDRD
tRD
tAWR
tWRWR
RD
tWRRD
tWR
tRDWR
WR
tRDD
tAD
tDOH
tWRD
tDRD
tDOS
Data In
Data Out
D0–D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 13. External Bus Asynchronous Timing
28
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
,5
1,5
Table 30. Reset, Stop, Wait, Mode Select, and Interrupt Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
See
Figure
Characteristic
Symbol
Min
Max
Unit
RESET Assertion to Address, Data and Control Signals
High Impedance
tRAZ
—
21
ns
Figure 14
Figure 14
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
275,000T
128T
—
—
ns
ns
RESET Deassertion to First External Address Output
Edge-sensitive Interrupt Request Width
tRDA
tIRW
tIDM
33T
1.5T
15T
34T
—
ns
ns
ns
Figure 14
Figure 15
Figure 16
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
—
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
tIG
16T
—
ns
Figure 16
Figure 17
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
tIRI
13T
2T
—
—
ns
ns
IRQA Width Assertion to Recover from Stop State4
tIW
tIF
Figure 18
Figure 18
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
—
—
275,000T
12T
ns
ns
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting Stop)
OMR Bit 6 = 0
tIRQ
Figure 19
Figure 19
—
—
275,000T
12T
ns
ns
OMR Bit 6 = 1
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
tII
—
—
275,000T
12T
ns
ns
OMR Bit 6 = 1
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
This is not the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
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RESET
tRA
tRAZ
tRDA
First Fetch
A0–A15,
D0–D15
PS, DS,
RD, WR
First Fetch
Figure 14. Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 15. External Interrupt Timing (Negative-Edge-Sensitive)
A0–A15,
PS, DS,
RD, WR
First Interrupt Instruction Execution
tIDM
IRQA,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 16. External Level-Sensitive Interrupt Timing
IRQA,
IRQB
tIRI
A0–A15,
PS, DS,
RD, WR
First Interrupt Vector
Instruction Fetch
Figure 17. Interrupt from Wait State Timing
30
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Serial Peripheral Interface (SPI) Timing
tIW
IRQA
tIF
A0–A15,
PS, DS,
RD, WR
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 18. Recovery from Stop State Using Asynchronous Interrupt Timing
tIRQ
IRQA
tII
A0–A15
PS, DS,
RD, WR
First IRQA Interrupt
Instruction Fetch
Figure 19. Recovery from Stop State Using IRQA Interrupt Service
RSTO
tRSTO
Figure 20. Reset Output Timing
3.8 Serial Peripheral Interface (SPI) Timing
1
Table 31. SPI Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
Figures 21-24
50
25
—
—
ns
ns
Enable lead time
Master
Slave
tELD
Figure 24
Figure 24
—
25
—
—
ns
ns
Enable lag time
Master
Slave
tELG
—
100
—
—
ns
ns
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1
Table 31. SPI Timing (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Clock (SCK) high time
Master
Slave
tCH
tCL
tDS
tDH
tA
Figures 21, 22,
23, 24
17.6
12.5
—
—
ns
ns
Clock (SCK) low time
Master
Slave
Figure 24
24.1
25
—
—
ns
ns
Data set-up time required for inputs
Master
Slave
Figures 21, 22,
23, 24
20
0
—
—
ns
ns
Data hold time required for inputs
Master
Slave
Figures 21, 22,
23, 24
0
2
—
—
ns
ns
Access time (time to data active from
high-impedance state)
Slave
Figure 24
Figure 24
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
tD
15.2
Data Valid for outputs
Master
Slave (after enable edge)
tDV
Figures 21, 22,
23, 24
—
—
4.5
20.4
ns
ns
Data invalid
Master
Slave
tDI
tR
tF
Figures 21, 22,
23, 24
0
0
—
—
ns
ns
Rise time
Master
Slave
Figures 21, 22,
23, 24
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
Figures 21, 22,
23, 24
—
—
9.7
9.0
ns
ns
1. Parameters listed are guaranteed by design.
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Serial Peripheral Interface (SPI) Timing
SS
(Input)
SS is held High on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
tDV
MOSI
(Output)
Master MSB out
tF
Bits 14–1
Master LSB out
tR
Figure 21. SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR
tDH
MISO
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
(Input)
tDV(ref)
tDV
Bits 14– 1
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 22. SPI Master Timing (CPHA = 1)
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SS
(Input)
tC
tF
tR
tELG
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tA
tF
tD
tR
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
Slave LSB out
tDI
tDS
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 23. SPI Slave Timing (CPHA = 0)
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tA
tCH
tR
tD
Slave LSB out
tDI
tF
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
tDS
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 24. SPI Slave Timing (CPHA = 1)
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Quad Timer Timing
3.9 Quad Timer Timing
1, 2
Table 32. Timer Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Timer input period
Symbol
PIN
Min
4T + 6
2T + 3
2T
Max
—
Unit
ns
Timer input high/low period
Timer output period
PINHL
POUT
—
ns
—
ns
Timer output high/low period
POUTHL
1T
—
ns
1.
In the formulas listed, T = the clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PINHL
PINHL
PIN
Timer Outputs
POUTHL
POUTHL
POUT
Figure 25. Timer Timing
3.10 Quadrature Decoder Timing
1, 2
Table 33. Quadrature Decoder Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Quadrature input period
Symbol
PIN
Min
Max
—
Unit
ns
8T + 12
4T + 6
2T + 3
Quadrature input high/low period
Quadrature phase period
PHL
—
ns
PPH
—
ns
1. In the formulas listed, T = the clock cycle. For 80MHz operation, T=12.5ns. VSS = 0V, VDD
=
3.0–3.6V,
TA = –40° to +85°C, CL ≤ 50pF.
2. Parameters listed are guaranteed by design.
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PPH PPH PPH PPH
Phase A
(Input)
PHL
PIN
PHL
Phase B
(Input)
PHL
PIN
PHL
Figure 26. Quadrature Decoder Timing
3.11 Serial Communication Interface (SCI) Timing
4
Table 34. SCI Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Symbol
Min
—
Max
Unit
Baud Rate1
BR
(fMAX*2.5)/(80)
Mbps
RXD2 Pulse Width
TXD3 Pulse Width
RXDPW
TXDPW
0.965/BR
1.04/BR
1.04/BR
ns
ns
0.965/BR
1. fMAX is the frequency of operation of the system clock in MHz.
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
RXD
SCI receive
data pin
RXDPW
(Input)
Figure 27. RXD Pulse Width
TXD
SCI receive
data pin
TXDPW
(Input)
Figure 28. TXD Pulse Width
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Analog-to-Digital Converter (ADC) Characteristics
3.12 Analog-to-Digital Converter (ADC) Characteristics
Table 35. ADC Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14, (for optimal
performance), ADC clock = 4MHz, 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
ADC input voltages
Symbol
Min
Typ
Max
Unit
2
01
12
—
—
VREF
12
VADCIN
—
V
Resolution
RES
INL
—
Bits
Integral Non-Linearity3
Differential Non-Linearity
LSB4
LSB4
+/- 2.5
+/- 0.9
+/- 4
+/- 1
DNL
Monotonicity
GUARANTEED
—
ADC internal clock5
Conversion range
fADIC
RAD
tADC
0.5
VSSA
—
5
MHz
V
—
6
VDDA
—
tAIC cycles6
tAIC cycles6
Conversion time
Sample time
tADS
—
1
—
pF6
—
Input capacitance
CADI
EGAIN
THD
—
0.93
60
5
1.00
64
—
1.08
—
Gain Error (transfer gain)5
Total Harmonic Distortion5
Offset Voltage5
VOFFSET
SINAD
ENOB
SFDR
-90
55
-25
60
+10
—
mV
—
Signal-to-Noise plus Distortion5
Effective Number of Bits5
9
10
—
bit
Spurious Free Dynamic Range5
Bandwidth
65
70
—
dB
BW
—
—
100
50
—
—
KHz
mA
ADC Quiescent Current (each dual ADC)
IADC
VREF Quiescent Current (each dual ADC)
IVREF
—
12
16.5
mA
1. For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert
to a digital output code of 0.
2. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF
to VDDA-0.3V.
3. Measured in 10-90% range.
4. LSB = Least Significant Bit.
5. Guaranteed by characterization.
6. tAIC = 1/fADIC
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.
ADC analog input
3
1
2
4
Figure 29. Equivalent Analog Input Circuit
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is
only connected to it at sampling time. (1pf)
3.13 Controller Area Network (CAN) Timing
2
Table 36. CAN Timing
Operating Conditions:
V
= V
= 0 V, V = V
= 3.0–3.6 V, T = –40° to +85°C, C ≤ 50pF, MSCAN Clock = 30MHz
SS
SSA
DD
DDA A L
Characteristic
Symbol
Min
—
5
Max
Unit
Baud Rate
Bus Wakeup detection 1
BRCAN
1
Mbps
T WAKEUP
µs
—
1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any
bus event (on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus
wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds
originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of
1Mbps.
2. Parameters listed are guaranteed by design
MSCAN_RX
CAN receive
data pin
T WAKEUP
(Input)
Figure 30. Bus Wakeup Detection
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JTAG Timing
3.14 JTAG Timing
1, 3
Table 37. JTAG Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
TCK frequency of operation2
Symbol
Min
Max
Unit
fOP
DC
10
MHz
TCK cycle time
tCY
tPW
tDS
100
50
—
—
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock pulse width
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
DE assertion time
0.4
1.2
—
—
tDH
—
tDV
26.6
23.5
—
tTS
—
tTRST
tDE
50
4T
—
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation,
T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
tCY
tPW
tPW
VIH
VM
VIL
VM
TCK
(Input)
VM = VIL + (VIH – VIL)/2
Figure 31. Test Clock Input Timing Diagram
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TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 32. Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 33. TRST Timing Diagram
DE
tDE
Figure 34. OnCE—Debug Event
40
56F807 Technical Data
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Package and Pin-Out Information 56F807
Part 4 Packaging
4.1 Package and Pin-Out Information 56F807
This section contains package and pin-out information for the 56F807. This device comes in two case types:
low-profile quad flat pack (LQFP) or mold array process ball grid assembly (MAPBGA). Figure 35 shows
the package outline for the LQFP case, Figure 36 shows the mechanical parameters for the LQFP case, and
Table 38 lists the pinout for the LQFP case. Figure 37 shows the mechanical parameters for the MAPBGA
case, and Table 39 lists the pinout for the MAPBGA package.
ORIENTATION
MARK
ANB7
ANB6
ANB5
ANB4
ANB3
ANB2
ANB1
ANB0
VSSA
A0
A1
A2
A3
A4
A5
A6
A7
VDD
A8
PIN 121
PIN 1
VDDA
VREF2
ANA7
ANA6
ANA5
ANA4
ANA3
ANA2
ANA1
ANA0
VSSA
A9
A10
A11
A12
A13
A14
A15
VSS
PS
DS
WR
RD
D0
D1
Motorola
56F807
VDDA
VREF
RESET
RSTO
VDD
VSS
VDD
D2
D3
D4
EXTAL
XTAL
D5
D6
VSS
D7
VSS
D8
VDD
D9
VDDA
VSSA
D10
VDD
D11
D12
D13
D14
D15
GPIOB0
EXTBOOT
FAULTA3
FAULTA2
FAULTA1
FAULTA0
PWMA5
PIN 81
PIN 41
Figure 35. Top View, 56F807 160-pin LQFP Package
56F807 Technical Data
41
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160X
0.20 C A-B D
D
b
GG
D
2
6
D
(b)
SECTION G-G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED
WHERE THELEADSEXIT THE PLASTIC BODY
AT DATUM PLANE H.
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25mm PER SIDE.
DIMENSIONS D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS
INCLUDING MOLD MISMATCH.
D1
2
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b
DIMENSION BY MORE THAN 0.08mm.
DAMBAR CAN NOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN A PROTRUSION AND AN
ADJACENT LEAD IS 0.07mm.
D1
4X
0.20 H A-B D
DETAIL F
6. EXACT SHAPE OF CORNERS MAY VARY.
0.08 C
156X e
C
MILLIMETERS
DIM MIN MAX
4X e/2
SEATING
PLANE
160X e
A
A1
A2
b
b1
c
c1
D
D1
e
---
0.05
1.35
0.17
0.17
0.09
0.09
1.60
0.15
1.45
0.27
0.23
0.20
0.16
M
0.08
C A-B D
θ2
θ1
H
26.00 BSC
24.00 BSC
0.50 BSC
R1
R2
E
E1
L
26.00 BSC
24.00 BSC
0.45
0.75
L1
R1
R2
S
1.00 REF
θ3
0.25
0.08
0.08
0.20
---
0.20
---
θ
GAGE
PLANE
S
L
(L1)
θ
0
0
11
11
7
---
13
13
°
°
°
°
°
θ 1
θ 2
θ 3
°
°
DETAIL F
CASE 1259-01
ISSUE O
Figure 36. 160-pin LQFP Mechanical Information
42
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Package and Pin-Out Information 56F807
Table 38. 56F807 LQFP Package Pin Identification by Pin Number
Pin No. Signal Name Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
2
A0
A1
41
42
GPIOB1
GPIOB2
81
82
PWMA5
121
122
DE
FAULTA0
VSS
3
4
5
6
7
A2
A3
A4
A5
A6
43
44
45
46
47
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
83
84
85
86
87
FAULTA1
FAULTA2
FAULTA3
EXTBOOT
VSSA
123
124
125
126
127
ISA0
ISA1
ISA2
TD0
TD1
8
9
A7
VDD
A8
48
49
50
51
VSS
88
89
90
91
VDDA
VDD
VSS
128
129
130
131
TD2
TD3
TC0
TC1
GPIOD0
GPIOD1
GPIOD2
10
11
A9
VSS
12
13
14
A10
A11
A12
52
53
54
GPIOD3
GPIOD4
GPIOD5
92
93
94
XTAL
EXTAL
VDD
132
133
134
TRST
TCS
TCK
15
16
A13
A14
55
56
TXD1
RXD1
95
96
VSS
VDD
135
136
TMS
TDI
17
18
A15
VSS
57
58
PWMB0
PWMB1
97
98
RSTO
137
138
TDO
RESET
VCAPC2
19
20
PS
DS
59
60
PWMB2
PWMB3
99
VREF
VDDA
139
140
MSCAN_TX
VDD
100
21
WR
61
PWMB4
101
VSSA
141
VSS
22
23
RD
D0
62
63
PWMB5
VDD
102
103
ANA0
ANA1
142
143
MSCAN_RX
SS
24
25
26
27
D1
D2
D3
D4
64
65
66
67
ISB0
VCAPC1
ISB1
104
105
106
107
ANA2
ANA3
ANA4
ANA5
144
145
146
147
SCLK
MISO
MOSI
PHA0
ISB2
56F807 Technical Data
43
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Table 38. 56F807 LQFP Package Pin Identification by Pin Number (Continued)
Pin No. Signal Name Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
28
29
30
31
D5
D6
D7
D8
68
69
70
71
VPP2
IRQA
108
109
110
111
ANA6
ANA7
VREF2
VDDA
148
149
150
151
PHB0
INDX0
HOME0
PHA1
IRQB
FAULTB0
32
33
34
D9
72
73
74
FAULTB1
FAULTB2
FAULTB3
112
113
114
VSSA
ANB0
ANB1
152
153
154
PHB1
VDD
D10
VDD
INDX1
35
36
D11
D12
75
76
PWMA0
VSS
115
116
ANB2
ANB3
155
156
HOME1
VPP
37
D13
77
PWMA1
117
ANB4
157
VSS
38
39
40
D14
D15
78
79
80
PWMA2
PWMA3
PWMA4
118
119
120
ANB5
ANB6
ANB7
158
159
160
CLKO
TXD0
RXD0
GPIOB0
44
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Package and Pin-Out Information 56F807
D
X
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
Y
M
K
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND
TOLERANCES PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
E
5. PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.
MILLIMETERS
DIM MIN MAX
0.20
A
A1
A2
b
1.32
0.27
1.18 REF
1.75
0.47
0.35
0.65
13X
e
D
E
e
15.00 BSC
15.00 BSC
1.00 BSC
0.50 BSC
S
METALIZED MARK FOR
PIN 1 IDENTIFICATION
IN THIS AREA
S
14 13 12 11 10
9
6
5
4
3
2
1
A
B
C
D
E
F
5
S
0.30 Z
A2
13X
e
A
G
H
J
160X
A1
0.15 Z
4
Z
K
L
M
DETAIL K
ROTATED 90 CLOCKWISE
°
N
P
3
160X
b
0.30 Z X Y
0.10 Z
VIEW M-M
CASE 1268-01
ISSUE O
DATE 04/06/98
Figure 37. 160 MAPBGA Mechanical Information
56F807 Technical Data
45
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Table 39. 160 MAPBGA Package Pin Identification by Pin Number
Solder
Ball
Solder
Ball
Solder
Ball
Solder
Ball
Signal Name
Signal Name
Signal Name
Signal Name
C3
B2
D3
C2
B1
A0
A1
A2
A3
A4
N4
P4
M4
L5
GPIOB5
GPIOB6
GPIOB7
VSS
K12
K13
L14
K11
K14
E10
D9
B9
E9
A9
TC1
TRST
TCS
TCK
TMS
VSSA
VDDA
VDD
VSS
N5
GPIOD0
VSS
D2
C1
D1
A5
A6
A7
P5
K5
N6
GPIOD1
GPIOD2
GPIOD3
J13
J12
J14
XTAL
EXTAL
VDD
D8
B8
A8
TDI
TDO
VCAPC2
E3
E2
E1
L6
K6
P6
GPIOD4
GPIOD5
TXD1
J11
H13
H12
E8
D7
E7
MSCAN_TX
VDD
VDD
A8
VSS
V
DD
A9
RSTO
VSS
F3
F2
F1
A10
A11
A12
N7
L7
P7
RXD1
H14
H11
G12
RESET
VREF
VDDA
D6
H1
H2
MSCAN_RX
PWMB0
PWMB1
D1
D2
G3
A13
K7
PWMB2
G11
J3
D3
VSSA
G2
G1
F4
A14
A15
VSS
L8
K8
P8
PWMB3
PWMB4
PWMB5
G14
B13
A14
ANA0
DE
J1
J2
K3
D4
D5
D6
VSS
G4
PS
L9
B12
ISA0
K1
D7
VDD
H4
J4
DS
WR
N8
P14
M13
L12
ISB0
A13
A12
B11
A11
ISA1
ISA2
TD0
TD1
L1
K2
L3
D8
D9
PWMA5
FAULTA0
FAULTA1
K4
P1
RD
D10
VDD
GPIOB1
M1
N3
P2
P3
GPIOB2
GPIOB3
GPIOB4
N14
L13
FAULTA2
FAULTA3
EXTBOOT
D10
B10
A10
TD2
TD3
TC0
L2
N1
M2
D11
D12
D13
M14
46
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Package and Pin-Out Information 56F807
Table 39. 160 MAPBGA Package Pin Identification by Pin Number (Continued)
Solder
Ball
Solder
Ball
Solder
Ball
Solder
Ball
Signal Name
Signal Name
Signal Name
Signal Name
N2
D14
N11
D14
D5
PHB0
VSS
VSSA
M3
L4
D15
GPIOB0
VCAPC1
ISB1
P13
N12
N13
M12
F11
PWMA1
PWMA2
PWMA3
PWMA4
ANA1
D11
D12
D13
C14
C13
ANA8
ANA9
B6
A5
E4
B5
A4
INDX0
HOME0
PHA1
PHB1
VDD
K10
K9
ANA10
ANA11
ANA12
P9
ISB2
L10
N9
VPP2
IRQA
G13
F12
F14
E11
F13
E12
E14
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
VREF2
C11
B14
C12
A7
ANA13
ANA14
ANA15
SS
D4
C4
B4
A2
B3
A1
A3
INDX1
HOME1
VPP
P10
P11
N10
L11
M11
IRQB
FAULTB0
FAULTB1
FAULTB2
FAULTB3
CLKO
TXD0
RXD0
VSS
E5
SCLK
MISO
MOSI
B7
A6
P12
PWMA0
E13
E6
PHA0
H3
D0
VDDA
56F807 Technical Data
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Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, T , in °C can be obtained from the equation:
J
Equation 1: TJ = TA + (PD × RθJA
)
Where:
T = ambient temperature °C
A
R
= package junction-to-ambient thermal resistance °C/W
θJA
P = power dissipation in package
D
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2: RθJA = RθJC + RθCA
Where:
R
R
R
= package junction-to-ambient thermal resistance °C/W
= package junction-to-case thermal resistance °C/W
= package case-to-ambient thermal resistance °C/W
θJA
θJC
θCA
R
is device-related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case-to-ambient thermal resistance, R
. For example, the user can change the air flow around
θCA
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from R
do not satisfactorily answer whether the
θJA
thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
•
Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.
•
•
Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.
Use the value obtained by the equation (T – T )/P where T is the temperature of the package
J
T
D
T
case determined by a thermocouple.
48
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The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that
the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface
between the case of the package and the interface material. A clearance slot or hole is normally required in
the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this case
temperature, the junction temperature is determined from the junction-to-case thermal resistance.
5.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Use the following list of considerations to assure correct operation:
•
Provide a low-impedance path from the board power supply to each V pin on the hybrid
DD
controller, and from the board ground to each V pin.
SS
•
The minimum bypass requirement is to place 0.1 µF capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor
on each of the V /V pairs, including V
/V
Ceramic and tantalum capacitors tend to
DD SS
DDA SSA.
provide better performance tolerances.
•
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and
DD
V
pins are less than 0.5 inch per capacitor lead.
SS
Bypass the V and V layers of the PCB with approximately 100 µF, preferably with a
DD
SS
high-grade capacitor such as a tantalum capacitor.
•
•
Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be
minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V and V circuits.
DD
SS
49
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•
•
Take special care to minimize noise levels on the VREF, V
and V
pins.
SSA
DDA
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at
power up for proper operation. Designs that do not require debugging functionality, such as
consumer products, TRST should be tied low.
•
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.
50
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Electrical Design Considerations
Part 6 Ordering Information
Table 40 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales
office or authorized distributor to determine availability and to order parts.
Table 40. 56F807 Ordering Information
Supply
Voltage
Pin
Count
Frequency
(MHz)
Part
Package Type
Order Number
56F807
56F807
3.0–3.6 V Low-Profile Quad Flat Pack (LQFP)
160
160
80
80
DSP56F807PY80
DSP56F807VF80
3.0–3.6 V Mold Array Process Ball Grid Array
(MAPBGA)
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USA/EUROPE/LOCATIONS NOT LISTED:
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P.O. Box 5405, Denver, Colorado 80217
1-800-521-6274 or 480-768-2130
JAPAN:
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu
Minato-ku
Tokyo 106-8573, Japan
81-3-3440-3569
Information in this document is provided solely to enable system and software
implementers to use Motorola products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.
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2 Dai King Street
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts.
Motorola does not convey any license under its patent rights nor the rights of
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components in systems intended for surgical implant into the body, or other
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DSP56F807/D
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