DSP56F826 [MOTOROLA]
Preliminary Technical Data DSP56F826 16-bit Digital Signal Processor; 初步的技术资料DSP56F826 16位数字信号处理器
| 型号： | DSP56F826 |
| 厂家： | 
MOTOROLA |
| 描述： | Preliminary Technical Data DSP56F826 16-bit Digital Signal Processor |
| 文件： | 总44页 (文件大小：594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSP56F826/D
Rev. # 0, 3/2001
Semiconductor Products Sector
DSP56F826
Preliminary Technical Data
DSP56F826 16-bit Digital Signal Processor
•
Up to 40 MIPS at 80MHz core frequency
•
Up to 64K × 16-bit words each of external
memory expansion for Program and Data
memory
•
DSP and MCU functionality in a unified,
C-efficient architecture
•
•
One Serial Port Interface (SPI)
•
•
Hardware DO and REP loops
One additional SPI or two optional Serial
Communication Interfaces (SCI)
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
•
•
•
•
•
•
One Synchronous Serial Interface (SSI)
One General Purpose Quad Timer
JTAG/OnCE™ for debugging
100-pin LQFP Package
•
•
•
•
•
31.5K × 16-bit words Program Flash
512 × 16-bit words Program RAM
2K × 16-bit words Data Flash
4K × 16-bit words Data RAM
2K × 16-bit words BootFLASH
16 dedicated and 30 shared GPIO
One Time-of-Day module
EXTBOOT
IRQB
IO
IO
RESET
IRQA
V
V
DD
SS
V
V
SS
V
V
SSA
DD
DDA
6
3
3
4
4
Low Voltage Supervisor
JTAG/
OnCE
Port
Analog Reg
TOD
Timer
Data ALU
Address
Generation
Unit
Bit
Manipulation
Unit
Program Controller
and
Hardware Looping Unit
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Interrupt
Controller
Program Memory
32252 x 16 Flash
512 x 16 SRAM
PAB
PDB
Quad Timer
or
GPIO
CLKO
PLL
16-Bit
DSP56800
Core
4
XTAL
Boot Flash
2048 x 16 Flash
Clock Gen
.
EXTAL
XDB2
CGDB
XAB1
XAB2
Data Memory
2048 x 16 Flash
4096 x 16 SRAM
SSI
or
GPIO
6
INTERRUPT
CONTROLS
IPBB
CONTROLS
16
SCI0 & SCI1
External
Address Bus
Switch
16
A[00:15]
or
GPIO
COP
or
SPI0
RESET
COP/
Watchdog
4
4
16
16
External
Data Bus
Switch
SPI1
or
GPIO
External
Bus
Interface
Unit
MODULE CONTROLS
D[00:15]
Application-
Specific
Memory &
Peripherals
IPBus Bridge
(IPBB)
ADDRESS BUS [8:0]
DATA BUS [15:0]
PS Select
DS Select
WR Enable
RD Enable
Bus
Control
Dedicated
GPIO
16
Figure 1. DSP56F826 Block Diagram
© Motorola, Inc., 2001. All rights reserved.
Part 1 Overview
1.1 DSP56F826 Features
1.1.1
Digital Signal Processing Core
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Efficient 16-bit DSP56800 Family DSP engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators, including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE Debug Programming Interface
1.1.2
Memory
•
Harvard architecture permits as many as three simultaneous accesses to program and data memory
On-chip memory including a low cost, high volume flash solution
— 31.5K × 16-bit words of Program Flash
•
— 512 × 16-bit words of Program RAM
— 2K × 16-bit words of Data Flash
— 4K × 16-bit words of Data RAM
— 2K × 16-bit words of BootFLASH
•
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64 K × 16-bit data memory
— As much as 64 K × 16-bit program memory
1.1.3
Peripheral Circuits for DSP56F826
•
•
•
One General Purpose Quad Timer totalling 7pins
One Serial Peripheral Interface with 4 pins (or four additional GPIO lines)
One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces totalling
4 pins
•
Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines)
2
DSP56F826 Preliminary Technical Data
ꢀ
DSP56F826 Description
•
•
•
•
•
•
•
•
•
Sixteen (16) dedicated general purpose I/O (GPIO) pins
Thirty (30) shared general purpose I/O (GPIO) pins
Computer-Operating Properly (COP) Watchdog timer
Two external interrupt pins
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock
Fabricated in high-density EMOS with 5V tolerant, TTL-compatible digital inputs
One Time of Day module
Energy Information
•
•
Dual power supply, 3.3V and 2.5V
Wait and Multiple Stop modes available
1.2 DSP56F826 Description
The DSP56F826 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution for general purpose applications.
Because of its low cost, configuration flexibility, and compact program code, the DSP56F826 is well-
suited for many applications. The DSP56F826 includes many peripherals that are especially useful for
applications such as: noise suppression, ID tag readers, sonic/subsonic detectors, security access devices,
remote metering, sonic alarms, POS terminals, feature phones.
The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid
development of optimized control applications.
The DSP56F826 supports program execution from either internal or external memories. Two data operands
can be accessed from the on-chip Data RAM per instruction cycle. The DSP56F826 also provides two
external dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The DSP56F826 DSP controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data
Flash (each programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data
RAM. It also supports program execution from external memory.
The DSP56F826 incorporates a total of 2K words of BootFLASH for easy customer-inclusion of field-
programmable software routines that can be used to program the main Program and Data Flash memory
areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of
256 words. The BootFLASH memory can also be either bulk- or page-erased.
This DSP controller also provides a full set of standard programmable peripherals including one
Synchronous Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI
or two Serial Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and quad timer can be
used as General Purpose Input/Outputs (GPIOs) if a timer function is not required.
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DSP56F826 Preliminary Technical Data
3
1.3 Best in Class Development Environment
The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces
that allow programmers to create their unique C application code independent of component architecture.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete,
scalable tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 1 are required for a complete description and proper design with the
DSP56F826. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/.
Table 1. DSP56F826 Chip Documentation
Topic
DSP56800
Description
Order Number
DSP56800FM/D
Detailed description of the DSP56800 family architecture,
and 16-bit DSP core processor and the instruction set
Family Manual
DSP56824/F826/F827
User’s Manual
Detailed description of memory, peripherals, and interfaces
of the DSP56824, DSP56F826, DSP56F827
TBD
DSP56F826
Technical Data Sheet
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
DSP56F826/D
DSP56F826PB/D
DSP56F826
Product Brief
Summary description and block diagram of the DSP56F826
core, memory, peripherals and interfaces
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when
low.
“asserted”
“deasserted”
Examples:
A high true (active high) signal is high or a low true (active low) signal is low.
A high true (active high) signal is low or a low true (active low) signal is high.
Voltage1
Signal/Symbol
Logic State
True
Signal State
Asserted
PIN
PIN
PIN
PIN
VIL/VOL
False
Deasserted
Asserted
VIH/VOH
VIH/VOH
VIL/VOL
True
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
4
DSP56F826 Preliminary Technical Data
ꢀ
Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the DSP56F826 are organized into functional groups, as shown in Table 2
and as illustrated in Figure 2. In Table 3 describes the signal or signals present on a pin.
Table 2. Functional Group Pin Allocations
Functional Group
Number of Pins
(3,4,1)
Power (VDD , VDDIO or VDDA
)
Ground (VSS , VSSIO or VSSA
PLL and Clock
)
(3,4,1)
3
Address Bus1
Data Bus
16
16
4
Bus Control
Interrupt and Program Control
5
Dedicated General Purpose Input/Output
Synchronous Serial Interface (SSI) Port
16
6
Serial Peripheral Interface (SPI) Port1
Serial Communications Interface (SCI) Ports
Quad Timer Module Ports
4
4
4
6
JTAG/On-Chip Emulation (OnCE)
1. Alternately, GPIO pins
ꢀ
DSP56F826 Preliminary Technical Data
5
DSP56F826
8
8
3
3
V
GPIOB0–7
GPIOD0–7
2.5V Power Port
Ground Port
DD
Dedicated
GPIO
V
SS
DDIO
V
4
4
3.3V Power Port
Ground Port
Analog Power Port (3.3V)
Ground Port
V
SSIO
SRD (GPIOC0)
SRFS (GPIOC1)
SRCK (GPIOC2)
STD (GPIOC3)
STFS (GPIOC4)
STCK (GPIOC5)
V
DDA
V
SSA
SSI Port or
GPIO
EXTAL(CLOCKIN)
XTAL
PLL and Clock
CLKO
External
Bus or GPIO
Address
A0-A15(GPIO/E0–E7,
GPIOA0–A7)
16
16
SCLK (GPIOF4)
MOSI (GPIOF5)
MISO (GPIOF6)
SS (GPIOF7)
SPI1 Port or
GPIO
External Data Bus
D0–D15
PS
DS
External Bus Control
SCI0 Port or
SPI0 Port
TXD0 (SCLK0)
RXD0 (MOSI0)
RD
WR
TA0 (GPIOF0)
TA1 (GPIOF1)
TA2 (GPIOF2)
TA3 (GPIOF3)
SCI1 Port or
SPI0 Port
TXD1 (MISO0)
RXD1 (SS0)
Quad Timer A
IRQA
Interrupt/
Program
Control
IRQB
RESET
EXTBOOT
TCK
TMS
TDI
JTAG/OnCE
Port
TDO
TRST
DE
1
Figure 2. DSP56F826 Signals Identified by Functional Group
1. Alternate pin functionality is shown in parenthesis.
6
DSP56F826 Preliminary Technical Data
ꢀ
Introduction
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1. When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
Type
Description
A0
A1
A2
A3
A4
A5
A6
A7
24
23
22
21
18
17
16
15
Output
Address Bus—A0–A7 specify the address for external program or data
memory accesses.
Output
Output
Output
Output
Output
Output
Output
GPIOE0–
GPIOE7
Input/Output
Port E GPIO—These eight General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is Address Bus.
A8
A9
14
13
12
11
10
9
Output
Output
Output
Output
Output
Output
Address Bus—A8–A15 specify the address for external program or data
memory accesses.
A10
A11
A12
A13
A14
A15
8
7
Output
Output
GPIOA0–
GPIOA7
Input/Output
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is Address Bus.
ꢀ
DSP56F826 Preliminary Technical Data
7
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1. When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
Type
Description
CLKO
65
Output
Clock Output—This pin outputs a buffered clock signal. By programming
the CLKO Select Register (SLKOSR), the user can select between
outputting a version of the signal applied to XTAL and a version of the DSP
master clock at the output of the PLL. The clock frequency on this pin can be
disabled by programming the CLKO Select Register (CLKOSR).
D0
D1
34
35
36
37
38
39
40
41
42
43
44
46
47
48
49
50
98
28
Input/Output
Data Bus— D0–D15 specify the data for external program or data memory
accesses. D0–D15 are tri-stated when the external bus is inactive.
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DE
DS
Output
Output
Debug Event—DE provides a low pulse on recognized debug events.
Data Memory Select—DS is asserted low for external data memory access.
8
DSP56F826 Preliminary Technical Data
ꢀ
Introduction
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1. When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
Type
Description
EXTAL
61
Input
Input
Input
External Crystal Oscillator Input—This input can be connected to an
4MHz external crystal. If a 4MHz or less external clock source is used,
EXTAL can be used as the input and XTAL must not be connected. For
more information, please refer to Section 3.5.2.
CLOCKIN
External Clock Input—This input can be connected to an external 8MHz
clock. For more information, please refer to Section 3.5.
The input clock can be selected to provide the clock directly to the DSP core.
This input clock can also be selected as input clock for the on-chip PLL.
EXTBOOT
25
External Boot—This input is tied to VDD to force device to boot from off-
chip memory. Otherwise, it is tied to ground.
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
GPIOD0
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
66
67
68
69
70
71
72
73
74
75
76
77
78
79
82
83
Input or Output
Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can
be individually programmed as input or output pins.
After reset, the default state is GPIO input.
Input or Output
Port D GPIO—These eight dedicated GPIO pins can be individually
programmed as an input or output pins.
After reset, the default state is GPIO input.
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DSP56F826 Preliminary Technical Data
9
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1. When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
Type
Description
IRQA
32
Input
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge- triggered. If
level-sensitive triggering is selected, an external pull up resistor is required
for wired-OR operation.
If the processor is in the Stop state and IRQA is asserted, the processor will
exit the Stop state.
IRQB
33
86
Input
External Interrupt Request B—The IRQB input is an external interrupt
request that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-
sensitive triggering is selected, an external pull up resistor is required for
wired-OR operation.
MISO
GPIOF6
MOSI
Input/Output
Input/Output
Input/Output
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a slave
device is placed in the high-impedance state if the slave device is not
selected.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is MISO.
85
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places data
on the MOSI line a half-cycle before the clock edge that the slave device
uses to latch the data.
GPIOF5
PS
Input/Output
Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
29
26
Program Memory Select—PS is asserted low for external program memory
access.
RD
Output
Read Enable—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the DSP data bus. When RD is deasserted high, the external
data is latched inside the DSP. When RD is asserted, it qualifies the A0–A15,
PS, and DS pins. RD can be connected directly to the OE pin of a Static
RAM or ROM.
10
DSP56F826 Preliminary Technical Data
ꢀ
Introduction
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1. When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
Type
Description
RESET
45
Input
Reset—This input is a direct hardware reset on the processor. When RESET
is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt
trigger input is used for noise immunity. When the RESET pin is deasserted,
the initial chip operating mode is latched from the external boot pin. The
internal reset signal will be deasserted synchronous with the internal clocks,
after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be asserted
together. The only exception occurs in a debugging environment when a
hardware DSP reset is required and it is necessary not to reset the OnCE/
JTAG module. In this case, assert RESET, but do not assert TRST.
RXD0
96
Input
Receive Data (RXD0)— receive data input
MOSI0
Input/
Output
SPI Master Out/Slave In—This serial data pin is an output from a master
device, and an input to a slave device. The master device places data on the
MOSI line one half-cycle before the clock edge the slave device uses to latch
the data.
After reset, the default state is SCI input.
RXD1
SS0
92
84
Input
Input
Receive Data (RXD1)— receive data input
SPI Slave Select—In maste mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
After reset, the default state is SCI input.
SCLK
Input/Output
Input/Output
SPI Serial Clock—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
GPIOF4
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SCLK.
SRCK
53
Input/Output
Input/Output
SSI Serial Receive Clock (STCK)—This bidirectional pin provides the
serial bit rate clock for the Receive section of the SSI. The clock signal can
be continuous or gated and can be used by both the transmitter and receiver
in synchronous mode.
GPIOC2
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
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DSP56F826 Preliminary Technical Data
11
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1. When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
Type
Description
SRD
51
Input/Output
SSI Receive Data (SRD)—This input pin receives serial data and transfers
the data to the SSI Receive Shift Receiver.
GPIOC0
SRFS
Input/Output
Input/ Output
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
52
SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by
the receive section of the SSI as frame sync I/O or flag I/O. The STFS can be
used only by the receiver. It is used to synchronize data transfer and can be
an input or an output.
GPIOC1
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
SS
87
56
Input
SPI Slave Select—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
GPIOF7
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SS.
STCK
Input/ Output
Input/Output
SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the
serial bit rate clock for the transmit section of the SSI. The clock signal can
be continuous or gated. It can be used by both the transmitter and receiver in
synchronous mode.
GPIOC5
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
STD
54
Output
SSI Transmit Data (STD)—This output pin transmits serial data from the
SSI Transmitter Shift Register.
GPIOC3
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
12
DSP56F826 Preliminary Technical Data
ꢀ
Introduction
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1. When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
Type
Description
STFS
55
Input
SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used
by the Transmit section of the SSI as frame sync I/O or flag I/O. The STFS
can be used by both the transmitter and receiver in synchronous mode. It is
used to synchronize data transfer and can be an input or output pin.
GPIOC4
TA0-3
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
91
90
89
88
Input/Output
Input/Output
TA0–3—Timer F Channels 0, 1, 2, and 3
GPIOF0-
GPIOF3
Port F GPIO—These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.
After reset, the default state is Quad Timer.
TCS
TCK
99
TCS—This pin is reserved for factory use. It must be tied to VSS for normal
use. In block diagrams, this pin is considered an additional VSS.
100
Input
Input
Output
Input
Input
Test Clock Input—This input pin provides a gated clock to synchronize the
test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.
TDI
TDO
TMS
TRST
2
3
1
4
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-
chip pull-up resistor.
Test Data Output—This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
Test Mode Select Input—This input pin is used to sequence the JTAG TAP
controller’s state machine. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
Test Reset—As an input, a low signal on this pin provides a reset signal to
the JTAG TAP controller. To ensure complete hardware reset, TRST should
be asserted whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware DSP reset is required and it is
necessary not to reset the JTAG/OnCE module. In this case, assert RESET,
but do not assert TRST.
ꢀ
DSP56F826 Preliminary Technical Data
13
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1. When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Signal
Pin No.
Type
Description
Name
TXD0
SCLK0
97
Output
Transmit Data (TXD0)—transmit data output
Input/Output
SPI Serial Clock—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
After reset, the default state is SCI output.
TXD1
93
Output
Transmit Data (TXD1)—transmit data output
MISO0
Input/Output
SPI Master In/Slave Out—This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave device is
placed in the high-impedance state if hte slave device is not selected.
After reset, the default state is SCI output.
VDD
VDD
20
64
94
59
5
VDD
Power—These pins provide power to the internal structures of the chip, and
are generally connected to a 2.5V supply.
VDD
VDD
VDD
VDDA
VDDIO
VDDIO
VDDIO
VDDIO
VSS
VDDA
VDDIO
VDDIO
VDDIO
VDDIO
VSS
Analog Power—This pin supplies an analog power source (generally 2.5V).
Power—These pins provide power to the I/O structures of the chip, and are
generally connected to a 3.3V supply.
30
57
80
19
63
95
60
6
GND—These pins provide grounding for the internal structures of the chip.
All should be attached to VSS.
VSS
VSS
VSS
VSS
VSSA
VSSIO
VSSIO
VSSIO
VSSIO
VSSA
VSSIO
VSSIO
VSSIO
VSSIO
Analog Ground—This pin supplies an analog ground.
GND In/Out—These pins provide grounding for the I/O ring on the chip.
All should be attached to VSS.
31
58
81
14
DSP56F826 Preliminary Technical Data
ꢀ
Introduction
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1. When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
Type
Description
WR
27
Output
Write Enable—WR is asserted during external memory write cycles. When
WR is asserted low, pins D0–D15 become outputs and the DSP puts data on
the bus. When WR is deasserted high, the external data is latched inside the
external device. When WR is asserted, it qualifies the A0–A15, PS, and DS
pins. WR can be connected directly to the WE pin of a Static RAM.
XTAL
62
Output
Crystal Oscillator Output—This output connects the internal crystal
oscillator output to an external crystal. If an external clock source over
4MHz is used, XTAL must be used as the input and EXTAL connected to
V
. For more information, please refer to Section 3.5.2.
SS
ꢀ
DSP56F826 Preliminary Technical Data
15
Part 3 Specifications
3.1 General Characteristics
The DSP56F826 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.
The term 5-volt tolerant refers to the capability of an I/O pin, built on a 3.3V compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible
I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage. This 5V tolerant capability, therefore, offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 4 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The DSP56F826 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate logic voltage level (e.g., either or V or V ).
DD
SS
Table 4. Absolute Maximum Ratings (V = 0 V)
SS
Characteristic
Symbol
VDD
VDDIO
VIN
Min
VSS – 0.3
VSS – 0.3
VSS – 0.3
—
Max
Unit
V
Supply voltage, core
3.0
4.0
Supply voltage, IO and analog
All other input voltages
V
VDDIO + 0.3
10
V
Current drain per pin excluding VDD, VSS
Junction temperature
I
mA
°C
°C
TJ
—
150
Storage temperature range
TSTG
–55
150
16
DSP56F826 Preliminary Technical Data
ꢀ
DC Electrical Characteristics
Table 5. Recommended Operating Conditions
Characteristic
Symbol
VDD
Min
2.25
3.0
–40
0
Max
2.75
3.6
Unit
V
Supply voltage, core
Supply Voltage, IO and analog
Ambient operating temperature
Flash program/erase temperature
VDDIO,VDDA
TA
V
85
°C
°C
TF
85
1
Table 6. Thermal Characteristics
100-pin LQFP
Characteristic
Symbol
Value
Unit
Thermal resistance junction-to-ambient
(estimated)
θJA
39.7
°C/W
I/O pin power dissipation
Power dissipation
PI/O
PD
User Determined
PD = (IDD x VDD) + PI/O
(TJ – TA) / θJA
W
W
°C
Maximum allowed PD
PDMAX
1. See Section 5.1 for more detail.
3.2 DC Electrical Characteristics
Table 7. DC Electrical Characteristics
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80 MHz
DDA A L op
SSIO
SS
SSA
DDIO
DD
Characteristic
Symbol
VIHC
VILC
VIH
Min
Typ
2.5
—
Max
Unit
V
Input high voltage (XTAL/EXTAL)
Input low voltage (XTAL/EXTAL)
Input high voltage
2.25
-0.3
2.0
-0.3
-1
2.75
0.5
5.5
0.8
1
V
—
V
Input low voltage
VIL
—
V
Input current low (pullups disabled)
Input current high (pullups disabled)
Output tri-state current low
IIL
—
µA
µA
µA
IIH
-1
—
1
IOZL
-10
—
10
ꢀ
DSP56F826 Preliminary Technical Data
17
Table 7. DC Electrical Characteristics (Continued)
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80 MHz
DDA A L op
SSIO
SS
SSA
DDIO
DD
Characteristic
Symbol
IOZH
VOH
VOL
IOH
Min
Typ
—
—
—
—
—
8
Max
Unit
µA
V
Output tri-state current high
Output High Voltage with IOH load
Output Low Voltage with IOL load
Output High Current
-10
VDD – 0.7
—
10
—
0.4
—
2
V
-300
—
µA
mA
pF
Output Low Current
IOL
Input capacitance
CIN
—
—
—
Output capacitance
COUT
IDD
—
12
pF
VDD supply current
Run 1
Wait2
—
—
—
50
20
2
TBD
TBD
TBD
mA
mA
mA
Stop
Low Voltage Interrupt3
VEI
VEIH
POR
—
—
—
2.7
50
TBD
—
V
mV
V
Low Voltage Interrupt Recovery Hysteresis
Power on Reset4
1.5
2.0
1. Run (operating) IDD measured using external square external square clock source (fosc = 4MHz) into XTAL. All in-
puts 0.2V from rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled.
PLL set to 80MHz out.
2. Wait IDD measured using external square wave clock source (fosc = 8MHz); all inpuyts 0.2V from rail; no DC loads;
less than 50 pF on all outputs. CL= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait
IDD; measured with PLL and LVI enabled
3. When VDD drops below VEI max value, an interrupt is generated.
4. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power
is ramping up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the
ramp up rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached,
at which time it self regulates.
18
DSP56F826 Preliminary Technical Data
ꢀ
AC Electrical Characteristics
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for
all pins except XTAL, which is tested using the input levels in Section 3.2. In Figure 3 the levels of VIH and
VIL for an input signal are shown.
Pulse Width
Low
VIL
High
VIH
90%
50%
10%
Input Signal
Midpoint1
Fall Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Rise Time
Figure 3. Input Signal Measurement References
Figure 4 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state.
Tri-stated, when a bus or signal is placed in a high impedance state.
Data Valid state, when a signal level has reached V or V
OL
OH.
•
Data Invalid state, when a signal level is in transition between V and V
OL OH.
Data2 Valid
Data2
Data1 Valid
Data1
Data3 Valid
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 4. Signal States
ꢀ
DSP56F826 Preliminary Technical Data
19
3.4 Flash Memory Characteristics
Table 8. Flash Memory Truth Table
XE1
YE2
SE3
OE4
PROG5
ERASE6
MAS17
NVSTR8
Mode
Standby
Read
L
H
H
H
H
L
H
H
L
L
L
H
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
L
H
L
L
Word Program
Page Erase
Mass Erase
H
H
H
1. X address enable, all rows are disabled when XE = 0
2. Y address enable, YMUX is disabled when YE = 0
3. Sense amplifier enable
4. Output enable, tri-state flash data out bus when OE = 0
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle
Table 9. IFREN Truth Table
Mode
IFREN = 1
IFREN = 0
Read
Read information block
Program information block
Erase information block
Erase both block
Read main memory block
Word program
Page erase
Mass erase
Program main memory block
Erase main memory block
Erase main memory block
20
DSP56F826 Preliminary Technical Data
ꢀ
Flash Memory Characteristics
Table 10. Timing Symbols
Characteristic
Symbol
See Figure(s)
X address access time
Y address access time
OE access time
-
Txa
Tya
-
-
Toa
PROG/ERASE to NVSTR set up time
NVSTR hold time
Figure 5, Figure 6, Figure 7
Figure 5, Figure 6
Figure 7
Tnvs*
Tnvh*
Tnvh1*
Tpgs*
Tpgh
Tads
NVSTR hold time(mass erase)
NVSTR to program set up time
Program hold time
Figure 5
Figure 5
Address/data set up time
Address/data hold time
Recovery time
Figure 5
Figure 5
Tadh
Figure 5, Figure 6, Figure 7
Figure 5
Trcv*
Thv
Cumulative program HV period
Program time
Figure 5
Tprog*
Terase*
Tme*
Erase time
Figure 6
Mass erase time
Figure 7
* The Flash interface unit provides registers for the control of these parameters.
ꢀ
DSP56F826 Preliminary Technical Data
21
Table 11. Flash Timing Parameters
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80 MHz
DDA A L op
SSIO
SS
SSA
DDIO
DD
Characteristic
Symbol
Min
Typ
Max
—
Unit
Program time1
Erase time2
20
20
—
—
—
—
—
us
ms
Tprog
Terase
Tme
—
Mass erase time3
100
10,000
10
—
ms
Endurance4
ECYC
DRET
—
cycles
years
Data Retention
—
The following parameters should only be used in the Manual Word Programming mode.
PROG/ERASE to NVSTR set up time
NVSTR hold time
—
—
—
—
—
—
5
5
—
—
—
—
—
—
us
us
us
us
us
ms
Tnvs
Tnvh
Tnvh1
Tpgs
Trcv
Thv
NVSTR hold time(mass erase)
NVSTR to program set up time
Recovery time
100
10
1
Cumulative program HV period5
3
1. Program specification guaranteed from TA = 0° C to 85° C.
2. Erase specification guaranteed from TA = 0° C to 85° C.
3. Mass erase specification guaranteed from TA = 0° C to 85° C.
4. One cycle is equal to an erase, program, and read.
5. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot
be programmed twice before next erase.
22
DSP56F826 Preliminary Technical Data
ꢀ
Flash Memory Characteristics
IFREN
XADR
XE
Tadh
YADR
YE
DIN
Tads
PROG
NVSTR
Tnvs
Tprog
Tpgh
Tpgs
Tnvh
Trcv
Thv
Figure 5. Flash Program Cycle
IFREN
XADR
XE
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Tnvh
Trcv
Terase
Figure 6. Flash Erase Cycle
ꢀ
DSP56F826 Preliminary Technical Data
23
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1
Trcv
Tme
Figure 7. Flash Mass Erase Cycle
3.5 External Clock Operation
The DSP56F826 system clock can be derived from a crystal or an external system clock signal. To generate
a reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
3.5.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 13. In Figure 8 a typical crystal oscillator circuit is shown.
Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters
determine the component values required to provide maximum stability and reliable start-up. The crystal
and associated components should be mounted as close as possible to the EXTAL and XTAL pins to
minimize output distortion and start-up stabilization time.
24
DSP56F826 Preliminary Technical Data
ꢀ
External Clock Operation
Crystal Frequency = 4MHz
EXTAL XTAL
Rz
Sample External Crystal
Parameters:
Rz = 20 MW
Figure 8. External Crystal Oscillator Circuit
3.5.2
External Clock Source
The recommended method of connecting an external clock is given in Figure 9. The external clock source
is connected to XTAL and the EXTAL pin is grounded.
DSP56F826
XTAL
EXTAL
V
External
Clock
SS
Figure 9. Connecting an External Clock Signal using XTAL
It is possible to instead drive EXTAL with an external clock, though this is not the recommended method.
If you elect to drive EXTAL with an external clock source the following conditions must be met:
1. XTAL must be completely un-loaded,
2. the maximum frequency of the applied clock must be less than 6MHz.
Figure 10 illustrates how to connect an external clock circuit with a external clock source using EXTAL as
the input.
DSP56F826
XTAL
EXTAL
External
No
Connection Clock ( < 6MHz)
Figure 10. Connecting an External Clock Signal using EXTAL
ꢀ
DSP56F826 Preliminary Technical Data
25
Table 12. External Clock Operation Timing Requirements
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80 MHz
SSIO
SS
SSA
DDIO
DD
DDA
A
L
op
Characteristic
Symbol
fosc
Min
0
Typ
—
Max
Unit
Frequency of operation (external clock driver)1
Clock Pulse Width2, 5
80
—
3
MHz
ns
tPW
6.25
—
—
External clock input rise time3, 5
External clock input fall time4, 5
trise
—
ns
tfall
—
—
3
ns
1. See Figure 9 for details on using the recommended connection of an external clock driver.
2. The high or low pulse width must be no smaller than 6.25 ns or the chip will not function.
3. External clock input rise time is measured from 10% to 90%.
4. External clock input fall time is measured from 90% to 10%.
5. Parameters shown are guaranteed by design.
VIH
External
Clock
90%
50%
10%
90%
50%
10%
tPW
tPW
VIL
tfall
trise
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 11. External Clock Timing
Table 13. PLL Timing
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80 MHz
SSIO
SS
SSA
DDIO
DD
DDA
A
L
op
Characteristic
Symbol
fosc
Min
2
Typ
4
Max
Unit
MHz
MHz
ms
External reference crystal frequency for the PLL1
PLL output frequency
6
fop
40
—
—
1
80
10
PLL stabilization time 2
tplls
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. This is the minimum time required after the PLL setup is changed to ensure reliable operation
26
DSP56F826 Preliminary Technical Data
ꢀ
External Bus Asynchronous Timing
3.6 External Bus Asynchronous Timing
1, 2
Table 14. External Bus Asynchronous Timing
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80 MHz
SSIO
SS
SSA
DDIO
DD
DDA
A
L
op
Characteristic
Address Valid to WR Asserted
Symbol
Unit
Min
Max
tAWR
6.5
—
ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR
7.5
—
—
ns
ns
(T*WS) + 7.5
WR Asserted to D0–D15 Out Valid
tWRD
tDOH
tDOS
—
T + 4.2
—
ns
ns
Data Out Hold Time from WR Deasserted
4.8
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
6.4
—
—
ns
ns
(T*WS) + 6.4
RD Deasserted to Address Not Valid
tRDA
0
—
—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
18.7
(T*WS) + 18.7
ns
ns
Input Data Hold to RD Deasserted
tDRD
tRD
0
—
ns
RD Assertion Width
Wait states = 0
Wait states > 0
19
—
—
ns
ns
(T*WS) + 19
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD
—
—
1
ns
ns
(T*WS) + 1
Address Valid to RD Asserted
tARDA
tRDD
-4.4
—
ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
—
—
2.4
ns
ns
(T*WS) + 2.4
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
WR Deasserted to WR Asserted
RD Deasserted to WR Asserted
tWRRD
tRDRD
tWRWR
tRDWR
6.8
0
—
—
—
—
ns
ns
ns
ns
14.1
12.8
ꢀ
DSP56F826 Preliminary Technical Data
27
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
A0–A15,
PS, DS
(See Note)
tARDD
tRDA
tARDA
tRDRD
tRD
tAWR
tWRWR
RD
tWRRD
tWR
tRDWR
WR
tRDD
tAD
tDOH
tWRD
tDRD
tDOS
Data Out
Data In
D0–D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 12. External Bus Asynchronous Timing
28
DSP56F826 Preliminary Technical Data
ꢀ
Reset, Stop, Wait, Mode Select, and Interrupt Timing
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 5
Table 15. Reset, Stop, Wait, Mode Select, and Interrupt Timing
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80 MHz
SSIO
SS
SSA
DDIO
DD
DDA
A
L
op
Typical
Min
Typical
Max
See
Figure
Characteristic
Symbol
Unit
RESET Assertion to Address, Data and Control Signals
High Impedance
tRAZ
—
21
ns
Figure 13
Figure 13
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
275,000T
128T
—
—
ns
ns
RESET De-assertion to First External Address Output
Edge-sensitive Interrupt Request Width
tRDA
tIRW
tIDM
33T
1.5T
—
34T
—
ns
ns
ns
Figure 13
Figure 14
Figure 15
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
15T
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
—
16T
ns
Figure 15
Figure 16
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
tIRI
—
—
13T
2T
ns
ns
IRQA Width Assertion to Recover from Stop State4
tIW
tIF
Figure 17
Figure 17
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
—
—
275,000T
12T
ns
ns
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
Figure 18
Figure 18
—
—
275,000T
12T
ns
ns
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
tII
—
—
275,000T
12T
ns
ns
OMR Bit 6 = 1
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5 ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two
cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the
Stop state. This is not the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
ꢀ
DSP56F826 Preliminary Technical Data
29
RESET
tRA
tRAZ
tRDA
First Fetch
A0–A15,
D0–D15
PS, DS,
RD, WR
First Fetch
Figure 13. Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 14. External Interrupt Timing (Negative-Edge-Sensitive)
A0–A15,
PS, DS,
RD, WR
First Interrupt Instruction Execution
tIDM
IRQA,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 15. External Level-Sensitive Interrupt Timing
30
DSP56F826 Preliminary Technical Data
ꢀ
Reset, Stop, Wait, Mode Select, and Interrupt Timing
IRQA,
IRQB
tIRI
A0–A15,
PS, DS,
RD, WR
First Interrupt Vector
Instruction Fetch
Figure 16. Interrupt from Wait State Timing
tIW
IRQA
tIF
A0–A15,
PS, DS,
RD, WR
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 17. Recovery from Stop State Using Asynchronous Interrupt Timing
tIRQ
IRQA
tII
A0–A15
PS, DS,
RD, WR
First IRQA Interrupt
Instruction Fetch
Figure 18. Recovery from Stop State Using IRQA Interrupt Service
ꢀ
DSP56F826 Preliminary Technical Data
31
3.8 Serial Peripheral Interface (SPI) Timing
1
Table 16. SPI Timing
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80 MHz
SSIO
SS
SSA
DDIO
DD
DDA
A
L
op
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
Figures 19,
20, 21, 22
50
50
—
—
ns
ns
Enable lead time
Master
Slave
tELD
tELG
tCH
tCL
Figure 22
Figure 22
—
25
—
—
ns
ns
Enable lag time
Master
Slave
—
100
—
—
ns
ns
Clock (SCLK) high time
Master
Slave
ns
ns
Figures 19,
20, 21, 22
17.6
25
—
—
Clock (SCLK) low time
Master
Slave
Figures 19,
20, 21, 22
24.1
25
—
—
ns
ns
Data setup time required for inputs
Master
Slave
tDS
Figures 19,
20, 21, 22
20
0
—
—
ns
ns
Data hold time required for inputs
Master
Slave
tDH
Figures 19,
20, 21, 22
0
2
—
—
ns
ns
Access time (time to data active from high-impedance state)
Slave
tA
Figure 22
Figure 22
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
tD
15.2
Data Valid for outputs
Master
Slave (after enable edge)
tDV
Figures 19,
20, 21, 22
—
—
4.5
20.4
ns
ns
Data invalid
Master
Slave
tDI
tR
tF
Figures 19,
20, 21, 22
0
0
—
—
ns
ns
Rise time
Master
Slave
Figures 19,
20, 21, 22
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
Figures 19,
20, 21, 22
—
—
9.7
9.0
ns
ns
1.Parameters listed are guaranteed by design.
32
DSP56F826 Preliminary Technical Data
ꢀ
Serial Peripheral Interface (SPI) Timing
SS
(Input)
SS is held High on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tCL
tF
tR
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
tDV
MOSI
(Output)
Master MSB out
Bits 14–1
Master LSB out
tR
tF
Figure 19. SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tCL
tF
SCLK (CPOL = 1)
(Output)
tCH
tDS
tDH
tR
MISO
(Input)
MSB in
tDI
Bits 14–1
LSB in
tDV
tDV(ref)
MOSI
(Output)
Master MSB out
Bits 14– 1
Master LSB out
tR
tF
Figure 20. SPI Master Timing (CPHA = 1)
ꢀ
DSP56F826 Preliminary Technical Data
33
SS
(Input)
tC
tF
tR
tELG
tCL
SCLK (CPOL = 0)
(Input)
tCH
tCL
tELD
SCLK (CPOL = 1)
(Input)
tF
tCH
tA
tR
tD
MISO
(Output)
Slave MSB out
Bits 14–1
Slave LSB out
tDI
tDS
tDV
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 21. SPI Slave Timing (CPHA = 0)
SS
(Input)
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tD
tF
tA
MISO
(Output)
Slave MSB out
Bits 14–1
Slave LSB out
tDV
tDS
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 22. SPI Slave Timing (CPHA = 1)
34
DSP56F826 Preliminary Technical Data
ꢀ
Quad Timer Timing
3.9 Quad Timer Timing
1, 2
Table 17. Timer Timing
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80 MHz
SSIO
SS
SSA
DDIO
DD
DDA
A
L
op
Characteristic
Symbol
PIN
Min
4T+6
Max
Unit
Timer input period
—
—
—
—
ns
ns
ns
ns
Timer input high/low period
Timer output period
PINHL
POUT
2T+3
2T-3
1T-3
Timer output high/low period
POUTHL
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5 ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PIN
PINHL
PINHL
Timer Outputs
POUT
POUTHL
POUTHL
Figure 23. Quad Timer Timing
3.10 Serial Communication Interface (SCI) Timing
4
Table 18. SCI Timing
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80 MHz
DDA A L op
SSIO
SS
SSA
DDIO
DD
Characteristic
Symbol
Min
Max
Unit
Baud Rate1
BR
(fMAX*2.5)/(80)
1.04/BR
Mbps
ns
—
RXD2 Pulse Width
TXD3 Pulse Width
RXDPW
TXDPW
0.965/BR
0.965/BR
1.04/BR
ns
1. fMAX is the frequency of operation of the system clock in MHz.
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
ꢀ
DSP56F826 Preliminary Technical Data
35
RXD
SCI receive
data pin
RXDPW
(Input)
Figure 24. RXD Pulse Width
TXD
SCI receive
data pin
TXDPW
(Input)
Figure 25. TXD Pulse Width
3.11 JTAG Timing
1, 3
Table 19. JTAG Timing
Operating Conditions: V
=V = V
= 0 V, V
=3.0 to 3.6V, V = V
= 2.25–2.75 V, T = –40° to +85°C, C ≤ 50 pF, f = 80MHz
SSIO
SS
SSA
DDIO
DD
DDA
A
L
op
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation2
TCK cycle time
fOP
tCY
tPW
tDS
DC
100
50
10
MHz
ns
—
—
TCK clock pulse width
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
ns
0.4
1.2
—
—
ns
tDH
tDV
tTS
—
ns
26.6
23.5
—
ns
—
ns
tTRST
tDE
50
ns
DE assertion time
4T
—
ns
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5 ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
36
DSP56F826 Preliminary Technical Data
ꢀ
JTAG Timing
tCY
tPW
tPW
VIH
VM
VIL
VM
TCK
(Input)
VM = VIL + (VIH – VIL)/2
Figure 26. Test Clock Input Timing Diagram
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 27. Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 28. TRST Timing Diagram
DE
tDE
Figure 29. OnCE—Debug Event
ꢀ
DSP56F826 Preliminary Technical Data
37
Part 4 Packaging
4.1 Package and Pin-Out Information DSP56F826
This section contains package and pin-out information for the 100-pin LQFP configuration of the
DSP56F826.
GPIOD1
GPIOD0
GPIOB7
GPIOB6
GPIOB5
TMS
TDI
TDO
TRST
VDDIO
PIN 76
ORIENTATION
MARK
PIN 1
GPIOB4
GPIOB3
GPIOB2
VSSIO
A15
A14
GPIOB1
GPIOB0
A13
A12
CLKO
VDD
VSS
A11
A10
A9
A8
A7
A6
A5
A4
Motorola
DSP56F826
XTAL
EXTAL
VSSA
VDDA
VSSIO
VDDIO
STCK
VSS
VDD
STFS
STD
SRCK
SRFS
A3
A2
A1
A0
PIN 51
PIN 26
SRD
EXTBOOT
Figure 30. Top View, DSP56F826 100-pin LQFP Package
38
DSP56F826 Preliminary Technical Data
ꢀ
Package and Pin-Out Information DSP56F826
Table 20. DSP56F826 Pin Identification by Pin Number
Signal
Name
Pin No.
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
2
TMS
TDI
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RD
WR
DS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
SRD
SRFS
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GPIOD2
GPIOD3
GPIOD4
GPIOD5
VDDIO
VSSIO
GPIOD6
GPIOD7
SCLK
MOSI
MISO
SS
3
TDO
TRST
VDDIO
VSSIO
A15
A14
A13
A12
A11
A10
A9
SRCK
4
PS
STD
5
VDDIO
VSSIO
IRQA
IRQB
D0
STFS
6
STCK
7
VDDIO
VSSIO
VDDA
VSSA
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D1
D2
EXTAL
XTAL
D3
D4
VSS
TA3
A8
D5
VDD
TA2
A7
D6
CLKO
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
GPIOD0
GPIOD1
TA1
A6
D7
TA0
A5
D8
RXD1
TXD1
VDD
A4
D9
VSS
VDD
A3
D10
RESET
D11
D12
D13
D14
D15
VSS
RXD0
TXD0
DE
A2
A1
A0
TCS
EXTBOOT
TCK
ꢀ
DSP56F826 Preliminary Technical Data
39
S
S
S
S
0.15(0.006)
AC T-U
Z
-T-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -AB- IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.
4. DATUMS-T-,-U-,AND-Z-TO BEDETERMINED
AT DATUM PLANE -AB-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.
-Z-
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE -AB-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION.DAMBARPROTRUSIONSHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014). DAMBAR CAN NOTBELOCATED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.003).
-U-
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
A
9
MILLIMETERS
DIM MIN MAX MIN MAX
INCHES
S
S
S
0.15(0.006)
AB T-U
Z
A
B
C
D
E
13.950 14.050 0.549 0.553
13.950 14.050 0.549 0.553
1.400 1.600 0.055 0.063
0.170 0.270 0.007 0.011
1.350 1.450 0.053 0.057
0.170 0.230 0.007 0.009
AE
AD
F
G
H
J
K
M
N
Q
R
S
0.500 BSC
0.020 BSC
-AB-
0.050 0.150 0.002 0.006
0.090 0.200 0.004 0.008
0.500 0.700 0.020 0.028
-AC-
SEATING
PLANE
G
96X
12 REF
12 REF
°
°
(24X PER SIDE)
0.090 0.160 0.004 0.006
1
°
5
1
°
5
°
°
AE
0.150 0.250 0.006 0.010
15.950 16.050 0.628 0.632
15.950 16.050 0.628 0.632
0.100(0.004) AC
V
W
X
0.200 REF
1.000 REF
0.008 REF
0.039 REF
°
M
R
D
F
0.25 (0.010)
E
C
GAUGE PLANE
J
N
W
°
Q
H
K
M
S
S
0.20(0.008)
AC T-U
Z
X
SECTION AE-AE
DETAIL AD
CASE 842F-01
Figure 31. 100-pin LQPF Mechanical Information
40
DSP56F826 Preliminary Technical Data
ꢀ
Thermal Design Considerations
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, T , in °C can be obtained from the equation:
J
Equation 1: TJ = TA + (PD × RθJA
)
Where:
T = ambient temperature °C
A
R
= package junction-to-ambient thermal resistance °C/W
θJA
P = power dissipation in package
D
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2: RθJA = RθJC + RθCA
Where:
R
R
R
= package junction-to-ambient thermal resistance °C/W
= package junction-to-case thermal resistance °C/W
= package case-to-ambient thermal resistance °C/W
θJA
θJC
θCA
R
is device-related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case-to-ambient thermal resistance, R
. For example, the user can change the air flow around
θCA
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from R
do not satisfactorily answer whether the
θJA
thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
•
Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.
•
Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.
ꢀ
DSP56F826 Preliminary Technical Data
41
Electrical Design Considerations
•
Use the value obtained by the equation (T – T )/P where T is the temperature of the package
J T D T
case determined by a thermocouple.
The junction-to-case thermal resistances quoted in this data sheet are determined using the first definition
on page 41. From a practical standpoint, that value is also suitable for determining the junction temperature
from a case thermocouple reading in forced convection environments. In natural convection, using the
junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the
case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal
metric, Thermal Characterization Parameter, or Ψ , has been defined to be (T – T )/P . This value gives
JT
J
T
D
a better estimate of the junction temperature in natural convection when using the surface temperature of
the package. Remember that surface temperature readings of packages are subject to significant errors
caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor.
The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the
package with thermally conductive epoxy.
5.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level
(e.g., either V or V ).
SS
DD
Use the following list of considerations to assure correct DSP operation:
•
Provide a low-impedance path from the board power supply to each V pin on the DSP, and from
DD
the board ground to each V (GND) pin.
SS
•
The minimum bypass requirement is to place six 0.01–0.1 µF capacitors positioned as close as
possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the eight V /V pairs, including V
/V
DD SS
DDA SSA.
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and
DD
V
(GND) pins are less than 0.5 inch per capacitor lead.
SS
•
•
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V and V .
DD SS
Bypass the V and V layers of the PCB with approximately 100 µF, preferably with a high-
DD
SS
grade capacitor such as a tantalum capacitor.
•
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.
ꢀ
DSP56F826 Preliminary Technical Data
42
•
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V and V circuits.
DD
SS
•
•
All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
Take special care to minimize noise levels on the VREF, V and V pins.
DDA
SSA
•
When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-
up device.
•
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. Designs that do not require
debugging functionality, such as consumer products, should tie these pins together.
•
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.
Part 6 Ordering Information
Table 21 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales
office or authorized distributor to determine availability and to order parts.
Table 21. DSP56F803 Ordering Information
Supply
Voltage
Pin
Count
Frequency
(MHz)
Part
Package Type
Order Number
DSP56F826
3.0–3.6 V
Plastic Quad Flat Pack (LQFP)
100
80
DSP56F803BU80
2.25-2.75 V
43
DSP56F826 Preliminary Technical Data
ꢀ
OnCE™ are trademarks of Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including
“Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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