DSP56F826-827UM [FREESCALE]
16-bit Digital Signal Controllers; 16位数字信号控制器型号: | DSP56F826-827UM |
厂家: | Freescale |
描述: | 16-bit Digital Signal Controllers |
文件: | 总60页 (文件大小:1136K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
56F827
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F827
Rev. 12
01/2007
freescale.com
56F827 General Description
•
•
Up to 40 MIPS at 80MHz core frequency
•
MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
DSP and MCU functionality in a unified,
C-efficient architecture
•
•
•
•
•
•
•
•
8-channel Programmable Chip Select
10-channel, 12-bit ADC
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•
•
•
•
•
Hardware DO and REP loops
64K × 16-bit words (128KB) Program Flash
1K × 16-bit words (2KB) Program RAM
4K × 16-bit words (8KB) Data Flash
4K × 16-bit words (8KB) Data RAM
Synchronous Serial Interface (SSI)
Serial Port Interface (SPI)
Serial Communications Interface (SCI)
Time-of-Day (TOD) Timer
Up to 64K × 16-bit words (128KB) external memory
expansion each for Program and Data memory
128-pin LQFP Package
•
•
JTAG/OnCE™ for debugging
General Purpose Quad Timer
16-dedicated and 48 shared GPIO
EXTBOOT
DEBUG
IRQB
IRQA
RESET
V
2
V
5
V
5
V
V
V
SSA
DDIO
SSIO
DD
SS
DDA
6
3
2
4
inputs
10
JTAG/
OnCE
Port
Low Voltage Supervisor
Analog Reg
ADC
V
V
, V
,
REFP REFMID
REFIN
3
Interrupt
Data ALU
Bit
Manipulation
Unit
Controller
Program Controller
and Hardware
Looping Unit
Address
Generation
Unit
V
REFLO
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
V
REFHI
Program and Boot
Memory
64512 x 16 Flash
1024 x 16 SRAM
PAB
PDB
16-Bit
56800
Core
CLKO
PLL
Quad Timer A/
or GPIO
4
VPP
XDB2
CGDB
XAB1
XAB2
Clock
Gen
XTAL
Data Memory
4096 x 16 Flash
4096 x 16 SRAM
SCI 2 or
GPIO
EXTAL
2
6
INTERRUPT
IPBB
CONTROLS
CONTROLS
SSI 0 or
GPI0
16
16
External
Address Bus
Switch
A[00:15]
or
GPIOA16[00:16]
COP
RESET
SCI 0 &1 or
SPI 0
External
Bus
Interface
Unit
COP/
Watchdog
16
16
4
MODULE
CONTROLS
SPI 1 or
GPIO
IPBus Bridge
(IPBB)
Application-
Specific
Memory &
Peripherals
D[00:15]
or
GPIOG16[00:16]
External
Data Bus
Switch
4
6
ADDRESS
BUS [8:0]
PCS [2:7}
Programmable
Chip Select
PS or PCS[0]
DS or PCS[1]
WR
Bus
Control
Dedicated
GPIO
DATA
BUS [15:0]
TOD
Timer
16
RD
56F827 Block Diagram
56F827 Technical Data, Rev. 12
Freescale Semiconductor
3
Part 1 Overview
1.1 56F827 Features
1.1.1
Processing Core
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Efficient 16-bit 56800 family processor engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE Debug Programming Interface
1.1.2
Memory
•
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
— 64K words of Program Flash
•
— 1K words of Program RAM
— 4K words of Data RAM
— 4K words of Data Flash
•
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64 K × 16 Data memory
— As much as 64 K × 16 Program memory
1.1.3
Peripheral Circuits for 56F827
One 10 channel, 12-bit, Analog-to-Digital Converter (ADC)
One General Purpose Quad Timer totaling 4 pins
•
•
•
One Serial Peripheral Interface with configurable four-pin port multiplexed with two Serial
Communications Interfaces totalling 4 pins or 4 GPIO pins
•
•
Three Serial Communication Interfaces with 2 pins each (or 6 additional GPIO pins)
Two Serial Peripheral Interface with configurable four-pin port (or 4 additional GPIO pins)
56F827 Technical Data, Rev. 12
4
Freescale Semiconductor
56F827 Description
•
•
•
•
•
•
•
•
•
•
One Synchronous Serial Interface with 6 pins (or 6 additional GPIO pins)
One 8-channel Programmable Chip Select
Sixteen dedicated and forty eight multiplexed GPIO pins (64 total)
Computer-Operating Properly (COP) Watchdog timer
Two external interrupt pins
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the core clock
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
One Time of Day (TOD) Timer
1.1.4
Power Information
•
Dual power supply, 3.3V and 2.5V
•
Wait and Multiple Stop modes available
1.2 56F827 Description
The 56F827 is a member of the 56800 core-based family of controllers. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution for general purpose applications. Because of its low cost,
configuration flexibility, and compact program code, the 56F827 is well-suited for many applications.
The 56F827 includes many peripherals that are especially useful for applications such as: noise
suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic
alarms, and telephony.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable
rapid development of optimized control applications.
The 56F827 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F827 also provides two external
dedicated interrupt lines, and up to 64 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F827 controller includes 64K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 1K words of Program RAM and 4K words of Data RAM. It
also supports program execution from external memory. The 56800 core is capable of accessing two data
operands from the on-chip Data RAM per instruction cycle.
This controller also provides a full set of standard programmable peripherals that include one 10-input,
12-bit Analog-to-Digital Converters (ADC), one Synchronous Serial Interface (SSI), two Serial Peripheral
Interfaces (SPI), three Serial Communications Interfaces (SCI). (Note: The second SPI is multiplexed with
56F827 Technical Data, Rev. 12
Freescale Semiconductor
5
the second and third SCIs, giving the option to select a second SPI or two additional SCIs.) This controller
also provides one Programmable Chip Select (PCS), and one Quad Timer. The SCI, SSI, SPI, Quad Timer
A, and select address and data lines can be used as General Purpose Input/Outputs (GPIOs) if those
functions are not required.
1.3 Award-Winning Development Environment
•
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
•
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 2-1 are required for a complete description and proper design with the
56F827. Documentation is available from local Freescale distributors, Freescale semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Table 1-1 56F827 Chip Documentation
Topic
Description
Order Number
56800EFM
56800E
Detailed description of the 56800 family architecture,
and 16-bit core processor and the instruction set
Family Manual
DSP56F826/F827
User’s Manual
Detailed description of memory, peripherals, and
interfaces of the 56F826 and 56F827
DSP56F826-827UM
DSP56F827
56F827
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
56F827
Errata
Details any chip issues that might be present
DSP56F827E
56F827 Technical Data, Rev. 12
6
Freescale Semiconductor
Data Sheet Conventions
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
“deasserted”
Examples:
A high true (active high) signal is high or a low true (active low) signal is low.
A high true (active high) signal is low or a low true (active low) signal is high.
Voltage1
Signal/Symbol
Logic State
True
Signal State
Asserted
PIN
PIN
PIN
PIN
VIL/VOL
False
Deasserted
Asserted
VIH/VOH
VIH/VOH
VIL/VOL
True
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F827 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. Table 2-2 describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins
(3,5,1,1)
Power (VDD, VDDIO, VDDA or VDDA_ADC
Ground (VSS, VSSIO, VSSA, orVSSA_ADC
VPP
)
)
(3,5,1,1)
1
3
PLL and Clock
Address Bus1
16
Data Bus1
16
Bus Control
4
4
Quad Timer Module Ports1
JTAG/On-Chip Emulation (OnCE)
6
16
6
Dedicated General Purpose Input/Output
Synchronous Serial Interface (SSI) Port1
Serial Peripheral Interface (SPI) Port1
4
4
2
Serial Communications Interface1 (SCI0, SCI1) Port2
Serial Communications Interface2 (SCI2) Port1
Analog to Digital Converter (ADC)
15
6
Programmable Chip Select (PCS)3
Interrupt and Program Control
5
1. Alternately, GPIO pins
2. Alternately, SPI pins
3. In addition, 2 Bus Control pins can be programmed as PCS[0-1].
56F827 Technical Data, Rev. 12
8
Freescale Semiconductor
Introduction
VDD
VDDA
GPIOB0–7
GPIOD0–7
2.5V Power
3.3V Analog Power
3.3V Analog Power
3.3V Power
8
8
Dedicated
GPIO
3
1
1
5
4*
1
1
5
VDDA_ADC
VDDIO
SRD (GPIOC0)
SRFS (GPIOC1)
SRCK (GPIOC2)
STD (GPIOC3)
STFS (GPIOC4)
STCK (GPIOC5)
1
1
1
1
1
1
VSS
Ground
VSSA
SSI Port
or GPIO
Analog Ground
Analog Ground
Ground
VSSA_ADC
VSSIO
VPP
56F827
Other
Supply Port
1
SCLK (GPIOF4)
MOSI (GPIOF5)
MISO (GPIOF6)
SS (GPIOF7)
1
1
1
1
EXTAL
XTAL(CLOCKIN)
CLKO
SPI1 Port
or GPIO
PLL
and
Clock
1
1
1
External
Address Bus or
GPIO
A0-A15(GPIOA0–15)
D0–D15(GPIOG0-15)
TXD0 (SCLK0)
RXD0 (MOSI0)
TXD1 (MISO0)
RXD1 (SS0)
1
1
1
1
16
16
SCI0,SCI1
Port or
SPI0 Port
External Data
Bus or GPIO
PS (PCS0)
DS (PCS1)
RD
1
1
1
1
TXD2 (GPIOC6)
RXD2 (GPIOC7)
1
1
External
Bus Control
SCI2 Port
or GPIO
WR
PCS2-7
Programmable
Chip Select
6
TA0 (GPIOF0)
TA1 (GPIOF1)
TA2 (GPIOF2)
TA3 (GPIOF3)
1
1
1
1
ANA0–9
VREFN
Quad Timer A
or GPIO
10
1
VREFP
1
ADC
Port
VREFMID
VREFLO
VREFHI
1
TCK
TMS
TDI
1
1
1
1
1
1
1
1
JTAG/OnCE™
Port
TDO
TRST
DE
IRQA
1
1
1
1
Interrupt/
Program
Control
IRQB
RESET
EXTBOOT
*Includes TCS pin, which is reserved for factory use and is tied to VSS
1
Figure 2-1 56F827 Signals Identified by Functional Group
1. Alternate pin functionality is shown in parenthesis.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
9
2.2 Signals and Package Information
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always
enabled. Exceptions:
1. When a pin is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP
Signal Name Pin No.
Type
VDD
Description
VDD
VDD
116
81
Power—These pins provide power to the internal structures of the chip, and
are generally connected to a 2.5V supply.
VDD
VDD
19
VDD
VDDA
62
VDDA
Analog Power—This pin is a dedicated power pin for the analog portion of the
chip and should be connected to a low-noise 3.3V supply.
VDDA_ADC
69
VDDA
Analog Power—This pin is a dedicated power pin for the analog portion of the
ADC module and should be connected to a low-noise 3.3V supply.
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VSS
113
82
56
29
4
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VSS
Power In/Out—These pins provide power to the I/O structures of the chip, and
are generally connected to a 3.3V supply.
115
80
20
61
63
GND—These pins provide grounding for the internal structures of the chip. All
should be attached to VSS.
VSS
VSS
VSS
VSS
VSSA
VSSA
VSSA
Analog Ground—This pin supplies an analog ground.
VSSA_ADC
Analog Ground—This pin is a dedicated ground pin for the analog portion of
the ADC module.
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
TCS
114
83
58
30
5
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
GND In/Out—These pins provide grounding for the I/O ring on the chip.
All should be attached to VSS.
43
Input/Output
(Schmitt)
TCS—This pin is reserved for factory use. It must be tied to VSS for normal
use. In block diagrams, this pin is considered an additional VSS.
56F827 Technical Data, Rev. 12
10
Freescale Semiconductor
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name Pin No.
Type
Description
VPP
90
Input
VPP—This pin should be left unconnected as an open circuit for normal
functionality.
EXTAL
59
Input
External Crystal Oscillator Input—This input should be connected to a
4MHz external crystal or ceramic resonator. For more information, please refer
to Section 3.6.
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.6.3.
XTAL
60
57
Output
Crystal Oscillator Output—This output connects the internal crystal oscillator
output to an external crystal or ceramic resonator. If an external clock source
over 4MHz is used, XTAL must be used as the input and EXTAL connected to
VSS. For more information, please refer to Section 3.6.3.
(CLOCKIN)
CLKO
Input
External Clock Input—This input should be used when using an external
clock or ceramic resonator.
Output
Clock Output—This pin outputs a buffered clock signal. By programming the
CLKO Select Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the device master clock
at the output of the PLL. The clock frequency on this pin can be disabled by
programming the CLKO Select Register (CLKOSR).
56F827 Technical Data, Rev. 12
Freescale Semiconductor
11
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name Pin No.
Type
Description
A0
21
Output
Address Bus—A0–A15 specify the address for external Program or Data
memory accesses.
(GPIOA0)
Input/Output
Port A GPIO—These 16 General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
A1
(GPIOA1)
22
23
24
25
26
27
28
31
32
33
34
35
36
37
38
After reset, the default state is Address Bus.
A2
(GPIOA2)
A3
(GPIOA3)
A4
(GPIOA4)
A5
(GPIOA5)
A6
(GPIOA6)
A7
(GPIOA7)
A8
(GPIOA8)
A9
(GPIOA9)
A10
(GPIOA10)
A11
(GPIOA11)
A12
(GPIOA12)
A13
(GPIOA13)
A14
(GPIOA14)
A15
(GPIOA15)
56F827 Technical Data, Rev. 12
12
Freescale Semiconductor
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name Pin No.
Type
Description
D0
125
Input/Output
Data Bus—D0–D15 specify the data for external Program or Data memory
accesses. D0-D15 are tri-stated when the external bus is inactive.
Port G GPIO—These 16 General Purpose I/O (GPIO) pins can be individually
(GPIOG0)
Input/Output
programmed as input or output pins.
D1
(GPIOG1)
126
127
128
1
After reset, the default state is Address Bus.
D2
(GPIOG2)
D3
(GPIOG3)
D4
(GPIOG4)
D5
2
(GPIOG5)
D6
3
(GPIOG6)
D7
6
(GPIOG7)
D8
7
(GPIOG8)
D9
8
(GPIOG9)
D10
9
(GPIOG10)
D11
(GPIOG11)
10
11
12
13
14
D12
(GPIOG12)
D13
(GPIOG13)
D14
(GPIOG14)
D15
(GPIOG15)
PS
(PCS0)
18
17
Output
Output
Program Memory Select—PS is asserted low for external program memory
access. This pin can also be programmed as a programmable chip select.
DS
Data Memory Select—DS is asserted low for external Data memory access.
(PCS1)
This pin can also be programmed as a programmable chip select.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
13
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name Pin No.
Type
Description
RD
15
Output
Read Enable—RD is asserted during external memory read cycles. When RD
is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the device data bus. When RD is deasserted high, the external
data is latched inside the device. When RD is asserted, it qualifies the
A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a
Static RAM or ROM.
WR
16
Output
Write Enable—WR is asserted during external memory write cycles. When
WR is asserted low, pins D0–D15 become outputs and the device puts data on
the bus. When WR is deasserted high, the external data is latched inside the
external device. When WR is asserted, it qualifies the A0–A15, PS, and DS
pins. WR can be connected directly to the WE pin of a Static RAM.
TA0
112
Input/Output
Input/Output
TA0–3—Timer A Channels 0, 1, 2, and 3
(GPIOF0)
Port F GPIO—These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.
TA1
(GPIOF1)
111
110
109
44
After reset, the default state is Quad Timer.
TA2
(GPIOF2)
TA3
(GPIOF3)
TCK
Input
(Schmitt)
Test Clock Input—This input pin provides a gated clock to synchronize the
test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.
TMS
46
Input
(Schmitt)
Test Mode Select Input—This input pin is used to sequence the JTAG TAP
controller’s state machine. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
TDI
TDO
TRST
48
47
45
Input
(Schmitt)
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
Input/Output
Test Data Output—This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
Input
(Schmitt)
Test Reset—As an input, a low signal on this pin provides a reset signal to the
JTAG TAP controller. To ensure complete hardware reset, TRST should be
asserted whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware device reset is required and it is
necessary not to reset the JTAG/OnCE module. In this case, assert RESET,
but do not assert TRST. TRST must always be asserted at power-up.
Note: For normal operation, connect TRST directly to VSS. If the design is to be
used in a debugging environment, TRST may be tied to VSS through a 1K resistor.
DE
41
Output
Debug Event—DE provides a low pulse on recognized debug events.
56F827 Technical Data, Rev. 12
14
Freescale Semiconductor
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name Pin No.
Type
Description
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
GPIOD0
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
SRD
124
123
122
121
120
119
118
117
98
Input/Output
Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can
be individually programmed as input or output pins.
After reset, the default state is GPIO input.
Input/ Output Port D GPIO—These eight dedicated GPIO pins can be individually
programmed as an input or output pins.
97
After reset, the default state is GPIO input.
96
95
94
93
92
91
55
Input/Output
Input/Output
SSI Receive Data (SRD)—This input pin receives serial data and transfers the
data to the SSI Receive Shift Receiver.
(GPIOC0)
SRFS
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
54
Input/Output
SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by the
receive section of the SSI as frame sync I/O or flag I/O. The STFS can be
used only by the receiver. It is used to synchronize data transfer and can be an
input or an output.
(GPIOC1)
SRCK
Input/Output
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
53
SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the serial
bit rate clock for the Receive section of the SSI. The clock signal can be
continuous or gated and can be used by both the transmitter and receiver in
synchronous mode.
(GPIOC2)
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
15
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name Pin No.
Type
Description
STD
52
Output
SSI Transmit Data (STD)—This output pin transmits serial data from the SSI
Transmitter Shift Register.
(GPIOC3)
Input/Output
Input
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
STFS
51
SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used by
the Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be
used by both the transmitter and receiver in synchronous mode. It is used to
synchronize data transfer and can be an input or output pin.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
(GPIOC4)
STCK
Input/Output
being individually programmed as input or output.
After reset, the default state is GPIO input.
50
Input/ Output SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the serial
bit rate clock for the transmit section of the SSI. The clock signal can be
continuous or gated. It can be used by both the transmitter and receiver in
synchronous mode.
(GPIOC5)
SCLK
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
102
101
100
Input/Output
SPI Serial Clock—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
(GPIOF4)
MOSI
Input/Output
Input/Output
After reset, the default state is SCLK.
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places data
on the MOSI line a half-cycle before the clock edge that the slave device uses
to latch the data.
(GPIOF5)
MISO
Input/Output
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave device is
placed in the high-impedance state if the slave device is not selected.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
(GPIOF6)
Input/Output
programmed as input or output.
After reset, the default state is MISO.
56F827 Technical Data, Rev. 12
16
Freescale Semiconductor
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name Pin No.
Type
Description
SS
99
Input/Output
SPI Slave Select—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
(GPIOF7)
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SS.
TXD0
108
Output
Transmit Data (TXD0)—transmit data output
(SCLK0)
Input/Output
SPI Serial Clock—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
After reset, the default state is SCI output.
RXD0
107
106
Input
Receive Data (RXD0)—receive data input
(MOSI0)
Input/Output
SPI Master Out/Slave In—This serial data pin is an input to a master device
and an output from a slave device. The MISO line of a slave device is placed
in the high-impedance state if the slave device is not selected.
TXD1
Output
Transmit Data (TXD1)—transmit data output
(MISO0)
Input/Output
SPI Master In/Slave Out—This serial data pin is an output to a master device
and an input from a slave device. The master device places data on the MOSI
line one half-cycle before the clock edge the slave device uses to latch the
data.
After reset, the default state is SCI input.
RXD1
(SS0)
105
Input
(Schmitt)
Receive Data (RXD1)— receive data input
Input
SPI Slave Select—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
After reset, the default state is SCI input.
TXD2
104
103
Output
Transmit Data (TXD2)—transmit data output
(GPIOC6)
Input/Output
Port C GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is GPIO output.
RXD2
Input/Output
Input/Output
Receive Data (RXD2)— receive data input
(GPIOC7)
Port C GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is GPIO input.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
17
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name Pin No.
Type
Description
PCS2
PCS3
PCS4
PCS5
PCS6
PCS7
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
ANA8
ANA9
VREFN
84
85
86
87
88
89
70
71
72
73
74
75
76
77
78
79
66
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Programmable Chip Select - PCS 2-7 is asserted low for external peripheral
chip select.
ANA0–9—Analog inputs to ADC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
ADC Reference—This pin is connected to the negative side of the ADC input
range. This pin requires a 0.1μF ceramic capacitor to VSSA and a start-up time
of 25ms, prior to beginning conversions.
VREFP
65
68
Input
Input
ADC Reference—This pin is connected to the positive side of the ADC input
range. This pin requires a 0.1μF ceramic capacitor to VSSA and a start-up time
of 25ms, prior to beginning conversions.
VREFMID
ADC Reference—This pin isconnected to the center of the ADC input range.
This pin requires a 0.1μF ceramic capacitor to VSSA and a start-up time of
25ms, prior to beginning conversions.
VREFLO
VREFHI
IRQA
64
67
40
Input
Input
ADC Reference—These pins are Negative Reference for ADC and are
generally connected to a VSSA
.
ADC Reference—These pins are Positive Reference for ADC and are
generally connected to a 3.3V Analog (VDDA_ADC) supply.
Input
(Schmitt)
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If
level-sensitive triggering is selected, an external pull-up resistor is required for
wired-OR operation.
If the processor is in the Stop state and IRQA is asserted, the processor will
exit the Stop state.
56F827 Technical Data, Rev. 12
18
Freescale Semiconductor
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name Pin No.
Type
Description
IRQB
49
Input
(Schmitt)
External Interrupt Request B—The IRQB input is an external interrupt
request that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-sensitive
triggering is selected, an external pull-up resistor is required for wired-OR
operation.
RESET
42
Input
(Schmitt)
Reset—This input is a direct hardware reset on the processor. When RESET
is asserted low, the device is initialized and placed in the Reset state. A
Schmitt trigger input is used for noise immunity. When the RESET pin is
deasserted, the initial chip operating mode is latched from the external boot
pin. The internal reset signal will be deasserted synchronous with the internal
clocks, after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be asserted
together. The only exception occurs in a debugging environment when a
hardware device reset is required and it is necessary not to reset the
OnCE/JTAG module. In this case, assert RESET, but do not assert TRST.
EXTBOOT
39
Input
External Boot—This input is tied to VDD to force device to boot from off-chip
(Schmitt)
memory. Otherwise, it is tied to VSS
.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
19
Part 3 Specifications
3.1 General Characteristics
The 56F827 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible
I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage. This 5V-tolerant capability, therefore, offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F827 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum-rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
56F827 Technical Data, Rev. 12
20
Freescale Semiconductor
General Characteristics
Table 3-1 Absolute Maximum Ratings
Characteristic
Supply voltage, core
Symbol
Min
Max
Unit
1
VSS - 0.3
VSS + 3.0
V
V
VDD
2
VSSIO - 0.3
VSSA - 0.3
VSSIO + 4.0
VSSA + 4.0
Supply voltage, IO
VDDIO
2
Supply voltage, Analog
Supply voltage, ADC
VDDA
VSSA_ADC-0.3
VSSA_ADC+0.3
VDDA_ADC
Digital input voltages
Analog input voltages (XTAL, EXTAL)
Analog input voltages (ANA0-7, VREF)
VIN
VINA
VSSIO - 0.3
V
SSIO + 5.5
V
VSSA - 0.3
VDDA + 0.3
VIN_ADC
VSSA_ADC-0.3
VSSA_ADC+0.3
Voltage difference VDD to VDD_IO, VDDA
Voltage difference VSS to VSS _IO, VSSA
ΔVDD
ΔVSS
I
- 0.3
- 0.3
—
0.3
0.3
10
V
V
Current drain per pin excluding VDD, VSS, VDDA
,
mA
VSSA,VDDIO, VSSIO
Junction temperature
TJ
—
150
150
°C
°C
Storage temperature range
1. VDD must not exceed VDDIO
TSTG
-55
2. VDDIO and VDDA must not differ by more that 0.5V
Table 3-2 Recommended Operating Conditions
Characteristic
Supply voltage, core
Symbol
VDD
Min
2.5
Typ
2.5
3.3
-
Max
2.75
Unit
V
V
Supply Voltage, IO and analog
V
DDIO,VDDA
ΔVDD
3.0
3.6
Voltage difference VDD to VDD_IO, VDDA
Voltage difference VSS to VSS _IO, VSSA
-0.1
-0.1
2.7
0.1
V
ΔVSS
-
0.1
V
ADC reference voltage, positive
ADC reference voltage, negative
Ambient operating temperature
VREFHI
VREFLO
TA
—
—
—
VDD_ADC
VREFHI
85
V
VSSA
–40
V
°C
56F827 Technical Data, Rev. 12
Freescale Semiconductor
21
6
Table 3-3 Thermal Characteristics
Value
128-pin LQFP
50.8
Characteristic
Symbol
Unit
Notes
Comments
Junction to ambient
RθJA
°C/W
2
Natural convection
Junction to ambient (@1m/sec)
RθJMA
46.5
43.9
°C/W
°C/W
2
Junction to ambient
Natural convection
Four layer board
(2s2p)
RθJMA
(2s2p)
1,2
Junction to ambient (@1m/sec)
Four layer board
(2s2p)
RθJMA
41.7
°C/W
1,2
Junction to case
RθJC
ΨJT
13.9
1.2
°C/W
°C/W
W
3
4
Junction to center of case
I/O pin power dissipation
Power dissipation
P I/O
P D
User Determined
P D = (IDD x VDD + P I/O
(TJ - TA) /RθJA
)
W
Junction to center of case
PDMAX
W
7
Notes:
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2. Junction to ambient thermal resistance, Theta-JA (R ) was simulated to be equivalent to the JEDEC
θJA
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on
a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number
of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the
non-single layer boards is Theta-JMA.
3. Junction to case thermal resistance, Theta-JC (R ), was simulated to be equivalent to the measured values
θJC
using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.
4. Thermal Characterization Parameter, Psi-JT (Ψ ), is the "resistance" from junction to reference point
JT
thermocouple on top center of case as defined in JESD51-2. Ψ is a useful value to use to estimate junction
JT
temperature in steady state customer environments.
5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
6. See Section 5.1 from more details on thermal design considerations.
7. TJ = Junction Temperature
TA = Ambient Temperature
56F827 Technical Data, Rev. 12
22
Freescale Semiconductor
DC Electrical Characteristics
3.2 DC Electrical Characteristics
Table 3-4 DC Electrical Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Input high voltage (XTAL/EXTAL)
Symbol
VIHC
VILC
VIHS
VILS
VIH
Min
2.25
0
Typ
—
—
—
—
—
—
—
—
—
—
—
—
30
—
—
—
Max
3.6
0.5
5.5
0.8
5.5
0.8
1
Unit
V
Input low voltage (XTAL/EXTAL)
V
Input high voltage (Schmitt trigger inputs)1
2.2
-0.3
2.0
-0.3
-1
V
Input low voltage (Schmitt trigger inputs)2
Input high voltage (all other digital inputs)
V
V
Input low voltage (all other digital inputs)
VIL
V
Input current high (pull-up/pull-down resistors disabled, VIN=VDD
)
IIH
μA
μA
μA
μA
μA
μA
KΩ
μA
μA
μA
Input current low (pull-up/pull-down resistors disabled, VIN=VSS
Input current high (with pull-up resistor, VIN=VDD
Input current low (with pull-up resistor, VIN=VSS
Input current high (with pull-down resistor, VIN=VDD
)
IIL
-1
1
)
IIHPU
IILPU
IIHPD
IILPD
-0
1
)
-210
20
-50
180
1
)
Input current low (with pull-down resistor, VIN=VSS
Nominal pull-up or pull-down resistor value
Output tri-state current low
)
-1
R
PU, RPD
IOZL
-10
-10
-15
10
10
15
Output tri-state current high
Input current high (analog inputs, VIN=VDDA
IOZH
2
IIHA
)
2
IILA
-15
—
15
μA
Input current low (analog inputs, VIN=VSSA
)
Output High Voltage (at IOH
)
VOH
VOL
IOH
VDD – 0.7
—
—
—
—
—
—
0.4
—
V
Output Low Voltage (at IOL
Output source current
Output sink current
)
—
4
V
mA
mA
mA
IOL
4
—
PWM pin output source current3
IOHP
10
—
56F827 Technical Data, Rev. 12
Freescale Semiconductor
23
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
PWM pin output sink current4
Symbol
IOLP
Min
16
—
Typ
—
Max
—
Unit
mA
pF
Input capacitance
Output capacitance
CIN
8
—
COUT
—
12
—
pF
5
VDD supply current
IDDT
Run 6
—
—
60
35
90
50
mA
mA
Wait7
Stop
—
6
15
mA
V
Low Voltage Interrupt, VDDIO power supply8
Low Voltage Interrupt, VDD power supply9
Power-on Reset10
VEIO
VEIC
2.4
2.7
3.0
2.0
—
2.2
1.7
2.4
2.0
V
V
VPOR
1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, TCK, TRST, TMS, TDI, and RXD1.
2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3. PWM pin output source current measured with 50% duty cycle.
4. PWM pin output sink current measured with 50% duty cycle.
5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA
)
6. Run (operating) IDD measured using 4MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs;
measured with all modules enabled.
7. Wait IDD measured using external square wave clock source (fosc = 4MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less
than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured
with PLL enabled.
8. This low-voltage interrupt monitors the VDDIO power supply. If VDDIO drops below VEIO, an interrupt is generated. Functionality of
the device is guaranteed under transient conditions when VDDIO >VEIO (between the minimum specified VDDIO and the point when
the VEIO interrupt is generated).
9. This low-voltage interrupt monitors the VDD power supply. If VDDIO drops below VEIC, an interrupt is generated. Functionality of
the device is guaranteed under transient conditions when VDD >VEIC (between the minimum specified VDD and the point when the
V
EIC interrupt is generated).
10. Power–on reset occurs whenever the VDD power supply drops below VPOR. While power is ramping up, this signal remains active
as long as VDD is below VPOR, no matter how long the ramp-up rate is.
56F827 Technical Data, Rev. 12
24
Freescale Semiconductor
Supply Voltage Sequencing and Separation Cautions
100
80
IDD Analog
IDD Total
IDD Digital
60
40
20
0
10
20
60
70
50
30
80
40
Freq. (MHz)
Figure 3-1 Maximum Run I vs. Frequency (see Note 6. in Table 3-4)
DD
3.3 Supply Voltage Sequencing and Separation Cautions
Figure 3-2 shows two situations to avoid in sequencing the V and V
V
supplies.
DD
DDIO, DDA
3.3V
VDDIO, VDDA
2
Supplies Stable
2.5V
VDD
1
0
Time
Notes: 1. VDD rising before VDDIO, VDDA
2. VDDIO, VDDA rising much faster than VDD
Figure 3-2 Supply Voltage Sequencing and Separation Cautions
56F827 Technical Data, Rev. 12
Freescale Semiconductor
25
V
should not be allowed to rise early (1). This is usually avoided by running the regulator for the V
DD
DD
supply (2.5V) from the voltage generated by the 3.3V V
supply, see Figure 3-3. This keeps V from
DDIO
DD
rising faster than V
.
DDIO
V
should not rise so late that a large voltage difference is allowed between the two supplies (2).
DD
Typically, this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 3-3. The series diodes forward bias when the difference between V and V reaches
DDIO
DD
approximately 1.4, causing V to rise as V
ramps up. When the V regulator begins proper
DD
DDIO
DD
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
V
> V > (V
- 1.4V)
DDIO
DD
DDIO
In practice, V
is typically connected directly to V
with some filtering.
DDA
DDIO
VDDIO, VDDA
3.3V
Regulator
Supply
VDD
2.5V
Regulator
Figure 3-3 Example Circuit to Control Supply Sequencing
3.4 AC Electrical Characteristics
Timing waveforms in Section 3.4 are tested using the VIL and VIH levels specified in the DC Characteristics
table. In Figure 3-4 the levels of VIH and VIL for an input signal are shown.
Pulse Width
Low
VIL
High
VIH
90%
Input Signal
50%
Midpoint1
10%
Fall Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Rise Time
Figure 3-4 Input Signal Measurement References
Figure 3-5 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
•
Data Invalid state, when a signal level is in transition between VOL and VOH
56F827 Technical Data, Rev. 12
26
Freescale Semiconductor
Flash Memory Characteristics
Data2 Valid
Data2
Data1 Valid
Data1
Data3 Valid
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 3-5 Signal States
3.5 Flash Memory Characteristics
Table 3-5 Flash Memory Truth Table
XE1
YE2
SE3
OE4
PROG5
ERASE6
MAS17
NVSTR8
Mode
Standby
Read
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
H
H
H
H
Word Program
Page Erase
Mass Erase
L
H
H
H
H
H
L
1. X address enable, all rows are disabled when XE = 0
2. Y address enable, YMUX is disabled when YE = 0
3. Sense amplifier enable
4. Output enable, tri-state Flash data out bus when OE = 0
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle
Table 3-6 IFREN Truth Table
Mode
IFREN = 1
IFREN = 0
Read
Read information block
Program information block
Erase information block
Erase both block
Read main memory block
Program main memory block
Erase main memory block
Erase main memory block
Word program
Page erase
Mass erase
56F827 Technical Data, Rev. 12
Freescale Semiconductor
27
Table 3-7 Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Program time
Symbol
Min
20
Typ
Max
Unit
us
Figure
–
–
–
–
–
–
Figure 3-6
Figure 3-7
Figure 3-8
Tprog*
Terase*
Tme*
Erase time
20
–
–
ms
Mass erase time
100
10,000
10
ms
Endurance1
ECYC
20,000
30
cycles
years
Data Retention1
DRET
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set
up time
–
5
–
us
Figure 3-6, Figure 3-7,
Tnvs*
Figure 3-8
NVSTR hold time
–
–
–
–
5
100
10
1
–
–
–
–
us
us
us
us
Figure 3-6, Figure 3-7
Figure 3-8
Tnvh*
Tnvh1*
Tpgs*
Trcv*
NVSTR hold time (mass erase)
NVSTR to program set up time
Recovery time
Figure 3-6,
Figure 3-6,
Figure 3-7,Figure 3-8
Cumulative program
HV period2
–
3
–
ms
Figure 3-6,
Thv
Program hold time3
–
–
–
–
–
–
–
–
–
Figure 3-6,
Figure 3-6,
Figure 3-6,
Tpgh
Tads
Tadh
Address/data set up time3
Address/data hold time3
1. One cycle is equal to an erase program and read.
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be
programmed twice before next erase.
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
56F827 Technical Data, Rev. 12
28
Freescale Semiconductor
Flash Memory Characteristics
IFREN
XADR
XE
Tadh
YADR
YE
DIN
Tads
PROG
NVSTR
Tnvs
Tprog
Tpgh
Tpgs
Tnvh
Trcv
Thv
Figure 3-6 Flash Program Cycle
IFREN
XADR
XE
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Tnvh
Trcv
Terase
Figure 3-7 Flash Erase Cycle
56F827 Technical Data, Rev. 12
Freescale Semiconductor
29
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1
Trcv
Tme
Figure 3-8 Flash Mass Erase Cycle
3.6 External Clock Operation
The 56F827 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
3.6.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 3-8. A recommended crystal oscillator circuit
is shown in Figure 3-9. Follow the crystal supplier’s recommendations when selecting a crystal, because
crystal parameters determine the component values required to provide maximum stability and reliable
start-up. The crystal and associated components should be mounted as close as possible to the EXTAL
and XTAL pins to minimize output distortion and start-up stabilization time.The internal 56F82x
oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-9, no
external load capacitors should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF
56F827 Technical Data, Rev. 12
30
Freescale Semiconductor
External Clock Operation
as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:
CL1 * CL2
CL1 + CL2
12 * 12
12 + 12
CL =
+ Cs =
+ 3 = 6 + 3 = 9pF
This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.
Recommended External Crystal
Parameters:
Rz = 1 to 3MΩ
EXTAL XTAL
Rz
fc = 4MHz (optimized for 4MHz)
fc
Figure 3-9 Connecting to a Crystal Oscillator Circuit
3.6.2
Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in
Figure 3-10. The resonator and components should be mounted as close as possible to the EXTAL and
XTAL pins. The internal 56F82x oscillator circuitry is designed to have no external load capacitors
present. As shown in Figure 3-9, no external load capacitors should be used.
Recommended Ceramic Resonator
Parameters:
Rz = 1 to 3 MΩ
EXTAL XTAL
Rz
fc = 4MHz (optimized for 4MHz)
fc
Figure 3-10 Connecting a Ceramic Resonator
Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators
(which contain an internal bypass capacitor to ground).
56F827 Technical Data, Rev. 12
Freescale Semiconductor
31
3.6.3
External Clock Source
The recommended method of connecting an external clock is given in Figure 3-11. The external clock
source is connected to XTAL and the EXTAL pin is held V
/2.
DDA
56F827
XTAL
EXTAL
V
/2
External
Clock
DDA
Figure 3-11 Connecting an External Clock Signal
Table 3-8 External Clock Operation Timing Requirements
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
fosc
Min
0
Typ
4
Max
Unit
MHz
ns
Frequency of operation (external clock driver)1
Clock Pulse Width3, 4
802
—
tPW
6.25
—
1. See Figure 3-11 for details on using the recommended connection of an external clock driver.
2. When using Time-of-Day (TOD), maximum external frequency is 6MHz.
3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
4. Parameters listed are guaranteed by design.
VIH
External
Clock
90%
50%
10%
90%
50%
10%
tPW
tPW
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 3-12 External Clock Timing
56F827 Technical Data, Rev. 12
32
Freescale Semiconductor
External Bus Asynchronous Timing
3.6.4
Phase Locked Loop Timing
Table 3-9 PLL Timing
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
fosc
Min
2
Typ
4
Max
6
Unit
MHz
MHz
ms
External reference crystal frequency for the PLL1
PLL output frequency2
fout/2
tplls
40
—
—
1
110
10
PLL stabilization time 3-40o to +85oC
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 4MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
3.7 External Bus Asynchronous Timing
1, 2
Table 3-10 External Bus Asynchronous Timing
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Unit
Min
Max
Address Valid to WR Asserted
tAWR
tWR
6.5
—
ns
WR Width Asserted
Wait states = 0
Wait states > 0
7.5
—
—
ns
ns
(T*WS) + 7.5
WR Asserted to D0–D15 Out Valid
tWRD
tDOH
tDOS
—
T + 4.2
—
ns
ns
Data Out Hold Time from WR Deasserted
4.8
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
2.2
—
—
ns
ns
(T*WS) + 6.4
RD Deasserted to Address Not Valid
tRDA
0
—
—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
18.7
(T*WS) + 18.7
ns
ns
56F827 Technical Data, Rev. 12
Freescale Semiconductor
33
1, 2
Table 3-10 External Bus Asynchronous Timing
(Continued)
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Unit
Min
Max
Input Data Hold to RD Deasserted
tDRD
tRD
0
—
ns
RD Assertion Width
Wait states = 0
Wait states > 0
19
—
—
ns
ns
(T*WS) + 19
Address Valid to Output Data Valid
Wait states = 0
Wait states > 0
tAD
—
—
1
ns
ns
(T*WS) + 1
Address Valid to RD Asserted
tARDA
tRDD
-4.4
—
ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
—
—
2.4
ns
ns
(T*WS) + 2.4
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
WR Deasserted to WR Asserted
RD Deasserted to WR Asserted
tWRRD
tRDRD
tWRWR
tRDWR
6.8
0
—
—
—
—
ns
ns
ns
ns
14.1
12.8
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
56F827 Technical Data, Rev. 12
34
Freescale Semiconductor
External Bus Asynchronous Timing
A0–A15,
PS, DS
tARDD
(See Note)
tRDA
tARDA
tRDRD
tRD
tAWR
tWRWR
RD
tWRRD
tWR
tRDWR
WR
tRDD
tAD
tDOH
tWRD
tDRD
tDOS
Data Out
Data In
D0–D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 3-13 External Bus Asynchronous Timing
56F827 Technical Data, Rev. 12
Freescale Semiconductor
35
3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 5
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
Figure 3-14
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—
21
ns
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
Figure 3-14
275,000T
128T
—
—
ns
ns
RESET Deassertion to First External Address Output
Edge-sensitive Interrupt Request Width
tRDA
tIRW
tIDM
33T
1.5T
15T
34T
—
ns
ns
ns
Figure 3-14
Figure 3-15
Figure 3-16
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
—
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
16T
—
ns
Figure 3-16
Figure 3-17
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
tIRI
13T
2T
—
—
ns
ns
IRQA Width Assertion to Recover from Stop State4
tIW
tIF
Figure 3-18
Figure 3-18
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
—
—
275,000T
12T
ns
ns
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
Figure 3-19
Figure 3-19
—
—
275,000T
12T
ns
ns
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
tII
—
—
275,000T
12T
ns
ns
OMR Bit 6 = 1
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
56F827 Technical Data, Rev. 12
36
Freescale Semiconductor
Reset, Stop, Wait, Mode Select, and Interrupt Timing
RESET
tRA
tRAZ
tRDA
A0–A15,
D0–D15
First Fetch
PS, DS,
RD, WR
First Fetch
Figure 3-14 Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 3-15 External Interrupt Timing (Negative-Edge-Sensitive)
A0–A15,
PS, DS,
RD, WR
First Interrupt Instruction Execution
tIDM
IRQA,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 3-16 External Level-Sensitive Interrupt Timing
56F827 Technical Data, Rev. 12
Freescale Semiconductor
37
IRQA,
IRQB
tIRI
A0–A15,
PS, DS,
RD, WR
First Interrupt Vector
Instruction Fetch
Figure 3-17 Interrupt from Wait State Timing
tIW
IRQA
tIF
A0–A15,
PS, DS,
RD, WR
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 3-18 Recovery from Stop State Using Asynchronous Interrupt Timing
tIRQ
IRQA
tII
A0–A15
PS, DS,
RD, WR
First IRQA Interrupt
Instruction Fetch
Figure 3-19 Recovery from Stop State Using IRQA Interrupt Service
56F827 Technical Data, Rev. 12
38
Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
3.9 Serial Peripheral Interface (SPI) Timing
1
Table 3-12 SPI Timing
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
Figures
3-20, 3-21,
3-22, 3-23
50
25
—
—
ns
ns
Enable lead time
Master
Slave
tELD
tELG
tCH
tCL
Figure 3-23
—
25
—
—
ns
ns
Enable lag time
Master
Slave
Figure 3-23
—
100
—
—
ns
ns
Clock (SCLK) high time
Master
Slave
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
24
12
—
—
Clock (SCLK) low time
Master
Slave
Figures
3-20, 3-21,
3-22, 3-23
24.1
12
—
—
ns
ns
Data set-up time required for inputs
Master
Slave
tDS
Figures
3-20, 3-21,
3-22, 3-23
20
0
—
—
ns
ns
Data hold time required for inputs
Master
Slave
tDH
Figures
3-20, 3-21,
3-22, 3-23
0
2
—
—
ns
ns
Access time (time to data active from high-impedance state)
Slave
tA
tD
Figure 3-23
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
Figure 3-23
15.2
Data Valid for outputs
Master
Slave (after enable edge)
tDV
Figures
3-20, 3-21,
3-22, 3-23
—
—
4.5
20.4
ns
ns
Data invalid
Master
Slave
tDI
tR
tF
Figures
3-20, 3-21,
3-22, 3-23
0
0
—
—
ns
ns
Rise time
Master
Slave
Figures
3-20, 3-21,
3-22, 3-23
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
Figures
3-20, 3-21,
3-22, 3-23
—
—
9.7
9.0
ns
ns
1. Parameters listed are guaranteed by design.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
39
SS
(Input)
SS is held High on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tCL
tF
tR
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
tDV
MOSI
(Output)
Master MSB out
tF
Bits 14–1
Master LSB out
tR
Figure 3-20 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tCL
tF
SCLK (CPOL = 1)
(Output)
tCH
tDS
tDH
tR
MISO
(Input)
MSB in
tDI
Bits 14–1
LSB in
tDV
tDV(ref)
MOSI
(Output)
Master MSB out
tF
Bits 14– 1
Master LSB out
tR
Figure 3-21 SPI Master Timing (CPHA = 1)
56F827 Technical Data, Rev. 12
40
Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
SS
(Input)
tC
tF
tR
tELG
tCL
SCLK (CPOL = 0)
(Input)
tCH
tCL
tELD
SCLK (CPOL = 1)
(Input)
tF
tCH
tA
tR
tD
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
Slave LSB out
tDI
tDS
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 3-22 SPI Slave Timing (CPHA = 0)
SS
(Input)
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tD
tF
tA
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
Slave LSB out
tDS
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 3-23 SPI Slave Timing (CPHA = 1)
56F827 Technical Data, Rev. 12
Freescale Semiconductor
41
3.10 Analog-to-Digital Converter (ADC) Timing
Table 3-13 ADC Characteristics
Characteristic
ADC Input voltage
Symbol
Min
Typ
Max
VREFHI
12
Unit
1
VADCIN
0
—
V
Resolution
RES
INL
12
—
—
—
Bits
Integral Non-Linearity2
LSB3
LSB3
+/- 1
+/- 3
+/- 1
Differential Non-Linearity
DNL
+/- 0.4
GUARANTEED
—
Monotonicity
ADC internal clock4
Conversion range
fADIC
RAD
tADPU
tADC
0.5
VREFLO
—
2.5
MHz
V
—
25
6
VREFHI
—
Power-up time
ms
tAIC cycles5
tAIC cycles5
Conversion time
—
—
Sample time
tADS
—
1
—
pF5
—
Input capacitance
CADI
EGAIN
VOFFSET
THD
—
0.95
-60
57
5
1.00
+15
66
—
1.10
+40
—
Gain Error (transfer gain)4
Offset Voltage4
mV
dB
bit
Total Harmonic Distortion4
Effective Number of Bits4
Spurious Free Dynamic Range4
ENOB
SFDR
SINAD
IADC
9.3
58
10.5
70
—
—
dB
dB
mA
μA
Signal-to-Noise plus Distortion4
ADC quiescent current
56
64
—
10
—
—
—
ADC quiescent current (power
down bit set high)
IADCPD
1
—
V
REF quiescent current
IVREF
1
1
mA
—
—
—
—
VREF quiescent current (power
IVREFPD
μA
down bit set high)
1. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to
DDA-0.3V.
V
56F827 Technical Data, Rev. 12
42
Freescale Semiconductor
Synchronous Serial Interface (SSI) Timing
2. Measured in 10-90% range.
3. LSB = Least Significant Bit.
4. Guaranteed by characterization.
5. t
= 1/f
ADIC
AIC
ADC analog input
1
3
2
4
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only
connected to it at sampling time. (1pf)
Figure 3-24 Equivalent Analog Input Circuit
3.11 Synchronous Serial Interface (SSI) Timing
1
Table 3-14 SSI Master Mode Switching Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz
Parameter
Symbol
fs
Min
—
Typ
—
Max
Units
MHz
ns
102
—
STCK frequency
STCK period3
tSCKW
tSCKH
tSCKL
100
—
504
STCK high time
—
—
—
ns
504
—
STCK low time
—
ns
Output clock rise/fall time
—
4
—
ns
ns
Delay from STCK high to STFS (bl) high - Master5
Delay from STCK high to STFS (wl) high - Master5
Delay from SRCK high to SRFS (bl) high - Master5
Delay from SRCK high to SRFS (wl) high - Master5
Delay from STCK high to STFS (bl) low - Master5
tTFSBHM
0.1
—
0.5
tTFSWHM
tRFSBHM
tRFSWHM
tTFSBLM
0.1
0.6
0.6
-1.0
—
—
—
—
0.5
1.3
1.3
-0.1
ns
ns
ns
ns
56F827 Technical Data, Rev. 12
Freescale Semiconductor
43
1
Table 3-14 SSI Master Mode Switching Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz
Parameter
Symbol
tTFSWLM
tRFSBLM
tRFSWLM
tTXEM
Min
-1.0
-0.1
-0.1
20
Typ
—
—
—
—
—
—
—
—
—
Max
-0.1
0
Units
ns
Delay from STCK high to STFS (wl) low - Master5
Delay from SRCK high to SRFS (bl) low - Master5
ns
Delay from SRCK high to SRFS (wl) low - Master5
0
ns
STCK high to STXD enable from high impedance - Master
22
ns
STCK high to STXD valid - Master
tTXVM
24
26
ns
STCK high to STXD not valid - Master
STCK high to STXD high impedance - Master
SRXD Setup time before SRCK low - Master
SRXD Hold time after SRCK low - Master
tTXNVM
tTXHIM
tSM
0.1
24
0.2
25.5
—
ns
ns
4
ns
tHM
4
—
ns
Synchronous Operation (in addition to standard internal clock parameters)
SRXD Setup time before STCK low - Master
SRXD Hold time after STCK low - Master
tTSM
tTHM
4
4
—
—
—
—
—
—
1. Master mode is internally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS
in the tables and in the figures.
4. 50% duty cycle
5. bl = bit length; wl = word length
56F827 Technical Data, Rev. 12
44
Freescale Semiconductor
Synchronous Serial Interface (SSI) Timing
tSCKW
tSCKH
tSCKL
STCK output
STFS (bl) output
STFS (wl) output
tTFSBHM
tTFSBLM
tTFSWHM
tTFSWLM
tTXVM
tTXEM
tTXNVM
tTXHIM
First Bit
Last Bit
STXD
SRCK output
tRFSBHM
tRFBLM
SRFS (bl) output
SRFS (wl) output
tRFSWHM
tRFSWLM
tTSM
tSM
tHM
tTHM
SRXD
Figure 3-25 Master Mode Timing Diagram
1
Table 3-15 SSI Slave Mode Switching Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Parameter
Symbol
fs
Min
—
Typ
—
—
—
—
4
Max
Units
MHz
ns
102
STCK frequency
STCK period3
tSCKW
tSCKH
tSCKL
—
100
—
504
STCK high time
ns
—
—
—
504
STCK low time
ns
Output clock rise/fall time
ns
—
56F827 Technical Data, Rev. 12
Freescale Semiconductor
45
1
Table 3-15 SSI Slave Mode Switching Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Parameter
Symbol
tTFSBHS
tTFSWHS
tRFSBHS
tRFSWHS
tTFSBLS
tTFSWLS
tRFSBLS
tRFSWLS
tTXES
Min
0.1
0.1
0.1
0.1
-1
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
46
46
46
46
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay from STCK high to STFS (bl) high - Slave5
Delay from STCK high to STFS (wl) high - Slave5
Delay from SRCK high to SRFS (bl) high - Slave5
Delay from SRCK high to SRFS (wl) high - Slave5
Delay from STCK high to STFS (bl) low - Slave5
Delay from STCK high to STFS (wl) low - Slave5
Delay from SRCK high to SRFS (bl) low - Slave5
-1
—
-46
-46
—
—
Delay from SRCK high to SRFS (wl) low - Slave5
—
STCK high to STXD enable from high impedance - Slave
—
STCK high to STXD valid - Slave
tTXVS
1
25
25
27
13
28.5
—
STFS high to STXD enable from high impedance (first bit) - Slave
STFS high to STXD valid (first bit) - Slave
STCK high to STXD not valid - Slave
tFTXES
tFTXVS
tTXNVS
tTXHIS
5.5
6
11
11
4
STCK high to STXD high impedance - Slave
SRXD Setup time before SRCK low - Slave
SRXD Hold time after SRCK low - Slave
tSS
tHS
4
—
Synchronous Operation (in addition to standard external clock parameters)
SRXD Setup time before STCK low - Slave
SRXD Hold time after STCK low - Slave
tTSS
tTHS
4
4
—
—
—
—
—
—
1. Slave mode is externally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have
been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the
tables and in the figures.
4. 50% duty cycle
5. bl = bit length; wl = word length
56F827 Technical Data, Rev. 12
46
Freescale Semiconductor
Quad Timer Timing
tSCKW
tSCKH
tSCKL
STCK input
STFS (bl) input
STFS (wl) input
tTFSBLS
tTFSBHS
tTFSWHS
tTFSWLS
tFTXVS
tFTXES
tTXVS
tTXNVS
tTXES
tTXHIS
First Bit
Last Bit
STXD
SRCK input
tRFBLS
tRFSBHS
SRFS (bl) input
SRFS (wl) input
tRFSWHS
tRFSWLS
tTSS
tSS
tHS
tTHS
SRXD
Figure 3-26 Slave Mode Clock Timing
3.12 Quad Timer Timing
1, 2
Table 3-16 Timer Timing
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz
Characteristic
Timer input period
Symbol
PIN
Min
4T+6
2T+3
2T
Max
—
Unit
ns
Timer input high/low period
Timer output period
PINHL
POUT
—
ns
—
ns
Timer output high/low period
POUTHL
1T
—
ns
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
47
Timer Inputs
PIN
PINHL
PINHL
Timer Outputs
POUT
POUTHL
POUTHL
Figure 3-27 Quad Timer Timing
3.13 Serial Communication Interface (SCI) Timing
4
Table 3-17 SCI Timing
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
—
Max
Unit
Baud Rate1
BR
(fMAX*2.5)/(80)
Mbps
RXD2 Pulse Width
TXD3 Pulse Width
RXDPW
TXDPW
0.965/BR
1.04/BR
1.04/BR
ns
ns
0.965/BR
1. fMAX is the frequency of operation of the system clock in MHz.
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
RXD
SCI receive
data pin
RXDPW
(Input)
Figure 3-28 RXD Pulse Width
TXD
SCI receive
data pin
TXDPW
(Input)
Figure 3-29 TXD Pulse Width
56F827 Technical Data, Rev. 12
48
Freescale Semiconductor
JTAG Timing
3.14 JTAG Timing
1, 3
Table 3-18 JTAG Timing
Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
TCK frequency of operation2
Symbol
Min
Max
Unit
fOP
DC
10
MHz
TCK cycle time
tCY
tPW
tDS
100
50
—
—
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock pulse width
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
DE assertion time
0.4
1.2
—
—
tDH
—
tDV
26.6
23.5
—
tTS
—
tTRST
tDE
50
4T
—
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
tCY
tPW
tPW
VIH
VM
VIL
VM
TCK
(Input)
VM = VIL + (VIH – VIL)/2
Figure 3-30 Test Clock Input Timing Diagram
56F827 Technical Data, Rev. 12
Freescale Semiconductor
49
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 3-31 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 3-32 TRST Timing Diagram
DE
tDE
Figure 3-33 OnCE—Debug Event
56F827 Technical Data, Rev. 12
50
Freescale Semiconductor
Package and Pin-Out Information 56F827
Part 4 Packaging
4.1 Package and Pin-Out Information 56F827
This section contains package and pin-out information for the 128-pin LQFP configuration of the 56F827.
RXD2
TXD2
RXD1
TXD1
RXD0
TXD0
VREFLO
VSSA_ADC
VDDA
VSSA
XTAL
PIN 64
PIN 102
EXTAL
TA3
TA2
TA1
VSSIO
CLKO
VDDIO
TA0
VDDIO
SRD
SRFS
VSSIO
VSS
SRCK
STD
VDD
GPIOB7
STFS
STCK
GPIOB6
GPIOB5
GPIOB4
GPIOB3
IRQB
TDI
TDO
TMS
GPIOB2
GPIOB1
GPIOB0
D0
TRST
TCK
TCS
RESET
DE
IRQA
ORIENTATION
MARK
PIN 39
D1
D2
D3
PIN 1
EXTBOOT
Figure 4-1 Top View, 56F827 128-pin LQFP Package
56F827 Technical Data, Rev. 12
Freescale Semiconductor
51
Table 4-1 56F827 Pin Identification by Pin Number
Pin No.
Signal Name
Pin No.
33
Signal Name
A10
Pin No.
65
Signal Name
VREFP
Pin No.
97
Signal Name
GPIOD1
GPIOD0
SS
1
2
3
4
5
D4
D5
34
A11
66
VREFN
98
D6
35
A12
67
VREFHI
99
VDDIO
VSSIO
36
A13
68
VREFMID
VDDA_ADC
100
101
MISO
37
A14
69
MOSI
6
D7
D8
38
39
40
41
42
43
44
45
46
47
48
A15
EXTBOOT
IRQA
DE
70
71
72
73
74
75
76
77
78
79
80
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
ANA8
ANA9
VSS
102
103
104
105
106
107
108
109
110
111
112
SCLK
RXD2
TXD2
RXD1
TXD1
RXD0
TXD0
TA3
7
8
D9
9
D10
D11
D12
D13
D14
D15
RD
10
11
12
13
14
15
16
RESET
TCS
TCK
TRST
TMS
TA2
TDO
TA1
WR
TDI
TA0
17
18
19
20
DS
PS
49
50
51
52
IRQB
STCK
STFS
STD
81
82
83
84
VDD
113
114
115
116
VDDIO
VSSIO
VSS
VDDIO
VSSIO
PCS2
VDD
VSS
VDD
21
22
23
24
A0
A1
A2
A3
53
54
55
56
SRCK
SRFS
SRD
85
86
87
88
PCS3
PCS4
PCS5
PCS6
117
118
119
120
GPIOB7
GPIOB6
GPIOB5
GPIOB4
VDDIO
25
26
A4
A5
57
58
CLKO
VSSIO
89
90
PCS7
VPP
121
122
GPIOB3
GPIOB2
27
A6
59
EXTAL
91
GPIOD7
123
GPIOB1
56F827 Technical Data, Rev. 12
52
Freescale Semiconductor
Package and Pin-Out Information 56F827
Table 4-1 56F827 Pin Identification by Pin Number (Continued)
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
28
29
A7
60
61
XTAL
VSSA
92
93
GPIOD6
GPIOD5
124
125
GPIOB0
D0
VDDIO
30
31
32
VSSIO
A8
62
63
64
VDDA
VSSA_ADC
VREFLO
94
95
96
GPIOD4
GPIOD3
GPIOD2
126
127
128
D1
D2
D3
A9
56F827 Technical Data, Rev. 12
Freescale Semiconductor
53
102
65
64
103
128
39
38
MILLIMETERS
DIM
MIN
---
MAX
1.60
0.15
1.45
0.27
0.23
0.20
0.16
A
A1
A2
b
b1
c
0.05
1.35
0.17
0.17
0.09
0.09
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF
THE PARTING LINE.
4. DATUMS A, B, AND D TO BE DETERMINED AT DATUM
PLANE H.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER
SIDE. DIMENSIONS D1 AND E1 DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM
PLANE H.
c1
D
22.00 BSC
D1
e
E
E1
L
L1
L2
S
20.00BSC
0.50 BSC
16.00 BSC
14.00 BSC
0.45
0.75
1.00 REF
0.50 REF
0.20
0.08
---
---
R1
R2
0
0.08
0.20
7o
---
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.35.
0o
0o
01
02
11o
13o
Case Outline - 1129-01
Figure 4-2 128-pin LQFP Mechanical Information
Please see www.freescale.com for the most current case outline.
56F827 Technical Data, Rev. 12
54
Freescale Semiconductor
Thermal Design Considerations
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, T , in °C can be obtained from the equation:
J
Equation 1:TJ = TA + (PD × RθJA
)
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2:RθJA = RθJC + RθCA
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
R
is device-related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case-to-ambient thermal resistance, R
. For example, the user can change the air flow around
θCA
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system-level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from R
the thermal performance is adequate, a system-level model may be appropriate.
do not satisfactorily answer whether
θJA
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
•
Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
55
•
•
Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.
Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case
determined by a thermocouple.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
5.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation:
•
Provide a low-impedance path from the board power supply to each VDD, VDDIO, and VDDA pin on the
controller, and from the board ground to each VSS,VSSIO, and VSSA (GND) pin.
•
The minimum bypass requirement is to place 0.1μF capacitors positioned as close as possible to the package
supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the
VDD/VSS pairs, including VDDA/VSSA and VDDIO/VSSIO. Ceramic and tantalum capacitors tend to provide
better performance tolerances.
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD, VDDIO, and
VDDA and VSS, VSSIO, and VSSA (GND) pins are less than 0.5 inch per capacitor lead.
56F827 Technical Data, Rev. 12
56
Freescale Semiconductor
Electrical Design Considerations
•
Bypass the VDD and VSS layers of the PCB with approximately 100μF, preferably with a high-grade
capacitor such as a tantalum capacitor.
•
•
Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
•
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
•
•
When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs
that do not require debugging functionality, such as consumer products, TRST should be tied low.
•
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
57
Part 6 Ordering Information
Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
Table 6-1 56F827 Ordering Information
Ambient
Frequency
(MHz)
Supply
Voltage
Pin
Count
Part
Package Type
Order Number
56F827
56F827
2.25–2.75V
2.25–2.75V
Low Profile Quad Flat Pack (LQFP)
Low Profile Quad Flat Pack (LQFP)
128
128
80
DSP56F827FG80
80
DSP56F827FG80E *
*This package is RoHS compliant.
56F827 Technical Data, Rev. 12
58
Freescale Semiconductor
Electrical Design Considerations
56F827 Technical Data, Rev. 12
Freescale Semiconductor
59
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Inc. All other product or service names are the property of their respective owners.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56F827
Rev. 12
01/2007
相关型号:
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