DSP56F807PB [ETC]
56F807 16-Bit Hybrid Controller Product Brief ; 56F807 16位混合控制器产品简介\n
| 型号： | DSP56F807PB |
| 厂家： | 
ETC |
| 描述： | 56F807 16-Bit Hybrid Controller Product Brief
|
| 文件： | 总2页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
HYBRID FLASH SOLUTION
56F807
16-bit Hybrid Controller
TARGET APPLICATIONS
BENEFITS
• Conveyors
• On-board voltage regulator and power
management is designed to reduce overall
system cost by allowing for a single
supply voltage
• Supports multiple processor connections
• UPS
• Servo drives
• Patented distortion correction in PWM for
reducing design risk and better
performance control
• Fuel management systems
• Lifts/elevators/cranes
• Underwater acoustics
• Industrial frequency inverters
• Noise cancellation
• General purpose devices
• Switched-mode power supplies
• Flash memory is engineered to provide
reliable, non-volatile memory storage,
eliminating the need for external storage
devices
• PWM and ADC modules are tightly
coupled to reduce processing overhead
• Low voltage interrupts protect the system
during brownout or power failure
• Easy to program with flexible application
development tools
• Simple interface with other asynchronous
serial communication devices and off-chip
EE memory
• Simple updating of Flash memory
through SPI, SCI or OnCE™, using on-chip
boot loader
• Program can boot directly from Flash
The 56F807 is a member of the 56800 core-based
family of Hybrid Controllers. It combines, on a single
chip, the processing power of a DSP and the
56F807 16-BIT HYBRID CONTROLLER
• Up to 40 MIPS at 80MHz core frequency
• Two 6 channel PWM modules
• Four 4 channel, 12-bit ADCs
• Two Quadrature Decoders
• CAN 2.0 A/B module
functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective
solution. Because of its low cost, configuration
flexibility, and compact program code, the 56F807 is
well-suited for many applications. The 56800 core is
based on a Harvard-style architecture consisting of
three execution units operating in parallel, allowing
as many as six operations per instruction cycle. The
microprocessor-style programming model and
optimized instruction set allow straightforward
generation of efficient, compact code for both DSP
and MCU applications. The instruction set is also
highly efficient for compilers to enable rapid
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• Two Serial Communication Interfaces
(SCIs)
• Serial Peripheral Interface (SPI)
• 70K On-chip Flash
- 60K Program Flash
- 8K Data Flash
• Four general purpose Quad Timers
• JTAG/OnCE port for debugging
• 14 dedicated and 18 shared GPIO lines
• 160-pin LQFP or 160 MAPBGA Packages
- 2K Boot Flash
• 2K Program RAM
• 4K Data RAM
development of optimized control applications.
ENERGY INFORMATION
Program Memory
COP/Watchdog
Ext Memory I/F
• Fabricated in high-density CMOS with 5V-
tolerant, TTL-compatible digital inputs
• On-chip regulators for digital and analog
circuitry to lower cost and reduce noise
2K RAM
60K Flash
• Uses a single 3.3V power supply
• Wait and Stop modes available
SPI
2K Boot Flash
(2) SCI
Up to 32 GPIO
(4) 16-Bit
Quad Timers
56800 Core
CAN 2.0 A/B
40 MIPS
Quad 4-Channel
ADC, 12-Bit
(2) 4-Channel
Quad Decoder
Data Memory
Power Mgmt
PLL
(2) 6-Channel
PWM
4K RAM
8K Flash
JTAG/OnCE
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
56800 CORE FEATURES
HYBRID FLASH SOLUTION
• Efficient 16-bit 56800 family hybrid
controller engine with dual Harvard
architecture
• Three internal address buses and one
external address bus
56F807
• Four internal data buses and one external
data bus
• As many as 40 Million Instructions Per
Second (MIPS) at 80MHz core frequency
PRODUCT DOCUMENTATION
• Instruction set supports both DSP and
controller functions
• Single-cycle 16 x 16-bit parallel Multiplier-
Accumulator (MAC)
DSP56800
Family Manual
Detailed description of the 56800
family architecture, and 16-bit DSP core
processor and the instruction set
• Controller-style addressing modes and
instructions for compact code
• Two 36-bit accumulators including
extension bits
• Efficient C compiler and local variable
support
Order Number: DSP56800FM/D
• 16-bit bidirectional barrel shifter
DSP56F80x
User’s Manual
Detailed description of memory,
peripherals, and interfaces of the
56F801, 56F802, 56F803,
• Parallel instruction set with unique
addressing modes
• Software subroutine and interrupt stack
with depth limited only by memory
• Hardware DO and REP loops
• JTAG/OnCE debug programming interface
56F805, and 56F807
Order Number: DSP56F801-7UM/D
56F807 MEMORY FEATURES
DSP56F807
Technical Data
Sheet
Electrical and timing specifications,
pin descriptions, and package
descriptions
• Harvard architecture permits as many as
three simultaneous accesses to program
and data memory
• Off-chip memory expansion capabilities
– As much as 64K data memory
– As much as 64K program memory
Order Number: DSP56F807/D
• On-chip memory including a low-cost,
high-volume Flash solution
DSP56F807
Product Brief
Summary description and block diagram
of the core, memory,
peripherals and interfaces
- 70K On-chip Flash
- 60K Program Flash
- 8K Data Flash
Order Number: DSP56F807PB/D
- 2K Boot Flash
- 2K Program RAM
- 4K Data RAM
AWARD-WINNING
DEVELOPMENT ENVIRONMENT
56F807 PERIPHERAL CIRCUIT FEATURES
• Processor Expert™ (PE) technology provides a rapid
application design (RAD) tool that combines easy-to-use
component-based software application creation with an
expert knowledge system.
• Two Pulse Width Modulator modules, each
with six PWM outputs, three Current Sense
inputs, and four Fault inputs, fault-tolerant
design with dead-time insertion; supports
both center- and edge-aligned modes
• Serial Peripheral Interface (SPI)
• Computer Operating Properly (COP)/
Watchdog timer
• The CodeWarrior™ Integrated Development Environment
(IDE) is a sophisticated tool for code navigation, compiling
and debugging. A comprehensive set of evaluation modules
(EVMs) and development system cards will support
concurrent engineering. Together, PE, the CodeWarrior tool
suite and EVMs create a comprehensive, scalable tools
solution for easy, fast and efficient development.
• Two dedicated external interrupt pins
• 14 dedicated General Purpose I/O (GPIO)
pins, 18 multiplexed GPIO pins
• Four 12-bit Analog-to-Digital Converters
(ADCs), which support two simultaneous
conversions; ADC and PWM modules can
be synchronized
• External reset input pin for hardware reset
• External reset output pin for system reset
• Two Quadrature Decoders
• JTAG/OnCE™ for unobtrusive, processor
speed-independent debugging
• Four dedicated General Purpose Quad
Timers
• Software-programmable, Phase Lock
Loop-based frequency synthesizer
• Two Serial Communication Interfaces (SCI)
• CAN 2.0 A/B module
ORDERING INFORMATION
PART
SUPPLY
VOLTAGE
PACKAGE TYPE
PIN COUNT
FREQUENCY
(MHz)
ORDER NUMBER
DSP56F807
DSP56F807
DSP56F807
DSP56F807
3.0–3.6V
3.0–3.6V
3.0–3.6V
3.0–3.6V
Low profile Quad Flat Pack (LQFP)
MAP Ball Grid Array (MAPBGA)
Low profile Quad Flat Pack (LQFP)
MAP Ball Grid Array (MAPBGA)
160
160
160
160
80
80
80
80
DSP56F807PY80
DSP56F807VF80
SPAK56F807PY80
SPAK56F807VF80
Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This
product incorporates SuperFlash® technology licensed from SST. All other product or service
names are the property of their respective owners. © Motorola, Inc. 2003
DSP56F807PB/D
For More Information On This Product,
REV 6
Go to: www.freescale.com
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