V436664Z24VG-75PC [MOSEL]
512MB 144-PIN UNBUFFERED SDRAM SODIMM, 64M x 64 3.3 VOLT; 512MB 144 -PIN UNBUFFERED SODIMM SDRAM ， 64M ×64 3.3伏
| 型号： | V436664Z24VG-75PC |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | 512MB 144-PIN UNBUFFERED SDRAM SODIMM, 64M x 64 3.3 VOLT |
| 文件： | 总12页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
V436664Z24V
512MB 144-PIN UNBUFFERED SDRAM
SODIMM, 64M x 64 3.3 VOLT
Features
Description
The V436664Z24V memory module is organized
■ JEDEC-standard 144 pin, Small-Outline, Dual in
67,108,864 x 64 bits in a 144 pin SODIMM. The
64M x 64 memory module uses 16 Mosel-Vitelic
32M x 8 SDRAM. The x64 modules are ideal for use
in high performance computer systems where
increased memory density and fast access times
are required.
line Memory Module (SODIMM)
■ Serial Presence Detect with E PROM
■ Nonbuffered
■ Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
■ Single +3.3V (± 0.3V) Power Supply
■ All Device Pins are LVTTL Compatible
■ 8192 Refresh Cycles every 64 ms
■ Self-Refresh Mode
■ Internal Pipelined Operation; Column Address
can be changed every System Clock
■ Programmable Burst Lengths: 1, 2, 4, 8
■ Auto Precharge and Piecharge all Banks by A10
■ Data Mask Function by DQM
2
Speed
Part Number
Grade
Configuration
V436664Z24VXXG-75PC -75PC, CL=2,3
(133 MHz)
64M x 64
V436664Z24VXXG-75
-75, CL=3
(133 MHz)
64M x 64
64M x 64
■ Mode Register Set Programming
■ Programmable (CAS Latency: 2, 3 Clocks)
■ SOC and WBGA component packaging
V436664Z24VXXG-10PC -10PC, CL=2
(100 MHz)
1
59
61
143
Pin 2 on Backside
Pin 144 on Backside
V436664Z24V Rev. 1.2 February 2002
1
V436664Z24V
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
VSS
VSS
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB1
DQMB5
VDD
VDD
A0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
97
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
CLK1
VSS
VSS
98
3
4
DQ0
DQ32
DQ1
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
5
NC
6
DQ33
DQ2
A3
NC
7
A1
NC
8
DQ34
DQ3
DQ35
VDD
A4
NC
A7
9
A2
A5
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
A8
BA0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
VDD
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
NC
VSS
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VDD
NC
VSS
DQ4
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
A9
DQ36
DQ5
DQ37
DQ6
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
DQ38
DQ7
DQ39
VSS
VSS
CKE1
CS0
A12
VSS
VSS
DQ20
DQ52
DQ21
DQ53
SDA
SCL
DQMB0
DQMB4
CS1
NC
VDD
VSS
VDD
Note:
1. RAS, CAS, WE CASx, CSx are active low signals.
Pin Names
A0–A12, BA0, BA1 Address, Bank Select
DQ0–DQ63
RAS
Data Inputs/Outputs
Row Address Strobes
Column Address Strobes
Write Enable
CAS
WE
CS0, CS1
DQMB0–DQMB7
CKE0, CKE1
CLK0, CLK1
SDA
Chip Select
Output Enable
Clock Enable
Clock
Serial Input/Output
Serial Clock
SCL
VDD
Power Supply
Ground
VSS
NC
No Connect (Open)
V436664Z24V Rev. 1.2 February 2002
2
V436664Z24V
Part Number Information
V
4
3
66 64 Z 2 4 V X X G - XX
SPEED
MOSEL VITELIC
75PC = PC133 CL2,3
MANUFACTURED
75
= PC133 CL3
10PC = PC100 CL2
SDRAM
LEAD FINISH
G = GOLD
3.3V
COMPONENT
PACKAGE S=SOC, B=WBGA
WIDTH
DEPTH
COMPONENT
REV LEVEL A=0.17u, B=0.14u
144 PIN SODIMM
X8 COMPONENT
LVTTL
4 BANKS
REFRESH
RATE 8K
Block Diagram
Block Diagram
CS0
CS0
CS
CS
CS
CS
DQM0
I/O1–I/O8
DQM4
I/O33–I/O40
DQM
DQM
DQM
DQM
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
D0
D8
D9
D4
D5
D12
D13
10Ω
10Ω
10Ω
10Ω
CS
CS
CS
CS
DQM1
I/O9–I/O16
DQM5
I/O41–I/O48
DQM
DQM
DQM
DQM
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
D1
CS1
CS1
CS
CS
CS
CS
DQM2
I/O17–I/O24
DQM6
I/O49–I/O56
DQM
DQM
DQM
DQM
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
D2
D3
D10
D11
D6
D7
D14
D15
10Ω
10Ω
10Ω
10Ω
CS
CS
CS
CS
DQM3
I/O25–I/O32
DQM7
I/O57–I/O64
DQM
DQM
DQM
DQM
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
E2PROM SPD (256 WORD X 8 BIT)
A12-A0, BA0, BA1
D0-D15
SA0
SA1
SA2
SCL
SA0 SDA
SA1
VDD
VSS
D0-D15
D0-D7
C0-C31
SA2
SCL
WP
RAS, CAS, WE
CKE0
D0-D15
47K
D0-D7
VCC
10K
D9-D15
CKE1
CLOCK WIRING
16M X 64
8 SDRAMS +3.3pF
CLK0
8 SDRAMS +3.3pF
CLK1
V436664Z24V Rev. 1.2 February 2002
3
V436664Z24V
Serial Presence Detect Information
2
2
A serial presence detect storage device - E PROM -
is assembled onto the module. Information about the
module configuration, speed, etc. is written into the
E PROM device during module production using a se-
2
rial presence detect protocol (I C synchronous 2-wire
bus)
SPD-Table for modules:
Hex Value
Byte Num-
ber
Function Described
SPD Entry Value
-75PC
80
-75
80
08
04
0D
0A
02
40
00
01
75
54
00
82
08
00
01
-10PC
80
0
Number of SPD bytes
128
1
Total bytes in Serial PD
256
08
08
2
Memory Type
SDRAM
04
04
3
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x8 SDRAM)
Number of DIMM Banks
13
0D
0A
02
0D
0A
02
4
10
5
2
6
Module Data Width
64
0
40
40
7
Module Data Width (continued)
Module Interface Levels
00
00
8
LVTTL
01
01
9
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
7.5 ns/10.0 ns
5.4 ns/10.0ns
none
75
A0
60
10
11
12
13
14
15
54
00
00
Self-Refresh, 7.8 µs
x8
82
82
SDRAM width, Primary
08
08
Error Checking SDRAM Data Width
n/a / x8
00
00
Minimum Clock Delay from Back to Back Ran-
dom Column Address
tccd = 1 CLK
01
01
16
17
18
19
20
21
22
23
Burst Length Supported
1, 2, 4 & 8
4
0F
04
06
01
01
00
0E
75
0F
04
06
01
01
00
0E
A0
0F
04
06
01
01
00
0E
A0
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
CL = 2 / 3
CS Latency = 0
WL = 0
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency = 2
Non Buffered/Non Reg.
Vcc tol ± 10%
7.5 ns/10.0 ns
24
Maximum Data Access Time from Clock for CL
= 2
5.4 ns/6.0 ns
54
60
60
25
26
Minimum Clock Cycle Time at CL = 1
Not Supported
Not Supported
00
00
00
00
00
00
Maximum Data Access Time from Clock at CL
= 1
27
28
Minimum Row Precharge Time
15 ns / 20 ns
0F
0E
14
0F
14
10
Minimum Row Active to Row Active Delay tRRD
14 ns/15 ns/16 ns
V436664Z24V Rev. 1.2 February 2002
4
V436664Z24V
SPD-Table for modules: (Continued)
Hex Value
Byte Num-
ber
Function Described
SPD Entry Value
15 ns/20 ns
-75PC
0F
-75
14
2D
40
15
08
15
08
00
02
43
40
00
-10PC
29
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
14
2D
40
20
10
20
10
00
12
B1
40
00
30
42 ns/45 ns
2A
40
31
256 Mbyte
64
1.5 ns/2.0 ns
0.8 ns/ 1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
15
33
SDRAM Input Hold Time
08
34
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
15
35
08
62-61
62
00
Revision 2 / 1.2
Mosel Vitelic
02
63
Checksum for Bytes 0 - 62
FE
40
64
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
65-71
72
00
1 = US, 2 = Taiwan
V436664Z24V
73-90
91-92
93
Module Part Number (ASCII)
PCB Identification Code
Current PCB Revision
Binary Coded year (BCD)
Binary Coded week (BCD)
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
94
95-98
byte 95 = LSB, byte 98 =
MSB
99-125
126
Reserved
00
64
00
64
00
64
Intel Specification for Frequency
Supported Frequency
Unused Storage Location
127
128+
00
00
00
V436664Z24V Rev. 1.2 February 2002
5
V436664Z24V
DC Characteristics
T = 0°C to 70°C; V = 0 V; V , V = 3.3V ± 0.3V
DDQ
A
SS
DD
Limit Values
Symbol Parameter
Min.
2.0
Max.
VCC+0.3
Unit
V
VIH
VIL
Input High Voltage
Input Low Voltage
–0.5
2.4
0.8
—
V
VOH
VOL
II(L)
Output High Voltage (IOUT = –4.0 mA)
Output Low Voltage (IOUT = 4.0 mA)
Input Leakage Current, any input
V
—
0.4
10
V
–10
µA
(0 V < VIN < 3.6 V, all other inputs = 0V)
IO(L)
Output leakage current
–10
10
µA
(DQ is disabled, 0V < VOUT < VCC
)
Capacitance
T = 0°C to 70°C; V = 3.3V ± 0.3V, f = 1 MHz
A
DD
Symbol
Parameter
Limit Values (Max.)
Unit
CI1
CI2
Input Capacitance (A0 to A11, RAS, CAS, WE)
Input Capacitance (CS0, CSI)
Input Capacitance (CLK0-CLK1)
Input Capacitance (CKE0, CKEI)
Input Capacitance (DQMB0-DQMB7)
Input Capacitance (SCL, SA0-2)
Input/Output Capacitance
40
25
28
20
10
8
pF
pF
pF
pF
pF
pF
pF
CICL
CI3
CI4
CSC
CIO
18
Absolute Maximum Ratings
Parameter
Max.
-1 to 4.6
-1 to 4.6
0 to +70
-55 to 125
12.7
Units
V
Voltage on VDD Supply Relative to VSS
Voltage on Input Relative to VSS
Operating Temperature
Storage Temperature
V
°C
°C
W
Power Dissipation
V436664Z24V Rev. 1.2 February 2002
6
V436664Z24V
Standby and Refresh Currents1
T = 0°C to 70°C, V = 3.3V ± 0.3V
A
CC
Sym-
bol
Parameter
Test Conditions
75PC/75 10PC
Unit
Note
ICC
1
Operating Current
Burst length = 4, CL = 3
1840
1360
mA
1,2
t
t
RC> = tRC(min),
CK> = tCK(min), IO = 0 mA
2 Bank Interleave Operation
I
CC2P
Precharged Standby Current in
Power Down Mode
CKE< = VIL(max), tCK> = tCK(min)
16
16
mA
mA
ICC2N
Precharged Standby Current in
Non-Power Down Mode
CKE> = VIH(min), tCK> = tCK(min), In-
put changed once in 3 cycles
320
240
CS = High
ICC3P
ICC3N
Active Standby Current in Power
Down Mode
CKE< = VIL(max), tCK> = tCK(min)
160
400
160
360
800
mA
mA
mA
Active Standby Current in Non-Pow- CKE> = VIH(min), tCK> = tCK(min), In-
CS = High
1, 2
er Down Mode
put changed one time
ICC
4
Burst Operating Current
Burst length = Full Page,
1200
t
t
RC = Infinite, CL = 3,
CK> = tCK(min), IO = 0 mA
2 Banks Activated
tRC>= tRC(min)
CKE = <0,2 V
I
I
CC5
CC6
Auto Refresh Current
Self Refresh Current
3840
48
3520
48
mA
mA
1,2
1,2
Standard
L-Version
28
28
V436664Z24V Rev. 1.2 February 2002
7
V436664Z24V
AC Characteristics 3,4
T = 0° to 70°C; V = 0V; V = 3.3V ± 0.3V, t = 1 ns
A
SS
CC
T
Limit Values
-75PC
-75
-10PC
#
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
Clock and Clock Enable
1
2
3
tCK
fCK
tAC
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
7.5
7.5
10
10
10
ns
ns
System frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
133
–
–
133
100
–
–
100
100
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
4,5
–
–
5.4
6
–
–
5.4
6
–
–
6
6
ns
ns
4
5
tCH
tCL
Clock High Pulse Width
Clock Low Pulse Width
2.5
2.5
1.5
0.8
2
–
–
–
–
–
–
–
2.5
2.5
1.5
0.8
2
–
–
–
–
–
–
–
3
3
2
1
2
8
1
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
6
6
7
7
8
9
6
tCS
Input Setup time
7
tCH
Input Hold Time
8
tCKSP
tCKSR
tT
CKE Setup Time (Power down mode)
CKE Setup Time (Self Refresh Exit)
Transition time (rise and fall)
9
8
8
10
1
1
Common Parameters
11
12
13
14
15
16
tRCD
tRC
tRAS
tRP
tRRD
tCCD
RAS to CAS delay
15
70
42
15
14
1
–
120k
–
20
70
45
20
15
1
–
120k
–
20
70
45
20
20
1
–
120k
–
ns
ns
Cycle Time
Active Command Period
Precharge Time
ns
–
–
–
ns
Bank to Bank Delay Time
CAS to CAS delay time (same bank)
–
–
–
ns
–
–
–
CLK
Refresh Cycle
10
64
10
64
10
64
17
18
tSREX
tREF
Self Refresh Exit Time
–
–
–
–
–
–
ns
9
8
Refresh Period (8192 cycles)
ms
Read Cycle
19
20
21
22
tOH
tLZ
Data Out Hold Time
3
0
3
2
–
–
3
0
3
2
–
–
3
0
3
2
–
–
8
–
ns
ns
4
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
tHZ
7.5
–
7.5
–
ns
10
tDQZ
CLK
Write Cycle
23
24
25
tDPL
tDAL
Data input to Precharge (write recovery)
Data In to Active/refresh
1
5
0
–
–
–
1
5
0
–
–
–
1
5
0
–
–
–
CLK
CLK
CLK
11
tDQW
DQM Write Mask Latency
V436664Z24V Rev. 1.2 February 2002
8
V436664Z24V
Notes:
1. The specified values are valid when addresses are changed no more than once during t (min.) and when No
CK
Operation commands are registered on every rising clock edge during t (min). Values are shown per module
RC
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during t (min.).
RC
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have V = 0.4V and V = 2.4V with the timing referenced to the 1.4V crossover point. The transition
IL
IH
time is measured between V and V . All AC measurements assume t = 1 ns with the AC output load circuit
IH
IL
T
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
0.4V
50 Ohm
CLOCK
tCL
Z=50 Ohm
tT
I/O
tSETUP tHOLD
50 pF
1.4V
INPUT
tAC
tAC
I/O
tLZ
tOH
50 pF
Measurement conditions for
tac and toh
1.4V
OUTPUT
tHZ
5. If clock rising time is longer than 1 ns, a time (t /2 -0.5) ns has to be added to this parameter.
T
6. Rated at 1.5V
7. If t is longer than 1 ns, a time (t -1) ns has to be added to this parameter.
T
T
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to t is satisfied once the Self Refresh Exit command
RC
is registered.
10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
t
is equivalent to t
+ t
.
RP
DAL
DPL
V436664Z24V Rev. 1.2 February 2002
9
V436664Z24V
Package Diagram
144 Pin SODIMM
0.039
1.25
0.787
1
59
61
143
Pin 2 on Backside
3.3V
0140
0.143
Pin 144 on Backside
2.661
NOTE:
1. All dimensions in inches.
Tolerances ±0.005 unless otherwise specified.
V436664Z24V Rev. 1.2 February 2002
10
V436664Z24V
Module Label Information
Module Density
MO SEL VITELIC
CAS Latency
2=CL2
Part Number
V436664Z24VXXX-XX 512MB CLX
PC133U-XXX-542-A
XXXX-XXXXXXX
3=CL3
Criteria of PC100 or PC133
(refer to MVI datasheet)
Assembly in Taiwan
DIMM manufacture date code
PC133 U -XXX 54 2
A
UNBUFFERED DIMM
Gerber file Intel PC100 x8 Based
C = 3 or 2 (CLK)
L
JEDEC SPD Revision 2
= 5.4 ns
t
= 3 or 2 (CLK)
= 3 or 2 (CLK)
RCD
t
t
AC
RP
V436664Z24V Rev. 1.2 February 2002
11
V436664Z24V
WORLDWIDE OFFICES
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
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© Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
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personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC makes no commitment to update or keep cur-
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document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
V436664Z24V Rev. 1.2 February 2002
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