V437216S04VCTG-75 [MOSEL]
3.3 VOLT 16M x 72 HIGH PERFORMANCE PC133 UNBUFFERED ECC SDRAM MODULE; 3.3伏16M X 72高性能PC133非缓冲ECC SDRAM模块
| 型号： | V437216S04VCTG-75 |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | 3.3 VOLT 16M x 72 HIGH PERFORMANCE PC133 UNBUFFERED ECC SDRAM MODULE |
| 文件： | 总12页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
V437216S04V(C)TG-75
MOSEL VITELIC
3.3 VOLT 16M x 72 HIGH PERFORMANCE
PC133 UNBUFFERED ECC SDRAM
MODULE
Features
Description
The V437216S04V(C)TG-75 memory module is
organized 16,777,216 x 64 bits in a 168 pin dual in
line memory module (DIMM). The 16M x 72
memory module uses 18 Mosel-Vitelic 8M x 8
SDRAM. The x72 modules are ideal for use in high
performance computer systems where increased
memory density and fast access times are required.
■ 168 Pin Unbuffered 16,777,216 x 72 bit
Oganization SDRAM ECC DIMMs
■ Utilizes High Performance 8M x 8 SDRAM in
TSOPII-54 Packages
■ Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
■ Single +3.3V (± 0.3V) Power Supply
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are LVTTL Compatible
■ 4096 Refresh Cycles every 64 ms
■ Serial Present Detect (SPD)
■ SDRAM Performance
Component Used
-7
143
5.4
Units
MHz
ns
t
t
Clock Frequency (max.)
CK
Clock Access Time CAS
Latency = 3
AC
■ Supported Latencies at 133 MHz Operation
CL
t
t
t
RC
RCD
RP
3
3
3
8
CLK
V437216S04V(C)TG-75-01
V437216S04V(C)TG-75 Rev. 1.2 September 2000
1
MOSEL VITELIC
V437216S04V(C)TG-75
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CB0
CB1
VSS
NC
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
85
86
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
2
3
87
4
VSS
A0
88
5
89
6
A2
DU
90
A3
DU
7
A4
CKE1
VSS
91
A5
NC
8
A6
92
A7
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
9
A8
I/O22
I/O23
I/O24
VSS
93
A9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
94
BA0
A11
VCC
CLK1
NC
95
96
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
97
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4
98
99
VSS
CKE0
CS3
DQM6
DQM7
DU
100
101
102
103
104
105
106
107
108
109
110
111
112
CS2
DQM2
DQM3
DU
VCC
NC
VCC
NC
CB5
NC
CLK2
NC
VSS
NC
CB2
CB3
VSS
I/O17
I/O18
NC
CB6
CB7
VSS
I/O49
I/O50
NC
WP
NC
SA0
VCC
WE
SDA
SCL
VCC
CAS
SA1
SA2
DQM0
VCC
DQM4
VCC
Pin Names
VSS
Ground
SCL
SDA
Clock for Presence Detect
A0–A11
I/O1–I/O64
RAS
Address Inputs
Serial Data OUT for Presence
Detect
Data Inputs/Outputs
Row Address Strobe
Column Address Strobe
Read/Write Input
Bank Selects
SA0–A2
Serial Data IN for Presence
Detect
CAS
WE
CB0–CB7
NC
Check Bits (x72 Organization)
No Connection
BA0, BA1
CKE0, CKE1
CS0–CS3
CLK0–CLK3
DQM0–DQM7
VCC
Clock Enable
DU
Don’t Use
Chip Select
Clock Input
Data Mask
Power (+3.3 Volts)
V437216S04V(C)TG-75 Rev. 1.2 September 2000
2
MOSEL VITELIC
V437216S04V(C)TG-75
Part Number Information
V
4
3
72
16
S
0
4
V
C
T
G
-
75
MOSEL-VITELIC
MANUFACTURED
133 MHz
(PC133 3-3-3)
GOLD
SDRAM
TSOP
COMPONENT REVISION LEVEL
BLANK = B REV.
3.3V
C = C REV.
WIDTH
LVTTL
DEPTH
4 BANKS
168 PIN UNBUFFERED
DIMM X 8 COMPONENT
REFRESH
RATE 4K
V437216S04V(C)TG-75-02
Block Diagram
CS1
CS0
CS
CS
CS
CS
DQM0
I/O1–I/O8
DQM4
I/O33–I/O40
DQM
DQM
DQM
DQM
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
D0
D1
D8
D9
D4
D5
D12
D13
10Ω
10Ω
10Ω
10Ω
CS
CS
CS
CS
DQM1
I/O9–I/O16
DQM5
I/O41–I/O48
DQM
DQM
DQM
DQM
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
CS
CS
DQM
DQM
(BC7:0)
I/O1–I/O8
I/O1–I/O8
D16
D17
CS3
CS2
CS
CS
CS
CS
DQM2
I/O17–I/O24
DQM6
I/O49–I/O56
DQM
DQM
DQM
DQM
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
D2
D3
D10
D11
D6
D7
D14
D15
10Ω
10Ω
10Ω
10Ω
CS
CS
CS
CS
DQM3
I/O25–I/O32
DQM7
I/O57–I/O64
DQM
DQM
DQM
DQM
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
I/O1–I/O8
E2PROM SPD (256 WORD X 8 BIT)
A11-A0, BA0, BA1
VDD
D0-D15 (D16, D17)
D0-D15 (D16, D17)
SA0
SA1
SA2
SCL
SA0 SDA
SA1
SA2
C0-C31, (C32...C35)
D0-D15 (D16, D17)
SCL
WP
VSS
RAS, CAS, WE
CKE0
D0-D15 (D16, D17)
D0-D7 (D16)
47K
VCC
10K
CLOCK WIRING
16M X 72
D9-D15 (D17)
CKE1
CLK0
5 SDRAM
5 SDRAM
4 SDRAM +3.3pF
4 SDRAM +3.3pF
CLK1
CLK2
CLK3
V437216S04V(C)TG-75-03
V437216S04V(C)TG-75 Rev. 1.2 September 2000
3
MOSEL VITELIC
V437216S04V(C)TG-75
Serial Presence Detect Information
2
A serial presence detect storage device -
written into the E PROM device during module pro-
2
2
E PROM - is assembled onto the module. Informa-
duction using a serial presence detect protocol (I C
tion about the module configuration, speed, etc. is
synchronous 2-wire bus)
SPD-Table for PC133 modules:
Hex Value
Byte Number Function Described
SPD Entry Value
16Mx72
80
0
1
Number of SPD bytes
128
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x8 SDRAM)
Number of DIMM Banks
12
0C
0A
02
4
10
5
2
6
Module Data Width
72
48
7
Module Data Width (continued)
Module Interface Levels
0
LVTTL
00
8
01
9
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
7.5 ns
75
10
11
12
13
14
15
5.4 ns
54
ECC
02
Self-Refresh, 15.6µs
x8
80
SDRAM width, Primary
08
Error Checking SDRAM Data Width
n/a / x8
08
Minimum Clock Delay from Back to Back Random
Column Address
t
= 1 CLK
01
ccd
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Burst Length Supported
1, 2, 4, 8 & full Page
4
8F
04
04
01
01
00
0E
00
00
00
00
14
0F
14
2D
Number of SDRAM Banks
Supported CAS Latencies
CL = 3
CS Latencies
CS Latency = 0
WL = 0
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency = 2
Maximum Data Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at CL = 1
Minimum Row Precharge Time
Non Buffered/Non Reg.
Vcc tol ± 10%
Not Supported
Not Supported
Not Supported
Not Supported
20 ns
Minimum Row Active to Row Active Delay t
15 ns
RRD
Minimum RAS to CAS Delay t
20 ns
RCD
Minimum RAS Pulse Width t
45 ns
RAS
V437216S04V(C)TG-75 Rev. 1.2 September 2000
4
MOSEL VITELIC
V437216S04V(C)TG-75
SPD-Table for PC133 modules: (Continued)
Hex Value
Byte Number Function Described
SPD Entry Value
16Mx72
20
31
32
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
128 MByte
1.5 ns
15
33
0.8 ns
08
34
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
1.5 ns
15
35
0.8 ns
08
62-61
62
00
Revision 2
02
63
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
B1
64
Mosel Vitelic
40
65-71
72
00
73-90
91-92
93
Module Part Number (ASCII)
PCB Identification Code
V437216S04V(C)TG-75
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
94
95-98
99-125
126
127
128+
Reserved
00
64
00
00
Intel Specification for Frequency
Reserved
Unused Storage Location
DC Characteristics
T = 0°C to 70°C; V = 0 V; V , V = 3.3V ± 0.3V
A
SS
DD
DDQ
Limit Values
Min.
Symbol Parameter
Max.
Unit
V
V
V
V
Input High Voltage
Input Low Voltage
Output High Voltage (I
2.0
–0.5
2.4
V
+0.3
V
V
IH
CC
0.8
IL
= –2.0 mA)
= 2.0 mA)
—
0.4
40
V
OH
OL
OUT
OUT
Output Low Voltage (I
—
V
I
Input Leakage Current, any input
–40
µA
I(L)
(0 V < V < 3.6 V, all other inputs = 0V)
IN
I
Output leakage current
–40
40
µA
O(L)
(DQ is disabled, 0V < V
< V
)
OUT
CC
V437216S04V(C)TG-75 Rev. 1.2 September 2000
5
MOSEL VITELIC
V437216S04V(C)TG-75
Capacitance
T = 0°C to 70°C; V = 3.3V ± 0.3V, f = 1 MHz
A
DD
Limit Values
Symbol
Parameter
Max. 16M x 72
Unit
pF
pF
pF
pF
pF
pF
pF
pF
C
Input Capacitance (A0 to A11, RAS, CAS, WE)
Input Capacitance (CS0-CS3)
30
20
30
20
15
20
8
I1
I2
C
C
Input Capacitance (CLK0-CLK3)
Input Capacitance (CKE0, CKE1)
Input Capacitance (DQM0-DQM7)
Input/Output Capacitance (I/O1-I/064)
Input Capacitance (SCL, SA0-2)
Input/Output Capacitance (SA0-SA2)
ICL
C
I3
I4
C
C
IO
SC
SD
C
C
10
Operating Currents
T = 0°C to 70°C, V = 3.3V ± 0.3V (Recommended operating conditions otherwise noted)
A
CC
Max.
-75
Symbol Parameter & Test Condition
Unit
Note
ICC1
Operating Current
= t , t = t .
CKMIN
1 bank operation
1400
mA
7
t
RC
RCMIN. RC
Active-precharge command cycling,
without Burst Operation
ICC2P
Precharge Standby Current in Power Down Mode
t
= min.
20
mA
7
7
CK
CS =V , CKE≤ V
IH
IL(max)
ICC2PS
ICC2N
t
t
= Infinity
= min.
20
mA
mA
CK
Precharge Standby Current in Non-Power Down Mode
CS =V , CKE≥ V
400
CK
IH
IL(max)
ICC2NS
ICC3
t
= Infinity
120
540
mA
mA
CK
No Operating Current
= min, CS = V
CKE ≥ V
IH(MIN.)
t
CK
IH(min)
bank ; active state ( 4 banks)
ICC3P
ICC4
CKE ≥ V
64
mA
mA
IL(MAX.)
(Power down mode)
Burst Operating Current
1400
7,8
7
t
= min
CK
Read/Write command cycling
ICC5
ICC6
Auto Refresh Current
2000
mA
t
= min
CK
Auto Refresh command cycling
Self Refresh Current
Self Refresh Mode, CKE=0.2V
18
mA
mA
L-version
7.2
Notes:
1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t and
CK
t
. Input signals are changed one time during t
.
RC
CK
2. These parameter depend on output loading. Specified values are obtained with output open.
V437216S04V(C)TG-75 Rev. 1.2 September 2000
6
MOSEL VITELIC
V437216S04V(C)TG-75
AC Characteristics
T = 0° to 70°C; V = 0V; V = 3.3V ± 0.3V, t = 1 ns
A
SS
CC
T
Limit Values
-75
#
Symbol
Parameter
Min.
Max.
Unit
Note
Clock and Clock Enable
1
2
3
t
t
t
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
s
CK
CK
AC
CH
7.5
10
–
–
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
100
MHz
MHz
Access Time from Clock
CAS Latency = 3
2, 4
–
_
5.4
6
ns
ns
CAS Latency = 2
4
5
6
t
Clock High Pulse Width
Clock Low Pulse Width
Transition Tim
2.5
2.5
0.3
–
–
ns
ns
ns
t
CL
t
1.2
T
Setup and Hold Times
7
8
t
Input Setup Time
Input Hold Time
1.5
0.8
1.5
0.8
15
0
–
–
ns
ns
ns
ns
ns
ns
5
5
5
5
IS
t
IH
9
t
Input Setup Time
CKE Hold Time
–
CKS
CKH
RSC
10
11
12
t
t
–
Mode Register Set-up Time
–
t
Power Down Mode Entry Time
7.5
SB
Common Parameters
13
14
15
16
17
18
t
Row to Column Delay Time
Row Precharge Time
20
20
45
60
15
1
–
ns
ns
6
6
6
6
6
RCD
t
–
RP
RAS
t
Row Active Time
100K
ns
t
Row Cycle Time
–
–
–
ns
RC
t
t
Activate(a) to Activate(b) Command Period
CAS(a) to CAS(b) Command Period
ns
RRD
CCD
CLK
Refresh Cycle
19
20
t
Refresh Period (4096 cycles)
Self Refresh Exit Time
—
64
ms
ns
REF
t
10
SREX
V437216S04V(C)TG-75 Rev. 1.2 September 2000
7
MOSEL VITELIC
V437216S04V(C)TG-75
AC Characteristics
T = 0° to 70°C; V = 0V; V = 3.3V ± 0.3V, t = 1 ns (Continued)
A
SS
CC
T
Limit Values
-75
#
Symbol
Parameter
Min.
Max.
Unit
Note
Read Cycle
21
t
Data Out Hold Time
2.7
1
–
–
ns
ns
2
7
OH
22
t
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
LZ
23
t
–
5.4
2
ns
HZ
24
t
–
CLK
DQZ
Write Cycle
25
26
t
Write Recovery Time
1
0
–
–
CLK
CLK
WR
t
DQM Write Mask Latency
DQW
V437216S04V(C)TG-75 Rev. 1.2 September 2000
8
MOSEL VITELIC
V437216S04V(C)TG-75
Notes:
1. The specified values are valid when addresses are changed no more than once during t (min.) and when No
CK
Operation commands are registered on every rising clock edge during t (min). Values are shown per module bank.
RC
2. The specified values are valid when data inputs (DQ’s) are stable during t (min.).
RC
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have V = 0.4V and V = 2.4V with the timing referenced to the 1.4V crossover point. The transition
IL
IH
time is measured between V and V . All AC measurements assume t = 1 ns with the AC output load circuit
IH
IL
T
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
0.4V
50 Ohm
CLOCK
INPUT
tCL
Z=50 Ohm
t
T
I/O
tSETUP tHOLD
50 pF
1.4V
tAC
tAC
I/O
tLZ
tOH
50 pF
Measurement conditions for
tac and toh
1.4V
OUTPUT
tHZ
5. If clock rising time is longer than 1 ns, a time (t /2 -0.5) ns has to be added to this parameter.
T
6. Rated at 1.5V
7. If t is longer than 1 ns, a time (t -1) ns has to be added to this parameter.
T
T
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self
Refresh Exit is not complete until a time period equal to t is satisfied once the Self Refresh Exit command is reg-
RC
istered.
10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
t
is equivalent to t
+ t
.
DAL
DPL
RP
V437216S04V(C)TG-75 Rev. 1.2 September 2000
9
MOSEL VITELIC
V437216S04V(C)TG-75
Package Diagram
SDRAM DIMM Module Package
All measurements in mm
133.35
127.35
(4.0 max)
1
10
11
40
41
84
42.18
1.27 ± 0.100
66.68
A
B
C
85
94
95
124
125
168
D
6.35
6.35
1.27
1.0 + 0.5
0.2 ± 0.15
2.0
2.0
Detail A
Detail B
Detail C
2.26
V437216S04V(C)TG-75-04
RADIUS
1.27 + 0.10
Tolerances: ± (0.13) unless otherwise specified.
V437216S04V(C)TG-75 Rev. 1.2 September 2000
10
MOSEL VITELIC
V437216S04V(C)TG-75
Label Information
MOSEL VITELIC
Part Number
V437216S04VCTG-75
PC133U-333-542-A
Taiwan XXXX-XXXXXXX
Criteria of PC100 or PC133
(refer to MVI datasheet)
DIMM manufacture date code
Trace Code
PC133U - 333 - 54 2 - A
UNBUFFERED DIMM
Gerber file Intel® PC100 x 8 Based
C
= 3 (CLK)
= 3 (CLK)
= 3 (CLK)
L
JEDEC SPD Revision 2.0
= 5.4 ns
t
RCD
t
RP
t
AC
V437216S04V(C)TG-75-05
V437216S04V(C)TG-75 Rev. 1.2 September 2000
11
MOSEL VITELIC WORLDWIDE OFFICES
V437216S04V(C)TG-75
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 01698-748515
FAX: 01698-748516
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2666-3307
FAX: 852-2770-8011
NO 19 LI HSIN ROAD
JAPAN
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-579-5888
FAX: 886-3-566-5888
WBG MARIVE WEST 25F
6, NAKASE 2-CHOME
MIHAMA-KU, CHIBA-SHI
CHIBA 261-7125
GERMANY
(CONTINENTAL
EUROPE & ISRAEL)
71083 HERRENBERG
BENZSTR. 32
PHONE: 81-43-299-6000
FAX: 81-43-299-6555
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
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FAX: 949-361-7807
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
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RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
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