V43728S04VCTG-10PC [MOSEL]
3.3 VOLT 8M x 72 HIGH PERFORMANCE PC100 UNBUFFERED ECC SDRAM MODULE; 3.3伏8M X 72高性能PC100非缓冲ECC SDRAM模块
| 型号： | V43728S04VCTG-10PC |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | 3.3 VOLT 8M x 72 HIGH PERFORMANCE PC100 UNBUFFERED ECC SDRAM MODULE |
| 文件： | 总11页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
V43728S04V(C)TG-10PC
MOSEL VITELIC
3.3 VOLT 8M x 72 HIGH PERFORMANCE
PC100 UNBUFFERED ECC SDRAM
MODULE
Features
Description
The V43728S04V(C)TG-10PC memory module
is organized 8,388,608 x 72 bits in a 168 pin dual in
line memory module (DIMM). The 8M x 72 memory
module uses 9 Mosel-Vitelic 8M x 8 SDRAM. The
x72 modules are ideal for use in high performance
computer systems where increased memory den-
sity and fast access times are required.
■ 168 Pin Unbuffered 8,388,608 x 72 bit
Oganization SDRAM ECC DIMMs
■ Utilizes High Performance 8M x 8 SDRAM in
TSOPII-54 Packages
■ Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
■ Single +3.3V (± 0.3V) Power Supply
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are LVTTL Compatible
■ 4096 Refresh Cycles every 64 ms
■ Serial Present Detect (SPD)
■ SDRAM Performance
Key Component Timing Parameters
-8PC
125
6
Units
MHz
ns
t
t
Clock Frequency (max.)
CK
Clock Access Time CAS
Latency = 3
AC
t
Latency = 2
6
ns
AC
■ Module Frequency vs AC Parameter
CL
Frequency
(CAS Latency)
t
t
t
Unit
CLK
CLK
RCD
RP
RC
V43728S04V(C)TG-10PC
100 MHz (PC)
3
2
2
2
7
2
2
7
V43728S04V(C)TG-10PC -01
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
1
MOSEL VITELIC
V43728S04V(C)TG-10PC
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
VSS
I/O1
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
85
86
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
2
3
I/O2
87
4
I/O3
VSS
A0
88
5
I/O4
89
6
VCC
I/O5
A2
DU
90
A3
DU
7
A4
CKE1
VSS
91
A5
NC
8
I/O6
A6
92
A7
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
9
I/O7
A8
I/O22
I/O23
I/O24
VSS
93
A9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
94
BA0
A11
VCC
CLK1
NC
I/O9
95
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO
CB1
VSS
NC
96
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
97
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4
98
99
VSS
CKE0
CS3
DQM6
DQM7
DU
100
101
102
103
104
105
106
107
108
109
110
111
112
CS2
DQM2
DQM3
DU
VCC
NC
VCC
NC
CB5
NC
CLK2
NC
VSS
NC
CB2
CB3
VSS
I/O17
I/O18
NC
CB6
CB7
VSS
I/O49
I/O50
NC
WP
NC
SA0
VCC
WE
SDA
SCL
VCC
CAS
SA1
SA2
DQM0
VCC
DQM4
VCC
Pin Names
A0–A11
I/O1–I/O64
RAS
Address Inputs
Data Inputs/Outputs
Row Address Strobe
Column Address Strobe
Read/Write Input
Bank Selects
CAS
WE
BA0, BA1
CKE0, CKE1
CS0–CS3
CLK0–CLK3
DQM0–DQM7
VCC
Clock Enable
Chip Select
Clock Input
Data Mask
Power (+3.3 Volts)
Ground
VSS
SCL
Clock for Presence Detect
SDA
Serial Data OUT for Presence
Detect
SA0–A2
Serial Data IN for Presence
Detect
CB0–CB7
NC
Check Bits (x72 Organization)
No Connection
DU
Don’t Use
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
2
MOSEL VITELIC
V43728S04V(C)TG-10PC
Part Number Information
V
4
3
72
8
S
0
4
V
C
T
G
-
10PC
MOSEL-VITELIC
MANUFACTURED
-10PC PC100 2-2-2
GOLD
SDRAM
TSOP
COMPONENT REVISION LEVEL
BLANK = B REV.
3.3V
C = C REV.
WIDTH
LVTTL
DEPTH
4 BANKS
168 PIN UNBUFFERED
DIMM X 8 COMPONENT
REFRESH
RATE 4K
V43728S04V(C)TG-10PC-02
Block Diagram
WE
CS0
CS
CS
D4
WE
WE
DQM0
I/O1–I/O8
DQM4
I/O40–I/O33
DQM
DQM
I/O1–I/O8
I/O1–I/O8
D0
10
10
10
10
10
CS
D1
CS
D5
WE
WE
DQM1
I/O9–I/O16
DQM5
I/O48–I/O41
DQM
DQM
I/O1–I/O8
I/O1–I/O8
CS
WE
DQM
BC0–7
CS2
I/O1–I/O8
CS
D2
CS
D6
WE
WE
DQM2
I/O17–I/O24
DQM6
I/O49–I/O56
DQM
DQM
I/O1–I/O8
I/O1–I/O8
10
10
10
10
WE
CS
D3
WE
CS
D7
DQM3
I/O25–I/O32
DQM7
I/O57–I/O64
DQM
DQM
I/O1–I/O8
I/O1–I/O8
E2PROM SPD (256 WORD X 8 BITS)
CKE0
CKE: SDRAM D0-D7
SCL0
SA2
SA1
SA0
SDA
RAS
CAS
WE
RAS: SDRAM D0-D7
CAS: SDRAM D0-D7
WE: SDRAM D0-D7
WP
47K
A(11:0)
A(11:0): SDRAM D0-D7
BA0, BA1: SDRAM D0-D7
BA0, BA1
CLOCK WIRING
D0-D7
VCC
VSS
C0-C17
CLOCK INPUT
LOAD
5 SDRAM
Termination
D0-D7
CLK0
CLK1
CLK2
CLK3
4 SDRAMS +3.3pF Cap
Termination
V43728S04V(C)TG-10PC -03
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
3
MOSEL VITELIC
V43728S04V(C)TG-10PC
Serial Presence Detect Information
2
A serial presence detect storage device -
written into the E PROM device during module pro-
2
2
E PROM - is assembled onto the module. Informa-
duction using a serial presence detect protocol (I C
tion about the module configuration, speed, etc. is
synchronous 2-wire bus)
SPD-Table:
Hex Value
100 MHz
Byte
Number Function Described
SPD Entry Value
-10PC
0
1
Number of SPD bytes
128
80
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x8 SDRAM)
Number of DIMM Banks
12
0C
09
4
9
5
1
01
6
Module Data Width
72
48
7
Module Data Width (continued)
Module Interface Levels
0
LVTTL
00
8
01
9
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
10.0 ns
A0
60
10
11
12
13
14
15
6.0 ns
Ecc
02
Self-Refresh, 15.6µs
x8
80
SDRAM width, Primary
08
Error Checking SDRAM Data Width
n/a / x8
08
Minimum Clock Delay from Back to Back Random
Column Address
t
= 1 CLK
01
ccd
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Burst Length Supported
1, 2, 4, 8 & full Page
4
8F
04
06
01
01
00
0E
A0
60
00
00
14
10
14
Number of SDRAM Banks
Supported CAS Latencies
CL = 2 & 3
CS Latency = 0
WL = 0
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency = 2
Maximum Data Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at CL = 1
Minimum Row Precharge Time
Non Buffered/Non Reg.
Vcc tol ± 10%
10.0 ns
6.0 ns
Not Supported
Not Supported
20 ns
Minimum Row Active to Row Active Delay t
16 ns
RRD
Minimum RAS to CAS Delay t
20 ns
RCD
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
4
MOSEL VITELIC
V43728S04V(C)TG-10PC
SPD-Table: (Continued)
Hex Value
100 MHz
-10PC
2D
10
Byte
Number Function Described
SPD Entry Value
30
31
Minimum RAS Pulse Width t
45 ns
64 MByte
2 ns
RAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
32
20
33
SDRAM Input Hold Time
1 ns
10
34
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
2 ns
20
35
1 ns
10
62-61
62
00
Revision 1.2
100 MHz
12
63
Checksum for Bytes 0 - 62
FD
XX
64-125
Manufacturers’s Information (Optional)
(FFh if not used)
126
127
Max. Frequency Specification
100 MHz Support Details
Unused Storage Location
64
AF
00
128+
DC Characteristics
T = 0°C to 70°C; V = 0 V; V , V = 3.3V ± 0.3V
A
SS
DD
DDQ
Limit Values
Symbol Parameter
Min.
2.0
Max.
Unit
V
V
V
V
V
Input High Voltage
Input Low Voltage
Output High Voltage (I
V
+0.3
IH
CC
–0.5
2.4
0.8
V
IL
= –2.0 mA)
= 2.0 mA)
—
0.4
40
V
OH
OL
OUT
OUT
Output Low Voltage (I
—
V
I
Input Leakage Current, any input
–40
µA
I(L)
(0 V < V < 3.6 V, all other inputs = 0V)
IN
I
Output leakage current
–40
40
µA
O(L)
(DQ is disabled, 0V < V
< V
)
OUT
CC
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
5
MOSEL VITELIC
V43728S04V(C)TG-10PC
Capacitance
T = 0°C to 70°C; V = 3.3V ± 0.3V, f = 1 MHz
A
DD
Limit Values
Symbol
Parameter
Max. 8M x 72
Unit
pF
pF
pF
pF
pF
pF
pF
pF
C
Input Capacitance (A0 to A11, RAS, CAS, WE)
Input Capacitance (CS0-CS3)
55
25
38
38
13
12
8
I1
I2
C
C
Input Capacitance (CLK0-CLK3)
Input Capacitance (CKE0, CKE1)
Input Capacitance (DQM0-DQM7)
Input/Output Capacitance (I/O1-I/064)
Input Capacitance (SCL, SA0-2)
Input/Output Capacitance (SA0-SA2)
ICL
C
I3
I4
C
C
IO
SC
SD
C
C
10
Standby and Refresh Currents1
T = 0°C to 70°C, V = 3.3V ± 0.3V
A
CC
Symbol Parameter
Test Conditions
Max. x72
Unit
Note
I
1
Operating Current
Burst length = 4, CL = 3
900
mA
1,2
CC
t
t
> = t (min),
RC
RC
CK
> = t (min), IO = 0 mA
CK
I
I
I
2P
Precharged Standby Current in Power
Down Mode
CKE< = V (max), t > = t (min)
27
18
mA
mA
mA
CC
CC
CC
IL
CK
CK
2PS
2N
CKE< = V (max), t = Infinite
IL CK
Precharged Standby Current in
Non-Power Down Mode
CKE> = V (min), t > = t (min),
180
CS =
High
IH
CK
CK
Input changed once in 3 cycles
I
2NS
CKE> = V (min), t = Infinite,
90
mA
CC
IH
CK
No Input change
I
I
I
3P
Active Standby Current in Power
Down Mode
CKE< = V (max), t > = t (min)
27
18
mA
mA
mA
CC
CC
CC
IL
CK
CK
3PS
3N
CKE< = V (max), t = Infinite
IL CK
Active Standby Current in Non-Power
Down Mode
CKE> = V (min), t > = t (min),
225
CS =
High
IH
CK
CK
Input changed one time
I
3NS
4
CKE> = V (min), t = Infinite,
135
855
mA
mA
CC
IH
CK
No Input change
I
Burst Operating Current
Burst length = Full Page,
1, 2
CC
t
t
= Infinite, CL = 3,
RC
CK
> = t (min), IO = 0 mA
CK
I
I
5
6
Auto Refresh Current
Self Refresh Current
t
>= t (min)
810
9
mA
mA
1,2
1,2
CC
RC
RC
CKE = <0,2 V
CC
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
6
MOSEL VITELIC
V43728S04V(C)TG-10PC
AC Characteristics 3,4
T = 0° to 70°C; V = 0V; V = 3.3V ± 0.3V, t = 1 ns
A
SS
CC
T
Limit Values
-10PC
#
Symbol Parameter
Min.
Max.
Unit
Note
Clock and Clock Enable
1
2
3
t
f
t
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
CK
CK
AC
CH
10
10
ns
ns
System frequency
CAS Latency = 3
CAS Latency = 2
–
–
100
100
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
4,5
–
–
6
6
ns
ns
4
5
t
Clock High Pulse Width
Clock Low Pulse Width
3
3
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
6
6
7
7
8
9
t
CL
CS
CH
6
t
Input Setup time
2
7
t
Input Hold Time
1
8
t
CKE Setup Time (Power down mode)
CKE Setup Time (Self Refresh Exit)
Transition time (rise and fall)
2.5
8
CKSP
CKSR
9
t
10
t
1
T
Common Parameters
11
12
13
14
15
16
t
RAS to CAS delay
20
70
45
20
16
1
–
120k
–
ns
ns
2 CLK
7 CLK
5 CLK
2 CLK
2 CLK
RCD
t
Cycle Time
RC
t
Active Command Period
Precharge Time
ns
RAS
t
–
ns
RP
t
t
Bank to Bank Delay Time
CAS to CAS delay time (same bank)
–
ns
RRD
CCD
–
CLK
Refresh Cycle
10
64
17
18
t
Self Refresh Exit Time
–
–
ns
9
8
SREX
t
Refresh Period (4096 cycles)
ms
REF
Read Cycle
19
20
21
22
t
Data Out Hold Time
3
0
3
2
–
–
9
–
ns
ns
4
OH
t
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
LZ
t
ns
10
HZ
t
CLK
DQZ
Write Cycle
23
24
25
t
Data input to Precharge (write recovery)
Data In to Active/refresh
2
5
0
–
–
–
CLK
CLK
CLK
DPL
DAL
t
11
t
DQM Write Mask Latency
DQW
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
7
MOSEL VITELIC
V43728S04V(C)TG-10PC
Notes:
1. The specified values are valid when addresses are changed no more than once during t (min.) and when No
CK
Operation commands are registered on every rising clock edge during t (min). Values are shown per module
RC
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during t (min.).
RC
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have V = 0.4V and V = 2.4V with the timing referenced to the 1.4V crossover point. The transition
IL
IH
time is measured between V and V . All AC measurements assume t = 1 ns with the AC output load circuit
IH
IL
T
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
0.4V
50 Ohm
CLOCK
INPUT
tCL
Z=50 Ohm
t
T
I/O
tSETUP tHOLD
50 pF
1.4V
tAC
tAC
I/O
tLZ
tOH
50 pF
Measurement conditions for
tac and toh
1.4V
OUTPUT
tHZ
5. If clock rising time is longer than 1 ns, a time (t /2 -0.5) ns has to be added to this parameter.
T
6. Rated at 1.5V
7. If t is longer than 1 ns, a time (t -1) ns has to be added to this parameter.
T
T
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to t is satisfied once the Self Refresh Exit command
RC
is registered.
10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
t
is equivalent to t
+ t
.
DAL
DPL
RP
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
8
MOSEL VITELIC
V43728S04V(C)TG-10PC
Package Diagram
L-DIM-168-30
SDRAM DIMM Module Package
All measurements in mm.
133.35
127.35
(2.54 max)
1
10
11
40
41
84
42.18
1.27 ± 0.100
66.68
A
B
C
85
94
95
124
125
168
D
6.35
6.35
1.27
1.0 ± 0.05
0.2 ± 0.15
2.0
2.0
Detail A
Detail B
Detail C
2.26
V43728S04V(C)TG-10PC -04
RADIUS
1.27 + 0.10
Tolerances: ± (0.13) unless otherwise specified.
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
9
MOSEL VITELIC
V43728S04V(C)TG-10PC
Label Information
MOSEL VITELIC
Part Number
V43728S04VCTG-10PC
PC100U-222-612-A
Taiwan XXXX-XXXXXXX
Criteria of PC100 or PC133
(refer to MVI datasheet)
DIMM manufacture date code
Trace Code
PC100U - 222 - 6 12 - A
UNBUFFERED DIMM
Gerber file Intel® PC100 x 8 Based
C
= 2 (CLK)
= 2 (CLK)
= 2 (CLK)
L
Intel SPD Revision 1.2
= 6 ns
t
RCD
t
RP
t
AC
V43728S04V(C)TG-10PC-05
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
10
MOSEL VITELIC WORLDWIDE OFFICES
V43728S04V(C)TG-10PC
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 01698-748515
FAX: 01698-748516
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
HONG KONG
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