V437216C04VDTG-75 [MOSEL]
3.3 VOLT 16M x 72 HIGH PERFORMANCE PC133 REGISTER PLL ECC SDRAM MODULE; 3.3伏16M X 72高性能PC133注册PLL ECC SDRAM模块
| 型号： | V437216C04VDTG-75 |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | 3.3 VOLT 16M x 72 HIGH PERFORMANCE PC133 REGISTER PLL ECC SDRAM MODULE |
| 文件： | 总12页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
V437216C04VDTG-75
MOSEL VITELIC
3.3 VOLT 16M x 72 HIGH PERFORMANCE
PC133 REGISTER PLL ECC SDRAM
MODULE
Features
Description
The V437216C04VDTG-75 memory module is
organized 16,777,216 x 72 bits in a 168 pin dual in
line memory module (DIMMꢀ. The 16M x 72
registered DIMM uses 18 Mosel-Vitelic 16M x 4
ECC SDRAM. The x72 registered modules are ideal
for use in high performance computer systems
ꢁhere increased memory density and fast access
times are required.
ꢀ 168 Pin Registered ECC 16,777,216 x 72 bit
Oganization SDRAM Modules
ꢀ Utilizes High Performance 16M x 4 SDRAM in
TSOPII-54 Packages
ꢀ Fully PC Board Layout Compatible to INTEL’S
Rev 1.2 Module Specification
ꢀ Single +3.3V ( 0.3Vꢀ Poꢁer Supply
ꢀ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleaveꢀ
ꢀ Auto Refresh (CBRꢀ and Self Refresh
ꢀ All Inputs, Outputs are LVTTL Compatible
ꢀ 4096 Refresh Cycles every 64 ms
ꢀ Serial Present Detect (SPDꢀ
ꢀ SDRAM Performance
Key Component Timing Parameters
-7
143
5.4
Units
MHz
ns
t
t
Clock Frequency (max.ꢀ
CK
Clock Access Time CAS
Latency = 3
AC
ꢀ Module Frequency vs AC Parameter
CL
Frequency
(CAS Latency)
t
t
t
Unit
RCD
RP
RC
V437216C04VDTG-75
133 MHz (PCꢀ
3
3
3
8
CLK
V437216C04VDTG-75 Rev. 1.2 July 2001
1
MOSEL VITELIC
V437216C04VDTG-75
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(APꢀ
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2
CB3
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1*
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2*
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1*
A12
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6
CB7
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
REGE
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3*
NC
SA0
SA1
SA2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO
CB1
VSS
NC
CB5
VSS
NC
NC
VCC
CAS
DQM4
NC
VCC
WE
DQM0
VCC
Notes:
*
These pins are not used in this module.
Pin Names
A0–A11
I/O1–I/O64
RAS
Address Inputs
SDA
Serial Data OUT for Presence
Detect
Data Inputs/Outputs
Roꢁ Address Strobe
Column Address Strobe
Read/Write Input
Bank Selects
SA0–A2
Serial Data IN for Presence
Detect
CAS
CB0–CB4
NC
Check Bits (x72 Organizationꢀ
No Connection
WE
BA0, BA1
CKE0
REGE
DU
Register Enable
Clock Enable
Don’t Use
CS0, CS2
CLK0–CLK3
DQM0–DQM7
VCC
Chip Select
Clock Input
Data Mask
Poꢁer (+3.3 Voltsꢀ
Ground
VSS
SCL
Clock for Presence Detect
V437216C04VDTG-75 Rev. 1.2 July 2001
2
MOSEL VITELIC
V437216C04VDTG-75
Module Part Number Information
V
4
3
72
16
C
0
4
V
D
T
G
-
75
MOSEL-VITELIC
MANUFACTURED
-75 PC133 3-3-3
SDRAM
GOLD
TSOP
D VERSION
3.3V
LVTTL
WIDTH
DEPTH
4 BANKS
168 PIN REGISTERED
DIMM X 4 COMPONENT
REFRESH
RATE 4K
Block Diagram
RCS0
CS
CS
RQM0
RQM4
DQM
DQM
I/O1–I/O4
I/O33–I/O36
I/O1–I/O4
I/O1–I/O4
D0
D9
D10
D11
D12
10Ω
10Ω
10Ω
10Ω
10Ω
CS
CS
DQM
DQM
I/O5–I/O8
I/O37–I/O40
I/O1–I/O4
I/O1–I/O4
D1
10Ω
CS
CS
RQM1
I/O9–I/O12
RQM5
I/O41–I/O44
DQM
DQM
I/O1–I/O4
I/O1–I/O4
D2
10Ω
CS
CS
DQM
DQM
I/O13–I/O16
I/O45–I/O48
I/O1–I/O4
I/O1–I/O4
RAS
CAS
R
E
G
I
S
T
E
R
RRAS
D0–D17
D0–D17
D0–D17
D3
10Ω
RCAS
RWE
CS
CS
WE
DQM
DQM
CB1–CB3
CB4–CB7
I/O1–I/O4
I/O1–I/O4
CKE0
R0CKE0, R1CKE0
RDQM0–RDQM7
RC0, RCS2
D4
D13
10Ω
10Ω
DQM0–DQM7
RCS2
CS
CS
CS0, CS
RQM2
RQM6
DQM
DQM
I/O17–I/O20
I/O49–I/O52
I/O1–I/O4
I/O1–I/O4
A0–A11
RA0–RA11
D0–D17
D5
D14
D15
D16
D17
10Ω
10Ω
10Ω
10Ω
10Ω
BA0, BA1
RBA0, RBA1 D0–D17
CS
CS
DQM
DQM
VDD
10K
I/O21–I/O24
I/O53–I/O56
I/O1–I/O4
I/O1–I/O4
D6
10Ω
REGE
CS
CS
RQM3
I/O25–I/O28
RQM7
I/O57–I/O60
DQM
DQM
PLL CLK
CLK0
10K
I/O1–I/O4
I/O1–I/O4
D7
10Ω
10K
CLK1–CLK3
CS
CS
D0–D17
PLL
DQM
DQM
12pF
I/O29–I/O32
I/O61–I/O64
I/O1–I/O4
I/O1–I/O4
12pF
D8
10Ω
V437216C04VDTG-75 Rev. 1.2 July 2001
3
MOSEL VITELIC
V437216C04VDTG-75
Serial Presence Detect Information
2
A serial presence detect storage device –
written into the E PROM device during module pro-
2
2
E PROM – is assembled onto the module. Informa-
duction using a serial presence detect protocol (I C
tion about the module configuration, speed, etc. is
synchronous 2-wire bus)
SPD-Table for 75 modules:
Hex Value
Byte Number Function Described
SPD Entry Value
16Mx72
80
0
1
Number of SPD bytes
128
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x4 SDRAM)
Number of DIMM Banks
12
0C
0A
01
4
10
5
1
6
Module Data Width
72
48
7
Module Data Width (continued)
Module Interface Levels
0
LVTTL
00
8
01
9
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
7.5 ns
75
10
11
12
13
14
15
5.4 ns
54
ECC
02
Self-Refresh, 15.8µs
x4
80
SDRAM width, Primary
04
Error Checking SDRAM Data Width
n/a / x4
04
Minimum Clock Delay from Back to Back Random
Column Address
t
= 1 CLK
01
ccd
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Burst Length Supported
1, 2, 4, 8, full page
4
8F
04
04
01
01
1F
0E
00
00
00
00
14
0F
14
2D
Number of SDRAM Banks
Supported CAS Latencies
CL = 3
CS Latencies
CS Latency = 0
WL = 0
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency = 2
Maximum Data Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at CL = 1
Minimum Row Precharge Time
Registered/Buffered
Vcc tol 10ꢀ
Not Supported
Not Supported
Not Supported
Not Supported
20 ns
Minimum Row Active to Row Active Delay t
15 ns
RRD
Minimum RAS to CAS Delay t
20 ns
RCD
Minimum RAS Pulse Width t
45 ns
RAS
V437216C04VDTG-75 Rev. 1.2 July 2001
4
MOSEL VITELIC
V437216C04VDTG-75
SPD-Table for 75 modules: (Continued)
Hex Value
Byte Number Function Described
SPD Entry Value
16Mx72
20
31
32
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
128 MByte
1.5 ns
15
33
0.8 ns
08
34
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
1.5 ns
15
35
0.8 ns
08
62-61
62
00
Revision 2
02
63
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
C6
40
64
Mosel Vitelic
65-71
72
00
73-90
91-92
93
Module Part Number (ASCII)
PCB Identification Code
V437216C04VDTG-75
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
94
95-98
99-125
126
127
128+
Reserved
00
64
8D
00
Intel Specification for Frequency
Reserved
Unused Storage Location
DC Characteristics
T = 0°C to 70°C; V = 0 V; V , V = 3.3V 0.3V
DDQ
A
SS
DD
Limit Values
Min.
Symbol Parameter
Max.
Unit
V
V
V
V
I
Input High Voltage
Input Low Voltage
Output High Voltage (I
2.0
–0.3
2.4
V
+0.3
CC
V
V
IH
0.8
IL
= –4.0 mA)
—
0.4
10
V
OH
OL
OUT
OUT
Output Low Voltage (I
= 4.0 mA)
—
V
Input Leakage Current, any input
–10
µA
I(L)
(0 V < V < 3.6 V, all other inputs = 0V)
IN
I
Output leakage current
–10
10
µA
O(L)
(DQ is disabled, 0V < V
< V
)
CC
OUT
V437216C04VDTG-75 Rev. 1.2 July 2001
5
MOSEL VITELIC
V437216C04VDTG-75
Capacitance
T = 0°C to 70°C; V = 3.3V 0.3V, f = 1 MHz
A
DD
Symbol
Parameter
Limit Values
Unit
pF
pF
pF
pF
pF
pF
pF
pF
C
C
Input Capacitance (A0 to A11, RAS, CAS, WE)
Input Capacitance (CS0-CS3)
Input Capacitance (CLK0)
Input Capacitance (CKE0)
Input Capacitance (DQM0-DQM7)
Input/Output Capacitance (I/O1-I/064)
Input Capacitance (SCL, SA0-2)
Input/Output Capacitance
15
15
20
15
15
16
8
I1
I2
C
ICL
C
I3
I4
C
C
IO
SC
SD
C
C
18
Absolute Maximum Ratings
Parameter
Max.
Units
V
Voltage on VDD Supply Relative to V
-1 to 4.6
-1 to 4.6
0 to +70
-55 to 125
9
SS
Voltage on Input Relative to V
Operating Temperature
Storage Temperature
Power Dissipation
V
SS
°C
°C
W
V437216C04VDTG-75 Rev. 1.2 July 2001
6
MOSEL VITELIC
V437216C04VDTG-75
Standby and Refresh Currents1
T = 0°C to 70°C, V = 3.3V 0.3V
A
CC
Symbol Parameter
Test Conditions
16M x 72
Unit
Note
I
1
Operating Current
Burst length = 4, CL = 3
2700
mA
1,2
CC
t
t
> = t (min),
RC
RC
> = t (min), IO = 0 mA
CK
CK
2 Bank Interleave Operation
I
I
I
I
2P
2N
3P
3N
Precharged Standby Current in Power CKE< = V (max), t > = t (min)
Down Mode
36
mA
mA
mA
mA
CC
CC
CC
CC
IL
CK
CK
Precharged Standby Current in
Non-Power Down Mode
CKE> = V (min), t > = t (min), Input
changed once in 3 cycles
810
144
990
CS =
High
IH
CK
CK
Active Standby Current in Power
Down Mode
CKE< = V (max), t > = t (min)
IL
CK
CK
Active Standby Current in Non-Power
Down Mode
CKE> = V (min), t > = t (min), Input
changed one time
CS =
High
IH
CK
CK
I
4
Burst Operating Current
t
t
= Infinite, CL = 3,
2160
mA
1, 2
CC
RC
> = t (min), IO = 0 mA
CK
CK
2 Banks Activated
I
I
5
6
Auto Refresh Current
Self Refresh Current
t
>= t (min)
2700
18
mA
mA
1,2
1,2
CC
CC
RC
RC
CKE = <0,2 V
Standard
L-version
7.2
V437216C04VDTG-75 Rev. 1.2 July 2001
7
MOSEL VITELIC
V437216C04VDTG-75
AC Characteristics 3,4
T = 0° to 70°C; V = 0V; V = 3.3V 0.3V, t = 1 ns
A
SS
CC
T
Limit Values
-75
#
Symbol Parameter
Min.
Max.
Unit
Note
Clock and Clock Enable
1
2
3
t
f
t
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
CK
CK
AC
CH
7.5
10
ns
ns
System frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
100
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
4,5
–
–
5.4
6
ns
ns
4
5
t
Clock High Pulse Width
Clock Low Pulse Width
2.5
2.5
1.5
0.8
2.5
8
–
–
ns
ns
ns
ns
ns
ns
ns
6
6
7
7
8
9
t
CL
CS
CH
6
t
Input Setup time
–
7
t
Input Hold Time
–
8
t
CKE Setup Time (Power down mode)
CKE Setup Time (Self Refresh Exit)
Transition time (rise and fall)
–
CKSP
CKSR
9
t
–
10
t
0.3
1.2
T
Common Parameters
11
12
13
14
15
16
t
RAS to CAS delay
20
60
45
20
15
1
–
ns
ns
6
6
6
6
6
RCD
t
Cycle Time
–
RC
t
Active Command Period
Precharge Time
100K
ns
RAS
t
–
–
–
ns
RP
t
t
Bank to Bank Delay Time
CAS to CAS delay time (same bank)
ns
RRD
CCD
CLK
Refresh Cycle
10
64
17
18
t
Self Refresh Exit Time
–
–
ns
SREX
t
Refresh Period (8192 cycles)
ms
REF
Read Cycle
19
20
21
22
t
Data Out Hold Time
3
1
3
–
–
–
7
2
ns
ns
2
7
OH
t
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
LZ
t
ns
HZ
t
CLK
DQZ
Write Cycle
23
24
t
Data input to Precharge (write recovery)
DQM Write Mask Latency
2
0
–
–
CLK
CLK
DPL
t
DQW
V437216C04VDTG-75 Rev. 1.2 July 2001
8
MOSEL VITELIC
V437216C04VDTG-75
Notes:
1. The specified values are valid when addresses are changed no more than once during t (min.) and when No
CK
Operation commands are registered on every rising clock edge during t (min). Values are shown per module
RC
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during t (min.).
RC
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have V = 0.4V and V = 2.4V with the timing referenced to the 1.4V crossover point. The transition
IL
IH
time is measured between V and V . All AC measurements assume t = 1 ns with the AC output load circuit
IH
IL
T
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
0.4V
50 Ohm
CLOCK
INPUT
tCL
Z=50 Ohm
t
T
I/O
tSETUP tHOLD
50 pF
1.4V
tAC
tAC
I/O
tLZ
tOH
50 pF
Measurement conditions for
tac and toh
1.4V
OUTPUT
tHZ
5. If clock rising time is longer than 1 ns, a time (t /2 -0.5) ns has to be added to this parameter.
T
6. Rated at 1.5V
7. If t is longer than 1 ns, a time (t -1) ns has to be added to this parameter.
T
T
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to t is satisfied once the Self Refresh Exit command
RC
is registered.
10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
t
is equivalent to t
+ t
.
DAL
DPL
RP
V437216C04VDTG-75 Rev. 1.2 July 2001
9
MOSEL VITELIC
V437216C04VDTG-75
Package Diagram
L-DIM-168-30
SDRAM DIMM Module Package
All measurements in mm
133.37
127.35
(4.0 max)
1
10
11
40
41
84
42.18
1.27 0.100
63.68
A
B
85
94
95
124
125
168
D
6.35
6.35
1.27
1.0 0.05
0.2 0.15
2.0
2.0
3.175
Detail A
Detail C
Detail B
2.26
RADIUS
1.27 + 0.10
Tolerances: (0.13) unless otherwise specified.
V437216C04VDTG-75 Rev. 1.2 July 2001
10
MOSEL VITELIC
V437216C04VDTG-75
Label Information
MOSEL VITELIC
Part Number
V437216C04VDTG-75
PC133R-333-542-A
Taiwan XXXX-XXXXXXX
Criteria of PC100 or PC133
(refer to MVI datasheet)
DIMM manufacture date code
Trace Code
PC133R - 333 - 54 2 - A
Registered DIMM
Gerber file Intel® PC100 x 4 Based
C
= 3 (CLK)
= 3 (CLK)
= 3 (CLK)
L
JEDEC SPD Revision 2.0
= 5.4 ns
t
RCD
t
RP
t
AC
V437216C04VDTG-75 Rev. 1.2 July 2001
11
MOSEL VITELIC WORLDWIDE OFFICES
V437216C04VDTG-75
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 44-1698-748515
FAX: 44-1698-748516
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
NO 19 LI HSIN ROAD
JAPAN
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-579-5888
FAX: 886-3-566-5888
ONZE 1852 BUILDING 6F
2-14-6 SHINTOMI, CHUO-KU
TOKYO 104-0041
GERMANY
PHONE: 03-3537-1400
FAX: 03-3537-1402
(CONTINENTAL
EUROPE & ISRAEL)
BENZSTRASSE 32
71083 HERRENBERG
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200
SAN CLEMENTE, CA 92672
PHONE: 949-361-7873
FAX: 949-361-7807
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 214-826-6176
FAX: 214-828-9754
7/01
Printed in U.S.A.
© Copyright 2001, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100ꢀ product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
相关型号：
©2020 ICPDF网 联系我们和版权申明