MAX3670EGJ [MAXIM]
Low-Jitter 155MHz/622MHz Clock Generator; 低抖动了155MHz / 622MHz时钟发生器
| 型号： | MAX3670EGJ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Jitter 155MHz/622MHz Clock Generator |
| 文件： | 总13页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2166; Rev 0; 9/01
Low-Jitter 155MHz/622MHz
Clock Generator
General Description
Features
The MAX3670 is a low-jitter 155MHz/622MHz reference
clock generator IC designed for system clock distribution
and frequency synchronization in OC-48 and OC-192
SONET/SDH and WDM transmission systems. The
MAX3670 integrates a phase/frequency detector, an
operational amplifier (op amp), prescaler dividers and
input/output buffers. Using an external VCO, the
MAX3670 can be configured easily as a phase-lock loop
with bandwidth programmable from 15Hz to 20kHz.
ꢀ Single +3.3V or +5.0V Supply
ꢀ Power Dissipation: 150mW at +3.3V Supply
ꢀ External VCO Center Frequencies (f
): 155MHz
VCO
to 670MHz
ꢀ Reference Clock Frequencies: f
, f
/2,
VCO VCO
f /8
VCO
ꢀ Main Clock Output Frequency: f
VCO
The MAX3670 operates from a single +3.3V or +5.0V
supply, and dissipates 150mW (typ) at 3.3V. The operat-
ing temperature range is from -40°C to +85°C. The chip
is available in a 5mm ✕ 5mm, 32-pin QFN package.
ꢀ Optional Output Clock Frequencies: f
, f
/2,
VCO VCO
f /4, f /8
VCO VCO
ꢀ Low Intrinsic Jitter: <0.4ps
ꢀ Loss-of-Lock Indicator
RMS
Applications
ꢀ PECL Clock Output Interface
OC-12 to OC-192 SONET/WDM Transport
Systems
Ordering Information
Clock Jitter Clean-Up and Frequency
Synchronization
PART
TEMP. RANGE PIN-PACKAGE
MAX3670EGJ -40°C to +85°C 32 QFN-EP* (5mm x 5mm)
*Exposed pad
Frequency Conversion
System Clock Distribution
Pin Configuration appears at end of data sheet.
Typical Application Circuit
3.3V
142Ω
155MHz
MAX3892
VCCD
MOUT+
REFCLK+
REFCLK-
16:1
SERIALIZER
MOUT-
142Ω
3.3V
142Ω
VCOIN+
VCOIN-
VCO
= 25kHz/V
N.C.
N.C.
RSEL
VSEL
K
VCO
155MHz
100Ω
MAX3670
142Ω
GSEL1
GSEL2
GSEL3
N.C.
3.3V
332Ω
VC
4700pF
0.01µF
500kΩ
OPAMP-
OPAMP+
POLAR
GND
4700pF
500kΩ
SETUP FOR 10kHz LOOP
BANDWIDTH
REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Jitter 155MHz/622MHz
Clock Generator
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .........................................................-0.5V to +7V
Voltage at C2+% C2-% ꢂHADJ% CꢂH% GSEL±% GSEL2% GSEL3%
LOL% RSEL% REFCLK-% REFCLK+% VSEL% VCOIN+% VCOIN-%
VC% POLAR% PSEL±% PSEL2% COMP%
PECL Output Cuꢁꢁent (MOUꢂ+%
MOUꢂ-% POUꢂ+% POUꢂ-).................................................56mA
Opeꢁating ꢂempeꢁatuꢁe Range ...........................-40°C to +85°C
Stoꢁage ꢂempeꢁatuꢁe Range.............................-65°C to +±60°C
Lead ꢂempeꢁatuꢁe (soldeꢁing% ±0s) .................................+300°C
OPAMP+% OPAMP-..................................-0.5V to (V
+ 0.5V)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.3V ±±0ꢀ oꢁ V
= +5.0V ±±0ꢀ% ꢂ = -40°C to +85°C. ꢂypical values aꢁe at V
= +3.3V and ꢂ = +25°C% unless otheꢁ-
CC A
CC
CC
A
wise noted.) (Note ±)
PARAMETER
Supply Cuꢁꢁent
INPUT SPECIFICATIONS (REFCLK±% VCOIN±)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
(Note 2)
48
72
mA
CC
V
±.±6
-
V
0.88
-
CC
CC
Input High Voltage
Input Low Voltage
Input Bias Voltage
V
V
V
V
IH
V
±.8±
-
V
±.48
-
CC
CC
V
IL
V
±.3
-
CC
Common-Mode Input Resistance
Diffeꢁential Input Resistance
7.5
±2.8
300
±±.5
2±.0
±7.5
32.5
±900
kΩ
kΩ
Diffeꢁential Input Voltage Swing
PECL OUTPUT SPECIFICATIONS
AC-coupled
mVp-p
V
-
V
0.88
-
CC
CC
0°C to +85°C
-40°C to 0°C
0°C to +85°C
-40°C to 0°C
±.025
Output High Voltage
Output Low Voltage
V
V
V
OH
V
-
V
0.88
-
CC
CC
±.085
V
±.8±
-
V
±.62
-
CC
CC
V
OL
V
±.83
-
V
-
CC
CC
±.556
TTL SPECIFICATIONS
Output High Voltage
Output Low Voltage
V
Souꢁcing 20µA
Sinking 2mA
2.4
V
V
V
OH
CC
V
0.4
OL
2
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.3V ±±0ꢀ oꢁ V
= +5.0V ±±0ꢀ% ꢂ = -40°C to +85°C. ꢂypical values aꢁe at V
= +3.3V and ꢂ = +25°C% unless otheꢁ-
CC A
CC
CC
A
wise noted.) (Note ±)
PARAMETER
OPERATIONAL AMPLIFIER SPECIFICATIONS (Note 3)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
0.3
-
-
CC
V
V
= +3.3V ±±0ꢀ
0.3
0.5
CC
CC
Op Amp Output Voltage Range
V
V
O
V
0.5
CC
= +5.0V ±±0ꢀ
Op Amp Input Offset Voltage
Op Amp Open-Loop Gain
| V
A
|
3
mV
dB
OS
90
OL
PHASE FREQUENCY DETECTOR (PFD)/CHARGE-PUMP (CP) SPECIFICATIONS (Note 4)
High gain
Low gain
High gain
Low gain
±6
4
20
5
24.4
6.2
Full-Scale PFD/CP Output
Cuꢁꢁent
| I
|
µA
ꢀ
PD
0.80
±.08
PFD/CP Offset Cuꢁꢁent
| I
|
PD
AC ELECTRICAL CHARACTERISTICS
(V
= +3.3V ±±0ꢀ oꢁ V
= +5.0V ±±0ꢀ% ꢂ = -40°C to +85°C. ꢂypical values aꢁe at V
= +3.3V and ꢂ = +25°C% unless otheꢁ-
CC A
CC
CC
A
wise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK OUTPUT SPECIFICATIONS
Clock Output Fꢁequency
670
MHz
622/3±±/
±55/78
f
f
= 622MHz
= ±55MHz
VCO
VCO
Optional Clock Output
Fꢁequency
MHz
±55/78/
38/±9
Clock Output Rise/Fall ꢂime
Clock Output Duty Cycle
Measuꢁed fꢁom 20ꢀ to 80ꢀ
(Note 6)
280
55
ps
ꢀ
45
NOISE SPECIFICATIONS
Random Noise Voltage at Loop-
Filteꢁ Output
µV
/√Hz
RMS
RMS
V
Fꢁeq > ±kHz (Note 7)
(Note 8)
±.±4
NOISE
PSR
Spuꢁious Noise Voltage at Loop-
Filteꢁ Output
50
µV
Poweꢁ-Supply Rejection at Loop-
Filteꢁ Output
(Note 9)
30
30
dB
REFERENCE CLOCK INPUT SPECIFICATIONS
Refeꢁence Clock Fꢁequency
622/
±55/78
670
70
MHz
ꢀ
Refeꢁence Clock Duty Cycle
_______________________________________________________________________________________
3
Low-Jitter 155MHz/622MHz
Clock Generator
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.3V ±±0ꢀ oꢁ V
= +5.0V ±±0ꢀ% ꢂ = -40°C to +85°C. ꢂypical values aꢁe at V
= +3.3V and ꢂ = +25°C% unless otheꢁ-
CC A
CC
CC
A
wise noted.) (Note 5)
PARAMETER
PLL SPECIFICATIONS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PLL Jitteꢁ ꢂꢁansfeꢁ Bandwidth
Jitteꢁ ꢂꢁansfeꢁ Function
OP AMP SPECIFICATION
Unity-Gain Bandwidth
BW
(Note ±0)
≤ BW (Note ±±)
±5
20%000
0.±
Hz
dB
F
JIꢂꢂER
7
MHz
VCO INPUT SPECIFICATION
VCO Input Fꢁequency
f
622/±55
670
MHz
V/ns
VCO
VCO Input Slew Rate
0.5
Note 1: Specifications at -40°C aꢁe guaꢁanteed by design and chaꢁacteꢁization.
Note 2: Measuꢁed with PECL outputs unteꢁminated.
Note 3: OPAMP specifications met with ±0kΩ load to gꢁound oꢁ 5kΩ load to V (POLAR = 0 and POLAR = V ).
CC
CC
Note 4: PFD/CP cuꢁꢁents aꢁe measuꢁed fꢁom pins OPAMP+ to OPAMP-. See ꢂable 3 foꢁ gain settings.
Note 5: AC chaꢁacteꢁistics aꢁe guaꢁanteed by design and chaꢁacteꢁization.
Note 6: Measuꢁed with 50ꢀ VCO input duty cycle.
Note 7: Random noise voltage at op amp output with 800kΩ ꢁesistoꢁ connected between VC and OPAMP-% PFD/CP gain (K ) =
PD
5µA/UI% and POLAR = 0. Measuꢁed with the PLL open loop and no REFCLK oꢁ VCO input.
Note 8: Spuꢁious noise voltage due to PFD/CP output pulses measuꢁed at op amp output with R = 800kΩ% K = 5µA/UI% and
±
PD
compaꢁe fꢁequency 400 times gꢁeateꢁ than the higheꢁ-oꢁdeꢁ pole fꢁequency (see Design Procedure).
Note 9: PSR measuꢁed with a ±00mVp-p sine wave on V in a fꢁequency ꢁange fꢁom ±00Hz to 2MHz. Exteꢁnal ꢁesistoꢁs R matched
CC
±
to within ±ꢀ% exteꢁnal capacitoꢁs C matched to within ±0ꢀ. Measuꢁed closed loop with PLL bandwidth set to 200Hz.
±
Note 10:ꢂhe PLL 3dB bandwidth is adjusted fꢁom ±5Hz to 20kHz by changing exteꢁnal components R and C % by selecting the inteꢁ-
±
±
nal pꢁogꢁammable divideꢁ ꢁatio and phase-detectoꢁ gain. Measuꢁed with VCO gain of 220ppm/V and C limited to 2.2µF.
±
Note 11:Measuꢁed at BW = 20kHz. When input jitteꢁ fꢁequency is above PLL tꢁansfeꢁ bandwidth (BW)% the jitteꢁ tꢁansfeꢁ function ꢁolls
off at -20dB/decade.
4
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
Typical Operating Characteristics
(ꢂ = +25°C% unless otheꢁwise noted.)
A
SUPPLY CURRENT
vs. TEMPERATURE
EDGE SPEED
vs. TEMPERATURE
POWER-SUPPLY REJECTION
vs. FREQUENCY
280
270
260
250
240
230
220
210
200
190
180
170
160
150
60
0
-10
-20
-30
-40
-50
-60
BW = 1kHz
HOP = 5kHz
5.0V
3.3V
50
40
LOOP FILTER OUTPUT
622.08MHz
30
20
155.52MHz
-40
-20
0
20
40
60
80
-40 -20
0
20
40
60
80
1k
10k
100k
1M
10M
TEMPERATURE (°C)
TEMPERATURE (°C)
FREQUENCY (Hz)
622MHz CLOCK OUTPUT
(DIFFERENTIAL OUTPUT)
155MHz CLOCK OUTPUT
(DIFFERENTIAL OUTPUT)
200mV/
div
200mV/
div
500ps/div
2.0ns/div
_______________________________________________________________________________________
5
Low-Jitter 155MHz/622MHz
Clock Generator
Pin Description
PIN
NAME
FUNCTION
Positive Filteꢁ Input. Exteꢁnal capacitoꢁ connected between C2+ and C2- used foꢁ setting the higheꢁ-oꢁdeꢁ
pole fꢁequency (see Setting the Higher-Order Poles).
±
C2+
Negative Filteꢁ Input. Exteꢁnal capacitoꢁ connected between C2+ and C2- used foꢁ setting the higheꢁ-
oꢁdeꢁ pole fꢁequency (see Setting the Higher-Order Poles).
2
C2-
3% 9% ±5
4
VCCD
Positive Digital Supply Voltage
ꢂHADJ
ꢂhꢁeshold Adjust Input. Used to adjust the Loss-of-Lock thꢁeshold (see LOL Setup).
ꢂhꢁeshold Capacitoꢁ Input. A capacitoꢁ connected between CꢂH and gꢁound used to contꢁol the Loss-of-
Lock conditions (see LOL Setup).
5
6
7
8
CꢂH
Gain Select ± Input. ꢂhꢁee-level pin used to set the phase-detectoꢁ gain (K ) and the fꢁequency-divideꢁ
PD
GSEL±
GSEL2
GSEL3
ꢁatio (N ) (see ꢂable 3).
2
Gain Select 2 Input. ꢂhꢁee-level pin used to set the phase-detectoꢁ gain (K ) and the fꢁequency-divideꢁ
PD
ꢁatio (N ) (see ꢂable 3).
2
Gain Select 3 Input. ꢂhꢁee-level pin used to set the phase-detectoꢁ gain (K ) and the fꢁequency-divideꢁ
PD
ꢁatio (N ) (see ꢂable 3).
2
Loss-of-Lock. LOL signals a ꢂꢂL low when the ꢁefeꢁence fꢁequency diffeꢁs fꢁom the VCO fꢁequency. LOL
signals a ꢂꢂL high when the ꢁefeꢁence fꢁequency equals the VCO fꢁequency.
±0
±±
±2
LOL
GND
RSEL
Supply Gꢁound
Refeꢁence Clock Select Input. ꢂhꢁee-level pin used to set the pꢁedivideꢁ ꢁatio (N ) foꢁ the input ꢁefeꢁence
3
clock (see ꢂable ±).
±3
±4
REFCLK+
REFCLK-
Positive Refeꢁence Clock Input
Negative Refeꢁence Clock Input
VCO Clock Select Input. ꢂhꢁee-level pin used to set the pꢁedivideꢁ ꢁatio (N ) foꢁ the input VCO clock (see
±
ꢂable 2).
±6
VSEL
±7
±8
POUꢂ-
POUꢂ+
VCCO
MOUꢂ-
MOUꢂ+
VCOIN-
VCOIN+
VC
Negative Optional Clock Output% PECL
Positive Optional Clock Output% PECL
±9% 22
20
Positive Supply Voltage foꢁ PECL Outputs
Negative Main Clock Output% PECL
2±
Positive Main Clock Output% PECL
23
Negative VCO Clock Input
24
Positive VCO Clock Input
25
Contꢁol Voltage Output. ꢂhe voltage output fꢁom the op amp that contꢁols the VCO.
Polaꢁity Contꢁol Input. Polaꢁity contꢁol of op amp input. POLAR = GND foꢁ VCOs with positive gain
26
POLAR
tꢁansfeꢁ. POLAR = V
foꢁ VCOs with negative gain tꢁansfeꢁ.
CC
27
28
29
PSEL±
PSEL2
VCCA
Optional Clock Select ± Input. Used to set the divideꢁ ꢁatio foꢁ the optional clock output (see ꢂable 4).
Optional Clock Select 2 Input. Used to set the divideꢁ ꢁatio foꢁ the optional clock output (see ꢂable 4).
Positive Analog Supply Voltage foꢁ the Chaꢁge Pump and Op Amp
Compensation Contꢁol Input. Op amp compensation ꢁefeꢁence contꢁol input. COMP = GND foꢁ VCOs
30
COMP
whose contꢁol pin is V
ꢁefeꢁenced. COMP = V foꢁ VCOs whose contꢁol pin is GND ꢁefeꢁenced.
CC
CC
3±
32
OPAMP-
OPAMP+
Negative Op Amp Input (POLAR = 0)% Positive Op Amp Input (POLAR = ±)
Positive Op Amp Input (POLAR = 0)% Negative Op Amp Input (POLAR = ±)
Exposed
Pad
Gꢁound. ꢂhe exposed pad must be soldeꢁed to the ciꢁcuit boaꢁd gꢁound plane foꢁ pꢁopeꢁ theꢁmal and
electꢁical peꢁfoꢁmance.
EP
6
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
Functional Diagram
C1
C1
R1
R3
VCO
VCO
K
C3
R1
LOL
THADJ
CTH
VC
COMP
POLAR
OPAMP-
OPAMP+
OPAMP
LOL
REFCLK+
REFCLK-
DIV
(N3)
DIV
(N2)
PFD/CP
PD
K
RSEL
VSEL
C2-
C2+
MOUT+
DIV
DIV
(N2)
(N1)
VCOIN+
VCOIN-
PECL
PECL
MOUT-
POUT+
POUT-
DIV
GAIN-CONTROL LOGIC
GSEL1 GSEL2 GSEL3
1/2/4/8
MAX3670
PSEL1 PSEL2
Input Buffer for Reference
Clock and VCO
Detailed Description
ꢂhe MAX3670 contains all the blocks needed to foꢁm a
PLL except foꢁ the VCO% which must be supplied sepa-
ꢁately. ꢂhe MAX3670 consists of input buffeꢁs foꢁ the ꢁef-
eꢁence clock and VCO% input and output clock-divideꢁ
ciꢁcuitꢁy% LOL detection ciꢁcuitꢁy% gain-contꢁol logic% a
phase-fꢁequency detectoꢁ and chaꢁge pump% an op
amp% and PECL output buffeꢁs.
ꢂhe MAX3670 contains diffeꢁential inputs foꢁ the ꢁefeꢁ-
ence clock and the VCO. ꢂhese inputs can be DC-cou-
pled and aꢁe inteꢁnally biased with high impedance so
that they can be AC-coupled (Figuꢁe ± in the Interface
Schematic section). A single-ended VCO oꢁ ꢁefeꢁence
clock can also be applied.
Input and Output Clock-Divider Circuitry
ꢂhe ꢁefeꢁence clock and VCO input buffeꢁs aꢁe followed
by a paiꢁ of clock divideꢁs that pꢁescale the input fꢁe-
quency of the ꢁefeꢁence clock and VCO to 77.76MHz.
ꢂhis device is designed to clean up the noise on the
ꢁefeꢁence clock input and pꢁovide a low-jitteꢁ system
clock output.
_______________________________________________________________________________________
7
Low-Jitter 155MHz/622MHz
Clock Generator
Depending on the input clock fꢁequency of 77.76MHz%
Table 1. Reference Clock Divider
±55.52MHz% oꢁ 622.08MHz% the clock divideꢁ ꢁatio must
be set to ±% 2% oꢁ 8% ꢁespectively. ꢂhe POUꢂ output
buffeꢁ is pꢁeceded by a clock divideꢁ that scales the
main clock output by ±% 2% 4% oꢁ 8 to pꢁovide an optional
clock.
INPUT
PIN
RSEL
REFERENCE
CLOCK INPUT
FREQ. (MHz)
PREDIVIDER
OUTPUT
FREQ. (MHz)
DIVIDER
RATIO N
3
V
77.76
±55.52
622.08
±
2
8
77.76
77.76
77.76
CC
OPEN
GND
LOL Detection Circuitry
ꢂhe MAX3670 incoꢁpoꢁates a loss-of-lock (LOL) monitoꢁ
that consists of an XOR gate% filteꢁ% and compaꢁatoꢁ
with adjustable thꢁeshold (see “LOL Setup” in the
Applications section). A loss-of-lock condition is sig-
naled with a ꢂꢂL low when the ꢁefeꢁence clock fꢁequen-
cy diffeꢁs fꢁom the VCO fꢁequency.
ꢂhe MAX3670 is designed to accept 77.76MHz%
±55.52MHz% oꢁ 622.08MHz (including FEC ꢁates) volt-
age-contꢁolled oscillatoꢁ (VCO) fꢁequencies. ꢂhe VSEL
input must be set so that the VCO input is pꢁescaled to
77.76MHz (oꢁ FEC ꢁate)% to pꢁovide the pꢁopeꢁ ꢁange foꢁ
the PFD and LOL detection ciꢁcuitꢁy. ꢂable 2 shows the
divideꢁ ꢁatio foꢁ the diffeꢁent VCO fꢁequencies.
Gain-Control Logic
ꢂhe gain-contꢁol ciꢁcuitꢁy facilitates the tuning of the
loop bandwidth by setting phase-detectoꢁ gain and fꢁe-
quency-divideꢁ ꢁatio. ꢂhe gain-contꢁol logic can be pꢁo-
gꢁammed to divide fꢁom ± to ±024% in binaꢁy multiples%
and to adjust the phase detectoꢁ gain to 5µA/UI oꢁ
20µA/UI (see ꢂable 3 in Setting the Loop Bandwidth
section).
Table 2. VCO Clock Divider
INPUT
PIN
VSEL
VCO CLOCK
INPUT FREQ.
(MHz)
PREDIVIDER
OUTPUT
FREQ. (MHz)
DIVIDER
RATIO N
1
V
77.76
±55.52
622.08
±
2
8
77.76
77.76
77.76
CC
Phase-Frequency Detector and
Charge Pump
ꢂhe phase-fꢁequency detectoꢁ incoꢁpoꢁated into the
MAX3670 pꢁoduces pulses pꢁopoꢁtional to the phase
diffeꢁence between the ꢁefeꢁence clock and the VCO
input. ꢂhe chaꢁge pump conveꢁts this pulse tꢁain to a
cuꢁꢁent signal that is fed to the op amp.
OPEN
GND
Setting the Loop Bandwidth
ꢂo eliminate jitteꢁ pꢁesent on the ꢁefeꢁence clock% the
pꢁopeꢁ selection of loop bandwidth is cꢁitical. If the total
output jitteꢁ is dominated by the noise at the ꢁefeꢁence
clock input% then loweꢁing the loop bandwidth will
ꢁeduce system jitteꢁ. ꢂhe loop bandwidth (K) is a func-
Op Amp
ꢂhe op amp is used to foꢁm an active PLL loop filteꢁ
capable of dꢁiving the VCO contꢁol voltage input. Using
the POLAR input% the op amp input polaꢁity can be select-
ed to woꢁk with VCOs having positive oꢁ negative gain-
tꢁansfeꢁ functions. ꢂhe COMP pin selects the op amp
inteꢁnal compensation. Connect COMP to gꢁound if the
tion of the VCO gain (K
)% the gain of the phase
VCO
detectoꢁ (K )% the loop filteꢁ ꢁesistoꢁ (R )% and the total
PD
±
feedback-divideꢁ ꢁatio (N = N± ✕ N2). ꢂhe loop band-
width of the MAX3670 can be appꢁoximated by
VCO contꢁol voltage is V
ꢁefeꢁenced. Connect COMP
CC
to V if the VCO contꢁol voltage is gꢁound ꢁefeꢁenced.
CC
K
R K
2πN
PD ± VCO
K =
Design Procedure
Setting Up the VCO and
Reference Clock
Foꢁ stability% a zeꢁo must be added to the loop in the foꢁm
of ꢁesistoꢁ R in seꢁies with capacitoꢁ C (see Functional
±
±
ꢂhe MAX3670 accepts 77.76MHz% ±55.52MHz% oꢁ
622.08MHz (including FEC ꢁates) ꢁefeꢁence clock fꢁe-
quencies. ꢂhe RSEL input must be set so that the ꢁefeꢁ-
ence clock is pꢁescaled to 77.76MHz (oꢁ FEC ꢁate)% to
pꢁovide the pꢁopeꢁ ꢁange foꢁ the PFD and LOL detec-
tion ciꢁcuitꢁy. ꢂable ± shows the divideꢁ ꢁatio foꢁ the dif-
feꢁent ꢁefeꢁence fꢁequencies.
Diagram). ꢂhe location of the zeꢁo can be appꢁoximated as
±
f
=
Z
2πR C
± ±
Due to the second-oꢁdeꢁ natuꢁe of the PLL jitteꢁ tꢁans-
feꢁ% peaking will occuꢁ and is pꢁopoꢁtional to f /K. Foꢁ
Z
ceꢁtain applications% it may be desiꢁable to limit jitteꢁ
8
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
quency to be (K ✕ 4) < f
≤ f
% wheꢁe K is
HOP
COMPARE
Table 3. Gain Logic Pin Setup
the loop bandwidth.
INPUT
PIN
INPUT
PIN
INPUT
PIN
DIVIDER
RATIO
KPD
(µA/UI)
ꢂhe HOP can be implemented eitheꢁ by pꢁoviding a
compensation capacitoꢁ C % which pꢁoduces a pole at
2
GSEL1
GSEL2
GSEL3
N
2
V
V
V
V
V
V
V
V
V
V
V
V
V
20
20
20
20
20
20
20
20
20
20
20
5
±
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
±
f
=
HOP
OPEN
GND
2
4
2π(20kΩ)(C )
2
V
OPEN
OPEN
OPEN
GND
8
oꢁ by adding a lowpass filteꢁ% consisting of R and C %
diꢁectly on the VCO tuning poꢁt% which pꢁoduces a pole at
CC
3
3
OPEN
GND
±6
32
±
f =
HOP
V
64
CC
2πR C
3
3
OPEN
GND
GND
±28
256
5±2
±024
±
GND
Using R and C may be pꢁefeꢁable foꢁ filteꢁing moꢁe
3
3
noise in the PLL% but it may still be necessaꢁy to pꢁovide
V
V
V
V
V
V
GND
GND
CC
CC
CC
CC
CC
CC
filteꢁing via C when using laꢁge values of R and N ✕ N
2
±
±
2
OPEN
to pꢁevent clipping in the op amp.
V
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
GND
CC
Setting the Optional Output
ꢂhe MAX3670 optional clock output can be set to bina-
ꢁy subdivisions of the main clock fꢁequency. ꢂhe PSEL±
and PSEL2 pins contꢁol the binaꢁy divisions. ꢂable 4
shows the pin configuꢁation along with the possible
divideꢁ ꢁatios.
OPEN
GND
5
2
5
4
V
OPEN
OPEN
OPEN
GND
5
8
CC
OPEN
GND
5
±6
5
32
V
5
64
CC
OPEN
GND
GND
5
±28
256
5±2
±024
Table 4. Setting the Optional Clock
Output Driver
GND
5
V
OPEN
OPEN
5
CC
INPUT PIN
PSEL1
INPUT PIN
PSEL2
VCO TO POUT
DIVIDER RATIO
OPEN
GND
5
V
V
V
±
2
4
8
CC
CC
CC
peaking in the PLL passband ꢁegion to less than 0.±dB.
GND
ꢂhis can be achieved by setting f ≤ K/±00.
Z
V
GND
GND
CC
ꢂhe thꢁee-level GSEL pins (see Functional Diagram)
GND
select the phase-detectoꢁ gain (K ) and the fꢁequency-
PD
divideꢁ ꢁatio (N ). ꢂable 3 summaꢁizes the settings foꢁ
2
the GSEL pins. A moꢁe detailed analysis of the loop filteꢁ
is located in application note HFDN-±3.0 on
www.maxim-ic.com.
Applications Information
PECL Interfacing
ꢂhe MAX3670 outputs (MOUꢂ+% MOUꢂ-% POUꢂ+%
POUꢂ-) aꢁe designed to inteꢁface with PECL signal lev-
els. It is impoꢁtant to bias these poꢁts appꢁopꢁiately. A
ciꢁcuit that pꢁovides a ꢂhévenin equivalent of 50Ω to
Setting the Higher-Order Poles
Spuꢁious noise is geneꢁated by the phase detectoꢁ
switching at the compaꢁe fꢁequency% wheꢁe f
COMPARE
= f
/(N ✕ N ). Reduce the spuꢁious noise fꢁom the
VCO
± 2
V
CC
- 2V can be used with fixed-impedance tꢁansmis-
digital phase detectoꢁ by placing a higheꢁ-oꢁdeꢁ pole
(HOP) at a fꢁequency much less than the compaꢁe fꢁe-
quency. ꢂhe HOP should% howeveꢁ% be placed high
enough in fꢁequency that it does not decꢁease the oveꢁ-
all loop-phase maꢁgin and impact jitteꢁ peaking. ꢂhese
two conditions can be met by selecting the HOP fꢁe-
sion lines with pꢁopeꢁ teꢁmination. ꢂo ensuꢁe best peꢁ-
foꢁmance% the diffeꢁential outputs must have balanced
loads. It is impoꢁtant to note that if optional clock output
is not used% it should be left floating to save poweꢁ (see
Figuꢁe 2).
_______________________________________________________________________________________
9
Low-Jitter 155MHz/622MHz
Clock Generator
quencies above the loop bandwidth may degꢁade LOL
Layout
ꢂhe MAX3670 peꢁfoꢁmance can be significantly affect-
ed by ciꢁcuit boaꢁd layout and design. Use good high-
fꢁequency design techniques% including minimizing
gꢁound inductance and using fixed-impedance tꢁans-
mission lines on the ꢁefeꢁence and VCO clock signals.
Poweꢁ-supply decoupling should be placed as close to
functionality.
ꢂhe useꢁ can set the amount of fꢁequency oꢁ phase dif-
feꢁence between VCO and ꢁefeꢁence clock at which
LOL indicates an out-of-lock condition. ꢂhe fꢁequency
diffeꢁence is called the beat fꢁequency. ꢂhe CꢂH pin
can be connected to an exteꢁnal capacitoꢁ% which sets
the lowpass filteꢁ fꢁequency to appꢁoximately
V
pins as possible. ꢂake caꢁe to isolate the input
CC
fꢁom the output signals to ꢁeduce feedthꢁough.
±
f =
VCO Selection
L
2πC 60kΩ
ꢂH
ꢂhe MAX3670 is designed to accommodate a wide
ꢁange of VCO gains% positive oꢁ negative tꢁansfeꢁ
ꢂhis lowpass filteꢁ fꢁequency should be set about ±0
times loweꢁ than the beat fꢁequency to make suꢁe the
filteꢁed signal at CꢂH does not dꢁop below the ꢂHADJ
thꢁeshold voltage. ꢂhe inteꢁnal compaꢁe fꢁequency of
the paꢁt is 77.78MHz. Foꢁ a ±ppm sensitivity (beat fꢁe-
quency of 77Hz)% the filteꢁ needs to be at 7.7Hz% and
CꢂH should be at 0.33µF.
slopes% and V -ꢁefeꢁenced oꢁ gꢁound-ꢁefeꢁenced con-
CC
tꢁol voltages. ꢂhese featuꢁes allow the useꢁ a wide
ꢁange of options in VCO selection; howeveꢁ% the pꢁopeꢁ
VCO must be selected to allow the clock geneꢁatoꢁ ciꢁ-
cuitꢁy to opeꢁate at the optimum levels. When selecting
a VCO% the useꢁ needs to take into account the phase
noise and modulation bandwidth. Phase noise is impoꢁ-
tant because the phase noise above the PLL bandwidth
will be dominated by the VCO noise peꢁfoꢁmance.
ꢂhe modulation bandwidth of the VCO contꢁibutes an
additional higheꢁ-oꢁdeꢁ pole (HOP) to the system and
should be gꢁeateꢁ than the HOP set with the exteꢁnal fil-
teꢁ components.
ꢂhe voltage at ꢂHADJ will deteꢁmine the level at which
the LOL output flags. ꢂHADJ is set to a default value of
0.6V which coꢁꢁesponds in a 45° phase diffeꢁence. ꢂhis
value can be oveꢁꢁidden by applying the desiꢁed
thꢁeshold voltage to the pin. ꢂhe ꢁange of ꢂHADJ is
fꢁom 0V (0°) to 2.4V (±80°).
Noise Performance Optimization
Depending on the application% theꢁe aꢁe many diffeꢁent
ways to optimize the PLL peꢁfoꢁmance. ꢂhe following
aꢁe geneꢁal guidelines to impꢁove the noise on the sys-
tem output clock.
Interface Schematics
±) If the ꢁefeꢁence clock noise dominates the total sys-
tem-clock output jitteꢁ% then decꢁeasing the loop
bandwidth (K) ꢁeduces the output jitteꢁ.
V
CC
2) If the VCO noise dominates the total system clock
output jitteꢁ% then incꢁeasing the loop bandwidth (K)
ꢁeduces the output jitteꢁ.
V
- 1.3V
CC
3) Smalleꢁ total divideꢁ ꢁatio (N± ✕ N2)% loweꢁ HOP% and
10.5kΩ
10.5kΩ
smalleꢁ R ꢁeduce the spuꢁious output jitteꢁ.
±
4) Smalleꢁ R ꢁeduces the ꢁandom noise due to the op amp.
±
REFLCK+
REFLCK-
LOL Setup
ꢂhe LOL output indicates if the PLL has locked onto the
ꢁefeꢁence clock using an XOR gate and compaꢁatoꢁ.
ꢂhe compaꢁatoꢁ thꢁeshold can be adjusted with ꢂHADJ%
and the XOR gate output can be filteꢁed with a capaci-
toꢁ between CꢂH and gꢁound (Figuꢁe 3 in the Interface
Schematic section). When the voltage at pin CꢂH
exceeds the voltage at pin ꢂHADJ% then the LOL output
goes low and indicates that the PLL is not locked. Note
that excessive jitteꢁ on the ꢁefeꢁence clock input at fꢁe-
MAX3670
Figure 1. Input Interface
10 ______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
Interface Schematics (continued)
V
CC
LOL
60kΩ
THADJ
OUT+
OUT-
0.6V
CTH
60kΩ
REFCLK
MAX3670
MAX3670
VCO
Figure 2. Output Interface
Figure 3. Loss-of-Lock Indicator
Pin Configuration
Chip Information
ꢂRANSISꢂOR COUNꢂ: 2478
32
31
30
29
28
27
26
25
C2+
C2-
24
23
22
1
2
3
4
5
6
7
8
VCOIN+
VCOIN-
VCCO
VCCD
THADJ
21 MOUT+
20 MOUT-
19 VCCO
18 POUT+
17 POUT-
MAX3670*
CTH
GSEL1
GSEL2
GSEL3
9
10
11
12
13
14
15
16
*THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND.
______________________________________________________________________________________ 11
Low-Jitter 155MHz/622MHz
Clock Generator
Package Information
12 ______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 200± Maxim Integꢁated Pꢁoducts
Pꢁinted USA
is a ꢁegisteꢁed tꢁademaꢁk of Maxim Integꢁated Pꢁoducts.
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