MAX3671ETN+ [MAXIM]
Low-Jitter Frequency Synthesizer with Selectable Input Reference; 低抖动频率合成器，可选择输入参考
| 型号： | MAX3671ETN+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Jitter Frequency Synthesizer with Selectable Input Reference |
| 文件： | 总16页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4437; Rev 0; 2/09
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3671
General Description
Features
The MAX3671 is a low-jitter frequency synthesizer that
accepts two reference clock inputs and generates nine
phase-aligned outputs. The device features 40kHz jitter
♦ Two Reference Clock Inputs: LVPECL
♦ Nine Phase-Aligned Clock Outputs: LVPECL
♦ Input Frequencies: 62.5MHz,125MHz, 250MHz,
transfer bandwidth, 0.3ps
(12kHz to 20MHz) inte-
RMS
312.5MHz
grated phase jitter, and best-in-class power-supply
noise rejection (PSNR), making it ideal for jitter clean-
up, frequency translation, and clock distribution in
Gigabit Ethernet applications.
♦ Output Frequencies: 62.5MHz, 125MHz,
156.25MHz, 250MHz, 312.5MHz
♦ Low-Jitter Generation: 0.3ps
(12kHz to 20MHz)
RMS
The MAX3671 operates from a single +3.3V supply and
typically consumes 400mW. The IC is available in an
8mm x 8mm, 56-pin TQFN package, and operates from
-40°C to +85°C.
♦ Clock Failure Indicator for Both Reference Clocks
♦ External Feedback Provides Zero-Delay Capability
♦ Low Output Skew: 20ps Typical
Applications
Gigabit Ethernet Routers and Switches
Frequency Translation
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX3671ETN+
-40°C to +85°C
56 TQFN-EP*
Jitter Cleanup
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Clock Distribution
Pin Configuration and Typical Application Circuits appear at
end of data sheet.
Functional Diagram
C
PLL
0.1μF
C
REG
0.22μF
SEL_CLK
DM
DA
PLL_BYPASS
OUTA_EN
REFCLK0
1
0
OUTA3
OUTA3
0
1
REFCLK0
REFCLK1
DIV M
PFD
62.5MHz
CP
VCO
DIV A
OUTA2
OUTA2
2.5GHz
REFCLK1
OUTA1
OUTA1
IN0FAIL
IN1FAIL
LOCK
SIGNAL QUALIFIER
AND
LOCK DETECT
OUTA0
OUTA0
DIV N
OUTB_EN
POWER-ON
RESET
(POR)
1
0
OUTB4
OUTB4
MR
DIV B
OUTB3
OUTB3
OUTB2
OUTB2
1
0
OUTB1
OUTB1
MAX3671
OUTB0
OUTB0
FB_SEL
FB_IN FB_IN
DB
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (V , VCC_VCO)..............-0.3V to +4.0V
Continuous Power Dissipation (T = +70°C)
CC
A
LVPECL Output Current (OUTA[3:0],
56-Pin TQFN (derate 47.6mW/°C above 70°C)..........3808mW
, OUTB[4:0],
OUTA[3:0]
) .............................-56mA
OUTB[4:0]
Operating Junction Temperature (T )................-55°C to +150°C
J
All Other Pins..............................................-0.3V to (V
+ 0.3V)
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX3671
ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, T = -40°C to +85°C, C
= 0.1µF, C
= 0.22µF. Typical values are at V = +3.3V, T = +25°C, unless
CC A
CC
A
PLL
REG
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
I
LVPECL outputs unterminated
120
175
mA
CC
POWER-ON RESET
V
CC
V
CC
Rising
Falling
(Note 1)
(Note 1)
2.55
2.45
V
V
LVCMOS/LVTTL INPUTS (MR, SEL_CLK, PLL_BYPASS, FB_SEL)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
2.0
V
V
IH
V
0.8
75
IL
I
V
V
= V
CC
μA
μA
IH
IN
IN
I
= GND
-75
2.4
IL
LVCMOS/LVTTL OUTPUTS (IN0FAIL, IN1FAIL, LOCK)
Output High Voltage
Output Low Voltage
V
I
I
= -8mA
V
V
OH
OH
OL
V
= +8mA
0.4
OL
LVPECL INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1, FB_IN, FB_IN) (Note 2)
V
0.7
-
CC
Input High Voltage
Input Low Voltage
Input Bias Voltage
V
V
V
V
IH
V
2.0
-
-
CC
V
IL
V
CC
V
1.34
-
CC
V
CMI
1.8
Differential-Input Swing
Differential-Input Impedance
Common-Mode Input Impedance
Input Capacitance
0.15
1.9
V
P-P
> 40
> 14
1.5
kꢀ
kꢀ
pF
μA
Input Current
V
= V - 0.7V, V = V - 2.0V
-100
+100
IH
CC
IL
CC
Input Inrush Current When Power
is Off (Steady State)
I
(Notes 3, 4)
(Notes 3, 4)
8
6
mA
mA
DC
Input Inrush Current Overshoot
When Power is Off
I
OVERSHOOT
2
_______________________________________________________________________________________
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3671
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, T = -40°C to +85°C, C
= 0.1µF, C
= 0.22µF. Typical values are at V = +3.3V, T = +25°C, unless
CC A
CC
A
PLL
REG
otherwise noted.)
PARAMETER
REFERENCE CLOCK INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Clock Frequency
f
Table 1
MHz
ppm
%
REF
Reference Clock Frequency
Tolerance
-200
40
+200
60
Reference Clock Duty Cycle
Reference Clock Amplitude
Detection Assert Threshold
V
DT
Differential swing (Notes 5, 6)
200
mV
P-P
LVPECL OUTPUTS (OUTA[3:0], OUT [3:0], OUTB[4:0], OUTB[4:0]) (Note 7)
A
V
1.13
-
V
0.98
-
V
0.83
-
CC
CC
CC
Output High Voltage
Output Low Voltage
V
V
OH
V
CC
-
V
CC
-
V
CC
-
V
V
OL
1.85
1.70
1.55
Differential-Output Swing
1.1
1.45
1.8
V
P-P
Output Current When Disabled
V
= V - 2.0V to V - 0.7V
130
μA
MHz
ps
O
CC
CC
Tables
2, 3
Output Frequency
Output Rise/Fall Time
Output Duty Cycle
f
OUT
t , t
20% to 80% (Note 8)
PLL_BYPASS = 0
PLL_BYPASS = 1 (Note 9)
Within output bank
All outputs
150
48
500
52
R
F
%
45
55
20
40
Output-to-Output Skew
t
ps
SKEW
OTHER AC ELECTRICAL SPECIFICATIONS
PLL Jitter Transfer Bandwidth
Jitter Peaking
40
0.1
62.5
2.5
0.3
kHz
dB
PFD Compare Frequency
VCO Center Frequency
MHz
GHz
Random Jitter Generation
Integrated 12kHz to 20MHz (Notes 5, 8)
(Note 10)
1.0
ps
RMS
Determinisitic Jitter Caused by
Power-Supply Noise
5
ps
P-P
Frequency Difference Between
Reference Clock and VCO
Within Which the PLL is
Considered in Lock
500
ppm
Frequency Difference Between
Reference Clock and VCO at
Which the PLL is Considered
Out-of-Lock
800
600
ppm
μs
PLL Lock Time
t
Figure 2
LOCK
_______________________________________________________________________________________
3
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, T = -40°C to +85°C, C
= 0.1µF, C
= 0.22µF. Typical values are at V = +3.3V, T = +25°C, unless
CC A
CC
A
PLL
REG
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Master Reset (MR) Minimum
Pulse Width
100
ns
Propagation Delay from Input to
FB_IN
FB_SEL = 1 (Notes 8, 11)
PLL_BYPASS = 1
-120
+120
ps
ns
MAX3671
Propagation Delay from Input to
Any Output
1.0
Note 1: During the power-on-reset time, the LVPECL outputs are held to logic-low (OUTxx = low, OUTxx = high). See the Power-
On-Reset (POR) section for more information.
Note 2: LVPECL inputs can be AC- or DC-coupled.
Note 3: For hot-pluggable purposes, the device can receive LVPECL inputs when no supply voltage is applied. Measured with
V
CC
pins connected to GND. See Figure 1.
Note 4: Measured with LVPECL input (V , V ) as specified.
IH IL
Note 5: Measured using reference clock input with 550ps rise/fall time (20% to 80%).
Note 6: When input differential swing is below the specified threshold, a clock failure is declared. See Figure 4.
Note 7: LVPECL outputs terminated 50Ω to V = V
- 2V.
TT
CC
Note 8: Guaranteed by design and characterization.
Note 9: Measured with 50% duty cycle at reference clock input.
Note 10: Measured with 50mV
sinusoidal noise on the power supply, f
= 100kHz.
P-P
NOISE
Note 11: Measured with f
= f
and matched slew rates.
REFCLKx
FB_IN
4
_______________________________________________________________________________________
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3671
INRUSH CURRENT
(mA)
I
OVERSHOOT
I
DC
t
Figure 1. LVPECL Input Inrush Current
POWER-ON-RESET (~ 20μs)
V
CC
REFCLK0
REFCLK1
OUTxx
HIGH
HIGH
IN0FAIL
IN1FAIL
t
(~ 600μs)
LOCK
LOCK
PLL LOCKED TO REFCLK0
SEL_CLK
LOW
Figure 2. Power-Up, PLL Locks to REFCLK0
_______________________________________________________________________________________
5
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
Typical Operating Characteristics
(V
CC
= 3.3V, T = +25°C, unless otherwise noted.)
A
PHASE NOISE AT 62.5MHz
PHASE NOISE AT 125MHz
PHASE NOISE AT 156.25MHz
-60
-70
-60
-70
-60
-70
RANDOM JITTER = 0.41ps
INTEGRATED 12kHz TO 20MHz
RANDOM JITTER = 0.29ps
INTEGRATED 12kHz TO 20MHz
RANDOM JITTER = 0.28ps
RMS
INTEGRATED 12kHz TO 20MHz
RMS
RMS
-80
-90
-80
-80
MAX3671
-90
-90
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
100
1k
10k
100k
1M
10M 100M
100
1k
10k
100k
1M
10M 100M
100
1k
10k
100k
1M
10M 100M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
PHASE NOISE AT 250MHz
PHASE NOISE AT 312.5MHz
JITTER TRANSFER
-60
-70
-60
-70
5
RANDOM JITTER = 0.27ps
INTEGRATED 12kHz TO 20MHz
RANDOM JITTER = 0.28ps
RMS
INTEGRATED 12kHz TO 20MHz
RMS
0
-5
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
-10
-15
-20
-25
-30
100
1k
10k
100k
1M
10M 100M
100
1k
10k
100k
1M
10M 100M
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
JITTER FREQUENCY (Hz)
DIFFERENTIAL OUTPUT WAVEFORM
DIFFERENTIAL OUTPUT WAVEFORM
REFERENCE CLOCK AMPLITUDE DETECTION
ASSERT THRESHOLD vs. INPUT FREQUENCY
300
AT 156.25MHz
AT 312.5MHz
MAX3671 toc07
MAX3671 toc08
280
260
240
220
200
180
160
140
120
100
INPUT RISE/FALL TIME = 550ps
200mV/div
200mV/div
INPUT RISE/FALL TIME = 270ps
50
100
150
200
250
300
350
800ps/div
400ps/div
REFERENCE CLOCK INPUT FREQUENCY (MHz)
6
_______________________________________________________________________________________
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3671
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, T = +25°C, unless otherwise noted.)
A
JITTER HISTOGRAM WITH SUPPLY NOISE
DETERMINISTIC JITTER
vs. POWER-SUPPLY NOISE AMPLITUDE
SUPPLY CURRENT
vs. TEMPERATURE
(SUPPLY NOISE = 50mV , 100kHz)
P-P
MAX3671 toc11
40
35
30
25
20
15
10
5
500
ALL OUTPUTS ENABLED
AND TERMINATED
450
400
350
300
250
200
150
100
50
f
= 100kHz
NOISE
DJ = 5ps
P-P
f
= 200kHz
NOISE
ALL OUTPUTS ENABLED
AND UNTERMINATED
f
= 1MHz
NOISE
0
0
0
50
100
150
200
250
300
-40
-15
10
35
60
85
2ps/div
SUPPLY NOISE AMPLITUDE (mV
)
TEMPERATURE (°C)
P-P
SPURS CAUSED BY POWER-SUPPLY NOISE
vs. SUPPLY NOISE FREQUENCY
DETERMINISTIC JITTER
vs. POWER-SUPPLY NOISE FREQUENCY
POWER-ON-RESET
MAX3671 toc15
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
40
35
30
25
20
15
10
5
f
= 125MHz
OUT
V
CC
SUPPLY NOISE = 100mV
P-P
SUPPLY NOISE = 100mV
P-P
OUTxx
LOCK
SUPPLY NOISE = 50mV
P-P
SUPPLY NOISE = 50mV
100k
P-P
0
10k
1M
10M
10k
100k
1M
10M
200μs/div
SUPPLY NOISE FREQUENCY (Hz)
SUPPLY NOISE FREQUENCY (Hz)
MASTER RESET
REFERENCE CLOCK FAILURE DETECTION
MAX3671 toc16
MAX3671 toc17
MR
REFCLK1
IN1FAIL
OUTxx
LOCK
LOCK
40μs/div
2ms/div
_______________________________________________________________________________________
7
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
Pin Description
PIN
NAME
FUNCTION
REFCLK0 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK0 fails the clock
qualification. Once a failed clock is detected, the indicator status is latched and updated
every 128 PFD cycles (~ 2μs).
1
IN0FAIL
2
3
4
5
6
RSVD1
RSVD2
REFCLK0
REFCLK0
DM
Reserved. Leave pin open.
Reserved. Connect to GND.
MAX3671
Reference Clock Input 0, Differential LVPECL
Four-Level Control Input for Reference Clock Input Divider. See Table 1.
Power Supply. Connect to +3.3V.
7, 22, 30, 41,
49, 52
V
CC
8, 14, 23, 29,
42, 48, 53
GND
Supply Ground
Master Reset, LVCMOS/LVTTL Input. Connect this pin high or leave open for normal
operation. Has internal 90kꢀ pullup to V . Connect low to reset the device. A reset is not
CC
required at power-up. If the output divider settings are changed on the fly, a reset is
required to phase align the outputs. This input has a 100ns minimum pulse width and is
asynchronous to the reference clock. While in reset, all clock outputs are held to logic-
low. See Table 6.
9
MR
10
11
REFCLK1
Reference Clock Input 1, Differential LVPECL
REFCLK1
Reference Clock Select, LVCMOS/LVTTL Input. Connect low or leave open to select REFCLK0
as the reference clock. Has internal 90kꢀ pulldown to GND. Connect high to select REFCLK1
as the reference clock.
12
SEL_CLK
13
15
VCC_VCO
CPLL
Power Supply for VCO. Connect to +3.3V.
Connection for PLL Filter Capacitor. Connect a 0.1μF capacitor between this pin and GND.
Connection for VCO Regulator Capacitor. Connect a 0.22μF capacitor between this pin and
GND.
16
CREG
External Feedback Select, LVCMOS/LVTTL Input. Connect high to select external feedback
for zero-delay buffer configuration. Connect low or leave open for internal feedback. Has
internal 90kꢀ pulldown to GND.
17
FB_SEL
18
19
20
21
24
25
26
27
28
31
32
33
34
35
36
FB_IN
FB_IN
External Feedback Clock Input, Differential LVPECL. Used for zero-delay buffer
configuration.
OUTB0
OUTB0
OUTB1
OUTB1
OUTB2
OUTB2
DB
Clock Output B0, Differential LVPECL
Clock Output B1, Differential LVPECL
Clock Output B2, Differential LVPECL
Four-Level Control Input for B-Group Output Divider. See Table 3.
Clock Output B3, Differential LVPECL
OUTB3
OUTB3
OUTB4
OUTB4
OUTB_EN
OUTA_EN
Clock Output B4, Differential LVPECL
Three-Level Control Input for B-Group Output Enable. See Table 5.
Three-Level Control Input for A-Group Output Enable. See Table 4.
8
_______________________________________________________________________________________
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3671
Pin Description (continued)
PIN
37
38
39
40
43
44
45
46
47
NAME
OUTA3
OUTA3
OUTA2
OUTA2
DA
FUNCTION
Clock Output A3, Differential LVPECL
Clock Output A2, Differential LVPECL
Four-Level Control Input for A-Group Output Divider. See Table 2.
Clock Output A1, Differential LVPECL
OUTA1
OUTA1
OUTA0
OUTA0
Clock Output A0, Differential LVPECL
PLL Bypass Control, LVCMOS/LVTTL Input. Connect low or open for normal operation. Has
internal 90kꢀ pulldown to GND. Connect high to bypass the PLL, connecting the selected
reference clock directly to the clock outputs. In this mode, the clock qualification function
is not valid. To reduce spurious jitter in bypass mode, the internal VCO should be disabled
by shorting the CREG pin to GND.
50
PLL_BYPASS
51
54
55
RSVD3
RSVD4
LOCK
Reserved. Connect to V
.
CC
Reserved. Leave pin open.
PLL Lock Indicator, LVCMOS/LVTTL Output. Low indicates PLL is locked.
REFCLK1 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK1 fails the clock
qualification. Once a failed clock is detected, the indicator status is latched and updated
every 128 PFD cycles (~ 2μs).
56
—
IN1FAIL
EP
Exposed Pad. Connect to supply ground for proper electrical and thermal performance.
divided reference frequency to the divided VCO output
Detailed Description
at 62.5MHz, and generates a control signal to keep the
VCO phase and frequency locked to the selected refer-
ence clock. Using a high-frequency VCO (2.5GHz) and
low-loop bandwidth (40kHz), the MAX3671 attenuates
reference clock jitter while maintaining lock and gener-
ates low-jitter clock outputs at multiple frequencies.
The MAX3671 integrates two differential LVPECL refer-
ence inputs with a 2:1 mux, a PLL with configurable
dividers, nine differential LVPECL clock outputs, and a
selectable external feedback input for zero-delay buffer
applications (see the Functional Diagram).
The two reference clock inputs are continuously moni-
tored for clock failure by the internal PLL and associat-
ed logic. If the primary clock fails, the user can switch
over to the secondary clock using the 2:1 mux.
Typical jitter generation is 0.3ps
to 20MHz).
(integrated 12kHz
RMS
To minimize supply noise-induced jitter, the VCO sup-
ply (VCC_VCO) is isolated from the core logic and out-
put buffer supplies. Additionally, the MAX3671 uses an
internal low-dropout (LDO) regulator to attenuate noise
from the power supply. This allows the device to
achieve excellent power-supply noise rejection, signifi-
cantly reducing the impact on jitter generation.
The PLL accepts reference input frequencies of 62.5,
125, 250, or 312.5MHz and generates output frequen-
cies of 62.5, 125, 156.25, 250, or 312.5MHz. The nine
clock outputs are organized into two groups (A and B).
Each group has a configurable frequency divider and
output-enable control.
Clock Failure Conditions
The MAX3671 clock failure detection is performed
using the combination of amplitude qualification and
PLL frequency and phase-error qualification. The failure
status is indicated for REFCLK0 and REFCLK1 at
Phase-Locked Loop (PLL)
The PLL contains a phase-frequency detector (PFD),
charge pump (CP) with a lowpass filter, and voltage-
controlled oscillator (VCO). The PFD compares the
_______________________________________________________________________________________
9
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
IN0FAIL and IN1FAIL, respectively. Once an indicator
is asserted low, it is latched and updated every 128
PFD cycles (~ 2µs).
BOTH INPUTS
V
CC
V
CC
OPEN
It should be noted that when the PLL is locked to a ref-
erence clock, the clock failure indicator for the other
reference clock is only valid for amplitude qualification
and frequency qualification.
MAX3671
130Ω
130Ω
Amplitude Qualification
A reference clock input fails amplitude qualification if
any of the following conditions occur:
LVPECL
MAX3671
82Ω
82Ω
• Either one or both inputs (REFCLKx, REFCLKx) are
shorted to V
or GND.
CC
• Both inputs (REFCLKx, REFCLKx) are disconnect-
ed from the source and have 130Ω to V
and 82Ω
CC
to GND at each input. See Figure 3.
Figure 3. Positions for Open-Circuit Detection
• Input reference clock differential swing is below the
clock failure assert threshold as specified in the
Electrical Characteristics. See Figure 4.
The response time for these conditions is typically
between 50ns and 300ns.
DIFFERENTIAL INPUT: (REFCLKx - REFCLKx)
Phase Qualification
A reference clock input fails phase qualification when
the phase error at the PFD output exceeds the error
window (0.75ns typical) for more than five of eight PFD
cycles. A reference clock input is qualified when phase
error at the PFD output is within the phase-error window
for eight consecutive PFD cycles. Note that phase qual-
ification only applies to the reference input currently
being used by the PLL.
V
DT
0V
Frequency Qualification
A reference clock input becomes frequency qualified if
the input frequency is within 2.4% of the nominal fre-
quency. The reference input becomes frequency dis-
qualified if the input frequency moves away from the
nominal frequency by more than 8%.
Figure 4. Input Amplitude Detection Threshold
10 ______________________________________________________________________________________
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3671
PLL Out-of-Lock Condition
Table 1. Divider M Configuration for Input
If the frequency difference between the reference clock
input and the VCO at the PFD input becomes within
500ppm, the PLL is considered to be in lock (LOCK =
0). When the frequency difference between the refer-
ence clock input and the VCO at the PFD input
becomes greater than 800ppm, the PLL is considered
out-of-lock. It should be noted that the LOCK indicator
is not part of the frequency qualification used for the
INxFAIL indicators.
Frequencies
CONNECTION FROM DM PIN INPUT FREQUENCY (MHz)
GND
62.5
125
V
CC
Open
250
10kꢀ to GND
312.5
Table 2. Divider A Configuration for
A-Group Output Frequencies
Input and Output Frequencies
The MAX3671 input and output dividers are configured
using four-level control inputs DM, DA, and DB. Each
divider is independent and can have a unique setting.
The input connection and associated frequencies are
listed in Tables 1, 2, and 3.
OUTPUT FREQUENCY AT
CONNECTION FROM DA PIN
OUTA[3:0] (MHz)
GND
62.5
125
V
CC
Output-Enable Controls
Each output group (A and B) has a three-level control
input OUTA_EN and OUTB_EN. See Tables 4 and 5 for
configuration settings. When clock outputs are dis-
abled, they are high impedance. Unused enabled out-
puts should be left open.
Open
156.25
312.5
10kꢀ to GND
Table 3. Divider B Configuration for
B-Group Output Frequencies
Power-On-Reset (POR)
At power-on, an internal signal is generated to hold the
MAX3671 in a reset state. This internal reset time is
OUTPUT FREQUENCY AT
CONNECTION FROM DB PIN
OUTB[4:0] (MHz)
GND
62.5
125
about 20µs after V
reaches 3.0V (Figure 2). During
CC
V
CC
the POR time, the outputs are held to logic-low (OUTxx
= low and OUTxx = high). See Table 6 for output signal
status during POR. After this internal reset time, the PLL
starts to lock to the reference clock selected by
SEL_CLK.
Open
250
10kꢀ to GND
312.5
Table 4. OUTA[3:0] Enable Control
A-GROUP OUTPUT DISABLED TO HIGH
CONNECTION FROM OUTA_EN PIN
A-GROUP OUTPUT ENABLED
IMPEDANCE
GND
OUTA0, OUTA1, OUTA2, OUTA3
—
V
*
—
OUTA0, OUTA1, OUTA2, OUTA3
OUTA2, OUTA3
CC
Open
OUTA0, OUTA1
*Connecting both OUTA_EN and OUTB_EN to V
enables a factory test mode and forces all indicators to GND. This is not a valid
CC
mode of operation.
Table 5. OUTB[4:0] Enable Control
B-GROUP OUTPUT DISABLED TO HIGH
CONNECTION FROM OUTB_EN PIN
B-GROUP OUTPUT ENABLED
IMPEDANCE
GND
OUTB0, OUTB1, OUTB2, OUTB3, OUTB4
—
V
*
OUTB0
OUTB1, OUTB2, OUTB3, OUTB4
OUTB3, OUTB4
CC
Open
OUTB0, OUTB1, OUTB2
*Connecting both OUTA_EN and OUTB_EN to V
enables a factory test mode and forces all indicators to GND. This is not a valid
CC
mode of operation.
______________________________________________________________________________________ 11
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
Master Reset
Applications Information
After power-up, an external master reset (MR) can be
provided to reset the internal dividers. This input
requires a minimum reset pulse width of 100ns (active
low) and is asynchronous to the reference clock. While
MR is low, all clock outputs are held to logic-low (OUTxx
= low, OUTxx = high). See Table 6 for the output signal
status during master reset. When the master reset input
is deasserted (MR = 1), the PLL starts to lock to the ref-
erence clock selected by SEL_CLK.
Interfacing with LVPECL Inputs
Figure 5 shows the equivalent LVPECL input circuit for
REFCLK0, REFCLK1, and FB_IN. These inputs are
internally biased to allow AC- or DC-coupling and have
> 40kΩ differential input impedance. When AC-cou-
pled, these inputs can accept LVDS, CML, and
LVPECL signals. Unused reference clock inputs should
be left open.
MAX3671
Master reset is only needed for applications where
divider configurations are changed on the fly and the
clock outputs need to maintain phase alignment. A
master reset is not required at power-up.
Interfacing with LVPECL Outputs
Figure 6 shows the equivalent LVPECL output circuit.
These outputs are designed to drive a pair of 50Ω
transmission lines terminated with 50Ω to V = V
-
TT
CC
2V. If a separate termination voltage (V ) is not avail-
TT
External Feedback for Zero-Delay Buffer
The MAX3671 can be operated with either internal or
external PLL feedback path, controlled by the FB_SEL
input. Connecting FB_SEL to GND selects internal feed-
back. For applications where a known phase relation-
ship between the reference clock input and the external
feedback input (FB_IN, FB_IN) are needed for phase
able, other termination methods can be used such as
those shown in Figures 7 and 8. Unused outputs,
enabled or disabled, can be left open or properly termi-
nated. For more information on LVPECL terminations
and how to interface with other logic families, refer to
Application Note 291: HFAN-01.0: Introduction to LVDS,
PECL, and CML.
synchronization, connect FB_SEL to V
for zero-delay
CC
buffer configuration and provide external feedback to
the FB_IN input.
Layout Considerations
The clock inputs and outputs are critical paths for the
MAX3671, and care should be taken to minimize dis-
continuities on the transmission lines. Maintain 100Ω
differential (or 50Ω single-ended) impedance in and out
of the MAX3671. Avoid using vias and sharp corners.
Termination networks should be placed as close as
possible to receiving clock inputs. Provide space
between differential output pairs to reduce crosstalk,
especially if the A and B group outputs are operating at
different frequencies.
PLL Bypass Mode
PLL bypass mode is provided for test purposes. In PLL
bypass mode (PLL_BYPASS = 1), the selected refer-
ence clock is connected to the LVPECL clock outputs
directly. The output clock frequency is the same as the
input clock frequency and the clock qualification func-
tion is not valid. To reduce spurious jitter in bypass
mode, the internal VCO should be disabled by shorting
the CREG pin to GND.
Table 6. Output Signal Status During Power-On-Reset or Master Reset
DURING POWER-ON-RESET
(FOR ~ 20μs AFTER V > 3.0V)
DURING MASTER RESET
OUTPUT
IN0FAIL
IN1FAIL
NOTES
(MR = 0)
CC
Forced high regardless of reference
input qualification.
1
Forced high regardless of reference
input qualification.
1
1
LOCK
PLL out-of-lock.
OUTA[3:0]
OUTB[4:0]
Logic-Low
Logic-Low
—
—
12 ______________________________________________________________________________________
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3671
The 56-pin TQFN package features an exposed pad
(EP), which provides a low-resistance thermal path for
heat removal from the IC and must be connected to the
circuit board ground plane for proper operation.
Power Supply and Ground Connections
The MAX3671 has seven supply connection pins;
installation of a bypass capacitor at each supply pin is
recommended. All seven supply connections should be
driven from the same source to eliminate the possibility
of independent power-supply sequencing. Excessive
supply noise can result in increased jitter.
V
CC
V
CC
V
CC
- 1.34V
> 20kΩ
> 20kΩ
200Ω
200Ω
REFCLKx, FB_IN
REFCLKx, FB_IN
MAX3671
ESD
STRUCTURES
Figure 5. Equivalent LVPECL Input Circuit
+3.3V
+3.3V
+3.3V
+3.3V
V
CC
130Ω
Z = 50Ω
130Ω
LVPECL
LVPECL
Z = 50Ω
OUTxx
OUTxx
82Ω
82Ω
Figure 7. Thevenin Equivalent LVPECL Termination
ESD
STRUCTURES
MAX3671
Figure 6. Equivalent LVPECL Output Circuit
______________________________________________________________________________________ 13
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
+3.3V
+3.3V
0.1μF
Z = 50Ω
50Ω
LVPECL
LVPECL
0.1μF
MAX3671
50Ω
0.1μF
Z = 50Ω
150Ω
150Ω
Figure 8. AC-Coupled LVPECL Termination
Pin Configuration
TOP VIEW
56 55 54 53 52 51 50 49 48 47 46 45 44 43
IN0FAIL
RSVD1
RSVD2
REFCLK0
REFCLK0
DM
1
2
3
4
5
6
7
8
9
42 GND
41
V
CC
40 OUTA2
39 OUTA2
38 OUTA3
37 OUTA3
36 OUTA_EN
35 OUTB_EN
34 OUTB4
33 OUTB4
32 OUTB3
31 OUTB3
V
CC
MAX3671
GND
MR
REFCLK1 10
REFCLK1 11
SEL_CLK 12
VCC_VCO 13
GND 14
EP*
30
V
CC
29 GND
15 16 17 18 19 20 21 22 23 24 25 26 27 28
THIN QFN
(8mm × 8mm × 0.8mm)
*THE EXPOSED PAD OF THE TQFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND
ELECTRICAL OPERATION.
14 ______________________________________________________________________________________
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3671
Typical Application Circuits
+3.3V
0.1μF
0.1μF
0.22μF
0.1μF
0.1μF
0.1μF
156.25MHz
Z = 50Ω
Z = 50Ω
REFCLK0
REFCLK0
OUTA3
OUTA3
Z = 50Ω
50Ω
50Ω
50Ω
62.5MHz
BACKPLANE
REFERENCE
CLOCK
10GE
PHY
0.1μF
0.1μF
50Ω
0.1μF
Z = 50Ω
150Ω
150Ω
MAX3671
0.1μF
156.25MHz
REFCLK1
REFCLK1
OUTA0
OUTA0
Z = 50Ω
50Ω
50Ω
10GE
PHY
0.1μF
0.1μF
Z = 50Ω
150Ω
150Ω
DM
DA
DB
OUTA_EN
OUTB_EN
+3.3V
0.1μF
125MHz
OUTB4
Z = 50Ω
50Ω
50Ω
GBE
PHY
0.1μF
0.1μF
OUTB4
Z = 50Ω
150Ω
150Ω
SEL_CLK
PLL_BYPASS
0.1μF
125MHz
FB_IN
FB_IN
FB_SEL
MR
OUTB0
OUTB0
Z = 50Ω
50Ω
50Ω
GBE
PHY
0.1μF
0.1μF
Z = 50Ω
150Ω
150Ω
______________________________________________________________________________________ 15
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
Typical Application Circuits (continued)
4 x 156.25MHz
OUTA[3:0]
62.5MHz
MAX3671
REFCLK0 OUTB[4:0]
62.5MHz
5 x 125MHz
8kHz
8kHz
IN0
IN1
CLK0
MAX3671
MAX9450
4 x 156.25MHz
5 x 312.5MHz
2 x 125MHz
OUTA[3:0]
MAX3671
125MHz
QA
REFCLK0 OUTB[4:0]
25MHz
MAX3624
QB[1:0]
Chip Information
Package Information
For the latest package outline information and land patterns, go
PROCESS: BiCMOS
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
56 TQFN-EP
T5688+3
21-0135
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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