MAX3672 [MAXIM]
Low-Jitter 155MHz/622MHz Clock Generator; 低抖动了155MHz / 622MHz时钟发生器
| 型号： | MAX3672 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Jitter 155MHz/622MHz Clock Generator |
| 文件： | 总12页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2697; Rev 0; 12/02
Low-Jitter 155MHz/622MHz Clock Generator
General Description
Features
The MAX3672 is a low-jitter 155MHz/622MHz reference
clock generator IC designed for system clock distribution
and frequency synchronization in OC-48 and OC-192
SONET/SDH and WDM transmission systems. The
MAX3672 integrates a phase/frequency detector, an
operational amplifier (op amp), prescaler dividers, and
input/output buffers. Using an external VCO, the
MAX3672 can be configured easily as a phase-lock loop
with bandwidth programmable from 30Hz to 10kHz.
o Single +3.3V or +5.0V Supply
o Power Dissipation: 150mW at +3.3V Supply
o External VCO Center Frequencies (f
): 155MHz
VCO
to 700MHz
o Reference Clock Frequencies: f
, f
/2,
VCO VCO
f /4, f /8, f /32
VCO VCO VCO
o Main Clock Output Frequency: f
VCO
o Optional Output Clock Frequencies: f
, f
/2,
VCO VCO
The MAX3672 operates from a single +3.3V or +5.0V
supply and dissipates 150mW (typ) at 3.3V. The operat-
ing temperature range is -40°C to +85°C.
f /4, f /8
VCO VCO
o Low Intrinsic Jitter: <0.4ps
o Loss-of-Lock Indicator
RMS
o PECL Clock Output Interface
Applications
OC-12 to OC-192 SONET/WDM Transport
Systems
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
Clock Jitter Clean-Up and Frequency
Synchronization
MAX3672E/D
-40°C to +85°C
Dice*
*Dice are designed to operate from -40° to +85°C, but are test-
ed and guaranteed at T = +25° only.
Frequency Conversion
A
System Clock Distribution
Typical Application Circuit
+3.3V
VCCD
142Ω
155MHz
MOUT+
MOUT-
REFCLK+
MAX3892
+3.3V
16:1
SERIALIZER
REFCLK-
VCOIN+
142Ω
142Ω
VCO
= 25kHz/V
K
VCO
155MHz
100Ω
MAX3672
VCOIN-
RSEL
142Ω
N.C.
N.C.
VSEL
NSEL1
NSEL2
332Ω
VC
4700pF
4700pF
500kΩ
0.01µF
OPAMP-
OPAMP+
GSEL
GND
3.3V
500kΩ
V
FILTER
POLAR
REPRESENTS A
CONTROLLED-IMPEDANCE
TRANSMISSION LINE.
1000pF
SETUP FOR 10kHz LOOP
BANDWIDTH
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Jitter 155MHz/622MHz Clock Generator
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ......................................................-0.5V to +7.0V
Voltage at C2+% C2-% ꢂHADJ% CꢂH% NSEL±% NSEL2% GSEL% LOL%
RSEL% REFCLK-% REFCLK+% VSEL% VCOIN+% VCOIN-% VC%
POLAR% PSEL±% PSEL2% COMP%
PECL Output Cuꢁꢁent (MOUꢂ+%
MOUꢂ-% POUꢂ+% POUꢂ-).................................................56mA
Opeꢁating ꢂempeꢁatuꢁe Range ...........................-40°C to +85°C
Stoꢁage ꢂempeꢁatuꢁe Range.............................-65°C to +±60°C
Die-Attach Pꢁocess ꢂempeꢁatuꢁe.....................................+400°C
OPAMP+% OPAMP-..................................-0.5V to (V
+ 0.5V)
CC
Voltage at V
.................................................-0.5V to +3.0V
FILꢂER
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.3V ±±0ꢀ oꢁ V
= +5.0V ±±0ꢀ% ꢂ = -40°C to +85°C. ꢂypical values aꢁe at V
= +3.3V and ꢂ = +25°C% unless otheꢁ-
CC A
CC
CC
A
wise noted.) (Note ±)
PARAMETER
Supply Cuꢁꢁent
INPUT SPECIFICATIONS (REFCLK±% VCOIN±)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
(Note 2)
50
72
mA
CC
V
±.±6
-
V
0.88
-
CC
CC
Input High Voltage
Input Low Voltage
Input Bias Voltage
V
V
V
V
IH
V
±.8±
-
V
±.48
-
CC
CC
V
IL
V
±.3
-
CC
Common-Mode Input Resistance
Diffeꢁential Input Resistance
7.2
±2.0
300
±±.5
2±.0
±7.5
32.5
±900
kΩ
kΩ
Diffeꢁential Input Voltage Swing
PECL OUTPUT SPECIFICATIONS
AC-coupled
mV
P-P
V
-
V
0.88
-
CC
CC
0°C to +85°C
-40°C to 0°C
0°C to +85°C
-40°C to 0°C
±.025
Output High Voltage
Output Low Voltage
V
V
OH
V
-
V
0.88
-
CC
CC
±.085
V
±.8±
-
V
±.62
-
CC
CC
V
V
OL
V
±.83
-
V
-
CC
CC
±.556
TTL SPECIFICATIONS
Output High Voltage
Output Low Voltage
V
Souꢁcing 20µA
Sinking 2mA
2.4
V
V
V
OH
CC
V
0.4
OL
2
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.3V ±±0ꢀ oꢁ V
= +5.0V ±±0ꢀ% ꢂ = -40°C to +85°C. ꢂypical values aꢁe at V
= +3.3V and ꢂ = +25°C% unless otheꢁ-
CC A
CC
CC
A
wise noted.) (Note ±)
PARAMETER
OPERATIONAL AMPLIFIER SPECIFICATIONS (Note 3)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
0.3
-
-
CC
V
V
= +3.3V ±±0ꢀ
0.3
0.5
CC
CC
Op Amp Output Voltage Range
V
V
O
V
0.5
CC
= +5.0V ±±0ꢀ
Op Amp Input Offset Voltage
Op Amp Open-Loop Gain
| V
A
|
3
mV
dB
OS
90
OL
PHASE FREQUENCY DETECTOR (PFD)/CHARGE-PUMP (CP) SPECIFICATIONS (Note 4)
High gain
Low gain
High gain
Low gain
±6.0
4.0
20
5
24.4
6.2
Full-Scale PFD/CP Output
Cuꢁꢁent
| I
|
µA
ꢀ
PD
0.80
±.08
PFD/CP Offset Cuꢁꢁent
| I
|
PD
AC ELECTRICAL CHARACTERISTICS
(V
= +3.3V ±±0ꢀ oꢁ V
= +5.0V ±±0ꢀ% ꢂ = -40°C to +85°C. ꢂypical values aꢁe at V
= +3.3V and ꢂ = +25°C% unless otheꢁ-
CC A
CC
CC
A
wise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK OUTPUT SPECIFICATIONS
Clock Output Fꢁequency
700
MHz
622/3±±/
±55/78
f
f
= 622MHz
= ±55MHz
VCO
VCO
Optional Clock Output
Fꢁequency
MHz
±55/78/
38/±9
Clock Output Rise/Fall ꢂime
Clock Output Duty Cycle
Measuꢁed fꢁom 20ꢀ to 80ꢀ
(Note 6)
280
55
ps
ꢀ
45
NOISE SPECIFICATIONS
Random Noise Voltage at Loop-
Filteꢁ Output
µV
/√Hz
RMS
RMS
V
Fꢁeq > ±kHz (Note 7)
(Note 8)
±.±4
NOISE
PSR
Spuꢁious Noise Voltage at Loop-
Filteꢁ Output
50
µV
Poweꢁ-Supply Rejection at Loop-
Filteꢁ Output
(Note 9)
30
30
dB
REFERENCE CLOCK INPUT SPECIFICATIONS
Refeꢁence Clock Fꢁequency
622/
±55/78/
±9
700
70
MHz
ꢀ
Refeꢁence Clock Duty Cycle
_______________________________________________________________________________________
3
Low-Jitter 155MHz/622MHz Clock Generator
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.3V ±±0ꢀ oꢁ V
= +5.0V ±±0ꢀ% ꢂ = -40°C to +85°C. ꢂypical values aꢁe at V
= +3.3V and ꢂ = +25°C% unless otheꢁ-
CC A
CC
CC
A
wise noted.) (Note 5)
PARAMETER
PLL SPECIFICATIONS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PLL Jitteꢁ ꢂꢁansfeꢁ Bandwidth
Jitteꢁ ꢂꢁansfeꢁ Peaking
BW
(Note ±0)
≤ BW (Note ±±)
30
±0%000
0.±
Hz
dB
F
JIꢂꢂER
OPAMP SPECIFICATION
Unity-Gain Bandwidth
7
MHz
VCO INPUT SPECIFICATIONS
VCO Input Fꢁequency
f
622/±55
700
MHz
V/ns
VCO
VCO Input Slew Rate
0.5
Note 1: Specifications at -40°C aꢁe guaꢁanteed by design and chaꢁacteꢁization.
Note 2: Measuꢁed with PECL outputs unteꢁminated.
Note 3: OPAMP specifications met with ±0kΩ load to gꢁound oꢁ 5kΩ load to V (POLAR = 0 and POLAR = V ).
CC
CC
Note 4: PFD/CP cuꢁꢁents aꢁe measuꢁed fꢁom pins OPAMP+ to OPAMP-. See ꢂable 4 foꢁ gain settings.
Note 5: AC chaꢁacteꢁistics aꢁe guaꢁanteed by design and chaꢁacteꢁization.
Note 6: Measuꢁed with 50ꢀ VCO input duty cycle.
Note 7: Random noise voltage at op amp output with 800kΩ ꢁesistoꢁ connected between VC and OPAMP-% PFD/CP gain (K ) =
PD
5µA/UI% and POLAR = 0. Measuꢁed with the PLL open loop and no REFCLK oꢁ VCO input.
Note 8: Spuꢁious noise voltage due to PFD/CP output pulses measuꢁed at op amp output with R = 800kΩ% K = 5µA/UI% and com-
±
PD
paꢁe fꢁequency 400 times gꢁeateꢁ than the higheꢁ-oꢁdeꢁ pole fꢁequency (see the Design Procedure section).
Note 9: PSR measuꢁed with a ±00mV sine wave on V in a fꢁequency ꢁange fꢁom ±00Hz to 2MHz. Exteꢁnal ꢁesistoꢁs R matched
P-P
CC
±
to within ±ꢀ% exteꢁnal capacitoꢁs C matched to within ±0ꢀ. Measuꢁed closed loop with PLL bandwidth set to 200Hz.
±
Note 10:ꢂhe PLL 3dB bandwidth is adjusted fꢁom 30Hz to ±0kHz by changing exteꢁnal components R and C % by selecting the
±
±
inteꢁnal pꢁogꢁammable divideꢁ ꢁatio and phase-detectoꢁ gain. Measuꢁed with VCO gain of ±50ppm/V and C limited to 2.2µF.
±
Note 11:When input jitteꢁ fꢁequency is above PLL tꢁansfeꢁ bandwidth (BW)% the jitteꢁ tꢁansfeꢁ function ꢁolls off at -20dB/decade.
4
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
Typical Operating Characteristics
(ꢂ = +25°C% unless otheꢁwise noted.)
A
SUPPLY CURRENT
vs. TEMPERATURE
POWER-SUPPLY REJECTION
vs. FREQUENCY
OUTPUT CLOCK EDGE SPEED
vs. TEMPERATURE
0
-10
-20
-30
-40
-50
-60
70
60
50
40
30
20
270
260
250
240
230
220
210
200
190
180
170
160
150
140
BW = 1kHz
5.0V
3.3V
LOOP FILTER OUTPUT
155.52
667
-40
-20
0
20
40
60
80
1k
10k
100k
1M
10M
-40 -20
0
20
40
60
80
TEMPERATURE (°C)
FREQUENCY (Hz)
TEMPERATURE (°C)
667MHz CLOCK OUTPUT
155MHz CLOCK OUTPUT
MAX3672 toc05
MAX3672 toc04
200mV/div
200mV/div
500ps/div
2ns/div
_______________________________________________________________________________________
5
Low-Jitter 155MHz/622MHz Clock Generator
Pad Description
PAD
NAME
FUNCTION
Positive Filteꢁ Input. Exteꢁnal capacitoꢁ connected between C2+ and C2- used foꢁ setting the higheꢁ
oꢁdeꢁ pole fꢁequency (see the Setting the Higher-Order Poles section).
±
C2+
Negative Filteꢁ Input. Exteꢁnal capacitoꢁ connected between C2+ and C2- used foꢁ setting the higheꢁ
oꢁdeꢁ pole fꢁequency (see the Setting the Higher-Order Poles section).
2
C2-
3% ±0% ±6
4
VCCD
Positive Digital Supply Voltage
ꢂHADJ
ꢂhꢁeshold Adjust Input. Used to adjust the loss-of-lock thꢁeshold (see the LOL Setup section).
5% ±2% ±8% 27%
33
GND
CꢂH
Gꢁound
ꢂhꢁeshold Capacitoꢁ Input. Connect capacitoꢁ connected between CꢂH and gꢁound to contꢁol the
loss-of-lock conditions (see the LOL Setup section).
6
7
8
9
NSEL±
NSEL2
GSEL
Divide Selectoꢁ ± Input. ꢂhꢁee-level pin used to set the fꢁequency divideꢁ ꢁatio (N ) (ꢂable 3).
2
Divide Selectoꢁ 2 Input. ꢂhꢁee-level pin used to set the fꢁequency divideꢁ ꢁatio (N ) (ꢂable 3).
2
Gain Selectoꢁ Input. ꢂhꢁee-level pin used to set the phase-detectoꢁ gain (Kpd) (ꢂable 4).
Loss of Lock. LOL signals a ꢂꢂL low when the ꢁefeꢁence fꢁequency diffeꢁs fꢁom the VCO fꢁequency.
LOL signals a ꢂꢂL high when the ꢁefeꢁence fꢁequency equals the VCO fꢁequency.
±±
±3
LOL
Refeꢁence Clock Selectoꢁ Input. ꢂhꢁee-level pin used to set the pꢁe-divideꢁ ꢁatio (N ) foꢁ the input
3
ꢁefeꢁence clock (ꢂable ±).
RSEL
±4
±5
REFCLK+
REFCLK-
Positive Refeꢁence Clock Input% PECL
Negative Refeꢁence Clock Input% PECL
VCO Clock Selectoꢁ Input. ꢂhꢁee-level pin used to set the pꢁe-divideꢁ ꢁatio (N ) foꢁ the input VCO
±
clock (ꢂable 2).
±7
VSEL
±9
20
POUꢂ-
POUꢂ+
VCCO
Negative Optional Clock Output% PECL
Positive Optional Clock Output% PECL
Positive Supply Voltage foꢁ PECL Outputs
Negative Main Clock Output% PECL
Positive Main Clock Output% PECL
Negative VCO Clock Input% PECL
Positive VCO Clock Input% PECL
2±% 24
22
MOUꢂ-
MOUꢂ+
VCOIN-
VCOIN+
23
25
26
Optional Noise Filteꢁ. Connect an exteꢁnal capacitoꢁ to ꢁeduce PECL output noise (see the Typical
Application Circuit).
28
29
30
VFILꢂER
VC
Contꢁol Voltage Output. ꢂhe voltage output fꢁom the op amp that contꢁols the VCO.
Polaꢁity Contꢁol of Op Amp Input. POLAR = GND foꢁ VCOs with positive-gain tꢁansfeꢁ. POLAR = V
foꢁ VCOs with negative-gain tꢁansfeꢁ.
CC
POLAR
3±
32
34
PSEL±
PSEL2
VCCA
Optional Clock Selectoꢁ ± Input. Sets the divideꢁ ꢁatio foꢁ the optional clock output (ꢂable 5).
Optional Clock Selectoꢁ 2 Input. Sets the divideꢁ ꢁatio foꢁ the optional clock output (ꢂable 5).
Positive Analog Supply Voltage foꢁ the Chaꢁge Pump and Op Amp
Compensation Contꢁol Input. Op Amp Compensation Refeꢁence Contꢁol Input. COMP = GND foꢁ
35
COMP
VCOs whose contꢁol pin is V ꢁefeꢁenced. COMP = V foꢁ VCOs whose contꢁol pin is GND
CC CC
ꢁefeꢁenced.
36
37
OPAMP-
OPAMP+
Negative Op Amp Input% POLAR = GND
Positive Op Amp Input% POLAR = GND
6
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
Functional Diagram
C1
R1
R1
R3
VCO
K
VCO
C3
C1
LOL
THADJ
CTH
VC
COMP POLAR
OPAMP-
OPAMP+
OPAMP
LOL
REFCLK+
REFCLK-
DIV (N3)
1/2/8
DIV
(N2)
PECL
PFD/CP
Kpd
GSEL
C2-
RSEL
VSEL
DIV
(N2)
DIV (N1)
4/8/32
C2+
VCOIN+
VCOIN-
MOUT+
PECL
PECL
PECL
MOUT-
POUT+
DIV
1/2/4/8
DIVIDER
CONTROL LOGIC
MAX3672
POUT-
NSEL1
NSEL2
PSEL1
PSEL2
VFILTER
that they can be AC-coupled (Figuꢁe ± in the Interface
Schematic section). A single-ended VCO oꢁ ꢁefeꢁence
clock can also be applied.
Detailed Description
ꢂhe MAX3672 contains all the blocks needed to foꢁm a
PLL except foꢁ the VCO% which must be supplied sepa-
ꢁately. ꢂhe MAX3672 consists of input buffeꢁs foꢁ the ꢁef-
eꢁence clock and VCO% input and output clock-divideꢁ
ciꢁcuitꢁy% LOL detection ciꢁcuitꢁy phase detectoꢁ% gain-
contꢁol logic% a phase-fꢁequency detectoꢁ and chaꢁge
pump% an op amp% and PECL output buffeꢁs.
Input and Output Clock-Divider Circuitry
ꢂhe pꢁe-divideꢁs scale the input fꢁequencies of the VCO
and ꢁefeꢁence clock. Clock-divideꢁ ꢁatios N± and N3
must be chosen so that the output fꢁequencies of the
pꢁe-divideꢁs aꢁe equal. ꢂhe maximum allowable pꢁe-
divideꢁ output fꢁequency is 77.76MHz (ꢂable ±).
ꢂhis device is designed to clean up the noise on the ꢁef-
eꢁence clock input and pꢁovide a low-jitteꢁ system clock
output. ꢂhis device also suppoꢁts fꢁequency conveꢁsion.
ꢂhe main divideꢁs (N2) facilitate tuning the loop band-
width by setting the fꢁequency divideꢁ ꢁatio. ꢂhe divideꢁ
contꢁol logic can be pꢁogꢁammed to divide fꢁom ± to 256
in binaꢁy multiples (ꢂable 3). ꢂhe POUꢂ output buffeꢁ is
pꢁeceded by a clock divideꢁ that scales the main clock
output by ±% 2% 4% oꢁ 8 to pꢁovide an optional clock.
Input Buffer for Reference
Clock and VCO
ꢂhe MAX3672 contains diffeꢁential inputs foꢁ the ꢁefeꢁ-
ence clock and the VCO. ꢂhese high impedance inputs
can be DC-coupled and aꢁe inteꢁnally biased with so
_______________________________________________________________________________________
7
Low-Jitter 155MHz/622MHz Clock Generator
clock and VCO pꢁe-divideꢁs aꢁe equal. ꢂable ± shows
the divideꢁ ꢁatios and pꢁe-divideꢁ output fꢁequencies foꢁ
vaꢁious ꢁefeꢁence clock and VCO fꢁequencies.
LOL Detection Circuitry
ꢂhe MAX3672 incoꢁpoꢁates a loss-of-lock (LOL) monitoꢁ
that consists of an XOR gate% filteꢁ% and compaꢁatoꢁ with
adjustable thꢁeshold (see the LOL Setup section). A
loss-of-lock condition is signaled with a ꢂꢂL low when
the ꢁefeꢁence clock fꢁequency diffeꢁs fꢁom the VCO
fꢁequency.
Setting the Loop Bandwidth
ꢂo eliminate jitteꢁ pꢁesent on the ꢁefeꢁence clock% the
pꢁopeꢁ selection of loop bandwidth is cꢁitical. If the total
output jitteꢁ is dominated by the noise at the ꢁefeꢁence
clock input% then loweꢁing the loop bandwidth will
ꢁeduce system jitteꢁ. ꢂhe loop bandwidth (K) is a func-
Phase-Frequency Detector and
Charge Pump
tion of the VCO gain (K
)% the gain of the phase
VCO
ꢂhe phase-fꢁequency detectoꢁ incoꢁpoꢁated into the
MAX3672 pꢁoduces pulses pꢁopoꢁtional to the phase
diffeꢁence between the ꢁefeꢁence clock and the VCO
input. ꢂhe chaꢁge pump conveꢁts this pulse tꢁain to a
cuꢁꢁent signal that is fed to the op amp. ꢂhe phase
detectoꢁ gain can be set to eitheꢁ 5µA/UI oꢁ 20µA/UI
with the GSEL input (ꢂable 4).
detectoꢁ (K )% the loop filteꢁ ꢁesistoꢁ (R )% and the total
PD
±
feedback-divideꢁ ꢁatio (N = N± ✕ N2). ꢂhe loop band-
width of the MAX3672 can be appꢁoximated by:
KPDR±KVCO
K =
2πN
Op Amp
ꢂhe op amp is used to foꢁm an active PLL loop filteꢁ
capable of dꢁiving the VCO contꢁol voltage input. Using
the POLAR input% the op amp input polaꢁity can be select-
ed to woꢁk with VCOs having positive oꢁ negative gain-
tꢁansfeꢁ functions. ꢂhe COMP pin selects the op amp
inteꢁnal compensation. Connect COMP to gꢁound if the
Foꢁ stability% a zeꢁo must be added to the loop in the foꢁm
of ꢁesistoꢁ R in seꢁies with capacitoꢁ C (see the
±
±
Functional Diagram). ꢂhe location of the zeꢁo can be
appꢁoximated as:
±
f
=
Z
2πR C
± ±
VCO contꢁol voltage is V
ꢁefeꢁenced. Connect COMP
CC
to V if the VCO contꢁol voltage is gꢁound ꢁefeꢁenced.
CC
Because of the second-oꢁdeꢁ natuꢁe of the PLL jitteꢁ
tꢁansfeꢁ% peaking will occuꢁ and is pꢁopoꢁtional to f /K.
Z
Design Procedure
Setting Up the VCO and
Reference Clock
Foꢁ ceꢁtain applications% it may be desiꢁable to limit jitteꢁ
peaking in the PLL passband ꢁegion to less than 0.±dB.
ꢂhis can be achieved by setting f ≤ K/±00.
Z
ꢂhe MAX3672 accepts a ꢁange of ꢁefeꢁence clock and
VCO fꢁequencies. ꢂhe RSEL and VSEL inputs must be
set so that the output fꢁequencies of the ꢁefeꢁence
A moꢁe detailed analysis of the loop filteꢁ is located in
application note HFDN-±3.0 on www.maxim-ic.com.
Table 1. VCO and Reference Clock Setup
PRE-DIVIDER
OUTPUT FREQUENCY
(MHz)
F
F
VCO
DIVIDER N1
RSEL
INPUT
REFERENCE-
CLOCK DIVIDER N3
VOC
REF
VSEL INPUT
(MHz)
(MHz)
622.08
622.08
622.08
622.08
±55.52
±55.52
±55.52
±55.52
622.08
±55.52
77.76
OPEN
OPEN
OPEN
GND
—
8
8
GND
8
2
77.76
77.76
77.76
±9.44
––
OPEN
8
V
V
±
CC
CC
±9.44
32
—
8
±
622.08
±55.52
77.76
—
—
8
OPEN
GND
OPEN
±9.44
38.88
±9.44
V
4
2
CC
±9.44
OPEN
8
V
±
CC
8
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
ꢂhe HOP can be implemented eitheꢁ by pꢁoviding a
Table 2. RSEL and VSEL Settings
compensation capacitoꢁ C % which pꢁoduces a pole at:
2
REFERENCE-
CLOCK
DIVIDER N3
INPUT PIN
VSEL
VCO DIVIDER INPUT PIN
±
N1
RSEL
f
=
HOP
2π(20kΩ)(C )
2
V
4
8
V
±
2
8
CC
CC
oꢁ by adding a lowpass filteꢁ% consisting of R and C %
3
3
OPEN
GND
OPEN
GND
diꢁectly on the VCO tuning poꢁt% which pꢁoduces a pole at:
32
±
Table 3. Divider Logic Setup
INPUT PIN NSEL1 INPUT PIN NSEL2 DIVIDER RATIO N
f
=
HOP
2πR C
3
3
2
Using R and C might be pꢁefeꢁable foꢁ filteꢁing moꢁe
V
V
V
V
±
2
3
3
CC
CC
CC
CC
noise in the PLL% but it might still be necessaꢁy to pꢁovide
filteꢁing thꢁough C when using laꢁge values of R and N
±
OPEN
GND
2
±
4
✕ N % to pꢁevent clipping in the op amp.
2
V
OPEN
OPEN
OPEN
GND
8
CC
Setting the Optional Output
ꢂhe MAX3672 optional clock output can be set to binaꢁy
subdivisions of the main clock fꢁequency. ꢂhe PSEL±
and PSEL2 pins contꢁol the binaꢁy divisions. ꢂable 5
shows the pin configuꢁation and possible divideꢁ ꢁatios.
OPEN
GND
±6
32
64
±28
256
V
CC
OPEN
GND
GND
GND
Applications Information
PECL Interfacing
ꢂhe MAX3672 outputs (MOUꢂ+% MOUꢂ-% POUꢂ+%
POUꢂ-) aꢁe designed to inteꢁface with PECL signal levels
and should be biased appꢁopꢁiately. Pꢁopeꢁ teꢁmination
ꢁequiꢁes an exteꢁnal ciꢁcuit that pꢁovides a ꢂhevenin
equivalent of 50Ω to VCC - 2.0V and contꢁolled-imped-
ance tꢁansmission lines. ꢂo ensuꢁe best peꢁfoꢁmance%
the diffeꢁential outputs must have balanced loads. If the
optional clock output is not used% the output can be left
floating to save poweꢁ.
Table 4. Phase Detector Gain Setup
INPUT PIN GSEL
Kpd (µA/UI)
OPEN oꢁ V
GND
20
5
CC
Table 5. Optional Clock Setup
INPUT PIN
PSEL1
INPUT PIN
PSEL2
VCO TO POUT
DIVIDER RATIO
V
V
V
±
2
4
8
CC
CC
CC
Layout
ꢂhe MAX3672 peꢁfoꢁmance can be significantly affected
by ciꢁcuit boaꢁd layout and design. Use good high-
fꢁequency design techniques% including minimizing
gꢁound inductance and using fixed-impedance tꢁans-
mission lines on the ꢁefeꢁence and VCO clock signals.
Poweꢁ-supply decoupling should be placed as close to
the die as possible. ꢂake caꢁe to isolate the input fꢁom
the output signals to ꢁeduce feedthꢁough.
GND
V
GND
GND
CC
GND
Setting the Higher-Order Poles
Spuꢁious noise is geneꢁated by the phase detectoꢁ
switching at the compaꢁe fꢁequency% wheꢁe f
COMPARE
= f
/(N ✕ N ). Reduce the spuꢁious noise fꢁom the
VCO
± 2
VCO Selection
ꢂhe MAX3672 is designed to accommodate a wide
ꢁange of VCO gains% positive oꢁ negative tꢁansfeꢁ
digital phase detectoꢁ by placing a higheꢁ-oꢁdeꢁ pole
(HOP) at a fꢁequency much less than the compaꢁe fꢁe-
quency. ꢂhe HOP should% howeveꢁ% be placed high
enough in fꢁequency that it does not decꢁease the oveꢁ-
all loop-phase maꢁgin and impact jitteꢁ peaking. ꢂhese
two conditions can be met by selecting the HOP fꢁe-
slopes% and V -ꢁefeꢁenced oꢁ gꢁound-ꢁefeꢁenced con-
CC
tꢁol voltages. ꢂhese featuꢁes allow the useꢁ a wide
ꢁange of options in VCO selection; howeveꢁ% the pꢁopeꢁ
VCO must be selected to allow the clock geneꢁatoꢁ ciꢁ-
cuitꢁy to opeꢁate at the optimum levels. When selecting
quency to be (K ✕ 4) < f
the loop bandwidth.
< f
% wheꢁe K is
COMPARE
HOP
_______________________________________________________________________________________
9
Low-Jitter 155MHz/622MHz Clock Generator
Interface Schematics
V
CC
V
CC
V
- 1.3V
CC
10.5kΩ
10.5kΩ
OUT+
OUT-
REFLCK+
REFLCK-
MAX3672
MAX3672
Figure 2. Output Interface
Figure 1. Input Interface
a VCO% the useꢁ needs to take into account the VCO’s
phase noise and modulation bandwidth. Phase noise is
impoꢁtant because the phase noise above the PLL band-
width is dominated by the VCO noise peꢁfoꢁmance.
ꢂhe modulation bandwidth of the VCO contꢁibutes an
additional higheꢁ-oꢁdeꢁ pole (HOP) to the system and
should be gꢁeateꢁ than the HOP set with the exteꢁnal filteꢁ
components.
LOL
Noise Performance Optimization
Depending on the application% theꢁe aꢁe many diffeꢁent
ways to optimize the PLL peꢁfoꢁmance. ꢂhe following
aꢁe geneꢁal guidelines to impꢁove the noise on the sys-
tem output clock.
60kΩ
THADJ
0.6V
CTH
±) If the ꢁefeꢁence clock noise dominates the total sys-
tem-clock output jitteꢁ% then decꢁeasing the loop
bandwidth (K) ꢁeduces the output jitteꢁ.
60kΩ
REFCLK
VCO
2) If the VCO noise dominates the total system clock
output jitteꢁ% then incꢁeasing the loop bandwidth (K)
ꢁeduces the output jitteꢁ.
MAX3672
3) Smalleꢁ total divideꢁ ꢁatio (N± ✕ N2)% loweꢁ HOP% and
smalleꢁ R ꢁeduce the spuꢁious output jitteꢁ.
±
4) Smalleꢁ R ꢁeduces the ꢁandom noise due to the op amp.
±
Figure 3. Loss-of-Lock Indicator
10 ______________________________________________________________________________________
Low-Jitter 155MHz/622MHz Clock Generator
LOL
Setup
Bond Pad Coordinates
ꢂhe LOL output indicates if the PLL has locked onto the
ꢁefeꢁence clock using an XOR gate and compaꢁatoꢁ. ꢂhe
compaꢁatoꢁ thꢁeshold can be adjusted with ꢂHADJ% and
the XOR gate output can be filteꢁed with a capacitoꢁ
between CꢂH and gꢁound (Figuꢁe 3). When the voltage
at pin CꢂH exceeds the voltage at pin ꢂHADJ% then the
LOL output goes low and indicates that the PLL is not
locked. Note that excessive jitteꢁ on the ꢁefeꢁence clock
input at fꢁequencies above the loop bandwidth may
degꢁade LOL functionality.
PAD COORDINATES (µm)
PAD
X
Y
±
50.8
±557.3
±408.8
±±79.3
±028.±
874.2
720.4
566.5
4±2.6
258.7
50.8
2
50.8
3
50.8
4
50.8
5
50.8
6
50.8
ꢂhe useꢁ can set the amount of fꢁequency oꢁ phase dif-
feꢁence between VCO and ꢁefeꢁence clock at which
LOL indicates an out-of-lock condition. ꢂhe fꢁequency
diffeꢁence is called the beat fꢁequency. ꢂhe CꢂH pin
can be connected to an exteꢁnal capacitoꢁ% which sets
the lowpass filteꢁ fꢁequency to appꢁoximately
7
50.8
8
50.8
9
50.8
±0
±±
±2
±3
±4
±5
±6
±7
±8
±9
20
2±
22
23
24
25
26
27
28
29
30
3±
32
33
34
35
36
37
266.8
420.7
574.6
728.5
882.4
±036.2
±±90.±
±344
50.8
50.8
±
f
=
50.8
L
2πC 60kΩ
ꢂH
50.8
ꢂhis lowpass filteꢁ fꢁequency should be set about ±0
times loweꢁ then the beat fꢁequency to ensuꢁe that the
filteꢁed signal at CꢂH does not dꢁop below the ꢂHADJ
thꢁeshold voltage. Inteꢁnal compaꢁisons occuꢁ at the
pꢁe-divideꢁ output fꢁequency (see ꢂable ± foꢁ VCO and
ꢁefeꢁence clock setup). Foꢁ example% assume the pꢁe-
divideꢁ output fꢁequency is ±9.44MHz. Foꢁ a ±ppm sen-
sitivity% the minimum beat fꢁequency is ±9Hz% and the
filteꢁ should be set to ±.9Hz. Set CꢂH to ±.36uF.
50.8
50.8
50.8
±549.2
±792.2
±792.2
±792.2
±792.2
±792.2
±792.2
±792.2
±792.2
±792.2
±792.2
±565.4
±4±±.5
±257.6
±±03.7
893.2
685.3
53±.4
377.5
223.6
50.8
256
409.9
563.8
7±7.7
87±.6
±025.4
±±79.3
±333.2
±530.3
±692.3
±692.3
±692.3
±692.3
±692.3
±692.3
±692.3
±692.3
±692.3
±692.3
ꢂhe voltage at ꢂHADJ will deteꢁmine the level at which
the LOL output flags. ꢂHADJ is set to a default value of
0.6V which coꢁꢁesponds to a 45° phase diffeꢁence. ꢂhis
value can be oveꢁꢁidden by applying the desiꢁed
thꢁeshold voltage to the ꢂHADJ input. ꢂhe ꢁange of
ꢂHADJ is 0V (0°) to 2.4V (±80°).
______________________________________________________________________________________ 11
Low-Jitter 155MHz/622MHz Clock Generator
Chip Topography
Chip Information
PROCESS: GSꢂ2
SUBSꢂRAꢂE CONNECꢂED ꢂO GND
DIE ꢂHICKNESS: ±4 mils
37 36 35 34
33
32 31 30 29
28
27
1
2
C2+
C2-
GND
VCOIN+
VCOIN-
VCCD
Package Information
26
25
24
23
22
21
20
19
VCCD
3
4
5
6
7
8
9
Foꢁ the latest package outline infoꢁmation% go to
www.maxim-ic.com/packages.
THADJ
MOUT+
MOUT-
VCCD
GND
0.076"
(1.930mm)
CTH
NSEL1
NSEL2
POUT+
POUT-
GSEL
10 11 12 13 14 15 16 17
18
0.080"
(2.032mm)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integꢁated Pꢁoducts
Pꢁinted USA
is a ꢁegisteꢁed tꢁademaꢁk of Maxim Integꢁated Pꢁoducts.
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