MAX3670EGJ-T [MICROSEMI]
Clock Generator, 670MHz, CMOS, 5 X 5 MM, QFN-32;
| 型号： | MAX3670EGJ-T |
| 厂家： | 
Microsemi |
| 描述： | Clock Generator, 670MHz, CMOS, 5 X 5 MM, QFN-32 时钟 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2166; Rev 2; 9/09
Low-Jitter 155MHz/622MHz
Clock Generator
MAX3670
General Description
Features
The MAX3670 is a low-jitter 155MHz/622MHz reference
clock generator IC designed for system clock distribution
and frequency synchronization in OC-48 and OC-192
SONET/SDH and WDM transmission systems. The
MAX3670 integrates a phase/frequency detector, an
operational amplifier (op amp), prescaler dividers and
input/output buffers. Using an external VCO, the
MAX3670 can be configured easily as a phase-lock loop
with bandwidth programmable from 15Hz to 20kHz.
♦ Single +3.3V or +5.0V Supply
♦ Power Dissipation: 150mW at +3.3V Supply
♦ External VCO Center Frequencies (f
): 155MHz
VCO
to 670MHz
♦ Reference Clock Frequencies: f
♦ Main Clock Output Frequency: f
, f
/2, f /8
VCO VCO VCO
VCO
♦ Optional Output Clock Frequencies: f
, f
/2,
VCO VCO
The MAX3670 operates from a single +3.3V or +5.0V
supply, and dissipates 150mW (typ) at 3.3V. The operat-
ing temperature range is from -40°C to +85°C. The chip
is available in a 5mm ✕ 5mm, 32-pin QFN package.
f /4, f /8
VCO VCO
♦ Low Intrinsic Jitter: < 0.4ps
♦ Loss-of-Lock Indicator
RMS
♦ PECL Clock Output Interface
Applications
OC-12 to OC-192 SONET/WDM Transport
Systems
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 QFN-EP*
Clock Jitter Clean-Up and Frequency
Synchronization
MAX3670EGJ
MAX3670ETJ+
32 Thin QFN-EP*
Frequency Conversion
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
System Clock Distribution
Pin Configuration appears at end of data sheet.
Typical Application Circuit
3.3V
142Ω
155MHz
MAX3892
VCCD
MOUT+
REFCLK+
REFCLK-
16:1
SERIALIZER
MOUT-
142Ω
3.3V
142Ω
VCOIN+
VCOIN-
VCO
= 25kHz/V
155MHz
N.C.
N.C.
RSEL
VSEL
K
VCO
100Ω
MAX3670
142Ω
GSEL1
GSEL2
GSEL3
N.C.
3.3V
332Ω
4700pF
VC
0.01μF
500kΩ
OPAMP-
OPAMP+
POLAR
GND
4700pF
500kΩ
SETUP FOR 10kHz LOOP
BANDWIDTH
REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE.
1
Low-Jitter 155MHz/622MHz
Clock Generator
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range..............................................-0.5V to +7V
Voltage Range at C2+, C2-, THADJ, CTH, GSEL1, GSEL2,
GSEL3, LOL, RSEL, REFCLK-, REFCLK+, VSEL, VCOIN+,
VCOIN-, VC, POLAR, PSEL1, PSEL2, COMP,
PECL Output Current (MOUT+,
MOUT-, POUT+, POUT-).................................................56mA
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
OPAMP+, OPAMP-..................................-0.5V to (V
+ 0.5V)
CC
Continuous Power Dissipation (T = +70°C)
A
32 QFN (derate 33.3mW/°C above +70°C) .....................2.7W
32 Thin QFN (derate 34.5mW/°C above +70°C)..............2.8W
MAX3670
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.3V 10ꢀ or V
= +5.0V 10ꢀ, T = -40°C to +85°C. Typical values are at V
= +3.3V and T = +25°C, unless other-
CC A
CC
A
wise noted.) (Note 1)
PARAMETER
Supply Current
INPUT SPECIFICATIONS (REFCLK , VCOIN )
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
(Note 2)
48
72
mA
CC
V
1.16
-
V
0.88
-
CC
CC
Input High Voltage
Input Low Voltage
Input Bias Voltage
V
V
V
V
IH
V
1.81
-
V
1.48
-
CC
CC
V
IL
V
1.3
-
CC
Common-Mode Input Resistance
Differential Input Resistance
7.5
12.8
300
11.5
21.0
17.5
32.5
1900
kΩ
kΩ
Differential Input Voltage Swing
PECL OUTPUT SPECIFICATIONS
AC-coupled
mVp-p
V
-
V
0.88
-
CC
CC
0°C to +85°C
-40°C to 0°C
0°C to +85°C
-40°C to 0°C
1.025
Output High Voltage
Output Low Voltage
V
V
V
OH
V
-
V
0.88
-
CC
CC
1.085
V
1.81
-
V
1.62
-
CC
CC
V
OL
V
1.83
-
V
-
CC
CC
1.556
TTL SPECIFICATIONS
Output High Voltage
Output Low Voltage
V
Sourcing 20µA
Sinking 2mA
2.4
V
V
V
OH
CC
V
0.4
OL
2
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
MAX3670
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.3V 10ꢀ or V
= +5.0V 10ꢀ, T = -40°C to +85°C. Typical values are at V
= +3.3V and T = +25°C, unless other-
CC A
CC
A
wise noted.) (Note 1)
PARAMETER
OPERATIONAL AMPLIFIER SPECIFICATIONS (Note 3)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
0.3
-
-
CC
V
V
= +3.3V 10ꢀ
0.3
0.5
CC
CC
Op Amp Output Voltage Range
V
V
O
V
0.5
CC
= +5.0V 10ꢀ
Op Amp Input Offset Voltage
Op Amp Open-Loop Gain
| V
A
|
3
mV
dB
OS
90
OL
PHASE FREQUENCY DETECTOR (PFD)/CHARGE-PUMP (CP) SPECIFICATIONS (Note 4)
High gain
Low gain
High gain
Low gain
16
4
20
5
24.4
6.2
Full-Scale PFD/CP Output
Current
| I
|
µA
ꢀ
PD
0.80
1.08
PFD/CP Offset Current
| I
|
PD
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.3V 10ꢀ or V
= +5.0V 10ꢀ, T = -40°C to +85°C. Typical values are at V
= +3.3V and T = +25°C, unless other-
CC A
CC
A
wise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK OUTPUT SPECIFICATIONS
Clock Output Frequency
670
MHz
622/311/
155/78
f
f
= 622MHz
= 155MHz
VCO
Optional Clock Output
Frequency
MHz
155/78/
38/19
VCO
Clock Output Rise/Fall Time
Clock Output Duty Cycle
Measured from 20ꢀ to 80ꢀ
(Note 6)
280
55
ps
ꢀ
45
NOISE SPECIFICATIONS
Random Noise Voltage at Loop-
Filter Output
µV
/√Hz
RMS
RMS
V
Freq > 1kHz (Note 7)
(Note 8)
1.14
NOISE
PSR
Spurious Noise Voltage at Loop-
Filter Output
50
µV
Power-Supply Rejection at Loop-
Filter Output
(Note 9)
30
30
dB
REFERENCE CLOCK INPUT SPECIFICATIONS
Reference Clock Frequency
622/
155/78
670
70
MHz
ꢀ
Reference Clock Duty Cycle
_______________________________________________________________________________________
3
Low-Jitter 155MHz/622MHz
Clock Generator
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.3V 10ꢀ or V
= +5.0V 10ꢀ, T = -40°C to +85°C. Typical values are at V
= +3.3V and T = +25°C, unless other-
CC A
CC
A
wise noted.) (Note 5)
PARAMETER
PLL SPECIFICATIONS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PLL Jitter Transfer Bandwidth
Jitter Transfer Function
OP AMP SPECIFICATION
Unity-Gain Bandwidth
BW
(Note 10)
≤ BW (Note 11)
15
20,000
0.1
Hz
dB
F
JITTER
MAX3670
7
MHz
VCO INPUT SPECIFICATION
VCO Input Frequency
f
622/155
670
MHz
V/ns
VCO
VCO Input Slew Rate
0.5
Note 1: Specifications at -40°C are guaranteed by design and characterization.
Note 2: Measured with PECL outputs unterminated.
Note 3: OPAMP specifications met with 10kΩ load to ground or 5kΩ load to V (POLAR = 0 and POLAR = V ).
CC
CC
Note 4: PFD/CP currents are measured from pins OPAMP+ to OPAMP-. See Table 3 for gain settings.
Note 5: AC characteristics are guaranteed by design and characterization.
Note 6: Measured with 50ꢀ VCO input duty cycle.
Note 7: Random noise voltage at op amp output with 800kΩ resistor connected between VC and OPAMP-, PFD/CP gain (K ) =
PD
5µA/UI, and POLAR = 0. Measured with the PLL open loop and no REFCLK or VCO input.
Note 8: Spurious noise voltage due to PFD/CP output pulses measured at op amp output with R = 800kΩ, K = 5µA/UI, and
1
PD
compare frequency 400 times greater than the higher-order pole frequency (see Design Procedure).
Note 9: PSR measured with a 100mVp-p sine wave on V in a frequency range from 100Hz to 2MHz. External resistors R matched
CC
1
to within 1ꢀ, external capacitors C matched to within 10ꢀ. Measured closed loop with PLL bandwidth set to 200Hz.
1
Note 10:The PLL 3dB bandwidth is adjusted from 15Hz to 20kHz by changing external components R and C , by selecting the inter-
1
1
nal programmable divider ratio and phase-detector gain. Measured with VCO gain of 220ppm/V and C limited to 2.2µF.
1
Note 11:Measured at BW = 20kHz. When input jitter frequency is above PLL transfer bandwidth (BW), the jitter transfer function rolls
off at -20dB/decade.
4
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
MAX3670
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
EDGE SPEED
vs. TEMPERATURE
SUPPLY CURRENT
vs. TEMPERATURE
POWER-SUPPLY REJECTION
vs. FREQUENCY
280
270
260
250
240
230
220
210
200
190
180
170
160
150
60
0
BW = 1kHz
HOP = 5kHz
-10
5.0V
3.3V
50
-20
40
-30
-40
-50
-60
LOOP FILTER OUTPUT
622.08MHz
30
20
155.52MHz
0
-40 -20
20
40
60
80
1k
10k
100k
1M
10M
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FREQUENCY (Hz)
TEMPERATURE (°C)
622MHz CLOCK OUTPUT
(DIFFERENTIAL OUTPUT)
155MHz CLOCK OUTPUT
(DIFFERENTIAL OUTPUT)
200mV/
div
200mV/
div
500ps/div
2.0ns/div
_______________________________________________________________________________________
5
Low-Jitter 155MHz/622MHz
Clock Generator
Pin Description
PIN
NAME
FUNCTION
Positive Filter Input. External capacitor connected between C2+ and C2- used for setting the higher-
order pole frequency (see Setting the Higher-Order Poles).
1
C2+
Negative Filter Input. External capacitor connected between C2+ and C2- used for setting the higher-
order pole frequency (see Setting the Higher-Order Poles).
2
C2-
3, 9, 15
4
VCCD
Positive Digital Supply Voltage
MAX3670
THADJ
Threshold Adjust Input. Used to adjust the Loss-of-Lock threshold (see LOL Setup).
Threshold Capacitor Input. A capacitor connected between CTH and ground used to control the Loss-
of-Lock conditions (see LOL Setup).
5
6
7
8
CTH
Gain Select 1 Input. Three-level pin used to set the phase-detector gain (K ) and the frequency-
PD
GSEL1
GSEL2
GSEL3
divider ratio (N ) (see Table 3).
2
Gain Select 2 Input. Three-level pin used to set the phase-detector gain (K ) and the frequency-
PD
divider ratio (N ) (see Table 3).
2
Gain Select 3 Input. Three-level pin used to set the phase-detector gain (K ) and the frequency-
PD
divider ratio (N ) (see Table 3).
2
Loss-of-Lock. LOL signals a TTL low when the reference frequency differs from the VCO frequency.
LOL signals a TTL high when the reference frequency equals the VCO frequency.
10
11
12
LOL
GND
RSEL
Supply Ground
Reference Clock Select Input. Three-level pin used to set the predivider ratio (N ) for the input
3
reference clock (see Table 1).
Positive Reference Clock Input
Negative Reference Clock Input
REFCLK
REFCLK-
13
14
VCO Clock Select Input. Three-level pin used to set the predivider ratio (N ) for the input VCO clock
1
(see Table 2).
16
VSEL
17
18
POUT-
POUT+
VCCO
MOUT-
MOUT+
VCOIN-
VCOIN+
VC
Negative Optional Clock Output, PECL
Positive Optional Clock Output, PECL
19, 22
20
Positive Supply Voltage for PECL Outputs
Negative Main Clock Output, PECL
21
Positive Main Clock Output, PECL
23
Negative VCO Clock Input
24
Positive VCO Clock Input
25
Control Voltage Output. The voltage output from the op amp that controls the VCO.
Polarity Control Input. Polarity control of op amp input. POLAR = GND for VCOs with positive gain
transfer. POLAR = V for VCOs with negative gain transfer.
CC
26
POLAR
27
28
29
PSEL1
PSEL2
VCCA
Optional Clock Select 1 Input. Used to set the divider ratio for the optional clock output (see Table 4).
Optional Clock Select 2 Input. Used to set the divider ratio for the optional clock output (see Table 4).
Positive Analog Supply Voltage for the Charge Pump and Op Amp
Compensation Control Input. Op amp compensation reference control input. COMP = GND for VCOs
30
COMP
whose control pin is V referenced. COMP = V for VCOs whose control pin is GND referenced.
CC
CC
31
32
OPAMP-
Negative Op Amp Input (POLAR = 0), Positive Op Amp Input (POLAR = 1)
Positive Op Amp Input (POLAR = 0), Negative Op Amp Input (POLAR = 1)
OPAMP+
Exposed Pad. The exposed pad must be soldered to the circuit board ground plane for proper thermal
and electrical performance.
—
EP
6
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
MAX3670
Functional Diagram
C1
C1
R1
R3
VCO
K
VCO
C3
R1
LOL
THADJ
CTH
VC
COMP
POLAR
OPAMP-
OPAMP+
OPAMP
LOL
REFCLK+
REFCLK-
DIV
(N3)
DIV
(N2)
PFD/CP
K
PD
RSEL
VSEL
C2-
C2+
MOUT+
DIV
(N1)
DIV
(N2)
VCOIN+
VCOIN-
PECL
PECL
MOUT-
POUT+
POUT-
DIV
1/2/4/8
GAIN-CONTROL LOGIC
GSEL1 GSEL2 GSEL3
MAX3670
PSEL1 PSEL2
Input Buffer for Reference
Clock and VCO
Detailed Description
The MAX3670 contains all the blocks needed to form a
PLL except for the VCO, which must be supplied sepa-
rately. The MAX3670 consists of input buffers for the ref-
erence clock and VCO, input and output clock-divider
circuitry, LOL detection circuitry, gain-control logic, a
phase-frequency detector and charge pump, an op
amp, and PECL output buffers.
The MAX3670 contains differential inputs for the refer-
ence clock and the VCO. These inputs can be DC-cou-
pled and are internally biased with high impedance so
that they can be AC-coupled (Figure 1 in the Interface
Schematic section). A single-ended VCO or reference
clock can also be applied.
Input and Output Clock-Divider Circuitry
The reference clock and VCO input buffers are followed
by a pair of clock dividers that prescale the input fre-
quency of the reference clock and VCO to 77.76MHz.
This device is designed to clean up the noise on the
reference clock input and provide a low-jitter system
clock output.
_______________________________________________________________________________________
7
Low-Jitter 155MHz/622MHz
Clock Generator
Depending on the input clock frequency of 77.76MHz,
Table 1. Reference Clock Divider
155.52MHz, or 622.08MHz, the clock divider ratio must
be set to 1, 2, or 8, respectively. The POUT output
buffer is preceded by a clock divider that scales the
main clock output by 1, 2, 4, or 8 to provide an optional
clock.
INPUT
PIN
RSEL
REFERENCE
CLOCK INPUT
FREQ. (MHz)
PREDIVIDER
OUTPUT
FREQ. (MHz)
DIVIDER
RATIO N
3
V
77.76
155.52
622.08
1
2
8
77.76
77.76
77.76
CC
OPEN
GND
LOL Detection Circuitry
The MAX3670 incorporates a loss-of-lock (LOL) monitor
that consists of an XOR gate, filter, and comparator
with adjustable threshold (see “LOL Setup” in the
Applications section). A loss-of-lock condition is sig-
naled with a TTL low when the reference clock frequen-
cy differs from the VCO frequency.
MAX3670
The MAX3670 is designed to accept 77.76MHz,
155.52MHz, or 622.08MHz (including FEC rates) volt-
age-controlled oscillator (VCO) frequencies. The VSEL
input must be set so that the VCO input is prescaled to
77.76MHz (or FEC rate), to provide the proper range for
the PFD and LOL detection circuitry. Table 2 shows the
divider ratio for the different VCO frequencies.
Gain-Control Logic
The gain-control circuitry facilitates the tuning of the
loop bandwidth by setting phase-detector gain and fre-
quency-divider ratio. The gain-control logic can be pro-
grammed to divide from 1 to 1024, in binary multiples,
and to adjust the phase detector gain to 5µA/UI or
20µA/UI (see Table 3 in Setting the Loop Bandwidth
section).
Table 2. VCO Clock Divider
INPUT
PIN
VCO CLOCK
INPUT FREQ.
(MHz)
PREDIVIDER
OUTPUT
FREQ. (MHz)
DIVIDER
RATIO N
1
VSEL
V
77.76
155.52
622.08
1
2
8
77.76
77.76
77.76
CC
Phase-Frequency Detector and
Charge Pump
The phase-frequency detector incorporated into the
MAX3670 produces pulses proportional to the phase
difference between the reference clock and the VCO
input. The charge pump converts this pulse train to a
current signal that is fed to the op amp.
OPEN
GND
Setting the Loop Bandwidth
To eliminate jitter present on the reference clock, the
proper selection of loop bandwidth is critical. If the total
output jitter is dominated by the noise at the reference
clock input, then lowering the loop bandwidth will
reduce system jitter. The loop bandwidth (K) is a func-
Op Amp
The op amp is used to form an active PLL loop filter
capable of driving the VCO control voltage input. Using
the POLAR input, the op amp input polarity can be select-
ed to work with VCOs having positive or negative gain-
transfer functions. The COMP pin selects the op amp
internal compensation. Connect COMP to ground if the
tion of the VCO gain (K
), the gain of the phase
VCO
detector (K ), the loop filter resistor (R ), and the total
PD
1
feedback-divider ratio (N = N1 ✕ N2). The loop band-
width of the MAX3670 can be approximated by
VCO control voltage is V
referenced. Connect COMP
CC
to V if the VCO control voltage is ground referenced.
CC
K
R K
2πN
PD 1 VCO
K =
Design Procedure
Setting Up the VCO and
Reference Clock
For stability, a zero must be added to the loop in the form
of resistor R in series with capacitor C (see Functional
1
1
The MAX3670 accepts 77.76MHz, 155.52MHz, or
622.08MHz (including FEC rates) reference clock fre-
quencies. The RSEL input must be set so that the refer-
ence clock is prescaled to 77.76MHz (or FEC rate), to
provide the proper range for the PFD and LOL detec-
tion circuitry. Table 1 shows the divider ratio for the dif-
ferent reference frequencies.
Diagram). The location of the zero can be approximated as
1
f
=
Z
2πR C
1 1
Due to the second-order nature of the PLL jitter trans-
fer, peaking will occur and is proportional to f /K. For
Z
certain applications, it may be desirable to limit jitter
8
_______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
MAX3670
quency to be (K ✕ 4) < f
≤ f
, where K is
COMPARE
HOP
Table 3. Gain Logic Pin Setup
the loop bandwidth.
INPUT
PIN
INPUT
PIN
INPUT
PIN
DIVIDER
RATIO
KPD
The HOP can be implemented either by providing a
compensation capacitor C , which produces a pole at
2
(µA/UI)
GSEL1
GSEL2
GSEL3
N
2
V
V
V
V
V
V
V
V
V
V
V
V
V
20
20
20
20
20
20
20
20
20
20
20
5
1
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
1
f
=
HOP
OPEN
GND
2
4
2π(20kΩ)(C )
2
V
OPEN
OPEN
OPEN
GND
8
or by adding a lowpass filter, consisting of R and C ,
directly on the VCO tuning port, which produces a pole at
CC
3
3
OPEN
GND
16
32
1
f =
HOP
V
64
CC
2πR C
3
3
OPEN
GND
GND
128
256
512
1024
1
GND
Using R and C may be preferable for filtering more
3
3
noise in the PLL, but it may still be necessary to provide
V
V
V
V
V
V
GND
GND
CC
CC
CC
CC
CC
CC
filtering via C when using large values of R and N ✕ N
2
1
1
2
OPEN
to prevent clipping in the op amp.
V
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
GND
CC
Setting the Optional Output
The MAX3670 optional clock output can be set to bina-
ry subdivisions of the main clock frequency. The PSEL1
and PSEL2 pins control the binary divisions. Table 4
shows the pin configuration along with the possible
divider ratios.
OPEN
GND
5
2
5
4
V
OPEN
OPEN
OPEN
GND
5
8
CC
OPEN
GND
5
16
5
32
V
5
64
CC
OPEN
GND
GND
5
128
256
512
1024
Table 4. Setting the Optional Clock
Output Driver
GND
5
V
OPEN
OPEN
5
CC
INPUT PIN
PSEL1
INPUT PIN
PSEL2
VCO TO POUT
DIVIDER RATIO
OPEN
GND
5
V
V
V
1
2
4
8
CC
CC
CC
peaking in the PLL passband region to less than 0.1dB.
GND
This can be achieved by setting f ≤ K/100.
Z
V
GND
GND
CC
The three-level GSEL pins (see Functional Diagram)
GND
select the phase-detector gain (K ) and the frequency-
PD
divider ratio (N ). Table 3 summarizes the settings for
2
the GSEL pins. A more detailed analysis of the loop filter
Applications Information
.
is located in application note HFDN-13.0
PECL Interfacing
The MAX3670 outputs (MOUT+, MOUT-, POUT+,
POUT-) are designed to interface with PECL signal lev-
els. It is important to bias these ports appropriately. A
circuit that provides a Thévenin equivalent of 50Ω to
Setting the Higher-Order Poles
Spurious noise is generated by the phase detector
switching at the compare frequency, where f
COMPARE
= f
/(N ✕ N ). Reduce the spurious noise from the
VCO
1 2
V
CC
- 2V can be used with fixed-impedance transmis-
digital phase detector by placing a higher-order pole
(HOP) at a frequency much less than the compare fre-
quency. The HOP should, however, be placed high
enough in frequency that it does not decrease the over-
all loop-phase margin and impact jitter peaking. These
two conditions can be met by selecting the HOP fre-
sion lines with proper termination. To ensure best per-
formance, the differential outputs must have balanced
loads. It is important to note that if optional clock output
is not used, it should be left unconnected to save
power (see Figure 2).
_______________________________________________________________________________________
9
Low-Jitter 155MHz/622MHz
Clock Generator
quencies above the loop bandwidth may degrade LOL
Layout
The MAX3670 performance can be significantly affect-
ed by circuit board layout and design. Use good high-
frequency design techniques, including minimizing
ground inductance and using fixed-impedance trans-
mission lines on the reference and VCO clock signals.
Power-supply decoupling should be placed as close to
functionality.
The user can set the amount of frequency or phase dif-
ference between VCO and reference clock at which
LOL indicates an out-of-lock condition. The frequency
difference is called the beat frequency. The CTH pin
can be connected to an external capacitor, which sets
the lowpass filter frequency to approximately
V
pins as possible. Take care to isolate the input
CC
from the output signals to reduce feedthrough.
MAX3670
1
f =
VCO Selection
L
2πC 60kΩ
TH
The MAX3670 is designed to accommodate a wide
range of VCO gains, positive or negative transfer
This lowpass filter frequency should be set about 10
times lower than the beat frequency to make sure the
filtered signal at CTH does not drop below the THADJ
threshold voltage. The internal compare frequency of
the part is 77.78MHz. For a 1ppm sensitivity (beat fre-
quency of 77Hz), the filter needs to be at 7.7Hz, and
CTH should be at 0.33µF.
slopes, and V -referenced or ground-referenced con-
CC
trol voltages. These features allow the user a wide
range of options in VCO selection; however, the proper
VCO must be selected to allow the clock generator cir-
cuitry to operate at the optimum levels. When selecting
a VCO, the user needs to take into account the phase
noise and modulation bandwidth. Phase noise is impor-
tant because the phase noise above the PLL bandwidth
will be dominated by the VCO noise performance.
The modulation bandwidth of the VCO contributes an
additional higher-order pole (HOP) to the system and
should be greater than the HOP set with the external fil-
ter components.
The voltage at THADJ will determine the level at which
the LOL output flags. THADJ is set to a default value of
0.6V which corresponds in a 45° phase difference. This
value can be overridden by applying the desired
threshold voltage to the pin. The range of THADJ is
from 0V (0°) to 2.4V (180°).
Noise Performance Optimization
Depending on the application, there are many different
ways to optimize the PLL performance. The following
are general guidelines to improve the noise on the sys-
tem output clock.
Interface Schematics
1) If the reference clock noise dominates the total sys-
tem-clock output jitter, then decreasing the loop
bandwidth (K) reduces the output jitter.
V
CC
2) If the VCO noise dominates the total system clock
output jitter, then increasing the loop bandwidth (K)
reduces the output jitter.
V
CC
- 1.3V
3) Smaller total divider ratio (N1 ✕ N2), lower HOP, and
10.5kΩ
10.5kΩ
smaller R reduce the spurious output jitter.
1
4) Smaller R reduces the random noise due to the op amp.
1
REFLCK+
REFLCK-
LOL Setup
The LOL output indicates if the PLL has locked onto the
reference clock using an XOR gate and comparator.
The comparator threshold can be adjusted with THADJ,
and the XOR gate output can be filtered with a capaci-
tor between CTH and ground (Figure 3 in the Interface
Schematic section). When the voltage at pin CTH
exceeds the voltage at pin THADJ, then the LOL output
goes low and indicates that the PLL is not locked. Note
that excessive jitter on the reference clock input at fre-
MAX3670
Figure 1. Input Interface
10 ______________________________________________________________________________________
Low-Jitter 155MHz/622MHz
Clock Generator
MAX3670
Interface Schematics (continued)
V
CC
LOL
60kΩ
THADJ
OUT+
OUT-
0.6V
CTH
60kΩ
REFCLK
VCO
MAX3670
MAX3670
Figure 2. Output Interface
Figure 3. Loss-of-Lock Indicator
Pin Configuration
Chip Information
TRANSISTOR COUNT: 2478
Package Information
32
31
30
29
28
27
26
25
For the latest package outline information and land
patterns, go to www.microsemi.com. Note that a “+”, “#”,
or“-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of
RoHS status.
C2+
C2-
24
23
22
1
2
3
4
5
6
7
8
VCOIN+
VCOIN-
VCCO
VCCD
THADJ
21 MOUT+
20 MOUT-
19 VCCO
18 POUT+
17 POUT-
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
MAX3670
CTH
GSEL1
GSEL2
GSEL3
32 QFN-EP
G3255-1
21-0091
21-0140
32 TQFN-EP
T3255+3
*EP
9
10
11
12
13
14
15
16
QFN/TQFN
*THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND.
______________________________________________________________________________________ 11
Low-Jitter 155MHz/622MHz
Clock Generator
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
0
9/01
Initial release.
—
Added the PKG CODE column to the Ordering Information table; updated the
package outline drawing in the Package Information section.
1
2
5/03
9/09
1, 12
1, 11
Added the lead(Pb)-free TQFN package to the Ordering Information table; replaced
the package outline drawing with a table in the Package Information section.
MAX3670
ꢀ ꢀ 12
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
Fax: +1 (949) 215-4996
相关型号：
MAX3670ETJ+D
Clock Generator, 670MHz, CMOS, 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220WHHD-2, TQFN-32
MICROSEMI
MAX3670ETJ+TD
Clock Generator, 670MHz, CMOS, 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220WHHD-2, TQFN-32
MICROSEMI
©2020 ICPDF网 联系我们和版权申明