MAX3670EVKIT [MAXIM]

Evaluation Kit for the MAX3670 ; 评估板MAX3670\n
MAX3670EVKIT
型号: MAX3670EVKIT
厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述:

Evaluation Kit for the MAX3670
评估板MAX3670\n

文件: 总6页 (文件大小:350K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
19-2265; Rev 0; 12/01  
MAX3670 Evaluation Kit  
General Description  
Features  
Fully Assembled and Tested  
5.0V Operation  
The MAX3670 evaluation kit (EV kit) is an assembled,  
surface-mount demonstration board that provides easy  
evaluation of the MAX3670155MHz to 670MHz refer-  
ence clock generator. The EV kit comes with external  
components and a 622.08MHz voltage-controlled crys-  
tal oscillator (VCXO).  
Ordering Information  
Component Suppliers  
PART  
TEMP RANGE  
IC PACKAGE  
SUPPLIER  
AVX  
PHONE  
FAX  
MAX3670EVKIT  
*Exposed pad  
-40°C to +85°C  
32 QFN-EP*  
843-448-9411  
408-224-8566  
770-436-1300  
1-88-VECTRON-1  
843-448-1943  
Coilcraft  
Murata  
408-224-6304  
770-436-3030  
Vectron  
1-888-PAX-VECTRON  
Electrical Component List  
DESIGNATION  
QTY  
DESCRIPTION  
DESIGNATION  
QTY  
DESCRIPTION  
C1, C4–C9,  
C12, C15, C16,  
C20, C22,  
R1, R11, R12,  
R13, R18R21,  
R23, R24, R26,  
R27, R29, R31  
0.1µF 10% ceramic capacitors  
(0402)  
17  
2
0
Open  
C31–C35  
0.015µF 10% ceramic  
capacitors (0805)  
R1A, R1B  
R2  
2
1
200k1% resistors (0402)  
1001% resistor (0402)  
C1A, C1B  
C2, C3, C3A,  
C10, C11, C14,  
C19, C21,  
C23–C27, C29,  
C30  
R3, R4, R6, R8,  
R10, R16, R17  
7
3321% resistors (0402)  
0
Open  
R5, R7, R9,  
R14, R15, R22,  
R28, R30, R32  
9
1
1
0resistors (0402)  
6800pF 10% ceramic  
capacitor (0805)  
C3B  
C13  
1
1
U1  
MAX3670EGJ 32 QFN-EP  
622.08MHz voltage-controlled  
SAW oscillator  
1µF 10% ceramic capacitor  
(0805)  
Y1  
Vectron VS500A622  
C17  
1
9
10µF 10% tantalum capacitor  
SMA connectors (edge-mount)  
None  
None  
None  
1
1
1
MAX3670 EV kit circuit board  
MAX3670 EV kit data sheet  
MAX3670 data sheet  
J1–J8, J11  
J9, J10, J12,  
J15, J16  
0
2
Open  
J13, J14  
Test points  
1 × 3-pin headers  
Shunts  
JU1–JU5,  
JU7–JU10  
9
JU1–JU13  
13  
4
JU6, JU11,  
JU12, JU13  
1 × 2-pin headers  
L1, L3, L4  
L2  
0
1
Open  
56nH inductor  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
MAX3670 Evaluation Kit  
6) Connect ground to GND.  
Quick Start  
1) Install shunts JU1, JU4, JU5, JU7, and JU10  
between pins 1 and 2.  
7) Apply a 1V  
differential clock input at 622.08MHz  
P-P  
to REFCLK+ and REFCLK-.  
8) Monitor MOUT+ and MOUT- with a 50system. A  
622.08MHz clock signal appears on the oscillo-  
scope.  
2) Install shunts JU11, JU12, and JU13.  
3) Open shunts JU3 and JU6.  
4) Install shunts JU2, JU8, and JU9 between pins 2  
and 3.  
5) Connect a 5V power supply to VCCA.  
Adjustment and Control Descriptions*  
COMPONENT  
NAME  
FUNCTION  
Sets the phase-detector gain (K ) and the frequency divider ratio (N ).  
PD  
2
JU1  
GSEL1  
Shunting between pins 1 and 2 sets to GND. Shunting between pins 2 and 3  
sets to V (see Table 1).  
CC  
Sets the phase-detector gain (K ) and the frequency divider ratio (N ).  
PD  
2
Shunting between pins 1 and 2 sets to GND. Shunting between pins 2 and 3  
sets to V (see Table 1).  
JU2  
GSEL2  
CC  
Sets the phase-detector gain (K ) and the frequency divider ratio (N ).  
PD  
2
Shunting between pins 1 and 2 sets to GND. Shunting between pins 2 and 3  
sets to V (see Table 1).  
JU3  
JU4  
GSEL3  
RSEL  
CC  
Sets the predivider ratio for the reference input clock. Shunting between pins 1  
and 2 sets to GND. Shunting between pins 2 and 3 sets to V (see Table 2).  
CC  
Sets the predivider ratio for the VCO input clock. Shunting between pins 1 and 2  
sets to GND. Shunting between pins 2 and 3 sets to V (see Table 3).  
CC  
JU5  
JU6  
VSEL  
Open when VCO is activated. Closed when VCO is disabled.  
Sets the internal compensation of the op amp. Shunting between pins 1 and 2  
sets the compensation to GND. Shunting between pins 2 and 3 sets the  
JU7  
COMP  
compensation to V  
.
CC  
Sets the output clock divider. Shunting between pins 1 and 2 sets to GND.  
Shunting between pins 2 and 3 sets to V (see Table 4).  
JU8  
JU9  
PSEL2  
PSEL1  
POLAR  
CC  
Sets the output clock divider. Shunting between pins 1 and 2 sets to GND.  
Shunting between pins 2 and 3 sets to V (see Table 4).  
CC  
Sets the polarity of the op amp. Shunting between pins 1 and 2 sets the  
polarity to GND. Shunting between pins 2 and 3 sets the polarity to V  
JU10  
.
CC  
*See Quick Start first.  
2
_______________________________________________________________________________________  
MAX3670 Evaluation Kit  
Adjustment and Control Descriptions (continued)  
COMPONENT  
JU11  
NAME  
FUNCTION  
Ensure that shunt is installed.  
JU12  
Ensure that shunt is installed.  
JU13  
Ensure that shunt is installed.  
Table 1. Gain Logic Pin Setup  
Table 2. Reference Clock Divider  
INPUT  
PIN  
GSEL1  
INPUT  
PIN  
GSEL2  
INPUT  
PIN  
GSEL3  
REFERENCE  
CLOCK INPUT  
FREQ (MHz)  
DIVIDER  
RATIO  
(N )  
3
PREDIVIDER  
OUTPUT  
FREQ (MHz)  
K
DIVIDER  
RATIO N  
INPUT  
PIN RSEL  
PD  
(µA/UI)  
V
V
V
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
5
1
2
V
77.76  
155.52  
622.08  
1
2
8
77.76  
77.76  
77.76  
CC  
CC  
CC  
CC  
OPEN  
GND  
V
V
OPEN  
GND  
CC  
CC  
V
V
4
CC  
CC  
V
OPEN  
OPEN  
OPEN  
GND  
V
V
V
V
V
V
8
CC  
CC  
CC  
CC  
CC  
CC  
CC  
OPEN  
GND  
16  
32  
64  
128  
256  
512  
1024  
1
Table 3. VCO Clock Divider  
V
CC  
VCO CLOCK  
INPUT FREQ  
(MHz)  
DIVIDER  
RATIO  
(N )  
1
PREDIVIDER  
OUTPUT  
FREQ (MHz)  
INPUT  
PIN VSEL  
OPEN  
GND  
GND  
GND  
V
V
V
V
V
V
GND  
GND  
CC  
CC  
CC  
CC  
CC  
CC  
V
77.76  
155.52  
622.08  
1
2
8
77.76  
77.76  
77.76  
CC  
OPEN  
OPEN  
GND  
V
OPEN  
OPEN  
OPEN  
OPEN  
OPEN  
OPEN  
OPEN  
OPEN  
OPEN  
GND  
CC  
OPEN  
GND  
5
2
5
4
V
OPEN  
OPEN  
OPEN  
GND  
5
8
CC  
Table 4. Optional Clock Output Divider  
OPEN  
GND  
5
16  
32  
64  
128  
256  
512  
1024  
5
INPUT PIN  
PSEL1  
INPUT PIN  
PSEL2  
VCO TO POUT  
DIVIDE RATIO  
V
5
CC  
OPEN  
GND  
GND  
5
V
V
V
1
2
4
8
CC  
CC  
CC  
GND  
5
GND  
V
OPEN  
OPEN  
5
CC  
V
GND  
GND  
CC  
OPEN  
GND  
5
GND  
_______________________________________________________________________________________  
3
MAX3670 Evaluation Kit  
V S E L  
V C  
P O 1  
V C C D  
R E F C L K -  
P S E L 1  
P S E L 2  
V C C A  
C O M P  
A M O P P -  
A M O P P +  
R E F C L K +  
R S E L  
G N D  
L O L  
V C C D  
Figure 1. MAX3670 EV Kit Schematic  
4
_______________________________________________________________________________________  
MAX3670 Evaluation Kit  
1.0"  
1.0"  
Figure 2. MAX3670 EV Kit Component Placement Guide—  
Component Side  
Figure 3. MAX3670 EV Kit Component Placement Guide—  
Solder Side  
1.0"  
1.0"  
Figure 5. MAX3670 EV Kit PC Board Layout—Solder Side  
Figure 4. MAX3670 EV Kit PC Board Layout—Component Side  
_______________________________________________________________________________________  
5
MAX3670 Evaluation Kit  
1.0"  
1.0"  
Figure 6. MAX3670 EV Kit PC Board Layout—Ground Plane  
Figure 7. MAX3670 EV Kit PC Board Layout—Power Plane  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600  
© 2001 Maxim Integrated Products  
Printed USA  
is a registered trademark of Maxim Integrated Products.  

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