MAX146BMJP [MAXIM]
+2.7Low-Power, 8-Channel, Serial 12-Bit ADCs; + 2.7Low功耗， 8通道，串行12位ADC
| 型号： | MAX146BMJP |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +2.7Low-Power, 8-Channel, Serial 12-Bit ADCs |
| 文件： | 总24页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0465; Rev 1; 6/97
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX146/MAX147 12-bit data-acquisition systems
c omb ine a n 8-c ha nne l multip le xe r, hig h-b a nd wid th
track/hold, and serial interface with high conversion
speed and low power consumption. The MAX146 oper-
ates from a single +2.7V to +3.6V supply; the MAX147
operates from a single +2.7V to +5.25V supply. Both
devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
♦ 8-Channel Single-Ended or 4-Channel
Differential Inputs
♦ Single-Supply Operation:
+2.7V to +3.6V (MAX146)
+2.7V to +5.25V (MAX147)
♦ Internal 2.5V Reference (MAX146)
♦ Low Power: 1.2mA (133ksps, 3V supply)
54µA (1ksps, 3V supply)
The 4-wire serial interface connects directly to SPI™/
QSPI™ and Microwire™ devices without external logic. A
serial strobe output allows direct connection to TMS320-
family digital signal processors. The MAX146/MAX147
use either the internal clock or an external serial-interface
clock to perform successive-approximation analog-to-
digital conversions.
1µA (power-down mode)
♦ SPI/QSPI/Microwire/TMS320-Compatible
4-Wire Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 20-Pin DIP/SSOP Packages
The MAX146 has an internal 2.5V reference, while the
MAX147 requires an external reference. Both parts have
a re fe re nc e -b uffe r a mp lifie r with a ± 1.5% volta g e -
adjustment range.
______________Ord e rin g In fo rm a t io n
INL
(LSB)
PART†
TEMP. RANGE PIN-PACKAGE
These devices provide a hard-wired SHDN pin and a
s oftwa re -s e le c ta b le p owe r-d own, a nd c a n b e p ro-
grammed to automatically shut down at the end of a con-
version. Accessing the serial interface automatically
powers up the MAX146/MAX147, and the quick turn-on
time allows them to be shut down between all conver-
sions. This technique can cut supply current to under
60µA at reduced sampling rates.
MAX146ACPP
MAX146BCPP
MAX146ACAP
MAX146BCAP
MAX146BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
±1/2
±1
±1/2
±1
20 SSOP
Dice*
±1
Ordering Information continued at end of data sheet.
Contact factory for availability of alternate surface-mount
packages.
†
The MAX146/MAX147 are available in 20-pin DIP and
SSOP packages.
*Dice are specified at T = +25°C, DC parameters only.
A
For 4-c ha nne l ve rs ions of the s e d e vic e s , s e e the
MAX1246/MAX1247 data sheet.
__________Typ ic a l Op e ra t in g Circ u it
________________________Ap p lic a t io n s
+3V
Portable Data Logging
Medical Instruments
Pen Digitizers
Data Acquisition
V
DD
V
CH0
DD
0.1µF
Battery-Powered Instruments
Process Control
0V TO
+2.5V
ANALOG
INPUTS
DGND
MAX146
AGND
COM
CPU
CH7
I/O
VREF
CS
4.7µF
SCLK
SCK (SK)
MOSI (SO)
MISO (SI)
Pin Configuration appears at end of data sheet.
DIN
DOUT
REFADJ
0.047µF
SSTRB
SHDN
V
SS
SPI and QSPI are registered trademarks of Motorola, Inc.
Microwire is a registered trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
ABSOLUTE MAXIMUM RATINGS
V
to AGND, DGND................................................. -0.3V to 6V
SSOP (derate 8.00mW/°C above +70°C) ................... 640mW
CERDIP (derate 11.11mW/°C above +70°C).............. 889mW
Operating Temperature Ranges
DD
AGND to DGND...................................................... -0.3V to 0.3V
CH0–CH7, COM to AGND, DGND ............ -0.3V to (V + 0.3V)
DD
VREF, REFADJ to AGND ........................... -0.3V to (V + 0.3V)
Digital Inputs to DGND .............................................. -0.3V to 6V
MAX146_C_P/MAX147_C_P .............................. 0°C to +70°C
MAX146_E_P/MAX147_E_P............................ -40°C to +85°C
MAX146_MJP/MAX147_MJP ........................ -55°C to +125°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10sec) ............................ +300°C
DD
Digital Outputs to DGND ........................... -0.3V to (V + 0.3V)
DD
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (T = +70°C)
A
Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +2.7V to +3.6V (MAX146); V = +2.7V to +5.25V (MAX147); COM = 0V; f = 2.0MHz; external clock (50% duty cycle); 15
DD
DD
SCLK
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500 V applied to
6/MAX147
VREF pin; T = T
to T ; unless otherwise noted.)
A
MIN
MAX
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
12
Bits
MAX14_A
MAX14_B
±0.5
LSB
±1.0
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
DNL
No missing codes over temperature
±1
±3
±4
±4
LSB
MAX14_A
MAX14_B
±0.5
±0.5
LSB
Gain Error (Note 3)
±0.5
LSB
Gain Temperature Coefficient
±0.25
ppm/°C
Channel-to-Channel Offset
Matching
±0.25
LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
SINAD
THD
70
73
-88
90
dB
dB
Up to the 5th harmonic
-80
SFDR
80
dB
65kHz, 2.500V (Note 4)
p-p
-85
2.25
1.0
dB
-3dB rolloff
MHz
MHz
Full-Power Bandwidth
CONVERSION RATE
5.5
35
6
7.5
65
Internal clock, SHDN = FLOAT
Conversion Time (Note 5)
t
µs
Internal clock, SHDN = V
CONV
DD
External clock = 2MHz, 12 clocks/conversion
Track/Hold Acquisition Time
Aperture Delay
t
1.5
µs
ns
ps
ACQ
30
<50
1.8
Aperture Jitter
SHDN = FLOAT
Internal Clock Frequency
External Clock Frequency
MHz
MHz
0.225
SHDN = V
DD
0.1
0
2.0
2.0
Data transfer only
2
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +3.6V (MAX146); V = +2.7V to +5.25V (MAX147); COM = 0V; f = 2.0MHz; external clock (50% duty cycle); 15
DD
DD
SCLK
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500 V applied to
VREF pin; T = T
to T ; unless otherwise noted.)
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
ANALOG/COM INPUTS
Unipolar, COM = 0V
Bipolar, COM = VREF / 2
On/off leakage current, V
0 to VREF
Input Voltage Range, Single-
Ended and Differential (Note 6)
V
±VREF / 2
±1
Multiplexer Leakage Current
Input Capacitance
= 0V or V
±0.01
16
µA
pF
CH_
DD
INTERNAL REFERENCE (MAX146 only, reference buffer enabled)
VREF Output Voltage
T
A
= +25°C
2.480
2.500
2.520
30
V
VREF Short-Circuit Current
mA
MAX146_C
MAX146_E
MAX146_M
±30
±30
±30
0.35
±50
VREF Temperature Coefficient
±60 ppm/°C
±80
mV
Load Regulation (Note 7)
Capacitive Bypass at VREF
0mA to 0.2mA output load
Internal compensation mode
External compensation mode
0
µF
4.7
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
0.047
µF
%
±1.5
EXTERNAL REFERENCE AT VREF (Buffer disabled)
VREF Input Voltage Range
(Note 8)
V
50mV
+
DD
V
1.0
18
VREF Input Current
VREF = 2.500V
100
25
150
µA
kΩ
µA
VREF Input Resistance
Shutdown VREF Input Current
0.01
10
V
0.5
-
DD
REFADJ Buffer Disable Threshold
EXTERNAL REFERENCE AT REFADJ
Capacitive Bypass at VREF
V
Internal compensation mode
External compensation mode
MAX146
0
µF
V/V
µA
4.7
2.06
2.00
Reference Buffer Gain
REFADJ Input Current
MAX147
MAX146
±50
±10
MAX147
_______________________________________________________________________________________
3
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +3.6V (MAX146); V = +2.7V to +5.25V (MAX147); COM = 0V; f = 2.0MHz; external clock (50% duty cycle); 15
DD
DD
SCLK
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500 V applied to
VREF pin; T = T
to T ; unless otherwise noted.)
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
V
≤ 3.6V
2.0
3.0
DD
V
IH
V
DIN, SCLK, CS Input High Voltage
V
DD
> 3.6V, MAX147 only
V
0.8
V
V
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance
SHDN Input High Voltage
SHDN Input Mid Voltage
IL
V
HYST
0.2
I
IN
V
= 0V or V
±0.01
±1
15
µA
pF
V
IN DD
C
(Note 9)
IN
V
SH
V
- 0.4
DD
1
V
SM
1.1
V
DD
- 1.1
0.4
V
V
SL
V
SHDN Input Low Voltage
I
SHDN = 0V or V
±4.0
µA
V
SHDN Input Current
S
DD
V
FLT
SHDN = FLOAT
V
DD
/ 2
SHDN Voltage, Floating
SHDN Maximum Allowed
Leakage, Mid Input
SHDN = FLOAT
±100
nA
DIGITAL OUTPUTS (DOUT, SSTRB)
I
= 5mA
0.4
0.8
SINK
Output Voltage Low
V
OL
V
I
= 16mA
SINK
Output Voltage High
V
OH
I
= 0.5mA
V - 0.5
DD
V
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
I
±0.01
±10
15
µA
pF
CS = V
L
DD
C
CS = V (Note 9)
OUT
DD
MAX146
MAX147
2.70
2.70
3.60
5.25
2.0
70
Positive Supply Voltage
V
V
DD
Operating mode, full-scale input
= 3.6V Fast power-down
1.2
30
mA
µA
Positive Supply Current, MAX146
I
DD
V
DD
Full power-down
1.2
1.8
0.9
2.1
1.2
10
V
DD
= 5.25V
= 3.6V
= 5.25V
= 3.6V
2.5
1.5
15
Operating mode,
full-scale input
Positive Supply Current, MAX147
Positive Supply Current, MAX147
Supply Rejection (Note 10)
I
DD
mA
V
DD
V
DD
µA
I
DD
Full power-down
V
DD
10
Full-scale input, external reference = 2.500V,
= 2.7V to V
PSR
±0.3
mV
V
DD
DD(MAX)
4
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
TIMING CHARACTERISTICS
(V = +2.7V to +3.6V (MAX146); V = +2.7V to +5.25V (MAX147); T = T
to T
; unless otherwise noted.)
DD
DD
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
1.5
100
0
TYP
MAX UNITS
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
t
µs
ns
ns
ACQ
t
DS
t
DH
MAX14_ _C/E
MAX14_ _M
20
200
ns
SCLK Fall to Output Data Valid
t
Figure 1
DO
20
240
t
Figure 1
Figure 2
240
240
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
DV
t
TR
t
100
0
CSS
CSH
t
SCLK Pulse Width High
SCLK Pulse Width Low
t
200
200
CH
t
CL
SCLK Fall to SSTRB
t
Figure 1
240
240
240
SSTRB
t
External clock mode only, Figure 1
External clock mode only, Figure 2
Internal clock mode only (Note 9)
CS Fall to SSTRB Output Enable
CS Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
SDV
t
STR
t
0
SCK
Note 1: Tested at V = 2.7V; COM = 0V; unipolar single-ended input mode.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX146—internal reference, offset nulled; MAX147—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to V
.
DD
Note 7: External load should not change during conversion for specified accuracy.
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9: Guaranteed by design. Not subject to production testing.
Note 10: Measured as V (2.7V) - V (V
) .
|
FS
FS
|
DD, MAX
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = 3.0V, VREF = 2.500V, f
= 2.0MHz, C
= 20pF, T = +25°C, unless otherwise noted.)
A
DD
SCLK
LOAD
INTEGRAL NONLINEARITY
vs. CODE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.50
0.5
0.4
0.3
0.50
0.45
0.40
0.35
0.30
0.25
0.20
V
DD
= 2.7V
0.45
0.40
0.35
0.30
0.25
0.20
0.15
MAX146
MAX147
0.2
0.1
MAX146
0
-0.1
MAX147
60
-0.2
-0.3
0.15
0.10
0.10
0.05
0
-0.4
-0.5
0.05
0
0
1024
2048
3072
4096
-60
-20
20
100
140
2.25 2.75 3.25 3.75 4.25 4.75 5.25
CODE
V
DD
(V)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = 3.0V, VREF = 2.500V, f
= 2.0MHz, C
= 20pF, T = +25°C, unless otherwise noted.)
A
DD
SCLK
LOAD
MAX146
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.00
1.75
1.50
1.25
1.00
0.75
0.50
3.5
3.0
2.5
2.0
2.5020
R = ∞
CODE = 101010100000
L
FULL POWER-DOWN
C
= 50pF
LOAD
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
MAX146
1.5
1.0
0.5
0
C
= 20pF
LOAD
6/MAX147
MAX147
2.25 2.75 3.25 3.75 4.25 4.75 5.25
2.25 2.75 3.25 3.75 4.25 4.75 5.25
2.25 2.75 3.25 3.75 4.25 4.75 5.25
SUPPLY VOLTAGE (V)
V
DD
(V)
V
DD
(V)
MAX146
SHUTDOWN CURRENT
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
2.0
2.501
1.3
1.2
1.1
1.0
2.500
2.499
MAX146
V
DD
= 3.6V
1.6
1.2
0.8
0.4
V
= 2.7V
DD
2.498
2.497
2.496
MAX147
0.9
0.8
2.495
2.494
R
= ∞
LOAD
CODE = 101010100000
-60 -20 20
TEMPERATURE (°C)
0
60
100
140
-60
-20
20
60
100
140
-60
-20
20
60
100
140
TEMPERATURE (°C)
TEMPERATURE (°C)
EFFECTIVE NUMBER OF BITS
vs. FREQUENCY
FFT PLOT
12.0
20
V
DD
= 2.7V
V
DD
= 2.7V
f
= 10kHz
IN
0
f
= 133kHz
11.8
11.6
11.4
11.2
11.0
SAMPLE
-20
-40
-60
-80
-100
-120
1
10
100
0
10
20 30
40
50
60
70
FREQUENCY (kHz)
FREQUENCY (kHz)
6
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = 3.0V, VREF = 2.500V, f
= 2.0MHz, C
= 20pF, T = +25°C, unless otherwise noted.)
LOAD A
DD
SCLK
GAIN ERROR
vs. SUPPLY VOLTAGE
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE
OFFSET vs. SUPPLY VOLTAGE
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
2.75 3.25 3.75 4.25 4.75 5.25
2.25
2.25 2.75 3.25 3.75 4.25 4.75 5.25
2.25
2.75 3.25 3.75 4.25 4.75 5.25
V
DD
(V)
V
DD
(V)
V
DD
(V)
GAIN ERROR
vs. TEMPERATURE
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
OFFSET vs. TEMPERATURE
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
-55
-5 20 45 70 95 120 145
-30
-55 -30
-5 20 45 70 95 120 145
TEMPERATURE (˚C)
-5
20 45
TEMPERATURE (˚C)
-55 -30
70 95 120 145
TEMPERATURE (˚C)
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
0.50
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
2.25 2.75 3.25 3.75 4.25 4.75 5.25
-30 -5
-55
20 45 70 95 120 145
TEMPERATURE (˚C)
V
(V)
DD
_______________________________________________________________________________________
7
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1–8
CH0–CH7
Sampling Analog Inputs
Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
9
COM
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX146/MAX147 down; otherwise, they are
fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode.
Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
10
SHDN
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX146 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
11
VREF
REFADJ to V
.
DD
12
13
14
15
REFADJ
AGND
DGND
DOUT
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
.
DD
6/MAX147
Analog Ground
Digital Ground
Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX146/MAX147 begin the
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external clock
mode).
16
SSTRB
17
18
DIN
Serial Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
CS
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
19
20
SCLK
V
DD
Positive Supply Voltage
V
DD
V
DD
6k
6k
C
DOUT
DOUT
DOUT
DOUT
C
50pF
C
50pF
C
LOAD
50pF
LOAD
LOAD
LOAD
6k
6k
50pF
DGND
a) High-Z to V and V to V
OH
DGND
DGND
DGND
b) High-Z to V and V to V
OL
OH
OL
OL
OH
a) V to High-Z
OH
b) V to High-Z
OL
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
8
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
_______________De t a ile d De s c rip t io n
The MAX146/MAX147 a na log -to-d ig ita l c onve rte rs
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible ser-
ial interface provides easy interface to microprocessors
(µPs). Fig ure 3 is a bloc k d ia g ra m of the MAX146/
MAX147.
on C
as a sample of the signal at IN+.
HOLD
The conversion interval begins with the input multiplex-
er switching C from the positive input (IN+) to the
HOLD
negative input (IN-). In single-ended mode, IN- is sim-
ply COM. This unbalances node ZERO at the compara-
tor’s inp ut. The c a p a c itive DAC a d jus ts d uring the
re ma ind e r of the c onve rs ion c yc le to re s tore nod e
ZERO to 0V within the limits of 12-bit resolution. This
P s e u d o -Diffe re n t ia l In p u t
The sampling architecture of the ADC’s analog com-
p a ra tor is illus tra te d in the e q uiva le nt inp ut c irc uit
(Fig ure 4). In s ing le -e nd e d mod e , IN+ is inte rna lly
switched to CH0–CH7, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from the fol-
lowing p a irs : CH0/CH1, CH2/CH3, CH4/CH5, a nd
CH6/CH7. Configure the channels with Tables 2 and 3.
action is equivalent to transferring a 16pF x [(V ) -
IN+
(V -)] c ha rg e from C
IN
to the b ina ry-we ig hte d
HOLD
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Tra c k /Ho ld
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-| is sampled. At the end of the
conversion, the positive input connects back to IN+,
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
b le within ± 0.5LSB (± 0.1LSB for b e s t re s ults ) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
. The
HOLD
and C
charges to the input signal.
HOLD
acquisition interval spans three SCLK cycles and ends
18
CS
19
SCLK
12-BIT CAPACITIVE DAC
INPUT
SHIFT
INT
17
10
DIN
CLOCK
VREF
REGISTER
CONTROL
LOGIC
COMPARATOR
SHDN
INPUT
MUX
C
HOLD
ZERO
HOLD
–
+
1
2
3
4
5
6
7
8
CH0
15
16
CH0
CH1
CH2
CH3
CH4
CH5
OUTPUT
SHIFT
DOUT
CH1
CH2
CH3
CH4
CH5
CH6
CH7
16pF
REGISTER
SSTRB
R
9k
IN
ANALOG
INPUT
MUX
T/H
C
SWITCH
CLOCK
IN
12-BIT
SAR
ADC
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
CH6
CH7
OUT
T/H
SWITCH
20
14
REF
V
DD
9
COM
A ≈ 2.06*
+1.21V
DGND
AGND
COM
20k
REFERENCE
(MAX146)
13
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
12
11
REFADJ
VREF
MAX146
MAX147
+2.500V
*A ≈ 2.00 (MAX147)
Figure 3. Block Diagram
Figure 4. Equivalent Input Circuit
_______________________________________________________________________________________
9
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
The time required for the T/H to acquire an input signal
An a lo g In p u t P ro t e c t io n
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
Internal protection diodes, which clamp the analog input
to V and AGND, allow the channel input pins to swing
DD
from AGND - 0.3V to V
+ 0.3V without d a ma g e .
DD
However, for accurate conversions near full scale, the
t
, is the maximum time the device takes to acquire
inputs must not exceed V by more than 50mV or be
ACQ
DD
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
t
= 9 x (R + R ) x 16pF
S IN
ACQ
where R = 9kΩ, R = the source impedance of the
IN
S
Qu ic k Lo o k
To quickly evaluate the MAX146/MAX147’s analog per-
formance, use the circuit of Figure 5. The MAX146/
MAX147 require a control byte to be written to DIN
before each conversion. Tying DIN to +3V feeds in con-
trol bytes of $FF (HEX), which trigger single -ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In exter-
nal clock mode, the SSTRB output pulses high for one
clock period before the most significant bit of the 12-bit
conversion result is shifted out of DOUT. Varying the
analog input to CH7 will alter the sequence of bits from
DOUT. A total of 15 clock cycles is required per con-
version. All transitions of the SSTRB and DOUT outputs
occur on the falling edge of SCLK.
input signal, and t
is never less than 1.5µs. Note
ACQ
that source impedances below 1kΩ do not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
inp ut s ourc e imp e d a nc e , limiting the ADC’s s ig na l
bandwidth.
6/MAX147
In p u t Ba n d w id t h
The ADC’s inp ut tra c king c irc uitry ha s a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
ra te b y us ing und e rs a mp ling te c hniq ue s . To a void
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
OSCILLOSCOPE
V
+3V
DD
MAX146
MAX147
SCLK
0.1µF
DGND
AGND
COM
0V TO
2.500V
ANALOG
INPUT
CH7
0.01µF
SSTRB
DOUT*
CS
SCLK
DIN
+3V
REFADJ
VREF
+3V
+3V
2MHz
OSCILLATOR
DOUT
SSTRB
2.5V
V
OUT
1000pF
CH1
CH2
CH3
CH4
C1
0.1µF
SHDN
N.C.
MAX872
COMP
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
OPTIONAL FOR MAX146,
REQUIRED FOR MAX147
Figure 5. Quick-Look Circuit
10 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
Table 1. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
BIT
NAME
DESCRIPTION
7(MSB)
START
The first logic “1” bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF/2 to +VREF/2.
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
1
PD1
PD0
Selects clock and power-down modes.
0(LSB)
PD1
PD0
Mode
0
0
1
1
0
1
0
1
Full power-down
Fast power-down (MAX146 only)
Internal clock mode
External clock mode
Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
0
SEL1
0
SEL0
0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
+
–
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
+
–
–
–
–
–
–
–
+
+
+
+
+
+
Table 3. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
+
–
–
+
–
+
–
+
–
+
______________________________________________________________________________________ 11
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
4) Transmit a byte of all zeros ($00 hex) and, simulta-
Ho w t o S t a rt a Co n ve rs io n
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX146/MAX147’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
neously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero and three trailing zeros. The total
conversion time is a function of the serial-clock fre-
q ue nc y a nd the a mount of id le time b e twe e n 8-b it
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
The MAX146/MAX147 a re c omp a tib le with SPI™/
QSPI™ and Microwire™ devices. For SPI, select the
correct clock polarity and sampling edge in the SPI
control registers: set CPOL = 0 and CPHA = 0. Micro-
wire, SPI, and QSPI all transmit a byte and receive a
byte at the same time. Using the Typical Operating
Circuit, the simplest software interface requires only
three 8-bit transfers to perform a conversion (one 8-bit
transfer to configure the ADC, and two more 8-bit trans-
fers to clock out the 12-bit conversion result). See Figure
20 for MAX146/MAX147 QSPI connections.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is two’s
complement (Figure 18). Data is clocked out at the
falling edge of SCLK in MSB-first format.
6/MAX147
Clo c k Mo d e s
The MAX146/MAX147 ma y us e e ithe r a n e xte rna l
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the e xte rna l c loc k s hifts d a ta in a nd out of the
MAX146/MAX147. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7–10 show the timing characteris-
tics common to both modes.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
CS
t
ACQ
SCLK
1
4
8
12
16
20
24
UNI/
BIP
SGL/
DIF
SEL2 SEL1 SEL0
PD1 PD0
DIN
SSTRB
DOUT
START
RB2
B8
RB3
B0
LSB
RB1
FILLED WITH
ZEROS
B11
MSB
B10 B9
B7
B6
B5
B4
B3
B2
B1
ACQUISITION
1.5µs
CONVERSION
A/D STATE
IDLE
IDLE
(f
SCLK
= 2MHz)
Figure 6. 24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with f
≤ 2MHz)
SCLK
12 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
• • •
CS
t
t
CH
t
CSH
CSS
t
t
CL
CSH
SCLK
• • •
t
DS
t
DH
DIN
• • •
t
DV
t
DO
t
TR
DOUT
• • •
Figure 7. Detailed Serial-Interface Timing
CS
• • •
• • •
t
t
STR
SDV
SSTRB
• • •
• • •
t
t
SSTRB
SSTRB
SCLK
• • • •
• • • •
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
External Clock
The conversion must complete in some minimum time,
or d roop on the s a mp le -a nd -hold c a p a c itors ma y
degrade conversion results. Use internal clock mode if
the serial clock frequency is less than 100kHz, or if
serial clock interruptions could cause the conversion
interval to exceed 120µs.
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte. Succes-
sive-approximation bit decisions are made and appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). SSTRB and DOUT go into a high-impedance
state when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 8 shows the SSTRB
timing in external clock mode.
Internal Clock
In internal clock mode, the MAX146/MAX147 generate
their own conversion clocks internally. This frees the µP
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
______________________________________________________________________________________ 13
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
Pulling CS high prevents data from being clocked into
the MAX146/MAX147 and three-states DOUT, but it
d oe s not a d ve rs e ly a ffe c t a n inte rna l c loc k mod e
conversion already in progress. When internal clock
mode is se le c te d, SSTRB d oe s not go into a high-
impedance state when CS goes high.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the c onve rs ion a t DOUT, followe d b y the
remaining bits in MSB-first format (Figure 9). CS does
not need to be held low once a conversion is started.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX146/MAX147 at clock rates exceeding 2.0MHz
if the minimum acquisition time (t
1.5µs.
) is kept above
ACQ
6/MAX147
CS
SCLK
DIN
1
4
8
18
24
2
3
5
6
7
9
10
11
12
19
20
21
22
23
UNI/ SGL/
BIP DIF
SEL2 SEL1 SEL0
PD1 PD0
START
SSTRB
t
CONV
FILLED WITH
ZEROS
B11
MSB
B0
LSB
DOUT
B10 B9
B2
B1
ACQUISITION
CONVERSION
A/D STATE
1.5µs
IDLE
IDLE
7.5µs MAX
(f
SCLK
= 2MHz) (SHDN = FLOAT)
Figure 9. Internal Clock Mode Timing
CS
t
CONV
t
CSS
t
t
SCK
CSH
SSTRB
SCLK
t
SSTRB
t
DO
PD0 CLOCK IN
DOUT
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure. 10. Internal Clock Mode SSTRB Detailed Timing
14 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
Da t a Fra m in g
clock mode. If CS is tied low and SCLK is continuous,
The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
guarantee a start bit by first clocking in 16 zeros.
Most microcontrollers (µCs) require that conversions
occur in multiples of 8 SCLK clocks; 16 clocks per con-
version is typically the fastest that a µC can drive the
MAX146/MAX147. Fig ure 11b s hows the s e ria l-
interface timing necessary to perform a conversion every
16 SCLK cycles in external clock mode.
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after V is applied.
DD
__________ Ap p lic a t io n s In fo rm a t io n
OR
P o w e r-On Re s e t
When power is first applied, and if SHDN is not pulled
low, inte rna l p owe r-on re s e t c irc uitry a c tiva te s the
MAX146/MAX147 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies stabi-
lize, the internal reset time is 10µs, and no conversions
should be performed during this phase. SSTRB is high
on power-up and, if CS is low, the first logical 1 on DIN
is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. (Also see Table 4.)
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
If CS is toggled before the current conversion is com-
plete, the next high bit clocked into DIN is recognized as
a start bit; the current conversion is terminated, and a
new one is started.
The fastest the MAX146/MAX147 can run with CS held
low between conversions is 15 clocks per conversion.
Figure 11a shows the serial-interface timing necessary to
perform a conversion every 15 SCLK cycles in external
CS
1
8
15
1
8
15 1
SCLK
DIN
S
CONTROL BYTE 2
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
DOUT
SSTRB
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
• • •
• • •
• • •
• • •
CS
1
8
16
1
8
16
SCLK
DIN
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DOUT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
B11 B10 B9 B8
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
______________________________________________________________________________________ 15
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
except the bandgap reference. With fast power-down
mode, the supply current is 30µA. Power-up time can be
shortened to 5µs in internal compensation mode.
Re fe re n c e -Bu ffe r Co m p e n s a t io n
In addition to its shutdown function, SHDN selects inter-
na l or e xte rna l c omp e ns a tion. The c omp e ns a tion
affects both power-up time and maximum conversion
speed. The100kHz minimum clock rate is limited by
droop on the sample-and-hold and is independent of
the compensation used.
Table 4 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7µF compen-
sation capacitor when the capacitor is initially fully
discharged. From fast power-down, start-up time can be
eliminated by using low-leakage capacitors that do not
discharge more than 1/2LSB while shut down. In power-
down, leakage currents at VREF cause droop on the ref-
erence bypass capacitor. Figures 12a and 12b show
the various power-down sequences in both external and
internal clock modes.
Floa t SHDN to s e le c t e xte rna l c omp e ns a tion. The
Typical Operating Circuit uses a 4.7µF capacitor at
VREF. A 4.7µF value ensures reference-buffer stability
and allows converter operation at the 2MHz full clock
spe e d . Exte rna l c ompe nsa tion inc re a se s powe r-up
time (see the Choosing Power-Down Mode section and
Table 4).
Pull SHDN hig h to s e le c t inte rna l c omp e ns a tion.
Internal compensation requires no external capacitor at
VREF and allows for the shortest power-up times. The
maximum clock rate is 2MHz in internal clock mode
and 400kHz in external clock mode.
6/MAX147
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 5, PD1 and PD0
also specify the clock mode. When software shutdown is
asserted, the ADC operates in the last specified clock
mode until the conversion is complete. Then the ADC
powers down into a low quiescent-current state. In internal
clock mode, the interface remains active and conversion
results may be clocked out after the MAX146/MAX147
enter a software power-down.
Ch o o s in g P o w e r-Do w n Mo d e
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down mode or fast power-down mode via bits 1
and 0 of the DIN control byte with SHDN high or floating
(Tables 1 and 5). In both software power-down modes,
the serial interface remains operational, but the ADC
does not convert. Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
The first logical 1 on DIN is interpreted as a start bit
a nd p owe rs up the MAX146/MAX147. Following
the start bit, the data input word or control byte also
determines clock mode and power-down states. For
example, if the DIN word contains PD1 = 1, then the
c hip re ma ins p owe re d up . If PD0 = PD1 = 0, a
power-down resumes after one conversion.
Full power-down mode turns off all chip functions that
draw quiescent current, reducing supply current to 2µA
(typ ). Fa s t p owe r-d own mod e turns off a ll c irc uitry
Table 4. Typical Power-Up Delay Times
REFERENCE-
VREF
POWER-UP
DELAY
(µs)
MAXIMUM
SAMPLING RATE
(ksps)
REFERENCE
BUFFER
BUFFER
COMPENSATION
MODE
POWER-DOWN
MODE
CAPACITOR
(µF)
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Internal
Internal
External
External
—
—
—
Fast
Full
Fast
Full
Fast
Full
5
26
300
26
4.7
4.7
—
See Figure 14c
133
133
133
133
See Figure 14c
2
2
—
—
16 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
CLOCK
MODE
EXTERNAL
EXTERNAL
SHDN
SETS SOFTWARE
POWER-DOWN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1 1
S X X X X X 0 0
S X X X X X 1 1
DOUT
VALID
DATA
INVALID
DATA
12 DATA BITS
POWERED UP
12 DATA BITS
HARDWARE
POWER-
DOWN
POWERED UP
MODE
SOFTWARE
POWERED UP
POWER-DOWN
Figure 12a. Timing Diagram Power-Down Modes, External Clock
CLOCK
MODE
INTERNAL
SETS
POWER-DOWN
SETS INTERNAL
CLOCK MODE
DIN
S X X X X X 1 0
S X X X X X 0 0
S
DOUT
DATA VALID
DATA VALID
SSTRB
MODE
CONVERSION
CONVERSION
POWER-DOWN
POWERED UP
POWERED UP
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down (Table 6). Unlike software power-down
mode, the conversion is not completed; it stops coin-
cidentally with SHDN being brought low. SHDN also
controls the clock frequency in internal clock mode.
Letting SHDN float sets the internal clock frequency to
1.8MHz. When returning to normal operation with SHDN
floating, there is a t delay of approximately 2MΩ x C ,
RC L
where C is the capacitive loading on the SHDN pin.
L
Pulling SHDN high sets internal clock frequency to
225kHz. This feature eases the settling-time requirement
for the reference voltage. With an external reference, the
MAX146/MAX147 can be considered fully powered up
within 2µs of actively pulling SHDN high.
______________________________________________________________________________________ 17
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
Figure 14a depicts the MAX146 power consumption for
P o w e r-Do w n S e q u e n c in g
The MAX146/MAX147 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 13, 14a, and 14b show
the average supply current as a function of the sam-
pling rate. The following discussion illustrates the vari-
ous power-down sequences.
one or eight channel conversions utilizing full power-
down mode and internal-reference compensation. A
0.047µF bypass capacitor at REFADJ forms an RC filter
with the internal 20kΩ reference resistor with a 0.9ms
time constant. To achieve full 12-bit accuracy, 10 time
constants or 9ms are required after power-up. Waiting
this 9ms in FASTPD mode instead of in full power-up
can reduce power consumption by a factor of 10 or
more. This is achieved by using the sequence shown in
Figure 15.
Lowest Power at up to 500
Conversions/Channel/Second
The following examples show two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
WITH EXTERNAL REFERENCE
10,000
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
(USING FULLPD)
6/MAX147
100
VREF = V = 3.0V
DD
R
= ∞
LOAD
R
LOAD
= ∞
CODE = 101010100000
CODE = 101010100000
1000
100
10
8 CHANNELS
8 CHANNELS
10
1 CHANNEL
1 CHANNEL
1
0.1
1
0.01
0.1
1
10 100 1k 10k 100k 1M
CONVERSION RATE (Hz)
0.1
1
10
100
1k
CONVERSION RATE (Hz)
Figure 13. Average Supply Current vs. Conversion Rate with
External Reference
Figure 14a. MAX146 Supply Current vs. Conversion Rate,
FULLPD
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
(USING FASTPD)
TYPICAL REFERENCE-BUFFER POWER-UP
DELAY vs. TIME IN SHUTDOWN
2.0
10,000
R
LOAD
= ∞
CODE = 101010100000
1.5
1.0
1000
100
8 CHANNELS
1 CHANNEL
0.5
0
10
1
0.001
0.01
0.1
1
10
0.1
1
10 100 1k 10k 100k 1M
CONVERSION RATE (Hz)
TIME IN SHUTDOWN (sec)
Figure 14b. MAX146 Supply Current vs. Conversion Rate,
FASTPD
Figure 14c. Typical Reference-Buffer Power-Up Delay vs. Time
in Shutdown
18 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
COMPLETE CONVERSION SEQUENCE
9ms WAIT
0 1
(ZEROS)
CH1
CH7
(ZEROS)
DIN
1
0 0
FULLPD
1.21V
1
1
1 1
1
0 0
FULLPD
1
0 1
FASTPD
FASTPD
NOPD
REFADJ
VREF
0V
2.50V
0V
τ = RC = 20kΩ x C
REFADJ
t
≈ 200µs
BUFFEN
Figure 15. MAX146 FULLPD/FASTPD Power-Up Sequence
Lowest Power at Higher Throughputs
Fig ure 14b s hows the p owe r c ons ump tion with
external-reference compensation in fast power-down,
with one and eight channels converted. The external
4.7µF c omp e ns a tion re q uire s a 200µs wa it a fte r
p owe r-up with one d ummy c onve rs ion. This g ra p h
shows fast multi-channel conversion with the lowest
power consumption possible. Full power-down mode
may provide increased power savings in applications
where the MAX146/MAX147 are inactive for long peri-
ods of time, but where intermittent bursts of high-speed
conversions are required.
+3.3V
24k
MAX146
REFADJ
510k
100k
12
0.047µF
Figure 16. MAX146 Reference-Adjust Circuit
In t e rn a l a n d Ex t e rn a l Re fe re n c e s
The MAX146 can be used with an internal or external
reference voltage, whereas an external reference is
required for the MAX147. An external reference can be
connected directly at VREF or at the REFADJ pin.
Table 5. Software Power-Down and
Clock Mode
An inte rna l b uffe r is d e s ig ne d to p rovid e 2.5V a t
VREF for b oth the MAX146 a nd the MAX147. The
MAX146’s internally trimmed 1.21V reference is buf-
fered with a 2.06 gain. The MAX147’s REFADJ pin is
also buffered with a 2.00 gain to scale an external 1.25V
reference at REFADJ to 2.5V at VREF.
PD1
PD0
DEVICE MODE
Full Power-Down
Fast Power-Down
0
0
0
1
1
1
0
1
Internal Clock
External Clock
Internal Reference (MAX146)
The MAX146’s full-scale range with the internal refer-
ence is 2.5V with unipolar inputs and ±1.25V with bipo-
lar inputs. The internal reference voltage is adjustable
to ±1.5% with the circuit in Figure 16.
Table 6. Hard-Wired Power-Down and
Internal Clock Frequency
REFERENCE
BUFFER
COMPENSATION FREQUENCY
INTERNAL
CLOCK
DEVICE
MODE
SHDN
STATE
External Reference
With both the MAX146 and MAX147, an external refer-
ence can be placed at either the input (REFADJ) or the
output (VREF) of the internal reference-buffer amplifier.
The REFADJ input impedance is typically 20kΩ for the
MAX146, and higher than 100kΩ for the MAX147. At
1
Floating
0
Enabled
Enabled
Internal
External
N/A
225kHz
1.8MHz
N/A
Power-Down
______________________________________________________________________________________ 19
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
VREF, the DC input resistance is a minimum of 18kΩ.
During conversion, an external reference at VREF must
deliver up to 350µA DC load current and have 10Ω or
less output impedance. If the reference has a higher
output impedance or is noisy, bypass it close to the
VREF pin with a 4.7µF capacitor.
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
Using the REFADJ input makes buffering the external
reference unnecessary. To use the direct VREF input,
disable the internal buffer by tying REFADJ to V . In
power-down, the input bias current to REFADJ is typi-
DD
FS = VREF + COM
ZS = COM
cally 25µA (MAX146) with REFADJ tied to V . Pull
DD
REFADJ to AGND to minimize the input bias current in
power-down.
VREF
4096
1LSB =
00 . . . 011
00 . . . 010
Tra n s fe r Fu n c t io n
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
00 . . . 001
00 . . . 000
6/MAX147
The external reference must have a temperature coeffi-
cient of 4ppm/°C or less to achieve accuracy to within
1LSB over the 0°C to +70°C commercial temperature
range.
0
1
2
3
FS
(COM)
FS - 3/2LSB
INPUT VOLTAGE (LSB)
Figure 17. Unipolar Transfer Function, Full Scale (FS) = VREF
+ COM, Zero Scale (ZS) = COM
Figure 17 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 18 shows the bipolar
input/output transfer function. Code transitions occur
ha lfwa y b e twe e n s uc c e s s ive -inte g e r LSB va lue s .
Output coding is binary, with 1LSB = 610µV (2.500V /
4096) for unip ola r op e ra tion, a nd 1LSB = 610µV
[(2.500V / 2 - -2.500V / 2) / 4096] for bipolar operation.
s up p ly s hould b e low imp e d a nc e a nd a s s hort a s
possible.
High-frequency noise in the V
power supply may
DD
affect the high-speed comparator in the ADC. Bypass
the s up p ly to the s ta r g round with 0.1µF a nd 1µF
capacitors close to pin 20 of the MAX146/MAX147.
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, a 10Ω resis-
tor can be connected as a lowpass filter (Figure 19).
La yo u t , Gro u n d in g , a n d Byp a s s in g
For b e s t p e rforma nc e , us e p rinte d c irc uit b oa rd s .
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Hig h -S p e e d Dig it a l In t e rfa c in g w it h QS P I
The MAX146/MAX147 can interface with QSPI using
the circuit in Figure 20 (f
= 2.0MHz, CPOL = 0,
SCLK
Figure 19 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at AGND, separate from the logic
ground. Connect all other analog grounds and DGND
to the star ground. No other digital system ground
should be connected to this ground. For lowest-noise
operation, the ground return to the star ground’s power
CPHA = 0). This QSPI circuit can be programmed to do a
conversion on each of the eight channels. The result is
stored in memory without taxing the CPU, since QSPI
incorporates its own microsequencer.
The MAX146/MAX147 are QSPI compatible up to the
maximum external clock frequency of 2MHz.
Table 7. Full Scale and Zero Scale
UNIPOLAR MODE
BIPOLAR MODE
Positive
Full Scale
Zero
Scale
Negative
Full Scale
Full Scale
Zero Scale
COM
VREF / 2
+ COM
-VREF / 2
+ COM
VREF + COM
COM
20 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
OUTPUT CODE
VREF
2
FS
=
+ COM
+ COM
011 . . . 111
011 . . . 110
SUPPLIES
ZS = COM
+3V
+3V
GND
-VREF
2
-FS =
000 . . . 010
000 . . . 001
000 . . . 000
VREF
4096
1LSB =
R* = 10Ω
111 . . . 111
111 . . . 110
111 . . . 101
V
DD
AGND
COM DGND
+3V DGND
100 . . . 001
100 . . . 000
DIGITAL
CIRCUITRY
MAX146
MAX147
COM*
- FS
+FS - 1LSB
*OPTIONAL
INPUT VOLTAGE (LSB)
≤
*COM VREF / 2
Figure 19. Power-Supply Grounding Connection
Figure 18. Bipolar Transfer Function, Full Scale (FS) =
VREF / 2 + COM, Zero Scale (ZS) = COM
4) The MAX146/MAX147’s SSTRB output is monitored
via the TMS320’s FSR input. A falling edge on the
SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX146/MAX147.
TMS 3 2 0 LC3 x In t e rfa c e
Figure 21 shows an application circuit to interface the
MAX146/MAX147 to the TMS320 in external clock mode.
The timing diagram for this interface circuit is shown in
Figure 22.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
Use the following steps to initiate a conversion in the
MAX146/MAX147 and to read the results:
1) The TMS320 s hould b e c onfig ure d with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
tied together with the MAX146/MAX147’s SCLK
input.
6) Pull CS high to disable the MAX146/MAX147 until
the next conversion is initiated.
2) The MAX146/MAX147’s CS pin is driven low by the
TMS320’s XF_ I/O port to enable data to be clocked
into the MAX146/MAX147’s DIN.
3) An 8-bit word (1XXXXX11) should be written to the
MAX146/MAX147 to initiate a conversion and place
the device into external clock mode. Refer to Table
1 to select the proper XXXXX bit values for your
specific application.
______________________________________________________________________________________ 21
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
+3V
+3V
0.1µF
1µF
(POWER SUPPLIES)
1
2
20
19
18
17
16
15
14
13
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SHDN
V
DD
SCK
SCLK
CS
PCS0
3
4
MOSI
MISO
MC683XX
ANALOG
INPUTS
DIN
MAX146
MAX147
5
6
SSTRB
DOUT
DGND
AGND
7
6/MAX147
8
9
REFADJ 12
11
(GND)
10
VREF
0.1µF
+2.5V
Figure 20. MAX146/MAX147 QSPI Connections, External Reference
XF
CLKX
CLKR
DX
CS
SCLK
TMS320LC3x
MAX146
MAX147
DIN
DR
DOUT
SSTRB
FSR
Figure 21. MAX146/MAX147-to-TMS320 Serial Interface
22 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX147
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0
HIGH
IMPEDANCE
SSTRB
HIGH
IMPEDANCE
DOUT
MSB
B10
B1
LSB
Figure 22. TMS320 Serial-Interface Timing Diagram
_Ord e rin g In fo rm a t io n (c o n t in u e d )
__________________P in Co n fig u ra t io n
INL
(LSB)
PART†
TEMP. RANGE PIN-PACKAGE
TOP VIEW
MAX146AEPP -40°C to +85°C
MAX146BEPP -40°C to +85°C
MAX146AEAP -40°C to +85°C
MAX146BEAP -40°C to +85°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
±1/2
±1
CH0
CH1
1
2
V
DD
20
19 SCLK
±1/2
±1
3
CS
CH2
18
17
20 SSOP
MAX146
MAX147
CH3
4
DIN
MAX146AMJP -55°C to +125°C 20 CERDIP**
MAX146BMJP -55°C to +125°C 20 CERDIP**
±1/2
±1
5
CH4
16 SSTRB
15 DOUT
CH5
6
MAX147ACPP
MAX147BCPP
MAX147ACAP
MAX147BCAP
MAX147BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
±1/2
±1
CH6
14
13
12
11
DGND
7
±1/2
±1
8
CH7
AGND
20 SSOP
REFADJ
9
COM
SHDN
Dice*
±1
VREF
10
MAX147AEPP -40°C to +85°C
MAX147BEPP -40°C to +85°C
MAX147AEAP -40°C to +85°C
MAX147BEAP -40°C to +85°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
±1/2
±1
DIP/SSOP
±1/2
±1
20 SSOP
MAX147AMJP -55°C to +125°C 20 CERDIP**
MAX147BMJP -55°C to +125°C 20 CERDIP**
±1/2
±1
†
Contact factory for availability of alternate surface-mount
packages.
___________________Ch ip In fo rm a t io n
* Dice are specified at T = +25°C, DC parameters only.
A
**Contact factory for availability of CERDIP package, and for
processing to MIL-STD-883B.
TRANSISTOR COUNT: 2554
______________________________________________________________________________________ 23
+2 .7 V, Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
________________________________________________________P a c k a g e In fo rm a t io n
6/MAX147
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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