MAX1471 [MAXIM]
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver; 315MHz的/ 434MHz的低功耗， 3V / 5V ASK / FSK超外差接收器
| 型号： | MAX1471 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver |
| 文件： | 总26页 (文件大小：804K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3272; Rev 0; 4/04
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
General Description
Features
♦ ASK and FSK Demodulated Data on Separate
The MAX1471 low-power, CMOS, superheterodyne, RF
dual-channel receiver is designed to receive both ampli-
tude-shift-keyed (ASK) and frequency-shift-keyed (FSK)
data without reconfiguring the device or introducing any
time delay normally associated with changing modula-
tion schemes. The MAX1471 requires few external com-
ponents to realize a complete wireless RF digital data
receiver for the 300MHz to 450MHz ISM bands.
Outputs
♦ Specified over Automotive -40°C to +125°C
Temperature Range
♦ Low Operating Supply Voltage Down to 2.4V
♦ On-Chip 3V Regulator for 5V Operation
♦ Low Operating Supply Current
7mA Continuous Receive Mode
1.1µA Deep-Sleep Mode
The MAX1471 includes all the active components
required in a superheterodyne receiver including: a low-
noise amplifier (LNA), an image-reject (IR) mixer, a fully
integrated phase-locked loop (PLL), local oscillator
(LO), 10.7MHz IF limiting amplifier with received-signal-
strength indicator (RSSI), low-noise FM demodulator,
and a 3V voltage regulator. Differential peak-detecting
data demodulators are included for both the FSK and
ASK analog baseband data recovery. The MAX1471
includes a discontinuous receive (DRX) mode for low-
power operation, which is configured through a serial
interface bus.
♦ Discontinuous Receive (DRX) Low-Power
Management
♦ Fast-On Startup Feature < 250µs
♦ Integrated PLL, VCO, and Loop Filter
♦ 45dB Integrated Image Rejection
♦ RF Input Sensitivity*
ASK: -114dBm
FSK: -108dBm
♦ Selectable IF BW with External Filter
♦ Programmable Through Serial User Interface
♦ RSSI Output and High Dynamic Range with AGC
The MAX1471 is available in a 32-pin thin QFN package
and is specified over the automotive -40°C to +125°C
temperature range.
*0.2% BER, 4kbps, Manchester-encoded data, 280kHz IF BW
Applications
Ordering Information
Automotive Remote Keyless Entry (RKE)
Tire Pressure Monitoring Systems
Garage Door Openers
Wireless Sensors
PART
TEMP RANGE
PIN-PACKAGE
MAX1471ATJ
-40°C to +125°C
32 Thin QFN-EP**
**EP = Exposed pad.
Pin Configuration
Wireless Keys
TOP VIEW
Security Systems
Medical Systems
32
31
30
29
28
27
26
25
Home Automation
DSA-
DSA+
OPA+
DFA
1
2
3
4
5
6
7
8
24 DV
DD
Local Telemetry Systems
23
22
DGND
DFF
21 OPF+
20 DSF+
MAX1471
XTAL2
XTAL1
19
18 PDMAXF
17
DSF-
AV
DD
LNAIN
PDMINF
9
10 11 12 13 14 15 16
THIN QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
ABSOLUTE MAXIMUM RATINGS
High-Voltage Supply, HV to DGND.......................-0.3V, +6.0V
Continuous Power Dissipation (T = +70°C)
A
IN
Low-Voltage Supply, AV
SCLK, DIO, CS, ADATA,
FDATA....................................(DGND - 0.3V) to (HV + 0.3V)
and DV
to AGND .....-0.3V, +4.0V
32-Pin Thin QFN (derate 21.3mW/°C above +70°C) ...1702mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
DD
DD
IN
All Other Pins.............................(AGND - 0.3V) to (AV
+ 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, AV = DV = HV = +2.4V to +3.6V, f = 300MHz to 450MHz, T = -40°C to +125°C, unless otherwise
DD
DD
IN
RF
A
noted. Typical values are at AV = DV = HV = +3.0V, f = 434 MHz, T = +25°C, unless otherwise noted.) (Note 1)
DD
DD
IN
RF
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
AV
and DV
unconnected from HV ,
DD IN
DD
Supply Voltage (5V)
HV
4.5
2.4
5.0
5.5
V
IN
but connected together
HV , AV , and DV
supply
connected to power
IN
DD
DD
Supply Voltage (3V)
Supply Current
Startup Time
V
3.0
7.0
705
3.6
8.4
855
V
DD
Operating
mA
Polling duty cycle: 10%
duty cycle
T
A
< +85°C
µA
mA
µA
DRX mode OFF current
Deep-sleep current
Operating
5.0
1.1
14.2
7.1
8.5
Polling duty cycle: 10%
duty cycle
865
T
A
< +105°C
I
DD
(Note 2)
DRX mode OFF current
Deep-sleep current
Operating
15.5
13.4
8.6
mA
µA
Polling duty cycle: 10%
duty cycle
900
T
A
< +125°C
(Note 2)
DRX mode OFF current
Deep-sleep current
44.1
36.4
Time for final signal detection, does not
include baseband filter settling (Note 2)
t
200
250
µs
ON
DIGITAL OUTPUTS (DIO, ADATA, FDATA)
HV
0.15
-
IN
Output High Voltage
V
I
= 250µA (Note 2)
SOURCE
V
V
OH
Output Low Voltage
V
I = 250µA (Note 2)
SINK
0.15
OL
DIGITAL INPUTS (CS, DIO, SCLK)
0.9 x
Input High Threshold
Input Low Threshold
V
V
V
IH
HV
IN
0.1 x
V
.
IL
HV
IN
2
_______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, AV = DV = HV = +2.4V to +3.6V, f = 300MHz to 450MHz, T = -40°C to +125°C, unless otherwise
DD
DD
IN
RF
A
noted. Typical values are at AV = DV = HV = +3.0V, f = 434 MHz, T = +25°C, unless otherwise noted.) (Note 1)
DD
DD
IN
RF
A
PARAMETER
Input-High Leakage Current
Input-Low Leakage Current
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
MAX
-10
10
UNITS
µA
I
(Note 2)
(Note 2)
(Note 2)
IH
I
µA
IL
C
2.0
pF
IN
VOLTAGE REGULATOR
Output Voltage
V
HV = 5.0V, I = 7.0mA
LOAD
3.0
V
REG
IN
AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, AV = DV = HV = +2.4V to +3.6V, f = 300MHz to 450MHz, T = -40°C to +125°C, unless otherwise
DD
DD
IN
RF
A
noted. Typical values are at AV = DV = HV = +3.0V, f = 434 MHz, T = +25°C, unless otherwise noted.) (Note 1)
DD
DD
IN
RF
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
0.2% BER, 4kbps
Manchester Code, 280kHz
IF BW, 50Ω
ASK
FSK
-114
-108
Receiver Sensitivity
RF
dBm
dBm
IN
Maximum Receiver Input Power
Level
RF
0
MAX
Receiver Input Frequency Range
Receiver Image Rejection
LNA/MIXER (Note 4)
f
300
450
MHz
dB
RF
IR
(Note 3)
45
f
f
= 315MHz
= 434MHz
1 - j4.7
1 - j3.4
RF
LNA Input Impedance
Z
Normalized to 50Ω
11
RF
Voltage Conversion Gain (High-
Gain Mode)
47.5
-38
12.2
-5
dB
dBm
dB
Input-Referred 3rd-Order
Intercept Point (High-Gain Mode)
Voltage Conversion Gain (Low-
Gain Mode)
Input-Referred 3rd-Order
Intercept Point (Low-Gain Mode)
dBm
LO Signal Feedthrough to
Antenna
-90
dBm
Mixer Output Impedance
IF
Z
330
Ω
OUT
Input Impedance
Operating Frequency
3dB Bandwidth
Z
330
10.7
10
Ω
11
f
IF
MHz
MHz
FM DEMODULATOR
Demodulator Gain
G
2.2
mV/kHz
FM
_______________________________________________________________________________________
3
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, AV = DV = HV = +2.4V to +3.6V, f = 300MHz to 450MHz, T = -40°C to +125°C, unless otherwise
DD
DD
IN
RF
A
noted. Typical values are at AV = DV = HV = +3.0V, f = 434 MHz, T = +25°C, unless otherwise noted.) (Note 1)
DD
DD
IN
RF
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG BASEBAND
Maximum Data Filter Bandwidth
Maximum Data Slicer Bandwidth
BW
BW
50
kHz
kHz
DF
100
DS
Maximum Peak Detector
Bandwidth
BW
50
kHz
PD
Manchester coded
33
66
Maximum Data Rate
kbps
Nonreturn to zero (NRZ)
CRYSTAL OSCILLATOR
Crystal Frequency
f
9.04
13.728
MHz
ppm/V
µH
XTAL
Frequency Pulling by V
3
50
3
DD
Maximum Crystal Inductance
Crystal Load Capacitance
pF
DIGITAL INTERFACE TIMING (see Figure 8)
Minimum SCLK Setup to Falling
Edge of CS
t
30
30
ns
ns
SC
Minimum CS Falling Edge to
SCLK Rising-Edge Setup Time
t
CSS
Minimum CS Idle Time
Minimum CS Period
t
125
ns
µs
CSI
t
2.125
CS
Maximum SCLK Falling Edge to
Data Valid Delay
t
80
30
30
ns
ns
ns
DO
Minimum Data Valid to SCLK
Rising-Edge Setup Time
t
DS
Minimum Data Valid to SCLK
Rising-Edge Hold Time
t
t
DH
Minimum SCLK High Pulse Width
Minimum SCLK Low Pulse Width
100
100
ns
ns
CH
t
CL
Minimum CS Rising Edge to
SCLK Rising-Edge Hold Time
t
30
25
25
ns
ns
ns
CSH
Maximum CS Falling Edge to
Output Enable Time
t
DV
Maximum CS Rising Edge to
Output Disable Time
t
TR
Note 1: Production tested at T = +85°C. Guaranteed by design and characterization over entire temperature range.
A
Note 2: Guaranteed by design and characterization. Not production tested.
Note 3: The oscillator register (0x3) is set to the nearest integer result of f
/ 100kHz (see the Oscillator Frequency Register section).
XTAL
Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 15nH inductive degeneration
from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA
source to ground. The equivalent input circuit is 50Ω in series with 2.2pF. The voltage conversion gain is measured with the
LNA input matching inductor, the degeneration inductor, and the LNA/mixer resonator in place, and does not include the IF fil-
ter insertion loss.
4
_______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Typical Operating Characteristics
(Typical Application Circuit, AV
= DV
= HV = +3.0V, f = 434MHz, T = +25°C, unless otherwise noted.)
DD IN RF A
DD
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. RF FREQUENCY
DEEP-SLEEP CURRENT
vs. TEMPERATURE
8.0
7.6
7.2
6.8
6.4
6.0
8.0
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
12
10
8
+125°C
+105°C
+105°C
+125°C
+85°C
+85°C
6
4
2
0
+25°C
-40°C
+25°C
-40°C
2.4
2.7
3.0
3.3
3.6
300
325
350
375
400
425
450
-40
-15
10
35
60
85
110
°
SUPPLY VOLTAGE (V)
RF FREQUENCY (MHz)
TEMPERATURE ( C)
SENSITIVITY
BIT-ERROR RATE
BIT-ERROR RATE
vs. TEMPERATURE (ASK DATA)
vs. AVERAGE INPUT POWER (ASK DATA)
vs. AVERAGE INPUT POWER (FSK DATA)
-102
-105
-108
-111
100
10
100
10
280kHz IF BW
0.2% BER
280kHz IF BW
280kHz IF BW
FREQUENCY DEVIATION = 50kHz
f
f
= 434MHz
= 315MHz
RF
RF
f
f
= 434MHz
RF
RF
f
f
= 434MHz
= 315MHz
1
1
RF
RF
0.2% BER
-114
-117
-120
0.2% BER
0.1
0.01
0.1
0.01
= 315MHz
-110
-123 -121 -119 -117 -115 -113 -111
AVERAGE INPUT POWER (dBm)
-115
-113
-108
-105
-40
-15
10
35
60
85
110
°
AVERAGE INPUT POWER (dBm)
TEMPERATURE ( C)
SENSITIVITY
vs. TEMPERATURE (FSK DATA)
SENSITIVITY vs. FREQUENCY
DEVIATION (FSK DATA)
RSSI vs. RF INPUT POWER
-98
-102
-104
-106
-108
-110
-112
1.6
1.4
1.2
1.0
0.8
280kHz IF BW
0.2% BER
280kHz IF BW
0.2% BER
AGC HYSTERESIS: 3dB
HIGH-GAIN MODE
-100
-102
FREQUENCY DEVIATION = 50kHz
AGC SWITCH
POINT
f
f
= 434MHz
= 315MHz
RF
-104
-106
-108
-110
-112
0.6
0.4
RF
0.2
0
LOW-GAIN MODE
-130 -110 -90 -70
-40
-15
10
35
60
85
110
1
10
FREQUENCY DEVIATION (kHz)
100
-30 -10 10
-50
°
TEMPERATURE ( C)
RF INPUT POWER (dBm)
_______________________________________________________________________________________
5
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Typical Operating Characteristics (continued)
(Typical Application Circuit, AV
= DV
= HV = +3.0V, f = 434MHz, T = +25°C, unless otherwise noted.)
DD IN RF A
DD
FSK DEMODULATOR OUTPUT
vs. IF FREQUENCY
SYSTEM VOLTAGE GAIN
vs. IF FREQUENCY
RSSI AND DELTA vs. IF INPUT POWER
MAX1471 toc10
2.0
60
50
40
30
20
10
0
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
3.5
UPPER SIDEBAND
2.5
1.5
1.6
1.2
0.8
0.4
0
RSSI
FROM RFIN
TO MIXOUT
45dB IMAGE
REJECTION
0.5
f
= 434MHz
RF
-0.5
-1.5
-2.5
-3.5
DELTA
LOWER SIDEBAND
-10
10.4
10.5 10.6 10.7 10.8 10.9 11.0
IF FREQUENCY (MHz)
0
5
10
15
20
25
30
-90
-70
-50
-30
-10
10
IF FREQUENCY (MHz)
RF INPUT POWER (dBm)
S11 LOG-MAGNITUDE PLOT WITH
MATCHING NETWORK OF RFIN (434MHz)
NORMALIZED IF GAIN
vs. IF FREQUENCY
IMAGE REJECTION
vs. TEMPERATURE
5
0
48
46
44
42
40
38
f
= 315MHz
RF
10dB/
div
-5
-10
-15
f
= 434MHz
RF
0dB
0dB
434MHz
-16.4dB
-20
1
10
100
START: 50MHz
STOP: 1GHz
-40 -15
10
35
60
85 110
IF FREQUENCY (MHz)
TEMPERATURE (°C)
S11 SMITH CHART OF RFIN (434MHz)
MAX1471 toc16
500MHz
200MHz
6
_______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Typical Operating Characteristics (continued)
(Typical Application Circuit, AV
= DV
= HV = +3.0V, f = 434MHz, T = +25°C, unless otherwise noted.)
DD IN RF A
DD
INPUT IMPEDANCE vs. INDUCTIVE
DEGENERATION
INPUT IMPEDANCE vs. INDUCTIVE
DEGENERATION
MAX1471 toc17
MAX1471 toc18
-125
-150
-175
-200
-225
-250
-275
-300
-325
-350
-125
-150
-175
-200
-225
-250
-275
-300
-325
-350
90
80
70
60
50
40
30
20
10
0
90
f
= 315MHz
f
= 434MHz
RF
L1 = 0nH
RF
80
70
60
50
40
30
20
10
0
L1 = 0nH
IMAGINARY IMPEDANCE
IMAGINARY
IMPEDANCE
REAL IMPEDANCE
REAL IMPEDANCE
10
1
100
1
10
INDUCTIVE DEGENERATION (nH)
100
INDUCTIVE DEGENERATION (nH)
PHASE NOISE vs. OFFSET FREQUENCY
PHASE NOISE vs. OFFSET FREQUENCY
-50
-60
-50
-60
f
= 315MHz
f
= 434MHz
RF
RF
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
Pin Description
PIN
1
NAME
DSA-
FUNCTION
Inverting Data Slicer Input for ASK Data
2
DSA+
OPA+
DFA
Noninverting Data Slicer Input for ASK Data
3
Noninverting Op-Amp Input for the ASK Sallen-Key Data Filter
4
Data-Filter Feedback Node. Input for the feedback of the ASK Sallen-Key data filter.
2nd Crystal Input
5
XTAL2
_______________________________________________________________________________________
7
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Pin Description (continued)
PIN
NAME
FUNCTION
6
XTAL1
1st Crystal Input
Analog Power-Supply Voltage for RF Sections. AV
regulator. Decouple to AGND with a 0.1µF capacitor.
is connected to an on-chip +3.0V low-dropout
DD
7
8
9
AV
DD
LNAIN
Low-Noise Amplifier Input
Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to AGND to set
LNA input impedance.
LNASRC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
LNAOUT
MIXIN+
MIXIN-
MIXOUT
AGND
IFIN-
Low-Noise Amplifier Output. Connect to mixer through an LC tank filter.
Differential Mixer Input. Must be AC-coupled to driving input.
Differential Mixer Input. Bypass to AGND with a capacitor.
330Ω Mixer Output. Connect to the input of the 10.7MHz IF filter.
Analog Ground
Differential 330Ω IF Limiter Amplifier Input. Bypass to AGND with a capacitor.
Differential 330Ω IF Limiter Amplifier Input. Connect to output of the 10.7MHz IF filter.
Minimum-Level Peak Detector for FSK Data
IFIN+
PDMINF
PDMAXF
DSF-
Maximum-Level Peak Detector for FSK Data
Inverting Data Slicer Input for FSK Data
DSF+
Noninverting Data Slicer Input for FSK Data
OPF+
Noninverting Op-Amp Input for the FSK Sallen-Key Data Filter
Data-Filter Feedback Node. Input for the feedback of the FSK Sallen-Key data filter.
Digital Ground
DFF
DGND
Digital Power-Supply Voltage for Digital Sections. Connect to AV . Decouple to DGND with a 10nF
DD
capacitor.
24
DV
DD
25
26
27
28
29
30
31
32
EP
FDATA
CS
Digital Baseband FSK Demodulator Data Output
Active-Low Chip-Select Input
Serial Data Input/Output
DIO
SCLK
Serial Interface Clock Input
HV
High-Voltage Supply Input. For 3V operation, connect HV to AV
IN
and DV
.
DD
IN
DD
ADATA
PDMINA
PDMAXA
GND
Digital Baseband ASK Demod Data Output
Minimum-Level Peak Detector for ASK Output
Maximum-Level Peak Detector for ASK Output
Exposed Paddle. Connect to ground.
8
_______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Functional Diagram
LNAOUT
10
MIXIN+
11
MIXIN-
12
MIXOUT IFIN-
13 15
IFIN+
16
IMAGE
REJECTION
IF LIMITING
AMPS
°
0
8
LNA
LNAIN
Σ
R
DF1
100kΩ
9
LNASRC
AGND
°
90
ASK
4
RSSI
DFA
14
DIVIDE
BY 32
VCO
R
DF2
6
5
XTAL1
XTAL2
CRYSTAL
OSCILLATOR
100kΩ
PHASE
DETECTOR
LOOP
FILTER
3
2
OPA+
DSA+
26
27
28
CS
DIO
FSK
DEMODULATOR
FSK
SERIAL INTERFACE,
CONTROL REGISTERS,
AND POLLING TIMER
ASK DATA FILTER
SCLK
DV
DD 24
31
PDMINA
DGND 23
R
DF1
100kΩ
R
DF2
100kΩ
32
1
PDMAXA
DSA-
FSK DATA
FILTER
30
3.0V
REG
ADATA
29
7
HV
IN
AV
DD
3.0V
MAX1471
25
19
18
17
PDMINF
20
21
22
FDATA
DSF-
PDMAXF
DSF+ OPF+ DFF
_______________________________________________________________________________________
9
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Automatic Gain Control (AGC)
Detailed Description
When the AGC is enabled, it monitors the RSSI output.
When the RSSI output reaches 1.28V, which corre-
sponds to an RF input level of approximately -64dBm,
the AGC switches on the LNA gain reduction attenuator.
The attenuator reduces the LNA gain by 35dB, thereby
reducing the RSSI output by about 0.55V. The LNA
resumes high-gain mode when the RSSI output level
drops back below 0.68V (approximately -67dBm at the
RF input) for a programmable interval called the AGC
dwell time. The AGC has a hysteresis of approximately
3dB. With the AGC function, the RSSI dynamic range is
increased, allowing the MAX1471 to reliably produce an
ASK output for RF input levels up to 0dBm with a modu-
lation depth of 18dB. AGC is not necessary and can be
disabled when utilizing only the FSK data path.
The MAX1471 CMOS superheterodyne receiver and a
few external components provide a complete ASK/FSK
receive chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates as high as 33kbps using Manchester Code
(66kbps nonreturn to zero) can be achieved.
The MAX1471 is designed to receive binary FSK or
ASK data on a 300MHz to 450MHz carrier. ASK modu-
lation uses a difference in amplitude of the carrier to
represent logic 0 and logic 1 data. FSK uses the differ-
ence in frequency of the carrier to represent a logic 0
and logic 1.
Low-Noise Amplifier (LNA)
The LNA is a cascode amplifier with off-chip inductive
degeneration that achieves approximately 28dB of volt-
age gain that is dependent on both the antenna-match-
ing network at the LNA input, and the LC tank network
between the LNA output and the mixer inputs.
The MAX1471 features an AGC lock controlled by the
AGC lock bit (see Table 8). When the bit is set, the LNA
is locked in its present gain state.
Mixer
A unique feature of the MAX1471 is the integrated
image rejection of the mixer. This device was designed
to eliminate the need for a costly front-end SAW filter for
many applications. The advantage of not using a SAW
filter is increased sensitivity, simplified antenna match-
ing, less board space, and lower cost.
The off-chip inductive degeneration is achieved by con-
necting an inductor from LNASRC to AGND. This induc-
tor sets the real part of the input impedance at LNAIN,
allowing for a flexible match to low input impedances
such as a PC board trace antenna. A nominal value for
this inductor with a 50Ω input impedance is 15nH at
315MHz and 10nH at 434MHz, but the inductance is
affected by PC board trace length. See the Typical
Operating Characteristics to see the relationship
between the inductance and input impedance. The
inductor can be shorted to ground to increase sensitivi-
ty by approximately 1dB, but the input match is not
optimized for 50Ω.
The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz intermediate frequency (IF) with low-side
injection (i.e., f = f - f ). The image-rejection circuit
LO
RF IF
then combines these signals to achieve approximately
45dB of image rejection. Low-side injection is required
as high-side injection is not possible due to the on-chip
image rejection. The IF output is driven by a source fol-
lower, biased to create a driving impedance of 330Ω to
interface with an off-chip 330Ω ceramic IF filter. The
voltage conversion gain driving a 330Ω load is approxi-
mately 19.5dB. Note that the MIXIN+ and MIXIN- inputs
are functionally identical.
The LC tank filter connected to LNAOUT comprises L2
and C9 (see the Typical Application Circuit). Select L2
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:
1
f =
L
×C
TOTAL
2π TOTAL
Phase-Locked Loop (PLL)
The PLL block contains a phase detector, charge
pump/integrated loop filter, voltage-controlled oscillator
(VCO), asynchronous 32x clock divider, and crystal
oscillator. This PLL does not require any external com-
ponents. The relationship between the RF, IF, and refer-
ence frequencies is given by:
where L
PARASITICS
= L2 + L
and C
= C9 +
TOTAL
PARASITICS
TOTAL
C
.
L
and C
include inductance and
PARASITICS
PARASITICS
capacitance of the PC board traces, package pins,
mixer input impedance, LNA output impedance, etc.
These parasitics at high frequencies cannot be
ignored, and can have a dramatic effect on the tank fil-
ter center frequency. Lab experimentation should be
done to optimize the center frequency of the tank.
f
= (f - f )/32
RF IF
REF
To allow the smallest possible IF bandwidth (for best sen-
sitivity), the tolerance of the reference must be minimized.
10 ______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
is suppressed by the integrated quadrature image-
rejection circuitry.
Intermediate Frequency (IF)
The IF section presents a differential 330Ω load to pro-
vide matching for the off-chip ceramic filter. It contains
five AC-coupled limiting amplifiers with a bandpass-fil-
ter-type response centered near the 10.7MHz IF fre-
quency with a 3dB bandwidth of approximately 10MHz.
For ASK data, the RSSI circuit demodulates the IF to
baseband by producing a DC output proportional to
the log of the IF signal level with a slope of approxi-
mately 16mV/dB. For FSK, the limiter output is fed into a
PLL to demodulate the IF.
For an input RF frequency of 315MHz, a reference fre-
quency of 9.509MHz is needed for a 10.7MHz IF fre-
quency (low-side injection is required). For an input RF
frequency of 433.92MHz, a reference frequency of
13.2256MHz is required.
The XTAL oscillator in the MAX1471 is designed to pre-
sent a capacitance of approximately 3pF between the
XTAL1 and XTAL2. If a crystal designed to oscillate
with a different load capacitance is used, the crystal is
pulled away from its stated operating frequency, intro-
ducing an error in the reference frequency. Crystals
designed to operate with higher differential load capac-
itance always pull the reference frequency higher.
FSK Demodulator
The FSK demodulator uses an integrated 10.7MHz PLL
that tracks the input RF modulation and determines the
difference between frequencies as logic-level ones and
zeros. The PLL is illustrated in Figure 1. The input to the
PLL comes from the output of the IF limiting amplifiers.
The PLL control voltage responds to changes in the fre-
quency of the input signal with a nominal gain of
2.2mV/kHz. For example, an FSK peak-to-peak devia-
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
tion of 50kHz generates a 110mV
signal on the con-
P-P
trol line. This control line is then filtered and sliced by
the FSK baseband circuitry.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
The FSK demodulator PLL requires calibration to over-
come variations in process, voltage, and temperature.
For more information on calibrating the FSK demodula-
tor, see the Calibration section. The maximum calibra-
tion time is 120µs. In DRX mode, the FSK demodulator
calibration occurs automatically just before the IC
enters sleep mode.
C
2
1
+C
1
+C
m
fp =
−
×106
C
C
case
load
case
spec
where:
f is the amount the crystal frequency pulled in ppm.
p
Crystal Oscillator
The XTAL oscillator in the MAX1471 is used to generate
the local oscillator (LO) for mixing with the received sig-
nal. The XTAL oscillator frequency sets the received
signal frequency as:
C
C
C
C
is the motional capacitance of the crystal.
m
is the case capacitance.
case
spec
load
is the specified load capacitance.
is the actual load capacitance.
f
= (f
x 32) +10.7MHz
When the crystal is loaded as specified, i.e., C
spec
=
RECEIVE
XTAL
load
C
, the frequency pulling equals zero.
The received image frequency at:
f
= (f
x 32) -10.7MHz
XTAL
IMAGE
TO FSK BASEBAND FILTER
AND DATA SLICER
IF
PHASE
DETECTOR
CHARGE
PUMP
LOOP
FILTER
LIMITING
AMPS
10.7MHz VCO
2.2mV/kHz
Figure 1. FSK Demodulator PLL Block Diagram
______________________________________________________________________________________ 11
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
ASK DATA OUT
V
DD
3.0V
SCLK
DIO
V
DD
C26
CS
FSK DATA OUT
32 31
30
29
28
27
26
25
V
DD
1
DSA-
24
23
C5
DV
DD
R3
C23
V
CC
2
3
DSA+
OPA+
DGND
C3
22
21
C4
Y1
DFF
4
5
DFA
OPF+
C22
C14
C15
MAX1471
C21
XTAL2
R8
20
19
V
DD
6
7
DSF+
DSF-
XTAL1
C27
AV
DD
C6
18
17
PDMAXF
PDMINF
L1
8
RF INPUT
LNAIN
C7
9
10 11
12
13 14
15 16
C12
C11
C8
C9
L2
L3
V
DD
IN GND
OUT
Y2
C10
Figure 2. Typical Application Circuit
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of the capacitors, use the following equations,
along with the coefficients in Table 2:
Data Filters
The data filters for the ASK and FSK data are imple-
mented as a 2nd-order lowpass Sallen-Key filter. The
pole locations are set by the combination of two on-
chip resistors and two external capacitors. Adjusting
the value of the external capacitors changes the corner
frequency to optimize for different data rates. The cor-
ner frequency in kHz should be set to approximately
1.5 times the fastest expected Manchester data rate in
kbps from the transmitter. Keeping the corner frequen-
cy near the data rate rejects any noise at higher fre-
quencies, resulting in an increase in receiver sensitivity.
b
C
C
=
=
F1
F2
a 100k π f
(
)( )(
)
C
a
4 100k π f
C
where f is the desired 3dB corner frequency.
C
The configuration shown in Figure 3 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
For example, choose a Butterworth filter response with
a corner frequency of 5kHz:
12 ______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 1. Component Values for Typical Application Circuit
COMPONENT
C3
VALUE FOR 433.92MHz RF
VALUE FOR 315MHz RF
220pF
DESCRIPTION (%)
220pF
470pF
10
C4
470pF
5
C5
0.047µF
0.1µF
0.047µF
0.1µF
10
C6
10
C7
100pF
100pF
5
C8
100pF
100pF
5
C9
1.0pF
2.2pF
0.1pF
C10
C11
C12
C14
C15
C21
C22
C23
C26
C27
L1
220pF
220pF
10
100pF
100pF
5
1500pF
15pF
1500pF
15pF
10
5
15pF
15pF
5
220pF
220pF
10
470pF
470pF
5
0.01µF
0.1µF
0.01µF
10
0.1µF
10
0.047µF
56nH
0.047µF
100nH
10
Coilcraft 0603CS
L2
16nH
30nH
Coilcraft 0603CS
L3
10nH
15nH
5
R3
25kΩ
25kΩ
5
R8
25kΩ
25kΩ
5
Y1
13.2256MHz
10.7MHz ceramic filter
9.509MHz
10.7MHz ceramic filter
Crystal
Y2
Murata SFECV10.7 series
Note: Component values vary depending on PC board layout.
set by the voltage on the DSA- pin for the ASK receive
chain (DSF- for the FSK receive chain), which is connect-
ed to the negative input of the data slicer comparator.
1.000
C
C
=
=
≈ 450pF
F1
1.414 100kΩ 3.14 5kHz
)( )( )(
(
)
Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
4 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approxi-
mately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The sizes of R and C affect how fast the threshold
tracks to the analog amplitude. Be sure to keep the cor-
ner frequency of the RC circuit much lower than the
lowest expected data rate.
1.414
≈ 225pF
F2
4 100kΩ 3.14 5kHz
Choosing standard capacitor values changes C to
F1
470pF and C to 220pF. In the Typical Application
F2
Circuit, C and C are named C4 and C3, respective-
F1
F2
ly, for ASK data, and C21 and C22 for FSK data.
Data Slicers
The purpose of a data slicer is to take the analog output
of a data filter and convert it to a digital signal. This is
achieved by using a comparator and comparing the ana-
log input to a threshold voltage. The threshold voltage is
______________________________________________________________________________________ 13
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Figure 5 shows a configuration that uses the positive and
Table 2. Coefficients to Calculate C
F1
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
and C
F2
FILTER TYPE
a
b
Butterworth
(Q = 0.707)
Peak Detectors
The maximum peak detectors (PDMAXA for ASK,
PDMAXF for FSK) and minimum peak detectors (PDMI-
NA for ASK, PDMINF for FSK), in conjunction with resis-
tors and capacitors shown in Figure 5, create DC
output voltages proportional to the high and low peak
values of the filtered ASK or FSK demodulated signals.
The resistors provide a path for the capacitors to dis-
charge, allowing the peak detectors to dynamically fol-
low peak changes of the data-filter output voltages.
1.414
1.000
0.618
Bessel
(Q = 0.577)
1.3617
MAX1471
The maximum and minimum peak detectors can be
used together to form a data-slicer threshold voltage at
a midvalue between the maximum and minimum volt-
age levels of the data stream (see the Data Slicers sec-
tion and Figure 5). The RC time constant of the peak-
detector combining network should be set to at least 5
times the data period.
RSSI OR
FSK DEMOD
100kΩ
100kΩ
DSA+
DSF+
OPA+
OPF+
DFA
DFF
If there is an event that causes a significant change in
the magnitude of the baseband signal, such as an AGC
gain switch or a power-up transient, the peak detectors
may “catch” a false level. If a false peak is detected,
the slicing level is incorrect. The MAX1471 has a fea-
ture called peak-detector track enable (TRK_EN),
where the peak-detector outputs can be reset (see
Figure 6). If TRK_EN is set (logic 1), both the maximum
and minimum peak detectors follow the input signal.
When TRK_EN is cleared (logic 0), the peak detectors
revert to their normal operating mode. The TRK_EN
function is automatically enabled for a short time and
then disabled whenever the IC recovers from the sleep
portion of DRX mode, or when an AGC gain switch
occurs. Since the peak detectors exhibit a fast
attack/slow decay response, this feature allows for an
extremely fast startup or AGC recovery. See Figure 7
for an illustration of a fast-recovery sequence. In addi-
tion to the automatic control of this function, the
TRK_EN bits can be controlled through the serial inter-
face (see the Serial Control Interface section).
C
C
F1
F2
Figure 3. Sallen-Key Lowpass Data Filter
MAX1471
DATA
SLICER
ADATA
FDATA
DSA-
DSF-
DSA+
DSF+
R
C
Power-Supply Connections
The MAX1471 can be powered from a 2.4V to 3.6V sup-
ply or a 4.5V to 5.5V supply. The device has an on-chip
linear regulator that reduces the 5V supply to 3V need-
ed to operate the chip.
Figure 4. Generating Data-Slicer Threshold Using a Lowpass
Filter
With this configuration, a long string of NRZ zeros or
ones can cause the threshold to drift. This configuration
works best if a coding scheme, such as Manchester
coding, which has an equal number of zeros and ones,
is used.
To operate the MAX1471 from a 3V supply, connect
DV , AV , and HV to the 3V supply. When using a
DD
DD
IN
5V supply, connect the supply to HV only and con-
IN
14 ______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
MAX1471
MAXIMUM PEAK
DETECTOR
MINIMUM PEAK
DETECTOR
DATA
SLICER
PDMINA
PDMINF
PDMAXA
PDMAXF
ADATA
FDATA
R
R
C
C
Figure 5. Generating Data-Slicer Threshold Using the Peak Detectors
MINIMUM PEAK
DETECTOR
PDMINA
PDMINF
BASEBAND
FILTER
TRK_EN = 1
TO SLICER
INPUT
MAXIMUM PEAK
DETECTOR
PDMAXA
PDMAXF
MAX1471
TRK_EN = 1
Figure 6. Peak-Detector Track Enable
nect AV
and DV
IN
together. In both cases, bypass
DD
a 0.1µF capacitor. Place all bypass capacitors as close
to the respective supply pin as possible.
DD
DV
and HV with a 0.01µF capacitor and AV
with
DD
DD
______________________________________________________________________________________ 15
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Serial Control Interface
RECEIVER ENABLED, TRK_EN SET
Communication Protocol
The MAX1471 can use a 4-wire interface or a 3-wire
interface (default). In both cases, the data input must
follow the timing diagrams shown in Figures 8 and 9.
TRK_EN CLEARED
MAX PEAK DETECTOR
Note that the DIO line must be held LOW while CS is
high. This is to prevent the MAX1471 from entering dis-
continuous receive mode if the DRX bit is high. The
data is latched on the rising edge of SCLK, and there-
fore must be stable before that edge. The data
sequencing is MSB first, the command (C[3:0]; see
Table 3), the register address (A[3:0]; see Table 4) and
the data (D[7:0]; see Table 5).
200mV/div
FILTER OUTPUT
MIN PEAK DETECTOR
DATA OUTPUT
DATA OUTPUT
2V/div
100µs/div
The mode of operation (3-wire or 4-wire interface) is
selected by DOUT_FSK and/or DOUT_ASK bits in the
configuration register. Either of those bits selects the
ASKOUT and/or FSKOUT line as a SERIAL data output.
Upon receiving a read register command (0x2), the
serial interface outputs the data on either pin, accord-
ing to Figure 10.
Figure 7. Fast Receiver Recovery in FSK Mode Utilizing Peak
Detectors
would do. The reset signal remains active for as long as
CS is high after the command is sent.
Continuous Receive Mode (DRX = 0)
In continuous receive mode, individual analog modules
can be powered on directly through the power configu-
ration register (register 0x0). The SLEEP bit (bit 0)
overrides the power settings of the remaining bits and
puts the part into deep-sleep mode when set. It is also
necessary to write the frequency divisor of the external
crystal in the oscillator frequency register (register 0x3)
to optimize image rejection and to enable accurate cali-
bration sequences for the polling timer and the FSK
If neither of these bits are 1, the 3-wire interface is
selected (default on power-up) and the DIO line is
effectively a bidirectional input/output line. DIO is
selected as an output of the MAX1471 for the following
CS cycle whenever a READ command is received. The
CPU must tri-state the DIO line on the cycle of CS that
follows a read command, so the MAX1471 can drive
the data output line. Figure 11 shows the diagram of
the 3-wire interface. Note that the user can choose to
send either 16 cycles of SCLK, as in the case of the 4-
wire interface, or just eight cycles, as all the registers
are 8-bits wide. The user must drive DIO low at the end
of the read sequence.
demodulator. This number is the integer result of f
100kHz.
/
XTAL
If the FSK receive function is selected, it is necessary to
perform an FSK calibration to improve receive sensitivi-
ty. Polling timer calibration is not necessary. See the
Calibration section for more information.
The MASTER RESET command (0x3) (see Table 3)
sends a reset signal to all the internal registers of the
MAX1471 just like a power-off and power-on sequence
t
CS
t
CSI
CS
t
t
CH
CSS
t
CSH
t
SC
t
CL
SCLK
DIO
t
t
DO
DH
t
TR
t
DI
t
DV
HIGH-IMPEDANCE
HI-Z
HIGH-IMPEDANCE
D7
D0
DATA IN
DATA OUT
Figure 8. Digital Communications Timing Diagram
16 ______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
CS
SCLK
DIO
C3
C2
C1
C0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS
DATA
COMMAND
Figure 9. Data Input Diagram
CS
SCLK
DIO
0
0
1
0
A3
A2
A1
A0
0
0
0
0
0
0
0
0
C3
R7
R7
C2
C1
C0
R4
A3
A2
A1
A0
R0
R0
D7
R7
R7
D0
R0
R0
READ
COMMAND
ADDRESS
DATA
COMMAND
ADDRESS
DATA
R6
R6
R5
R3
R2
R2
R1
ADATA (IF DOUT_ASK = 1)
FDATA (IF DOUT_FSK = 1)
REGISTER
DATA
REGISTER DATA
R5
R4
R3
R1
REGISTER
DATA
REGISTER DATA
Figure 10. Read Command on a 4-Wire SERIAL Interface
Discontinuous Receive Mode (DRX = 1)
In the discontinuous receive mode (DRX = 1), the
power signals of the different modules of the MAX1471
toggle between OFF and ON, according to internal
DIO serves as the wake-up signal for the CPU, which
must then start its wake-up procedure, and drive DIO
low before t
expires (t
+ t ). Once t expires,
CPU RF RF
LOW
the MAX1471 enables the FSKOUT and/or ASKOUT
data outputs. The CPU must then keep DIO low for as
long as it may need to analyze any received data.
Releasing DIO causes the MAX1471 to pull up DIO,
timers t
, t
, and t . It is also necessary to write
OFF CPU RF
the frequency divisor of the external crystal in the oscil-
lator frequency register (register 0x3). This number is
the integer result of f
/ 100kHz. Before entering the
reinitiating the t
timer.
XTAL
OFF
discontinuous receive mode for the first time, it is also
necessary to calibrate the timers (see the Calibration
section).
Oscillator Frequency Register (Address: 0x3)
The MAX1471 has an internal frequency divider that
divides down the crystal frequency to 100kHz. The
MAX1471 uses the 100kHz clock signal when calibrating
itself and also to set the image-rejection frequency. The
hexadecimal value written to the oscillator frequency reg-
The MAX1471 uses a series of internal timers (t
,
OFF
t
, and t ) to control its power-up. The timer
CPU
RF
sequence begins when both CS and DIO are one. The
MAX1471 has an internal pullup on the DIO pin, so the
user must tri-state the DIO line when CS goes high.
ister is the nearest integer result of f
/ 100kHz.
XTAL
The external CPU can then go to a sleep mode during
t . A high-to-low transition on DIO, or a low level on
OFF
______________________________________________________________________________________ 17
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
CS
SCLK
0
0
1
0
A3
A2
A1
A0
0
0
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
R7
R0
DIO
READ
COMMAND
REGISTER
DATA
ADDRESS
DATA
REGISTER DATA
16 BITS OF DATA
CS
SCLK
DIO
0
0
1
0
A3
A2
A1
A0
0
0
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
A3
READ
COMMAND
ADDRESS
DATA
REGISTER DATA
8 BITS OF DATA
Figure 11. Read Command in 3-Wire Interface
ister. To calculate the dwell time, use the following
equation:
Table 3. Command Bits
C[3:0]
0x0
DESCRIPTION
No operation
Write data
2Reg0xA
Dwell Time =
0x1
f
XTAL
0x2
Read data
where Reg 0xA is the value of register 0xA in decimal.
0x3
Master reset
Not used
To calculate the value to write to register 0xA, use the
following equation and use the next integer higher than
the calculated result:
0x4–0xF
For example, if data is being received at 315MHz, the
crystal frequency is 9.509375MHz. Dividing the crystal
frequency by 100kHz and rounding to the nearest inte-
ger gives 95, or 0x5F hex. So for 315MHz, 0x5F would
be written to the oscillator frequency register.
Reg 0xA ≥ 3.3 x log10 (Dwell Time x f
)
XTAL
For Manchester Code (50% duty cycle), set the dwell
time to at least twice the bit period. For nonreturn-to-
zero (NRZ) data, set the dwell to greater than the peri-
od of the longest string of zeros or ones. For example,
using Manchester code at 315MHz (f
9.509375MHz) with a data rate of 4kbps (bit period =
125µs), the dwell time needs to be greater than 250µs:
AGC Dwell Timer Register (Address: 0xA)
The AGC dwell timer holds the AGC in low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state. This is
important for ASK since the modulated data may have
a high level above the threshold and a low level below
the threshold, which without the dwell timer would
cause the AGC to switch on every bit.
=
XTAL
Reg 0xA ≥ 3.3 x log10 (250µs x 9.509375MHz) ≈11.14
Choose the register value to be the next integer value
higher than 11.14, which is 12 or 0x0C hex.
The default value of the AGC dwell timer on power-up
or reset is 0x0D.
The AGC dwell time is dependent on the crystal fre-
quency and the bit settings of the AGC dwell timer reg-
18 ______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 4. Register Summary
REGISTER
A[3:0]
REGISTER NAME
Power configuration
Configuration
DESCRIPTION
Enables/disables the LNA, AGC, mixer, baseband, peak detectors, and sleep mode
(see Table 6).
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
Sets options for the device such as output enables, off-timer prescale, and
discontinuous receive mode (see Table 7).
Controls AGC lock, peak-detector tracking, as well as polling timer and FSK
calibration (see Table 8).
Control
Sets the internal clock frequency divisor. This register must be set to the integer
Oscillator frequency
result of f
/ 100kHz (see the Oscillator Frequency Register section).
XTAL
Off timer—t
OFF
(upper byte)
Sets the duration that the MAX1471 remains in low-power mode when DRX is active
(see Table 10).
Off timer—t
OFF
(lower byte)
Increases maximum time the MAX1471 stays in lower power mode while CPU wakes
up when DRX is active (see Table 11).
CPU recovery timer—t
CPU
RF settle timer—t
(upper byte)
RF
During the time set by the settle timer, the MAX1471 is powered on with the peak
detectors and the data outputs disabled to allow time for the RF section to settle.
DIO must be driven low at any time during t
restarts (see Table 12).
= t
+ t or the timer sequence
CPU RF
LOW
RF settle timer—t
(lower byte)
RF
Provides status for PLL lock, AGC state, crystal operation, polling timer, and FSK
calibration (see Table 9).
0x9
0xA
Status register (read only)
AGC dwell timer
Controls the dwell (release) time of the AGC.
Calibration
FSK_CAL_DONE bit in the status register (register 0x8)
is one, and the FSK_CAL_EN bit is reset to zero.
The MAX1471 must be calibrated to ensure accurate
timing of the off timer in discontinuous receive mode or
when receiving FSK signals. The first step in calibration
is ensuring that the oscillator frequency register
(address: 0x3) has been programmed with the correct
divisor value (see the Oscillator Frequency Register
section). Next, enable the mixer to turn the crystal dri-
ver on.
When in continuous receive mode and receiving FSK
data, recalibrate the FSK receiver after a significant
change in temperature or supply voltage. When in dis-
continuous receive mode, the polling timer and FSK
receiver (if enabled) are automatically calibrated during
every wake-up cycle.
Off Timer (t
)
OFF
Calibrate the polling timer by setting POL_CAL_EN = 1
in the configuration register (register 0x1). Upon com-
pletion, the POL_CAL_DONE bit in the status register
(register 0x8) is 1, and the POL_CAL_EN bit is reset to
zero. If using the MAX1471 in continuous receive
mode, polling timer calibration is not needed.
The first timer, t
(see Figure 12), is a 16-bit timer
OFF
that is configured using: register 0x4 for the upper byte,
register 0x5 for the lower byte, and bits PRESCALE1
and PRESCALE0 in the configuration register (register
0x1). Table 10 summarizes the configuration of the t
OFF
timer. The PRESCALE1 and PRESCALE2 bits set the
size of the shortest time possible (t time base). The
FSK receiver calibration is a two-step process. Set
FSKCALLSB = 1 (register 0x1) or to reduce the calibra-
tion time, accuracy can be sacrificed by setting the
FSKCALLSB = 0. Next, initiate FSK receiver calibration,
set FSK_CAL_EN = 1. Upon completion, the
OFF
data written to the t
registers (0x4 and 0x5) is multi-
plied by the time base to give the total t
OFF
time. On
OFF
power-up, the off timer registers are set to zero and
must be written before using DRX mode.
______________________________________________________________________________________ 19
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 5. Register Configuration
ADDRESS
A3 A2 A1 A0
DATA
D7
D6
D5
D4
D3
D2
D1
D0
POWER CONFIGURATION (0x0)
MIXER_
EN
FSKBB_
EN
FSKPD_ ASKBB_ ASKPD_
0 0 0 0
CONFIGURATION (0x1)
0 0 0 1
LNA_EN AGC_EN
SLEEP
EN
EN
EN
GAIN
FSKCALL
SB
FSK_
DOUT
ASK_
DOUT
TOFF_
PS1
TOFF_
PS0
DRX_
MODE
X
SET*
CONTROL (0x2)
0 0 1 0
AGC
LOCK
FSKTRK_ ASKTRK_
POL_
CAL_EN
FSK_CAL
_EN
X
X
X
EN
d3
t11
t3
EN
d2
t10
t2
OSCILLATOR FREQUENCY (0x3)
0 0 1 1
d7
t15
t7
d6
t14
t6
d5
t13
t5
d4
t12
t4
d1
t9
t1
t1
t9
t1
d0
t8
t0
t0
t8
t0
OFF TIMER (upper byte) (0x4)
0 1 0 0
OFF TIMER (lower byte) (0x5)
0 1 0 1
CPU RECOVERY TIMER (0x6)
0 1 1 0
t7
t6
t5
t4
t3
t2
RF SETTLE TIMER (upper byte) (0x7)
0 1 1 1
t15
t7
t14
t6
t13
t5
t12
t4
t11
t3
t10
t2
RF SETTLE TIMER (lower byte) (0x8)
1 0 0 0
STATUS REGISTER (read only) (0x9)
LOCK
DET
CLK
ALIVE
POL_CAL FSK_CAL
1 0 0 1
AGCST
X
X
X
_DONE
_DONE
AGC DWELL TIMER (0xA)
1 0 1 0
X
X
X
dt4
dt3*
dt2*
dt1
dt0*
*Power-up state = 1. All other bits, power-up state = 0.
During t
, the MAX1471 is operating with very low
counting down, while DIO is held low by the MAX1471.
At the end of t , the t counter begins.
OFF
supply current (5.0µA typ), where all of its modules are
turned off, except for the t timer itself. Upon com-
CPU
RF
OFF
t
is an 8-bit timer, configured through register 0x6.
CPU
The possible t
pletion of the t
by asserting DIO low.
time, the MAX1471 signals the user
OFF
settings are summarized in Table 11.
CPU
The data written to the t
by 120µs to give the total t
register (0x6) is multiplied
CPU
time. On power-up, the
CPU
CPU Recovery Timer (t
)
CPU
CPU timer register is set to zero and must be written
before using DRX mode.
The second timer, t
(see Figure 12), is used to delay
CPU
the power-up of the MAX1471, thereby providing extra
power savings and giving a CPU the time required to
complete its own power-on sequence. The CPU is sig-
naled to begin powering up when the DIO line is pulled
RF Settle Timer (t
)
RF
The third timer, t (see Figure 12), is used to allow the
RF
RF sections of the MAX1471 to power up and stabilize
low by the MAX1471 at the end of t
. t
then begins
OFF CPU
before ASK or FSK data is received. t begins count-
RF
20 ______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 6. Power Configuration Register (Address: 0x0)
BIT LOCATION
(0 = LSB)
POWER-UP
STATE
BIT ID
BIT NAME
LNA enable
AGC enable
Mixer enable
FUNCTION
1 = Enable LNA
0 = Disable LNA
LNA_EN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1 = Enable AGC
0 = Disable AGC
AGC_EN
1 = Enable mixer
0 = Disable mixer
MIXER_EN
FSKBB_EN
FSKPD_EN
ASKBB_EN
ASKPD_EN
SLEEP
FSK baseband
enable
1 = Enable FSK baseband
0 = Disable FSK baseband
FSK peak
detector enable
1 = Enable FSK peak detectors
0 = Disable FSK peak detectors
ASK baseband
enable
1 = Enable ASK baseband
0 = Disable ASK baseband
ASK peak
detector enable
1 = Enable ASK peak detectors
0 = Disable ASK peak detectors
1 = Deep-sleep mode
0 = Normal operation
Sleep mode
ing once t
has expired. At the beginning of t , the
Typical Power-Up Procedure
Here is a typical power-up procedure for receiving either
ASK or FSK signals at 315MHz in continuous mode:
CPU
RF
modules selected in the power control register (register
0x0) are powered up with the exception of the peak
detectors and have the t period to settle.
RF
1) Write 0x3000 to reset the part.
At the end of t , the MAX1471 stops driving DIO low
RF
2) Write 0x10FE to enable all RF and baseband sections.
and enables ADATA, FDATA, and peak detectors if
chosen to be active in the power configuration register
(0x0). The CPU must be awake at this point, and must
hold DIO low for the MAX1471 to remain in operation.
The CPU must begin driving DIO low any time during
3) Write 0x135F to set the oscillator frequency register
to work with a 315MHz crystal.
4) Write 0x1120 to set FSKCALLSB for an accurate
FSK calibration.
t
= t
+ t . If the CPU fails to drive DIO low,
CPU RF
LOW
5) Write 0x1201 to begin FSK calibration.
DIO is pulled high through the internal pullup resistor,
and the timer sequence is restarted, leaving the
MAX1471 powered down. Any time the DIO line is dri-
ven high while the DRX = 1, the DRX sequence is initi-
ated, as defined in Figure 12.
6) Read 0x2900 and verify that bit 0 is 1 to indicate
FSK calibration is done.
The MAX1471 is now ready to receive ASK or FSK data.
Due to the high sensitivity of the receiver, it is recom-
mended that the configuration registers be changed
only when not receiving data. Receiver desensitization
may occur, especially if odd-order harmonics of the
SCLK line fall within the IF bandwidth.
t
is a 16-bit timer, configured through registers 0x7
RF
(upper byte) and 0x8 (lower byte). The possible t set-
RF
tings are in Table 12. The data written to the t register
RF
(0x7 and 0x8) is multiplied by 120µs to give the total t
RF
time. On power-up, the RF timer registers are set to
zero and must be written before using DRX mode.
______________________________________________________________________________________ 21
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 7. Configuration Register (Address: 0x1)
BIT LOCATION
(0 = LSB)
POWER-UP
STATE
BIT ID
BIT NAME
FUNCTION
X
Don’t care
7
6
0
1
Don’t care.
0 = LNA low-gain state.
1 = LNA high-gain state.
For manual gain control, enable the AGC (AGC_EN =
1), set LNA gain state to desired setting, then disable
the AGC (AGC_EN = 0).
GAINSET
Gain set
FSKCALLSB = 1 enables a longer, more accurate
FSK calibration.
FSKCALLSB = 0 provides for a quick, less accurate
FSK calibration.
FSK accurate
calibration
FSKCALLSB
5
0
This bit enables the FDATA pin to act as the serial
data output in 4-wire mode. (See the Communication
Protocol section.)
DOUT_FSK
DOUT_ASK
FSKOUT enable
ASKOUT enable
4
3
0
0
This bit enables the ADATA pin to act as the serial
data output in 4-wire mode. (See the Communication
Protocol section.)
TOFF_PS1
TOFF_PS0
Off-timer prescale
Off-timer prescale
2
1
0
0
Sets LSB size for the off timer. (See the Off Timer
section.)
1 = Discontinuous receive mode. (See the
Discontinuous Receive Mode section.)
0 = Continuous receive mode. (See the Continuous
Receive Mode section.)
DRX_MODE
Receive mode
0
0
can have a dramatic effect on the effective inductance
of a passive component. For example, a 0.5in trace
connecting a 100nH inductor adds an extra 10nH of
inductance or 10%.
Layout Considerations
A properly designed PC board is an essential part of
any RF/microwave circuit. On high-frequency inputs
and outputs, use controlled-impedance lines and keep
them as short as possible to minimize losses and radia-
tion. At high frequencies, trace lengths that are on the
order of λ/10 or longer act as antennas.
To reduce the parasitic inductance, use wider traces
and a solid ground or power lane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
Keeping the traces short also reduces parasitic induc-
tance. Generally, 1in of a PC board trace adds about
20nH of parasitic inductance. The parasitic inductance
close to all V
or HV connections.
IN
DD
22 ______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 8. Control Register (Address: 0x2)
BIT LOCATION
(0 = LSB)
POWER-UP
STATE
BIT ID
BIT NAME
FUNCTION
X
AGCLOCK
X
None
AGC lock
None
7
6
Don’t care
0
Don’t care.
Locks the LNA gain in its present state.
Don’t care.
5, 4
FSK peak
detector track
enable
Enables the tracking mode of the FSK peak detectors
when FSKTRK_EN = 1. (See the Peak Detectors
section.)
FSKTRK_EN
ASKTRK_EN
3
2
0
0
ASK peak
detector track
enable
Enables the tracking mode of the ASK peak detectors
when ASKTRK_EN = 1.
(See the Peak Detectors section.)
POL_CAL_EN = 1 starts the polling timer calibration.
Calibration of the polling timer is needed when using
the MAX1471 in discontinous receive mode.
POL_CAL_EN resets when calibration completes
properly. (See the Calibration section.)
Polling timer
calibration enable
POL_CAL_EN
FSK_CAL_EN
1
0
0
0
FSK_CAL_EN starts the FSK receiver calibration.
FSK_CAL_EN resets when calibration completes
properly. (See the Calibration section.)
FSK calibration
enable
Table 9. Status Register (Read Only) (Address: 0x9)
BIT LOCATION
BIT ID
LOCKDET
AGCST
BIT NAME
Lock detect
AGC state
FUNCTION
(0 = LSB)
0 = Internal PLL is not locked so the MAX1471 will not receive data.
1 = Internal PLL is locked.
7
0 = LNA in low-gain state.
1 = LNA in high-gain state.
6
Clock/crystal
alive
0 = No valid clock signal seen at the crystal inputs.
1 = Valid clock at crystal inputs.
CLKALIVE
X
5
4, 3, 2
1
None
Don’t care.
Polling timer
calibration done
0 = Polling timer calibraton in progress or not completed.
1 = Polling timer calibration is complete.
POL_CAL_DONE
FSK calibration
done
0 = FSK calibration in progress or not completed.
1 = FSK calibration is compete.
FSK_CAL_DONE
0
______________________________________________________________________________________ 23
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
CS
DIO
t
t
OFF
OFF
t
t
CPU
CPU
t
LOW
t
t
RF
RF
ADATA OR
FDATA
Figure 12. DRX Mode Sequence of the MAX1471
Table 10. Off-Timer (t ) Configuration
OFF
MIN t
REG 0x4 = 0x00
REG 0x5 = 0x01
MAX t
OFF
REG 0x4 = 0xFF
REG 0x5 = 0xFF
OFF
t
TIME BASE
(1 LSB)
OFF
PRESCALE1
PRESCALE0
0
0
1
1
0
1
0
1
120µs
480µs
120µs
480µs
7.86s
31.46s
1920µs
7680µs
1.92ms
7.68ms
2 min 6s
8 min 23s
Table 11. CPU Recovery Timer (t
Configuration
)
Chip Information
TRANSISTOR COUNT: 21,344
CPU
PROCESS: CMOS
TIME BASE
(1 LSB)
MIN t
REG 0x6 = 0x01
MAX t
CPU
REG 0x6 = 0xFF
CPU
120µs
120µs
30.72ms
Table 12. RF Settle Timer (t
Configuration
)
RF
MIN t
REG 0x7 = 0x00
REG 0x8 = 0x01
MAX t
RF
REG 0x7 = 0xFF
REG 0x8 = 0xFF
RF
TIME BASE
(1 LSB)
120µs
120µs
7.86s
24 ______________________________________________________________________________________
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
0.15
C A
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
PIN # 1
I.D.
0.15
C
B
PIN # 1 I.D.
0.35x45∞
E/2
E2/2
C
(NE-1) X
e
L
E2
E
k
L
DETAIL A
e
(ND-1) X
e
DETAIL B
e
L
C
L
C
L
L1
L
L
e
e
0.10
C
A
0.08
C
C
A1 A3
PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
1
E
21-0140
2
______________________________________________________________________________________ 25
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
D2 E2
MIN. NOM. MAX. MIN. NOM. MAX.
DOWN
BONDS
ALLOWED
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
16L 5x5
32L 5x5
40L 5x5
PKG.
CODES
T1655-1 3.00 3.10 3.20 3.00 3.10 3.20
NO
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
T1655-2 3.00 3.10 3.20 3.00 3.10 3.20 YES
NO
T2055-3 3.00 3.10 3.20 3.00 3.10 3.20 YES
A1
-
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.05
0.20 REF.
T2055-2 3.00 3.10 3.20 3.00 3.10 3.20
A3
b
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
NO
T2055-4 3.00 3.10 3.20 3.00 3.10 3.20
D
E
T2855-1 3.15 3.25 3.35 3.15 3.25 3.35
T2855-2 2.60 2.70 2.80 2.60 2.70 2.80
NO
NO
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
T2855-3 3.15 3.25 3.35 3.15 3.25 3.35 YES
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
YES
NO
T2855-4 2.60 2.70 2.80 2.60 2.70 2.80
T2855-5 2.60 2.70 2.80 2.60 2.70 2.80
T2855-6 3.15 3.25 3.35 3.15 3.25 3.35
L
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
NO
N
ND
16
4
4
20
5
5
28
7
7
32
8
8
40
10
10
2.80
3.20
T2855-7 2.60 2.70
T3255-2
T3255-3 3.00 3.10
2.60 2.70 2.80 YES
NO
3.00 3.10 3.20 YES
NO
3.00 3.10
3.00 3.10 3.20
NE
3.20
WHHB
WHHC
WHHD-1
WHHD-2
-
JEDEC
T3255-4 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40 YES
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3 AND T2855-6.
PACKAGE OUTLINE
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
2
E
21-0140
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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