LTC4232IDHC-1#PBF [Linear]
LTC4232-1 - 5A Integrated Hot Swap Controller; Package: DFN; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC4232IDHC-1#PBF |
| 厂家： | 
Linear |
| 描述： | LTC4232-1 - 5A Integrated Hot Swap Controller; Package: DFN; Pins: 16; Temperature Range: -40°C to 85°C 光电二极管 |
| 文件： | 总18页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4232-1
5A Integrated Hot Swap
Controller
FeaTures
DescripTion
The LTC®4232-1 is an integrated solution for Hot Swap
applications that allows a board to be safely inserted and
removed from a live backplane. The part integrates a Hot
Swap controller, power MOSFET and current sense resis-
tor in a single package for small form factor applications.
n
Reduced 16ms Turn-On Delay
n
Small Footprint
33mΩ MOSFET with R
n
SENSE
n
n
n
n
n
n
n
n
n
n
Wide Operating Voltage Range: 2.9V to 15V
Adjustable, 10% Accurate Current Limit
Current and Temperature Monitor Outputs
Overtemperature Protection
Adjustable Current Limit Timer Before Fault
Power Good and Fault Outputs
Adjustable Inrush Current Control
2% Accurate Undervoltage and Overvoltage Protection
Pin Compatible with LTC4217 (DFN Package Only)
Available in 16-Lead 5mm × 3mm DFN Package
The LTC4232-1 provides separate inrush current control
and a 10% accurate 5A current limit with foldback cur-
rent limiting. The current limit threshold can be adjusted
dynamically using an external pin. Additional features
include a current monitor output that amplifies the sense
resistor voltage for ground referenced current sensing
andaMOSFETtemperaturemonitoroutput.Thermallimit,
overvoltage, undervoltage and power good monitoring
are also provided.
applicaTions
ThePCIExpresscompliantLTC4232-1allowsfasterturn-on
thantheLTC4232byprovidingashorter(16ms)debounce
delay and external control of the GATE ramp rate.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation and PowerPath is a trademark of Linear Technology Corporation. All
other trademarks are the property of their respective owners.
n
RAID Systems, Solid State Drives
n
Server I/O Cards
PCI Express Systems
n
n
Industrial
Typical applicaTion
12V, 5A Card Resident Application with Auto-Retry
Power-Up Waveforms
V
12V
5A
OUT
V
OUT
FB
12V
DD
+
150k
20k
V
*
IN
150µF
CONTACT BOUNCE
107k
10V/DIV
UV
10k
FLT
I
IN
LTC4232DHC-1
1A/DIV
5.23k
10k
3.3nF
100k
OV
PG
V
OUT
10V/DIV
GATE
4.7nF
TIMER
I
SET
PG
10V/DIV
0.1µF
I
INTV
CC
ADC
MON
1µF
GND
20k
42321 TA01a
42321 TA01b
4ms/DIV
*TVS: DIODES INC. SMAJ17A
42321fb
1
For more information www.linear.com/LTC4232-1
LTC4232-1
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
Supply Voltage (V )................................. –0.3V to 28V
DD
V
1
2
3
4
5
6
7
8
16
15
14
V
Input Voltages
DD
DD
SET
MON
UV
OV
I
I
FB, OV, UV ..............................................–0.3V to 12V
TIMER................................................... –0.3V to 3.5V
TIMER
13 FB
17
SENSE
SENSE .............................V – 10V or – 0.3V to V
DD
DD
INTV
12 FLT
11 PG
10 GATE
CC
Output Voltages
GND
OUT
OUT
I
, I
................................................. –0.3V to 3V
SET MON
PG, FLT .................................................. –0.3V to 35V
9
OUT
OUT ............................................ –0.3V to V + 0.3V
DD
DHC PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
INTV .................................................. –0.3V to 3.5V
CC
GATE (Note 3)........................................ –0.3V to 33V
T
= 125°C, θ = 43°C/W
JA
EXPOSED PAD (PIN 17) IS SENSE,
= 43°C/W SOLDERED, OTHERWISE θ = 140°C/W
JMAX
Operating Ambient Temperature Range
θ
JA
JA
LTC4232C-1 ............................................. 0°C to 70°C
LTC4232I-1 ..........................................–40°C to 85°C
Junction Temperature (Notes 4, 5)........................ 125°C
Storage Temperature Range .................. –65°C to 150°C
orDer inForMaTion
LEAD FREE FINISH
LTC4232CDHC-1#PBF
LTC4232IDHC-1#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4232CDHC-1#TRPBF 42321
LTC4232IDHC-1#TRPBF 42321
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
elecTrical characTerisTics The l denotes those specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Characteristics
l
l
l
V
Input Supply Range
2.9
15
3
V
mA
V
DD
I
Input Supply Current
MOSFET On, No Load
1.6
DD
V
Input Supply Undervoltage Lockout
OUT Leakage Current
V
Rising
2.63
2.73
2.85
DD(UVL)
DD
l
l
I
V
V
= V
= V
= 0V, V = 15V
0
2
150
4
µA
µA
OUT
OUT
OUT
GATE
GATE
DD
= 12V
1
l
l
l
l
R
MOSFET + Sense Resistor On-Resistance
Current Limit Threshold
15
33
5.6
1.5
2.9
50
6.1
1.8
3.3
mΩ
A
ON
I
V = 1.23V, I Open
5.0
1.2
2.6
LIM(TH)
SET
V
FB
V
FB
= 0V, I Open
A
SET
= 1.23V, R = 20kΩ
A
SET
42321fb
2
For more information www.linear.com/LTC4232-1
LTC4232-1
elecTrical characTerisTics The l denotes those specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
Inputs
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
l
l
I
OV, UV, FB Input Current
OV, UV, FB Threshold Voltage
OV Hysteresis
V = 1.2V
0
1.235
20
1
1.26
30
µA
V
IN
V
V
Rising
1.21
10
TH
PIN
UV
ΔV
ΔV
mV
mV
V
OV(HYST)
UV(HYST)
UV(RTH)
UV Hysteresis
50
80
110
0.7
30
V
UV Reset Threshold Voltage
FB Power Good Hysteresis
V
Falling
0.55
10
0.62
20
ΔV
mV
kΩ
FB(HYST)
R
I
Internal Resistor
SET
19
20
21
ISET
Outputs
l
l
l
l
l
l
l
l
V
V
INTV Output Voltage
V
= 5V, 15V, I = 0mA, –10mA
LOAD
2.8
3.1
0.4
0
3.3
0.8
V
V
INTVCC
OL
CC
DD
PG, FLT Output Low Voltage
PG, FLT Input Leakage Current
TIMER High Threshold
I
= 2mA
SINK
I
V = 30V
10
µA
V
OH
V
V
V
V
V
V
Rising
Falling
= 0V
1.2
0.1
–80
1.4
1.6
1.235
0.21
–100
2
1.28
0.3
TIMER(H)
TIMER(L)
TIMER
TIMER
TIMER
TIMER
TIMER Low Threshold
V
I
I
I
TIMER Pull-Up Current
–120
2.6
µA
µA
%
TIMER(UP)
TIMER(DN)
TIMER(RATIO)
TIMER Pull-Down Current
= 1.2V
TIMER Current Ratio I
/I
2
2.7
TIMER(DN) TIMER(UP)
BW
I
I
I
Bandwidth
250
20
kHz
µA/A
µA
µA
µA
mA
IMON
MON
MON
MON
l
l
l
l
A
IMON
Current Gain
Offset Current
I
I
= 2.5A
18.5
21.5
4.5
OUT
OUT
I
I
I
I
= 150mA
0
OFF(IMON)
GATE(UP)
GATE(DN)
GATE(FST)
Gate Pull-Up Current
Gate Drive On, V
= V
= 12V
–18
180
–24
250
140
–29
400
GATE
OUT
Gate Pull-Down Current
Gate Drive Off, V
= 18V, V
= 12V
GATE
OUT
Gate Fast Pull-Down Current
Fast Turn Off, V
= 18V, V
= 12V
GATE
OUT
AC Characteristics
l
l
l
t
Input High (OV), Input Low (UV) to Gate Low
Propagation Delay
V
< 16.5V Falling
GATE
8
1
10
5
µs
µs
PHL(GATE)
t
Short-Circuit to Gate Low
V
V
= 0, Step I
to 6A,
PHL(ILIM)
FB
GATE
SENSE
< 15V Falling
t
t
t
t
Turn-On Delay
Step V to 2V, V
> 13V
to 3A
8
16
1
24
ms
µs
D(ON)
UV
GATE
UV
LOW
to Clear Fault Latch Delay
D(FAULT)
D(CB)
l
l
Circuit Breaker Filter Delay Time (Internal)
Auto-Retry Turn-On Delay (Internal)
V
= 0V, Step I
1.3
8
2
2.7
24
ms
ms
FB
SENSE
16
D(AUTO-RETRY)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V
above OUT. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: T is calculated from the ambient temperature, T , and power
J A
dissipation, P , according to the formula:
D
T = T + (P • 43°C/W)
J
A
D
42321fb
3
For more information www.linear.com/LTC4232-1
LTC4232-1
Typical perForMance characTerisTics TA = 25°C, VDD = 12V unless otherwise noted.
UV Low-High Threshold
vs Temperature
IDD vs VDD
INTVCC Load Regulation
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.8
1.6
1.4
1.234
1.232
1.230
1.228
1.226
V
= 5V
DD
V
= 3.3V
DD
85°C
25°C
–40°C
1.2
1.0
0
–2
–4
–6
–8 –10 –12 –14
(mA)
0
5
10
15
(V)
20
25
30
–50
–25
0
25
50
75
100
I
V
TEMPERATURE (°C)
LOAD
DD
42321 G02
42321 G01
42321 G03
Timer Pull-Up Current
vs Temperature
Current Limit Delay
UV Hysteresis vs Temperature
(tPHL(ILIM) vs Overdrive)
0.10
0.08
0.06
0.04
–110
–105
–100
–95
1000
100
10
1
–90
0.1
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
0
10
20
30
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT CURRENT (A)
42321 G04
42321 G05
42321 G06
Current Limit Adjustment
(IOUT vs RSET
Internal ISET Resistor (RISET
)
Current Limit Threshold Foldback
)
vs Temperature
6
5
4
3
2
1
0
6
5
4
3
2
1
0
22
21
20
19
18
I
OPEN
SET
0
0.2
0.4
0.6
0.8
1.0
1.2
1k
10k
100k
(Ω)
1M
10M
–50
–25
0
25
50
75
100
FB VOLTAGE (V)
R
TEMPERATURE (°C)
SET
42321 G07
42321 G08
42321 G09
42321fb
4
For more information www.linear.com/LTC4232-1
LTC4232-1
Typical perForMance characTerisTics TA = 25°C, VDD = 12V unless otherwise noted.
PG, FLT Output Low Voltage
vs Current
RON vs VDD and Temperature
MOSFET SOA Curve
10
1
14
12
10
8
60
50
40
30
20
10
0
PG
FLT
V
= 3.3V, 12V
DD
1ms
10ms
6
100ms
1s
10s
DC
0.1
0.01
4
T
= 25°C
A
2
MULTIPLE PULSE
DUTY CYCLE = 0.2
0
0.1
1
10
100
0
2
4
6
8
10
12
–50
–25
0
25
50
75
100
V
(V)
CURRENT (mA)
TEMPERATURE (°C)
DS
42321 G11
42321 G12
42321 G10
GATE Pull-Up Current
vs Temperature
Gate Drive
vs Gate Pull-Up Current
IMON vs Temperature and VDD
7
6
5
4
3
2
1
0
–105
–100
–95
–26.0
–25.5
–25.0
–24.5
–24.0
V
LOAD
= 3.3V, 12V
DD
V
= 12V
DD
I
= 5A
–90
V
= 3.3V
DD
–85
–80
0
–5
–10
–15
(µA)
–20
–50
–25
0
25
TEMPERATURE (°C)
50
75
100
–50
–25
0
25
50
75
100
–25
–30
TEMPERATURE (°C)
I
GATE
42321 G15
42321 G13
42321 G14
Gate Drive vs VDD
Gate Drive vs Temperature
VISET vs Temperature
6.2
6.0
5.8
5.6
5.4
5.2
6.15
6.14
6.13
6.12
6.11
6.10
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0
5
10
15
(V)
20
25
30
–50
–25
0
25
50
75
100
–50 –25
0
25 50 75 100 125 150
V
TEMPERATURE (°C)
TEMPERATURE (°C)
DD
42321 G16
42321 G17
42321 G18
42321fb
5
For more information www.linear.com/LTC4232-1
LTC4232-1
pin FuncTions
FB: Foldback and Power Good Input. Connect this pin to
an external resistive divider from OUT. If the voltage falls
below 0.6V, the current limit is reduced using a foldback
profile (see the Typical Performance Characteristics sec-
tion). If the voltage falls below 1.21V, the PG pin will pull
low to indicate the power is bad.
OUT: Output of Internal MOSFET Switch. Connect this pin
directly to the load.
OV: Overvoltage Comparator Input. Connect this pin to an
external resistive divider from V . If the voltage at this
DD
pin rises above 1.235V, an overvoltage is detected and
the switch turns off. Tie to GND if unused.
FLT: Overcurrent Fault Indicator. Open-drain output pulls
low when an overcurrent fault has occurred and the circuit
breaker trips. For overcurrent auto-retry tie to UV pin (see
the Applications Information section for details).
PG: Power Good Indicator. Open-drain output pulls low
whentheFBpindropsbelow1.21Vindicatingthepoweris
bad. If the FB pin rises above 1.23V and the GATE to OUT
voltage exceeds 4.2V, the open-drain pull-down releases
the PG pin to go high.
GATE:GateDriveforInternalN-channelMOSFET.Aninternal
24µA current source charges the gate of the N-channel
MOSFET.Aresistorandcapacitornetworkfromthispinsets
the turn-on rate. During an undervoltage or overvoltage
condition a 250µA pull-down current turns the MOSFET
off. During a short-circuit or undervoltage lockout condi-
tion, a 140mA pull-down current source between GATE
and OUT is activated.
SENSE: Current Sense Node and MOSFET Drain. The cur-
rent limit circuit controls the GATE pin to limit the sense
voltage between the V and SENSE pins to 42mV (5.6A)
DD
orlessdependingonthevoltageattheFBpin.Theexposed
pad on DHC packages are connected to SENSE and must
be soldered to an electrically isolated printed circuit board
trace to properly transfer the heat out of the package.
GND: Device Ground.
TIMER: Timer Input. Connect a capacitor between this pin
and ground to set a 12ms/µF duration for current limit
before the switch is turned off. If the UV pin is toggled
low while the MOSFET switch is off, the switch will turn on
againfollowingacooldowntimeof518ms/µFduration.Tie
I
: Current Monitor Output. The current in the internal
MON
MOSFETswitchisdividedby50,000andsourcedfromthis
pin. Placing a 20k resistor from this pin to GND creates a
0Vto2Vvoltageswingwhencurrentrangesfrom0Ato5A.
this pin to INTV for a fixed 2ms overcurrent delay. Note
CC
INTV : Internal 3.1V Supply Decoupling Output. This pin
CC
that the fixed 2ms overcurrent delay is not recommended
must have a 1µF or larger bypass capacitor. Overloading
whenauto-retryisenabled(seeApplicationsInformation).
this pin can disrupt internal operation.
UV: Undervoltage Comparator Input. Tie high if unused.
I
:CurrentLimitAdjustmentPin. Fora5.6Acurrentlimit
SET
Connect this pin to an external resistive divider from V .
DD
value open this pin. This pin is driven by a 20k resistor
in series with a voltage source. The pin voltage is used
to generate the current limit threshold. The internal 20k
If the UV pin voltage falls below 1.15V, an undervoltage is
detected and the switch turns off. Pulling this pin below
0.62V resets the overcurrent fault and allows the switch
to turn back on (see the Applications Information section
for details). If overcurrent auto-retry is desired then tie
this pin to the FLT pin.
resistor (R ) and an external resistor (R ) between
ISET
SET
I
andgroundcreateanattenuatorthatlowersthecurrent
SET
limit value. Due to circuit tolerance, R
should not be
SET
less than 2k. In order to match the temperature variation
of the sense resistor, the voltage on this pin increases at
thesamerateasthesenseresistanceincreases. Therefore
V : Supply Voltage and Current Sense Input. This pin
DD
has an undervoltage lockout threshold of 2.73V.
the voltage at I pin is made proportional to temperature
SET
of the MOSFET switch.
42321fb
6
For more information www.linear.com/LTC4232-1
LTC4232-1
FuncTional DiagraM
SENSE
(EXPOSED PAD)
GATE
INTERNAL 7.5mΩ
SENSE RESISTOR
INTERNAL 25mΩ
MOSFET
6.15V
V
DD
OUT
I
I
MON
SET
CLAMP
X1
CHARGE
PUMP
AND GATE
DRIVER
f = 2MHz
–
+
R
ISET
20k
CS
0.6V POSITIVE
TEMPERATURE
COEFFICIENT
REFERENCE
+–
OUT
FB
CM
FOLDBACK
0.6V
+
–
1.235V
0.62V
+
–
UV
RST
OV
PG
UV
1.235V
LOGIC
PG
+
–
0.21V
+
–
FLT
TM1
TM2
INTV
CC
OV
+
–
100µA
1.235V
2µA
+
–
V
DD
V
DD
–
1.235V
3.1V
GEN
INTV
UVLO1
CC
2.73V
+
–
+
UVLO2
TIMER
2.65V
42321 BD
GND
42321fb
7
For more information www.linear.com/LTC4232-1
LTC4232-1
operaTion
The Functional Diagram displays the main circuits of
the device. The LTC4232-1 is designed to turn a board’s
supply voltage on and off in a controlled manner allowing
the board to be safely inserted and removed from a live
backplane. TheLTC4232-1includesa25mΩMOSFETand
a 7.5mΩ current sense resistor. During normal opera-
tion, the charge pump and gate driver turn on the pass
MOSFET’s gate to provide power to the load. The inrush
currentcontrolisaccomplishedbyaresistorandcapacitor
network connected to the GATE pin. This circuit limits the
GATE ramp rate and hence controls the voltage ramp rate
of the output capacitor.
ing the 2µA current source until the voltage drops below
0.21V (Comparator TM1) which tells the logic to start
an internal 16ms timer. At this point, the pass transistor
has cooled and it is safe to turn it on again. Latchoff is
the normal operating condition following overcurrent
turn-off. Retry is initiated by pulling the UV pin low for
a minimum of 1µs then high. Auto-retry is implemented
by tying the FLT to the UV pin.
The output voltage is monitored using the FB pin and the
PG comparator to determine if the power is available for
the load. The power good condition is signaled by the PG
pin using an open-drain pull-down transistor.
Thecurrentsense(CS)amplifiermonitorstheloadcurrent
usingthevoltagesensedacrossthecurrentsenseresistor.
The CS amplifier limits the current in the load by reduc-
ing the GATE-to-OUT voltage in an active control loop. It
is simple to adjust the current limit threshold using the
TheFunctionalDiagramalsoshowsthemonitoringblocks
of the LTC4232-1. The two comparators on the left side
include the UV and OV comparators. These comparators
determineiftheexternalconditionsarevalidpriortoturning
on the MOSFET. But first the undervoltage lockout circuits
UVLO1 and UVLO2 must validate the input supply and
current limit adjustment (I ) pin. This allows a different
SET
threshold during other times such as start-up.
the internally generated 3.1V supply (INTV ) and gener-
CC
A short circuit on the output to ground causes significant
power dissipation during active current limiting. To limit
this power, the foldback amplifier reduces the current
limit value from 5.6A to 1.5A in a linear manner as the
FB pin drops below 0.6V (see the Typical Performance
Characteristics section).
ate the power up initialization to the logic circuits. If the
external conditions remain valid for 16ms the MOSFET is
allowed to turn on.
Other features include MOSFET current and temperature
monitoring. The current monitor (CM) outputs a current
proportionaltothesenseresistorcurrent.Thiscurrentcan
drive an external resistor or other circuits for monitoring
purposes. AvoltageproportionaltotheMOSFETtempera-
If an overcurrent condition persists, the TIMER pin ramps
up with a 100µA current source until the pin voltage
exceeds 1.235V (comparator TM2). This indicates to the
logic that it is time to turn off the pass MOSFET to prevent
overheating. At this point the TIMER pin ramps down us-
ture is output to the I pin. The MOSFET is protected by
SET
a thermal shutdown circuit.
42321fb
8
For more information www.linear.com/LTC4232-1
LTC4232-1
applicaTions inForMaTion
The typical LTC4232-1 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. A complete application circuit
is shown in Figure 1. External component selection is
discussed in detail in the following sections.
V
DD
+ 6.15V
GATE
OUT
SLOPE = 24µA/C
GATE
V
DD
Turn-On Sequence
Several conditions must be present before the internal
42321 F02
t1
t2
pass MOSFET can be turned on. First the supply V must
DD
exceed its undervoltage lockout level. Next the internally
Figure 2. Supply Turn-On
generated supply INTV must cross its 2.65V undervolt-
CC
agethreshold.Thisgeneratesa25µspower-on-resetpulse
The voltage at the GATE pin rises with a slope equal to
whichclearsthefaultregisterandinitializesinternallatches.
24µA/C
and the supply inrush current is set at:
GATE
After the power-on-reset pulse, the UV and OV pins must
indicate that the input voltage is within the acceptable
range. All of these conditions must be satisfied for the
duration of 16ms to ensure that any contact bounce dur-
ing the insertion has ended.
CL
IINRUSH
=
•24µA
CGATE
When the GATE voltage reaches the MOSFET threshold
voltage, the switch begins to turn on and the OUT volt-
age follows the GATE voltage as it increases. Once OUT
reaches V , the GATE will ramp up until clamped by the
6.15V Zener between GATE and OUT.
The MOSFET is turned on by charging up the GATE with a
24µA charge pump generated current source (Figure 2).
DD
V
12V
2A
OUT
V
OUT
LTC4232-1
12V
DD
C
R5
COMP
Z1*
3.3nF
150k
+
R3
C
L
FB
140k
150µF
R6
20k
UV
FLT
OV
GATE
R
R1
GATE
100k
C
4.7nF
226k
R7
10k
GATE
R2
20k
R4
20k
PG
I
SET
R
SET
20k
TIMER
INTV
CC
I
MON
ADC
UV = 9.88V
OV = 15.2V
PG = 10.5V
C
C1
1µF
T
R
GND
MON
0.1µF
20k
42321 F01
*TVS Z1: DIODES INC. SMAJ17A
Figure 1. 2A, 12V Card Resident Application
42321fb
9
For more information www.linear.com/LTC4232-1
LTC4232-1
applicaTions inForMaTion
As the OUT voltage rises, so will the FB pin which is moni-
toring it. Once the FB pin crosses its 1.235V threshold
and the GATE to OUT voltage exceeds 4.2V, the PG pin
will cease to pull low and indicate that the power is good.
If V drops below 2.65V for greater than 5µs or INTV
DD CC
drops below 2.5V for greater than 1µs, a fast shutdown
of the switch is initiated. The GATE is pulled down with a
140mA current to the OUT pin.
Parasitic MOSFET Oscillation
Overcurrent Fault
When the N-channel MOSFET ramps up the output dur-
ing power-up it operates as a source follower. The source
follower configuration may self-oscillate in the range of
25kHz to 300kHz when the load capacitance is less than
10µF, especially if the wiring inductance from the supply
The LTC4232-1 features an adjustable current limit with
foldbackthatprotectsagainstshort-circuitsandexcessive
loadcurrent.Topreventexcessivepowerdissipationinthe
switch during active current limit, the available current is
reduced as a function of the output voltage sensed by the
FBpin.AgraphintheTypicalPerformanceCharacteristics
curves shows the Current Limit Threshold Foldback.
to the V pin is greater than 3µH. The possibility of oscil-
DD
lation will increase as the load current (during power-up)
increases. There are two ways to prevent this type of
oscillation. The simplest way is to avoid load capacitances
below 10µF. For wiring inductance larger than 20µH, the
minimumloadcapacitancemayextendto100µF.Asecond
Anovercurrentfaultoccurswhenthecurrentlimitcircuitry
has been engaged for longer than the timeout delay set
by the TIMER. Current limiting begins when the MOSFET
current reaches 1.5A to 5.6A (depending on the foldback).
The GATE pin is then brought down with a 140mA GATE-
to-OUT current. The voltage on the GATE is regulated in
order to limit the current to less than 5.6A. At this point,
a circuit breaker time delay starts by charging the external
timing capacitor with a 100µA pull-up current from the
TIMER pin. If the TIMER pin reaches its 1.235V threshold,
the internal switch turns off (with a 250µA current from
GATE to ground). Included in the Typical Performance
Characteristics curves is a graph of the Safe Operating
Area for the MOSFET. From this graph one can determine
the MOSFET’s maximum time in current limit for a given
output power.
choice is to connect an external gate capacitor C >1.5nF
P
as shown in Figure 3.
GATE
C
P
OPTIONAL
2.2nF
RC TO LOWER
INRUSH CURRENT
LTC4232-1
42321 F03
Figure 3. Compensation for Small CLOAD
Turn-Off Sequence
The switch can be turned off by a variety of conditions. A
normal turn-off is initiated by the UV pin going below its
1.235V threshold. Additionally, several fault conditions
will turn off the switch. These include an input overvolt-
age (OV pin), overcurrent circuit breaker (SENSE pin) or
overtemperature. Normally the switch is turned off with
a 250µA current pulling down the GATE pin to ground.
With the switch turned off, the OUT voltage drops which
pulls the FB pin below its threshold. PG then pulls low to
indicate output power is no longer good.
Tying the TIMER pin to INTV will force the part to use
CC
the internally generated (circuit breaker) delay of 2ms.
In either case the FLT pin is pulled low to indicate an
overcurrent fault has turned off the pass MOSFET. For a
given circuit breaker time delay, the equation for setting
the timing capacitor’s value is as follows:
C = t • 0.083[µF/ms]
T
CB
42321fb
10
For more information www.linear.com/LTC4232-1
LTC4232-1
applicaTions inForMaTion
component allows the GATE pin to undershoot during a
short circuit on the output and chatter as it settles. This
After the switch is turned off, the TIMER pin begins
discharging the timing capacitor with a 2µA pull-down
current. When the TIMER pin reaches its 0.21V threshold,
an internal 16ms timer is started. After the 16ms delay,
the switch is allowed to turn on again if the overcurrent
fault latch has been cleared. Bringing the UV pin below
0.6V for minimum of 1µs and then high will clear the fault
chatter could last about 1µs to 2µs for every nF of C
GATE
capacitance.
Typical Compensation
Alternate Compensation
OUT
OUT
C
COMP
latch. If the TIMER pin is tied to INTV then the switch is
3.3nF
GATE
CC
LTC4232-1
GATE
LTC4232-1
R
R
GATE
270Ω
allowed to turn on again (after an internal 16ms delay), if
100k
GATE
the overcurrent fault latch is cleared.
C
C
GATE
4.7nF
GATE
4.7nF
42321 F05
Tying the FLT pin to the UV pin allows the part to self-clear
the fault and turn the MOSFET on as soon as TIMER pin
has ramped below 0.21V. In this auto-retry mode the
LTC4232-1 repeatedly tries to turn on after an overcurrent
at a period determined by the capacitor on the TIMER pin.
Figure 5. Compensation Components on the GATE Pin
Current Limit Adjustment
The default value of the active current limit is 5.6A. The
current limit threshold can be adjusted lower by placing
When the TIMER pin is tied to INTV the internal 16ms
CC
turn-ondelayisnotsufficienttopreventoverheatingduring
auto-retry into a shorted load. Using an external timing
capacitor is recommended when using auto-retry mode.
a resistor between the I
pin and ground. As shown in
SET
the Functional Block Diagram the voltage at the I
pin
SET
(viatheclampcircuit)setstheCSamplifier’sbuilt-inoffset
The waveform in Figure 4 shows how the output latches
off following a short-circuit. The current in the MOSFET
is 1.4A as the timer ramps up.
voltage. This offset voltage directly determines the active
current limit value. With the I pin open, the voltage at
SET
the I
pin is determined by a positive temperature co-
SET
V
efficient reference. This voltage is set to 0.618V at room
temperature which corresponds to a 5.6A current limit at
room temperature.
OUT
10V/DIV
I
OUT
2A/DIV
An external resistor R placed between the I pin and
SET
SET
groundformsaresistivedividerwiththeinternal20kR
∆V
GATE
ISET
10V/DIV
sourcing resistor. The divider acts to lower the voltage at
TIMER
2V/DIV
theI pinandthereforelowerthecurrentlimitthreshold.
SET
42321 F04
The overall current limit threshold precision is reduced to
1ms/DIV
12% when using a 20k resistor to halve the threshold.
Figure 4. Short-Circuit Waveform
Using a switch (connected to ground) in series with R
SET
The R
, C
GATE GATE
and C
network on the GATE pin
COMP
allows the active current limit to change only when the
switch is closed. This feature can be used to program a
reduced running current while the maximum available
current limit is used at startup.
compensates the current limit regulation loop. It is pos-
sible to eliminate C and use only the R and C
COMP
GATE
GATE
network, which will require R
Figure 5). This alternate compensation with one less
to reduce to 270Ω (see
GATE
42321fb
11
For more information www.linear.com/LTC4232-1
LTC4232-1
applicaTions inForMaTion
Monitor MOSFET Temperature
tor that is charged with this current. When the capacitor
voltage trips the comparator and the capacitor is reset, a
timer is started. The time between resets will indicate the
MOSFET current.
The voltage at the I pin increases linearly with increas-
SET
ing temperature. The temperature profile of the I pin is
SET
shownintheTypicalPerformanceCharacteristicssection.
Using a comparator or ADC to measure the I
voltage
SET
Monitor OV and UV Faults
provides an indicator of the MOSFET temperature.
Protecting the load from an overvoltage condition is the
main function of the OV pin. In Figure 1 an external resis-
tive divider (driving the OV pin) connects to a comparator
The I voltage follows the formula:
SET
RSET
SET +RISET
VISET
=
• T+273°C • 2.093[mV/°C]
(
)
to turn off the MOSFET when the V voltage exceeds
DD
R
15.2V. If the V pin subsequently falls back below 14.9V,
DD
the switch will be allowed to turn on immediately. In the
LTC4232-1 the OV pin threshold is 1.235V when rising,
and 1.215V when falling out of overvoltage.
TheMOSFETtemperatureiscalculatedusingR
of20k.
ISET
R
+20k • V
ISET
(
)
SET
T =
– 273°C
RSET • 2.093[mV/°C]
The UV pin functions as an undervoltage protection pin
or as an “ON” pin. In the Figure 1 application the MOSFET
When R is not present, T becomes:
SET
turns off when V falls below 9.23V. If the V pin sub-
DD
DD
V
ISET
sequently rises above 9.88V for 100ms, the switch will
be allowed to turn on again. The LTC4232-1 UV turn-on/
off thresholds are 1.235V (rising) and 1.155V (falling).
T =
– 273°C
2.093 [mV/°C]
There is an overtemperature circuit in the LTC4232-1 that
In the cases of an undervoltage or overvoltage the MOS-
FET turns off and there is indication on the PG status pin.
When the overvoltage is removed the MOSFET’s gate
ramps up immediately.
monitorsaninternalvoltagesimilartotheI pinvoltage.
SET
When the die temperature exceeds 145°C the circuit turns
off the MOSFET until the temperature drops to 125°C.
Monitor MOSFET Current
Power Good Indication
The current in the MOSFET passes through an internal
7.5mΩ sense resistor. The voltage on the sense resistor is
converted to a current that is sourced out of the I
In addition to setting the foldback current limit threshold,
the FB pin is used to determine a power good condition.
The Figure 1 application uses an external resistive divider
on the OUT pin to drive the FB pin. The PG comparator
indicateslogichighwhenOUTpinrisesabove10.5V. Ifthe
OUT pin subsequently falls below 10.3V the comparator
toggles low. On the LTC4232-1 the PG comparator drives
high when the FB pin rises above 1.235V and low when
it falls below 1.215V.
pin.
MON
The gain of I
amplifier is 20µA/A referenced from the
SENSE
MOSFET current. This output current can be converted to
a voltage using an external resistor to drive a comparator
or ADC. The voltage compliance for the I
pin is from
MON
0V to INTV – 0.7V.
CC
A microcontroller with a built-in comparator can build a
simple integrating single-slope ADC by resetting a capaci-
42321fb
12
For more information www.linear.com/LTC4232-1
LTC4232-1
applicaTions inForMaTion
Once the PG comparator is high the GATE pin voltage is
monitored with respect to the OUT pin. Once the GATE
minus OUT voltage exceeds 4.2V the PG pin goes high.
This indicates to the system that it is safe to load the OUT
pin while the MOSFET is completely turned “on”. The PG
pin goes low when the GATE is commanded off (using
the UV, OV or SENSE pins) or when the PG comparator
drives low.
Thepeakpowerdissipationof12Vat750mA(or9W)must
not exceed the SOA of the pass MOSFET for 2.4ms (see
MOSFET SOA graph in the Typical Performance Charac-
teristics section).
Next the power dissipated in the MOSFET during overcur-
rent must be limited. The active current limit uses a timer
to prevent excessive energy dissipation in the MOSFET.
Theworst-casepowerdissipationoccurswhenthevoltage
versus current profile of the foldback current limit is at
the maximum. This occurs when the current is 6.1A and
Design Example
Consider the following design example (Figure 6): V =
the voltage is one half of the V or 6V. See the Current
IN
UVON
IN
12V, I
= 5A. I
OVOFF
= 750mA, C = 150µF, V
PGTHRESHOLD
=
LimitThresholdFoldbackgraphintheTypicalPerformance
Characteristics section to view this profile. In order to
survive 36W, the MOSFET SOA dictates a maximum time
of 10ms (see SOA graph). Therefore, it is acceptable to set
MAX
9.88V, V
INRUSH
= 15.2V, V
L
= 10.5V. A current
limit fault triggers an automatic restart of the power-up
sequence.
the current limit timeout using C to be 1.2ms:
T
The inrush current is set to 750mA using C
:
GATE
1.2ms
12[ms/µF]
IGATE(UP)
24µA
750mA
CT =
= 0.1µF
CGATE =CL
=150µF
≅ 4.7nF
IINRUSH
After the 1.2ms timeout the FLT pin needs to pull-down
on the UV pin to restart the power-up sequence.
Calculate the time it takes to charge C :
L
CL •V
150µF •12V
IN
tCHARGEUP
=
=
= 2.4ms
I
750mA
INRUSH
V
12V
5A
OUT
V
OUT
FB
12V
DD
+
R5
R3
Z1*
C
L
150k
140k
UV
150µF
FLT
R6
20k
R4
20k
R1
R7
10k
LTC4232-1
226k
OV
C
3.3nF
COMP
PG
R2
20k
GATE
R
GATE
100k
C
4.7nF
GATE
TIMER
C
T
0.1µF
I
SET
INTV
CC
I
MON
ADC
UV = 9.88V
OV = 15.2V
PG = 10.5V
C1
1µF
R
MON
GND
20k
42321 F06
*TVS Z1: DIODES INC. SMAJ17A
Figure 6. 5A, 12V Card Resident Application
42321fb
13
For more information www.linear.com/LTC4232-1
LTC4232-1
applicaTions inForMaTion
The values for overvoltage, undervoltage and power good
thresholds using the resistive dividers on the UV, OV and
FB pins match the requirements of turn-on at 9.88V and
turn-off at 15.2V.
exhibits a sheet resistance of about 0.5mΩ/square. Small
resistances add up quickly in high current applications.
There are two V pins on opposite sides of the package
DD
that connect to the sense resistor and MOSFET. The PCB
The final schematic in Figure 6 results in very few external
components. The pull-up resistor, R7, connects to the PG
layout should be balanced and symmetrical to each V
DD
pin to balance current in the MOSFET bond wires. Figure 7
shows a recommended layout for the LTC4232-1.
pin while the 20k (R
voltage at a ratio:
) converts the I
MON
current to a
MON
Although the MOSFET is self protected from overtem-
perature, it is recommended to solder the backside of the
package to a copper trace to provide a good heat sink.
Note that the backside is connected to the SENSE pin and
cannotbesolderedtothegroundplane.Duringnormalloads
the power dissipated in the MOSFET is as high as 1.9W.
A 10mm × 10mm area of 1oz copper should be sufficient.
This area of copper can be divided in many layers.
V
IMON
= 20[µA/A] • 20k • I = 0.4[V/A] • I
OUT OUT
In addition there is a 1µF bypass (C1) on the INTV pin.
CC
Layout Considerations
In Hot Swap applications where load currents can be 5A,
narrowPCBtracksexhibitmoreresistancethanwidertracks
and operate at elevated temperatures. The minimum trace
width for 1oz copper foil is 0.02" per amp to make sure
the trace stays at a reasonable temperature. Using 0.03"
per amp or wider is recommended. Note that 1oz copper
It is also important to put C1, the bypass capacitor for
the INTV pin as close as possible between the INTV
CC
CC
and GND.
HEAT SINK
V
OUT
DD
VIA TO
SINK
C
GND
42321 F07
Figure 7. Recommended Layout
42321fb
14
For more information www.linear.com/LTC4232-1
LTC4232-1
applicaTions inForMaTion
Additional Applications
In addition to Hot Swap applications, the LTC4232-1 also
functions as a backplane resident switch for removable
load cards (see Figure 8.)
The LTC4232-1 has a wide operating range from 2.9V to
15V. The UV, OV and PG thresholds are set with few resis-
tors.Allotherfunctionsareindependentofsupplyvoltage.
Thelastpageshowsa3.3VapplicationwithaUVthreshold
of 2.87V, an OV threshold of 3.77V and a PG threshold
of 3.05V.
V
12V
5A
OUT
12V
V
OUT
LTC4232DHC-1
DD
C
R7
R5
COMP
12V
Z1*
3.3nF
10k
150k
R1
FB
GATE
PG
226k
R6
20k
OV
R
GATE
R4
20k
100k
R2
20k
LOAD
C
GATE
R3
FLT
UV
4.7nF
140k
TIMER
I
SET
42321 F08
INTV
CC
I
MON
ADC
C
C1
1µF
T
R
MON
GND
0.1µF
20k
UV = 9.88V
OV = 15.2V
PG = 10.5V
*TVS Z1: DIODES INC. SMAJ17A
Figure 8. 12V, 5A Backplane Resident Application with Insertion Activated Turn-On
42321fb
15
For more information www.linear.com/LTC4232-1
LTC4232-1
package DescripTion
Please refer to http://www.linear.com/product/LTC4232-1#packaging for the most recent package drawings.
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 0.05
3.50 0.05
1.65 0.05
2.20 0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
4.40 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.40 0.10
5.00 0.10
(2 SIDES)
TYP
9
16
R = 0.20
TYP
3.00 0.10
(2 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHC16) DFN 1103
8
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
4.40 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
42321fb
16
For more information www.linear.com/LTC4232-1
LTC4232-1
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
08/15 Raised I
maximum from 340µA to 400µA
3
GATE(DN)
B
01/16 Changed TVS to SMAJ17A in application circuit.
Clarified that operating temperature range refers to ambient.
1, 9, 13, 15, 18
2
3
Added BW
and t
specifications.
IMON
D(FAULT)
Updated INTV and I pin functions.
6
CC
SET
Added equations to calculate MOSFET temperature from V
12
ISET.
42321fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
17
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC4232-1
Typical applicaTion
3.3V, 5A Card Resident Application with Auto-Retry
V
3.3V
5A
OUT
V
OUT
LTC4232DHC-1
FB
3.3V
DD
+
14.7k
10k
*
100µF
17.4k
UV
FLT
OV
10k
3.16k
10k
3.3nF
PG
GATE
100k
TIMER
I
SET
0.1µF
1µF
4.7nF
INTV
CC
I
MON
ADC
UV = 2.87V
OV = 3.77V
PG = 3.05V
GND
20k
42321 TA02
* TVS: DIODES INC. SMAJ17A
relaTeD parTs
PART NUMBER
LTC4210
DESCRIPTION
COMMENTS
Single Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Negative Voltage, Hot Swap Controller
Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6
Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10
Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10
Operates from 0V to –16V, MSOP-10
LTC4211
LTC4212
LTC4214
2
LTC4215
Hot Swap Controller with I C Compatible
Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage
Monitoring
LTC4217
LTC4218
2A Integrated Hot Swap Controller
Operates from 2.9V to 26.5V, Adjustable 5% Accurate Current Limit
Operates from 2.9V to 26.5V, Adjustable Current Limit, SSOP-16, DFN-16
Hot Swap Controller with 5% Accurate (15mV)
Current Limit
LTC4219
LT4220
5A Integrated Hot Swap Controller
12V and 5V Preset Versions, 10% Accurate Current Limit
Positive and Negative Voltage Dual Channels Hot Operates from 2.7V to 16.5V, SSOP-16
Swap Controller
LTC4221
LTC4230
LTC4227
Dual Hot Swap Controller/Sequencer
Triple Channels Hot Swap Controller
Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16
Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20
Dual Ideal Diode and Single Hot Swap Controller Operates from 2.9V to 18V, PowerPath™ and Inrush Current Control for
Redundant Supplies
LTC4228
Dual Ideal Diode and Hot Swap Controller
Operates from 2.9V to 18V, PowerPath and Inrush Current Control for Two Rails,
MicroTCA, Redundant Power Supplies, and Supply Holdup Applications
LTC4233
LTC4234
10A Guaranteed SOA Hot Swap Controller
20A Guaranteed SOA Hot Swap Controller
Operates from 2.9V to 15V, Adjustable 11% Accurate Current Limit
Operates from 2.9V to 15V, Adjustable 11% Accurate Current Limit
42321fb
LT 0116 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
18
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC4232-1
●
●
LINEAR TECHNOLOGY CORPORATION 2014
相关型号：
LTC4234CWHH#PBF
LTC4234 - 20A Guaranteed SOA Hot Swap Controller; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C
Linear
LTC4235CUFD-2#TRPBF
LTC4235 - Dual 12V Ideal Diode-OR and Single Hot Swap Controller with Current Monitor; Package: QFN; Pins: 20; Temperature Range: 0°C to 70°C
Linear
LTC4235IUFD-1#TRPBF
LTC4235 - Dual 12V Ideal Diode-OR and Single Hot Swap Controller with Current Monitor; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C
Linear
LTC4235IUFD-2#TRPBF
LTC4235 - Dual 12V Ideal Diode-OR and Single Hot Swap Controller with Current Monitor; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明