LTC4235IUFD-2#TRPBF [Linear]
LTC4235 - Dual 12V Ideal Diode-OR and Single Hot Swap Controller with Current Monitor; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C;
| 型号： | LTC4235IUFD-2#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC4235 - Dual 12V Ideal Diode-OR and Single Hot Swap Controller with Current Monitor; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C |
| 文件： | 总22页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4235
Dual 12V Ideal Diode-OR
and Single Hot Swap Controller
with Current Monitor
FeaTures
DescripTion
The LTC®4235 offers ideal diode-OR and Hot SwapTM
functions for two 12V power rails by controlling external
n
Ideal Diode-OR and Inrush Current Control for
Redundant Supplies
n
N-channel MOSFETs. MOSFETs acting as ideal diodes
replace two high power Schottky diodes and the associ-
ated heat sinks, saving power and board area. A Hot Swap
control MOSFET allows a board to be safely inserted and
removed from a live backplane by limiting inrush current.
The supply output is also protected against short-circuit
faults with a foldback current limit and circuit breaker.
Low Loss Replacement for Power Schottky Diodes
Enables Safe Board Insertion into a Live Backplane
n
n
9V to 14V Operation
n
n
n
n
n
n
n
n
n
n
n
Current Monitor Output
Controls N-Channel MOSFETs
Limits Peak Fault Current in ≤ 1µs
Adjustable Current Limit with Foldback
Adjustable Current Limit Fault Delay
0.5µs Ideal Diode Turn-On and Turn-Off Time
Smooth Switchover without Oscillation
Fault and Power Good Outputs
LTC4235-1: Latch Off After Fault
LTC4235-2: Automatic Retry After Fault
20-Pin 4mm x 5mm QFN Package
The LTC4235 regulates the forward voltage drop across
the MOSFETs to ensure smooth current transfer from one
supply to the other without oscillation. The ideal diodes
turn on quickly to reduce the load voltage droop during
supply switchover. If the input supply fails or is shorted,
a fast turn-off minimizes reverse-current transients.
A current sense amplifier translates the voltage across the
senseresistortoagroundreferencedsignal.TheLTC4235
allows turn-on/off control, and reports fault and power
good status for the supply.
applicaTions
n
Redundant Power Supplies
High Availability Systems and Servers
Telecom and Network Infrastructure
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot
Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of
their respective owners. Protected by U.S. Patents, including 7920013, 8022679.
n
n
Typical applicaTion
Ideal Diode-OR with Hot Swap Application
Smooth Supply Switchover
SiR158DP
12V
12V
IN2
0.1µF
SiR158DP
0.003Ω
SiR158DP
IN1
12V
7A
IN1
1V/DIV
+
0.1µF
0.1µF
C
IN2
1V/DIV
LOAD
I
IN1
+
–
13.7k
CPO1 IN1 DGATE1 CPO2
IN2 DGATE2
REG SENSE SENSE HGATE OUT
2A/DIV
ON
FAULT
I
IN2
2k
2A/DIV
LTC4235
PWRGD
4235 TA01b
200ms/DIV
IMON
ADC
EN
INTV
CC
GND
D2OFF
FTMR
0.1µF
0.1µF
4235 TA01a
4235f
1
For more information www.linear.com/LTC4235
LTC4235
absoluTe MaxiMuM raTings (Notes 1, 2)
Supply Voltages
CPO1, CPO2 (Note 3)............................. –0.3V to 35V
DGATE1, DGATE2 (Note 3)..................... –0.3V to 35V
HGATE (Note 4) ..................................... –0.3V to 35V
OUT ....................................................... –0.3V to 24V
Average Currents
IN1, IN2.................................................. –0.3V to 24V
INTV ..................................................... –0.3V to 7V
CC
+
+
REG ...........................SENSE – 5V to SENSE + 0.3V
Input Voltages
ON, D2OFF, EN ...................................... –0.3V to 24V
FAULT, PWRGD ....................................................5mA
FTMR.....................................–0.3V to INTV + 0.3V
INTV ...............................................................10mA
CC
CC
+
–
SENSE , SENSE ................................... –0.3V to 24V
Operating Ambient Temperature Range
Output Voltages
LTC4235C................................................ 0°C to 70°C
LTC4235I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
IMON ....................................................... –0.3V to 7V
FAULT, PWRGD ...................................... –0.3V to 24V
pin conFiguraTion
TOP VIEW
20 19 18 17
–
+
SENSE
SENSE
1
2
3
4
5
6
16 PWRGD
15 FAULT
14 ON
IN1
21
INTV
13 D2OFF
12 REG
CC
GND
IN2
11 IMON
7
8
9 10
UFD PACKAGE
20-LEAD (4mm × 5mm) PLASTIC QFN
T
= 125°C, θ = 43°C/W (NOTE 5)
JA
JMAX
EXPOSED PAD (PIN 21) PCB GND CONNECTION OPTIONAL
orDer inForMaTion
LEAD FREE FINISH
LTC4235CUFD-1#PBF
LTC4235CUFD-2#PBF
LTC4235IUFD-1#PBF
LTC4235IUFD-2#PBF
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4235CUFD-1#TRPBF 42351
LTC4235CUFD-2#TRPBF 42352
20-Lead (4mm x 5mm) Plastic QFN
20-Lead (4mm x 5mm) Plastic QFN
20-Lead (4mm x 5mm) Plastic QFN
20-Lead (4mm x 5mm) Plastic QFN
0°C to 70°C
LTC4235IUFD-1#TRPBF
LTC4235IUFD-2#TRPBF
42351
42352
–40°C to 85°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
4235f
2
For more information www.linear.com/LTC4235
LTC4235
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
V
Input Supply Range
9
14
4
V
mA
V
IN
I
Input Supply Current
Internal Regulator Voltage
2.7
5
IN
V
V
I = 0, –500µA
4.5
2.1
30
5.5
2.3
90
INTVCC
Internal V Undervoltage Lockout
INTV Rising
2.2
60
V
INTVCC(UVL)
CC
CC
∆V
Internal V Undervoltage Lockout
mV
INTVCC(HYST)
CC
Hysteresis
Ideal Diode Control
l
l
l
∆V
Forward Regulation Voltage
(V – V +)
2
15
12
28
14
mV
V
FWD(REG)
INn
SENSE
∆V
DGATE
External N-Channel Gate Drive
(V – V
∆V
= 0.15V; I = 0, –1µA
10
FWD
)
INn
DGATEn
I
I
I
I
t
t
t
CPOn Pull-Up Current
CPO = IN = 12V
–50
–90
–1.5
1.5
–120
µA
A
CPO(UP)
DGATEn Fast Pull-Up Current
DGATEn Fast Pull-Down Current
DGATE2 Off Pull-Down Current
DGATEn Turn-On Delay
∆V
∆V
= 0.2V, ∆V
= 0V, CPO = 17V
DGATE(FPU)
DGATE(FPD)
DGATE2(DN)
ON(DGATE)
OFF(DGATE)
PLH(DGATE2)
FWD
FWD
DGATE
= –0.2V, ∆V
= 5V
A
DGATE
l
l
l
l
D2OFF = 2V, ∆V
= 2.5V
= 10nF
= 10nF
50
100
0.25
0.2
200
0.5
µA
µs
µs
µs
DGATE2
∆V
∆V
= 0.2V , C
DGATE
FWD
FWD
DGATEn Turn-Off Delay
= –0.2V, C
0.5
DGATE
D2OFF Low to DGATE2 High
50
100
Hot Swap Control
∆V
l
l
Current Limit Sense Voltage Threshold
SENSE
+
OUT = 11V
OUT = 0V
22.5
5.8
25
27.5
10.8
mV
mV
SENSE(TH)
(V
+ – V
–)
SENSE
8.3
+
l
l
V
+
SENSE Undervoltage Lockout
SENSE Rising
1.8
10
1.9
50
2
V
SENSE (UVL)
+
∆V
+
SENSE Undervoltage Lockout
Hysteresis
90
mV
SENSE (HYST)
+
+
l
l
l
I
I
+
SENSE Pin Current
SENSE = 12V
0.3
10
10
0.8
40
12
1.3
100
14
mA
µA
V
SENSE
–
–
–
SENSE Pin Current
SENSE = 12V
SENSE
∆V
External N-Channel Gate Drive
HGATE
I = 0, –1µA
HGATE
(V
– V
)
OUT
l
l
l
∆V
Gate High Threshold (V
– V )
OUT
3.6
–7
1
4.2
–10
2
4.8
–13
4
V
µA
HGATE(H)
HGATE(UP)
HGATE(DN)
HGATE
I
I
External N-Channel Gate Pull-Up Current Gate Drive On, HGATE = 0V
External N-Channel Gate Pull-Down
Current
Gate Drive Off, OUT = 12V,
HGATE = OUT + 5V
mA
l
I
External N-Channel Gate Fast Pull-Down Fast Turn-Off, OUT = 12V,
100
200
350
mA
HGATE(FPD)
Current
HGATE = OUT + 5V
l
l
l
V
OUT Power Good Threshold
OUT Rising
10.2
110
10.5
170
0.5
10.8
240
1
V
mV
µs
OUT(PGTH)
∆V
OUT Power Good Hysteresis
OUT(PGHYST)
PHL(SENSE)
+
–
t
t
Sense Voltage (SENSE – SENSE )
High to HGATE Low
∆V
= 200mV, C
= 10nF
SENSE
+
HGATE
l
l
l
ON Low to HGATE Low
10
20
10
20
40
20
µs
µs
µs
OFF(HGATE)
EN High to HGATE Low
+
SENSE Low to HGATE Low
SENSE UVLO
l
t
t
ON High, EN Low to HGATE Turn-On
50
100
150
ms
D(HGATE)
Delay
l
ON to HGATE Propagation Delay
ON = Step 0.8V to 2V
10
20
µs
P(HGATE)
4235f
3
For more information www.linear.com/LTC4235
LTC4235
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.
SYMBOL
Inputs
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
V
V
D2OFF Pin High Threshold
D2OFF Pin Low Threshold
D2OFF Pin Hysteresis
D2OFF Rising
D2OFF Falling
1.21
1.19
10
1.235
1.215
20
1.26
1.24
30
V
V
D2OFF(H,TH)
D2OFF(L,TH)
∆V
mV
V
D2OFF(HYST)
ON(TH)
V
V
ON Pin Threshold Voltage
ON Pin Fault Reset Threshold Voltage
ON Pin Hysteresis
ON Rising
ON Falling
1.21
0.57
40
1.235
0.6
1.26
0.63
120
1
V
ON(RESET)
∆V
80
mV
µA
V
ON(HYST)
I
Input Leakage Current (ON, D2OFF)
EN Pin Threshold Voltage
EN Pin Hysteresis
V = 5V
0
IN(LEAK)
V
EN Rising
1.185
60
1.235
110
–10
1.235
0.2
1.284
200
–13
1.272
0.25
–120
2.7
EN(TH)
∆V
mV
µA
V
EN(HYST)
I
EN Pull-Up Current
EN = 1V
–7
EN(UP)
V
V
FTMR Pin High Threshold
FTMR Pin Low Threshold
FTMR Pull-Up Current
1.198
0.15
–80
1.3
FTMR(H)
V
FTMR(L)
I
I
FTMR = 1V, In Fault Mode
FTMR = 2V, No Faults
–100
2
µA
µA
%
FTMR(UP)
FTMR(DN)
FTMR Pull-Down Current
Auto-Retry Duty Cycle
D
0.07
0.15
20
0.23
40
RETRY
t
ON Low to FAULT High
µs
RST(ON)
Outputs
l
l
I
OUT Pin Current
OUT = 11V, IN = 12V, ON = 2V
OUT = 13V, IN = 12V, ON = 2V
30
100
2.5
170
4
µA
mA
OUT
l
l
V
V
Output Low Voltage (FAULT, PWRGD)
Output High Voltage (FAULT, PWRGD)
I = 1mA
I = 3mA
0.15
0.4
0.4
1.2
V
V
OL
OH
l
I = –1µA
INTV
INTV
V
CC
CC
– 1
– 0.5
l
l
I
I
Input Leakage Current (FAULT, PWRGD) V = 18V
Output Pull-Up Current (FAULT, PWRGD) V = 1.5V
0
1
µA
µA
OH
PU
–7
–10
–13
Current Monitor
l
l
∆V
Floating Regulator Voltage
(V + – V
I
= 1µA
REG
3.6
25
4.1
4.6
V
REG
)
REG
SENSE
+
∆V
SENSE(FS)
Input Sense Voltage Full Scale
(V + – V –)
SENSE = 12V
mV
SENSE
SENSE
l
l
l
l
l
V
IMON Input Offset Voltage
IMON Voltage Gain
∆V
∆V
∆V
∆V
∆V
= 0V
150
101
5.5
40
µV
V/V
V
IMON(OS)
SENSE
SENSE
SENSE
SENSE
SENSE
G
= 20mV and 5mV
= 70mV
99
100
20
IMON
V
V
IMON Maximum Output Voltage
IMON Minimum Output Voltage
IMON Output Resistance
3.5
IMON(MAX)
IMON(MIN)
= 200µV
mV
kΩ
R
= 200µV
15
27
IMON(OUT)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of
the device pins are negative. All voltages are referenced to GND unless
otherwise specified.
Note 3: An internal clamp limits the DGATE and CPO pins to a minimum of
10V above and a diode below IN. Driving these pins to voltages beyond the
clamp may damage the device.
Note 4: An internal clamp limits the HGATE pin to a minimum of 10V
above and a diode below OUT. Driving this pin to voltages beyond the
clamp may damage the device.
Note 5: Thermal resistance is specified when the exposed pad is soldered
to a 3" x 5", four layer, FR4 board.
4235f
4
For more information www.linear.com/LTC4235
LTC4235
TA = 25°C, VIN = 12V, unless otherwise noted.
Typical perForMance characTerisTics
IN Supply Current vs Voltage
SENSE+ Current vs Voltage
OUT Current vs Voltage
3.5
3
1.4
1.2
1
3.5
3
V + = V – 0.5V
SENSE IN
V
= 12V, V
+ = 11.5V
SENSE
IN
2.5
2
2.5
2
0.8
0.6
0.4
0.2
0
V
OUT
= 0V
V
OUT
= 12V
1.5
1
1.5
1
0.5
0
0.5
0
–0.5
0
3
6
9
12
15
18
0
3
6
9
12
15
18
0
3
6
9
12
15
18
V
(V)
V
+ (V)
SENSE
V
(V)
OUT
IN
4235 G01
4235 G02
4235 G03
Hot Swap Gate Voltage vs IN
Voltage
Hot Swap Gate Voltage vs Current
CPO Voltage vs Current
14
12
10
8
14
12
10
8
12
10
8
V
OUT
= V
V = V
OUT IN
IN
V
IN
= 12V
6
6
4
4
2
6
2
0
0
4
–2
0
–2
–4
–6
–8
–10
–12
0
3
6
9
12
15
18
0
–20 –40 –60 –80 –100 –120 –140
(µA)
I
(µA)
V
(V)
I
CPO
HGATE
IN
4235 G04
4235 G05
4235 G06
FAULT, PWRGD
Output Low Voltage vs Current
Diode Gate Voltage vs Current
Diode Gate Voltage vs IN Voltage
12
10
8
14
12
10
8
0.6
0.5
0.4
0.3
0.2
0.1
0
V
+ = V – 0.15V
V + = V – 0.15V
SENSE IN
SENSE
IN
V
IN
= 12V
6
4
2
6
0
–2
4
0
–20 –40 –60 –80 –100 –120 –140
(µA)
0
3
6
9
12
15
18
0
1
2
3
4
5
I
V
(V)
IN
CURRENT (mA)
DGATE
4235 G07
4235 G08
4235 G09
4235f
5
For more information www.linear.com/LTC4235
LTC4235
TA = 25°C, VIN = 12V, unless otherwise noted.
Typical perForMance characTerisTics
Current Limit Delay vs Sense
Current Sense Amplifier Input
Offset Voltage vs Temperature
40
Current Limit Threshold Foldback
Voltage
30
25
20
15
10
5
100
10
1
C
= 10nF
HGATE
35
30
25
20
15
10
5
0
0.1
0
0
2
4
6
8
10
12
0
40
80
120
+ – V
160
–) (mV)
SENSE
200
–50
–25
0
25
50
75
100
V
(V)
SENSE VOLTAGE (V
TEMPERATURE (°C)
OUT
SENSE
4235 G10
4235 G11
4235 G12
IMON Voltage Gain vs
Temperature
IMON Propagation Delay vs
Sense Voltage
IMON Voltage vs Sense Voltage
5
4
3
2
1
0
101
100.5
100
120
100
80
60
40
20
0
99.5
99
0
10
20
30
40
–) (mV)
50
–50
–25
0
25
50
75
100
0
1
2
3
4
5
SENSE VOLTAGE (V
+ – V
TEMPERATURE (°C)
SENSE VOLTAGE (V
+ – V
SENSE
–) (mV)
SENSE
4235 G15
SENSE
SENSE
4235 G13
4235 G14
Ideal Diode Start-Up Waveform
on IN Power-Up
HGATE Start-Up Waveform on ON
Toggling High
IN
10V/DIV
ON
5V/DIV
+
HGATE
10V/DIV
OUT
SENSE
10V/DIV
CPO
10V/DIV
DGATE
10V/DIV
PWRGD
10V/DIV
4235 G16
4235 G17
10ms/DIV
20ms/DIV
4235f
6
For more information www.linear.com/LTC4235
LTC4235
pin FuncTions
CPO1, CPO2: Charge Pump Output. Connect a capacitor
from CPO1 or CPO2 to the corresponding IN1 or IN2 pin.
The value of this capacitor is approximately 10x the gate
HGATE: Hot Swap MOSFET Gate Drive Output. Connect
this pin to the gate of the external N-channel MOSFET for
HotSwapcontrol.Aninternal10µAcurrentsourcecharges
the MOSFET gate. An internal clamp limits the gate volt-
age to 12V above and a diode voltage below OUT. During
an undervoltage generated turn-off, a 2mA pull-down
discharges HGATE to ground. During an output short or
capacitance (C ) of the external MOSFET for ideal diode
ISS
control. The charge stored on this capacitor is used to pull
up the ideal diode MOSFET gate during a fast turn-on.
Leavethispinopeniffastidealdiodeturn-onisnotneeded.
INTV undervoltage lockout, a fast 200mA pull-down
CC
DGATE1, DGATE2: Ideal Diode MOSFET Gate Drive Out-
put. Connect this pin to the gate of an external N-channel
MOSFET for ideal diode control. An internal clamp limits
the gate voltage to 12V above and a diode voltage below
IN.Duringfastturn-on,a1.5Apull-upchargesDGATEfrom
CPO. During fast turn-off, a 1.5A pull-down discharges
DGATE to IN.
discharges HGATE to OUT.
IN1, IN2: Positive Supply Input and Ideal Diode MOSFET
Gate Drive Return. Connect this pin to the power input
side of the external ideal diode MOSFET. The 5V INTV
CC
supply is generated from IN1, IN2 and OUT via an internal
diode-OR. The voltage sensed at this pin is used to control
DGATE. The gate fast pull-down current returns through
this pin when DGATE is discharged.
D2OFF: Control Input. A rising edge above 1.235V turns
off the external ideal diode MOSFET in the IN2 supply path
and a falling edge below 1.215V allows the MOSFET to be
turned on. Connect this pin to an external resistive divider
fromIN1tomakeIN1thehigherpriorityinputsupplywhen
IN1 and IN2 are equal.
INTV : Internal 5V Supply Decoupling Output. This pin
CC
must have a 0.1µF or larger capacitor to GND. An external
load of less than 500µA can be connected at this pin. An
undervoltage lockout threshold of 2.2V will turn off both
MOSFETs.
EN: Enable Input. Ground this pin to enable Hot Swap
control. If this pin is pulled high, the Hot Swap MOSFET
is not allowed to turn on. A 10µA current source pulls
IMON: Current Sense Monitoring Output. This pin voltage
is proportional to the sense voltage across the current
sense resistor with a voltage gain of 100. An internal 20k
resistor is connected from this pin to ground.
this pin up to a diode below INTV . Upon EN going low
CC
when ON is high, there is a start-up delay of 100ms for
debounce, after which the fault is cleared.
ON: ON Control Input. A rising edge above 1.235V turns
ontheexternalHotSwapMOSFETandafallingedgebelow
1.155Vturnsitoff. Connectthispintoanexternalresistive
FAULT: Overcurrent Fault Status Output. Output that pulls
low when the fault timer expires during an overcurrent
fault. Otherwise it is pulled high by a 10µA current source
+
divider from SENSE to monitor the supply undervoltage
to a diode below INTV . It may be pulled above INTV
condition. Pulling the ON pin below 0.6V resets the fault
CC
CC
using an external pull-up. Leave open if unused.
latch after an overcurrent fault. Tie to INTV if unused.
CC
FTMR:FaultTimerCapacitorTerminal.Connectacapacitor
between this pin and ground to set a 12ms/µF duration
for current limit before the external Hot Swap MOSFET is
turned off. The duration of the off time is 8s/µF, resulting
in a 0.15% duty cycle.
OUT: Hot Swap MOSFET Gate Drive Return. Connect this
pintotheoutputsideoftheexternalMOSFET.Thegatefast
pull-down current returns through this pin when HGATE
is discharged. An internal resistive divider connected be-
tween this pin and GND is used for current limit foldback
and power good monitor for 12V operation. If the OUT
voltage falls below 10.33V, the PWRGD pin pulls high to
indicate the power is bad. If the voltage falls below 7.65V,
the output current limit is reduced.
GND: Device Ground.
4235f
7
For more information www.linear.com/LTC4235
LTC4235
pin FuncTions
+
PWRGD:PowerStatusOutput. Outputthatpullslowwhen
the OUT pin rises above 10.5V and the MOSFET gate drive
between HGATE and OUT exceeds 4.2V. Otherwise it is
pulled high by a 10µA current source to a diode below
SENSE : Positive Current Sense Input. Connect this pin to
the diode-OR output of the external ideal diode MOSFETs
andinputofthecurrentsenseresistor. Thevoltagesensed
at this pin is used for monitoring the current limit and
also to control DGATE for forward voltage regulation and
reverse turn-off. This pin has an undervoltage lockout
threshold of 1.9V that will turn off the Hot Swap MOSFET.
INTV . It may be pulled above INTV using an external
CC
CC
pull-up. Leave open if unused.
REG: Internal Regulated Supply for Current Sense Ampli-
–
fier. A 0.1µF or larger capacitor should be tied from REG to
SENSE : Negative Current Sense Input. Connect this pin
+
SENSE . This pin is not designed to drive external circuits.
to the output of the current sense resistor. The current
limit circuit controls HGATE to limit the voltage between
+
–
SENSE and SENSE to 25mV or less depending on the
voltage at the OUT pin.
4235f
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For more information www.linear.com/LTC4235
LTC4235
block DiagraM
+
–
OUT
150k
IN1 SENSE
SENSE
IN2
REG
4.1V
FOLDBACK
20k 0.9V
HGATE
200Ω
+
CL
–
+
CM
–
GATE
DRIVER
12V
IMON
20k
OUT
10µA
100µA
CHARGE
PUMP 1
f = 2MHz
CHARGE
PUMP 2
f = 2MHz
CPO2
CPO1
100µA
+
GD1
–
+
–
DGATE1
DGATE2
GD2
12V
12V
15mV
15mV
INTV
CC
5V LDO
UVLO1
UVLO2
PG1
DOFF
+
–
D2OFF
+
–
DGATE2 OFF
2.2V
1.235V
1.235V
ON
+
–
+
SENSE
1.9V
–
+
HGATE ON
ON
4.2V
+
–
RST
HGATE
–
+
FAULT RESET
INTV
INTV
CC
0.6V
10µA
OUT
PG2
+
–
EN
EN
LOGIC
10.5V
INTV
+
–
INTV
CC
CC
1.235V
100µA
CC
10µA
10µA
TM1
TM2
1.235V
–
+
PWRGD
FAULT
FTMR
GND
–
+
0.2V
2µA
EXPOSED PAD
4235 BD
4235f
9
For more information www.linear.com/LTC4235
LTC4235
operaTion
The LTC4235 functions as an input supply diode-OR with
The high side current sense amplifier (CM) provides ac-
curate monitoring of current through the current sense
resistor. The sense voltage is amplified by 100 times and
level shifted from the positive rail to a ground-referred
output at the IMON pin. The output signal is analog and
may be used as is or measured with an ADC.
inrush current limiting and overcurrent protection by
controlling the external N-channel MOSFETs (M , M
D1
D2
and M ) on a supply path. This allows boards to be safely
H
insertedandremovedinsystemswithabackplanepowered
byredundantsupplies.TheLTC4235hasasingleHotSwap
controller and two separate ideal diode controllers, each
providing independent control for the two input supplies.
When the ideal diode MOSFET is turned on, the gate drive
amplifier controls DGATE to servo the forward voltage
When the LTC4235 is first powered up, the gates of the
external MOSFETs are held low, keeping them off. As the
DGATE2pull-upcanbedisabledbytheD2OFFpin,DGATE2
will pull high only when the D2OFF pin is pulled low. The
gate drive amplifier (GD1, GD2) monitors the voltage be-
drop (V – V
+) across the MOSFET to 15mV. If the
SENSE
IN
load current causes more than 15mV of voltage drop,
the gate voltage rises to enhance the MOSFET. For large
output currents, the MOSFET’s gate is driven fully on and
the voltage drop is equal to I
•R
of the MOSFET.
LOAD DS(ON)
+
tween the IN and SENSE pins and drives the respective
In the case of an input supply short-circuit when the
MOSFETs are conducting, a large reverse current starts
flowing from the load towards the input. The gate drive
amplifier detects this failure condition and turns off the
ideal diode MOSFET by pulling down the DGATE pin.
DGATE pin. The amplifier quickly pulls up the DGATE pin,
turning on the MOSFET for ideal diode control, when it
senses a large forward voltage drop. With the ideal diode
+
MOSFETs acting as input supply diode-OR, the SENSE
pin voltage rises to the highest of the supplies at the IN1
and IN2 pins. An external capacitor connected at the CPO
pin provides the charge needed to quickly turn on the ideal
diode MOSFET. An internal charge pump charges up this
capacitor at device power-up. The DGATE pin sources
current from the CPO pin and sinks current into the IN
and GND pins.
In the case where an overcurrent fault occurs on the sup-
ply output, the current is limited with foldback. After a
delay set by 100µA charging the FTMR pin capacitor, the
fault timer expires and pulls the HGATE pin low, turning
off the Hot Swap MOSFET. The FAULT pin is also latched
low. At this point, the DGATE pin continues to pull high
and keeps the ideal diode MOSFET on.
Pulling the ON pin high and EN pin low initiates a 100ms
debounce timing cycle. After this timing cycle, a 10µA cur-
rent source from the charge pump ramps up the HGATE
pin. When the Hot Swap MOSFET turns on, the inrush
currentislimitedatalevelsetbyanexternalsenseresistor
Internal clamps limit both the DGATE to IN and CPO to IN
voltages to 12V. The same clamp also limits the DGATE
and CPO pins to a diode voltage below the IN pin. Another
internal clamp limits the HGATE to OUT voltage to 12V
and also clamps the HGATE pin to a diode voltage below
the OUT pin.
+
–
(R ) connected between the SENSE and SENSE pins.
S
An active current limit amplifier (CL) servos the gate of
the MOSFET to 25mV or less across the current sense
resistor depending on the voltage at the OUT pin. Inrush
current can be further reduced, if desired, by adding a
capacitor from HGATE to GND. When OUT voltage rises
above 10.5V and the MOSFET’s gate drive (HGATE to OUT
voltage) exceeds 4.2V, the PWRGD pin pulls low.
Power to the LTC4235 is supplied from either the IN or
OUT pins, through an internal diode-OR circuit to a low
dropout regulator (LDO). That LDO generates a 5V supply
at the INTV pin and powers the LTC4235’s internal low
CC
voltage circuitry.
4235f
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For more information www.linear.com/LTC4235
LTC4235
applicaTions inForMaTion
High availability systems often employ parallel-connected
powersuppliesorbatteryfeedstoachieveredundancyand
enhance system reliability. Power ORing diodes are com-
monlyusedtoconnectthesesuppliesatthepointofloadat
theexpenseofpowerlossduetosignificantdiodeforward
voltage drop. The LTC4235 minimizes this power loss by
using external N-channel MOSFETs as the pass elements,
allowing for a low voltage drop from the supply to the load
when the MOSFETs are turned on. When an input source
voltage drops below the output common supply voltage,
the appropriate MOSFET is turned off, thereby matching
the function and performance of an ideal diode. By adding
a current sense resistor and a Hot Swap MOSFET after
theparallel-connectedidealdiodeMOSFETs, theLTC4235
enhances the ideal diode performance with inrush current
limiting and overcurrent protection (see Figure 1). This
allows the board to be safely inserted and removed from
a live backplane without damaging the connector.
highest of the supplies at the IN and OUT pins to power the
devicethroughtheLDO.Thediode-ORschemepermitsthe
device’s power to be kept alive by the OUT voltage when
the IN supplies have collapsed or shut off.
AnundervoltagelockoutcircuitpreventsalloftheMOSFETs
from turning on until the INTV voltage exceeds 2.2V. A
CC
0.1µF capacitor is recommended between the INTV and
CC
GND pins, close to the device for bypassing. No external
supply should be connected at the INTV pin so as not
CC
to affect the LDO’s operation. A small external load of less
than 500µA can be connected at the INTV pin.
CC
Turn-On Sequence
The board power supply at the OUT pin is controlled
with external N-channel MOSFETs (M , M and M ) in
D1
D2
H
Figure 1. The ideal diode MOSFETs connected in parallel
on the supply side function as a diode-OR, while M on
H
the load side acts as a Hot Swap MOSFET controlling the
power supplied to the output load. The sense resistor R
Internal V Supply
S
CC
monitors the load current for overcurrent detection. The
The LTC4235 operates with an input supply from 9V to
14V. The power supply to the device is internally regulated
at 5V by a low dropout regulator (LDO) with an output at
HGATE capacitor C controls the gate slew rate to limit
HG
the inrush current. Resistor R with C compensates
HG
HG
thecurrentcontrolloop, whileR preventshighfrequency
H
the INTV pin. An internal diode-OR circuit selects the
CC
oscillations in the Hot Swap MOSFET.
Figure 1. Card Resident Diode-OR with Hot Swap Application
M
D1
SiR158DP
V
IN1
12V
Z1
SMAJ15A
C2
0.1µF
M
R
M
H
SiR158DP
D2
S
SiR158DP
0.003Ω
V
12V
7A
IN2
12V
+
Z2
SMAJ15A
C
L
680µF
R
H
10Ω
C3
0.1µF
R
HG
C4
0.1µF
1k
C
HG
10nF
R3
R4
R2
+
–
100k 100k
CPO1
ON
IN1 DGATE1 CPO2
IN2 DGATE2 REG SENSE SENSE HGATE
OUT
13.7k
FAULT
PWRGD
C5
0.1µF
R1
2k
LTC4235
IMON
ADC
EN
INTV
CC
FTMR
D2OFF
GND
4235 F01
C
FT
C1
0.1µF
BACKPLANE CARD
CONNECTOR CONNECTOR
0.1µF
4235f
11
For more information www.linear.com/LTC4235
LTC4235
applicaTions inForMaTion
During a normal power-up, the ideal diode MOSFETs turn
onfirst.Assoonastheinternallygeneratedsupply,INTV ,
Turn-Off Sequence
CC
The external MOSFETs can be turned off by a variety of
conditions. A normal turn-off for the Hot Swap MOSFET is
initiated by pulling the ON pin below its 1.155V threshold
(80mV ON pin hysteresis), or pulling the EN pin above its
1.235V threshold. Additionally, an overcurrent fault that
exceeds the fault timer period also turns off the Hot Swap
MOSFET. Normally, the LTC4235 turns off the MOSFET by
pulling the HGATE pin to ground with a 2mA current sink.
rises above its 2.2V undervoltage lockout threshold, the
internal charge pump is allowed to charge up the CPO
pins. Because the ideal diode MOSFETs are connected in
+
parallelasadiode-OR,theSENSE pinvoltageapproaches
the highest of the supplies at the IN1 and IN2 pins. The
MOSFET associated with the lower input supply voltage
willbeturnedoffbythecorrespondinggatedriveamplifier.
Before the Hot Swap MOSFET can be turned on, EN must
remainlowandONmustremainhighfora100msdebounce
timingcycletoensurethatanycontactbouncesduringthe
insertion have ceased. At the end of the debounce cycle,
the internal fault latch is cleared. The Hot Swap MOSFET
is then allowed to turn on by charging up HGATE with a
10µA current source from the charge pump. The voltage
All of the MOSFETs turn off when INTV falls below its
CC
undervoltage lockout threshold (2.2V). The DGATE pin is
pulled down with a 100µA current to one diode voltage
below the IN pin, while the HGATE pin is pulled down to
the OUT pin by a 200mA current. When D2OFF is pulled
high above 1.235V, the ideal diode MOSFET in the IN2
power path is turned off with DGATE2 pulled low by a
100µA current.
at the HGATE pin rises with a slope equal to 10µA/C and
HG
the supply inrush current flowing into the load capacitor
The gate drive amplifier controls the ideal diode MOSFET
to prevent reverse current when the input supply falls
C is limited to:
L
CL
CHG
+
below SENSE . If the input supply collapses quickly, the
IINRUSH
=
•10µA
gate drive amplifier turns off the ideal diode MOSFET with
a fast pull-down circuit. If the input supply falls at a more
modest rate, the gate drive amplifier controls the MOSFET
The OUT voltage follows the HGATE voltage when the Hot
Swap MOSFET turns on. If the voltage across the current
+
to maintain SENSE at 15mV below IN.
sense resistor R becomes too high based on the OUT pin
S
voltage, the inrush current will be limited by the internal
currentlimitingcircuitry.OncetheMOSFETgateoverdrive
exceeds 4.2V and the OUT pin voltage is above 10.5V,
the PWRGD pin pulls low to indicate that the power is
good. Once OUT reaches the input supply voltage, HGATE
continues to ramp up. An internal 12V clamp limits the
HGATE voltage above OUT.
Board Presence Detect with EN
If ON is high when the EN pin goes low, indicating a board
presence, the LTC4235 initiates a debounce timing cycle
for contact debounce. Upon board insertion, any bounces
on the EN pin restart the timing cycle. When the debounce
timing cycle is done, the internal fault latch is cleared. If
the EN pin remains low at the end of the timing cycle,
HGATE is charged up with a 10µA current source to turn
on the Hot Swap MOSFET.
When the ideal diode MOSFET is turned on, the gate
drive amplifier controls the gate of the MOSFET to servo
the forward voltage drop across the MOSFET to 15mV.
If the load current causes more than 15mV of drop, the
MOSFET gate is driven fully on and the voltage drop is
If the EN pin goes high, indicating a board removal, the
HGATE pin is pulled low with a 2mA current sink after a
20µs delay, turning off the Hot Swap MOSFET without
clearing any latched fault.
equal to I
•R
.
LOAD DS(ON)
4235f
12
For more information www.linear.com/LTC4235
LTC4235
applicaTions inForMaTion
Overcurrent Fault
OUT
The LTC4235 features an adjustable current limit with
foldback that protects the external MOSFET against short
circuits or excessive load current. The voltage across the
10V/DIV
HGATE
10V/DIV
external sense resistor R is monitored by an active cur-
S
rent limit amplifier. The amplifier controls the gate of the
Hot Swap MOSFET to reduce the load current as a func-
tion of the output voltage sensed by the OUT pin during
active current limit. A graph in the Typical Performance
Characteristics shows the current limit sense voltage
versus OUT voltage.
I
LOAD
20A/DIV
4235 F03
5µs/DIV
Figure 3. Severe Short-Circuit on 12V Output
An overcurrent fault occurs when the output has been in
currentlimitforlongerthanthefaulttimerperiodconfigured
at the FTMR pin. Current limiting begins when the sense
Intheeventofasevereshort-circuitfaultonthe12Voutput
as shown in Figure 3, the output current can surge to tens
ofamperes.TheLTC4235respondswithin1µstobringthe
currentundercontrolbypullingtheHGATEtoOUTvoltage
downtozerovolts.Almostimmediately,thegateoftheHot
Swap MOSFET recovers rapidly due to the charge stored
+
–
voltage between the SENSE and SENSE pins reaches
8.3mV to 25mV depending on the OUT pin voltage. The
gate of the Hot Swap MOSFET is brought under control by
the current limit amplifier and the output current is regu-
lated to limit the sense voltage to less than 25mV. At this
point, the fault timer starts with a 100µA current charging
the FTMR pin capacitor. If the FTMR pin voltage exceeds
its 1.235V threshold, the external MOSFET turns off with
HGATE pulled to ground by 2mA and FAULT pulls low.
in the R and C network and current is actively limited
HG
HG
until the fault timer expires. Due to parasitic supply lead
inductance, an input supply without any bypass capaci-
tor may collapse during the high current surge and then
spike upwards when the current is interrupted. Figure 10
shows the input supply transient suppressors comprising
After the Hot Swap MOSFET turns off, the FTMR pin ca-
pacitor is discharged with a 2µA pull-down current until
its threshold reaches 0.2V. This is followed by a cool-off
period of 14 timing cycles as described in the FTMR Pin
Functions. Figure 2 shows an overcurrent fault on the
12V output.
of Z1, R
, C
and Z2, R
, C
for the two
SNUB1 SNUB1
SNUB2 SNUB2
supplies if there is no input capacitance.
FTMR Pin Functions
An external capacitor C connected from the FTMR pin
FT
to GND serves as fault timing when the supply output is
in active current limit. When the voltage across the sense
resistorexceedsthefoldbackcurrentlimitthreshold(from
25mV to 8.3mV), FTMR pulls up with 100µA. Otherwise,
it pulls down with 2µA. The fault timer expires when the
1.235V FTMR threshold is exceeded, causing the FAULT
pin to pull low. For a given fault timer period, the equation
OUT
10V/DIV
HGATE
10V/DIV
for setting the external capacitor C value is:
I
FT
LOAD
20A/DIV
C = t • 0.083 [µF/ms]
FT
FT
4235 F02
After the fault timer expires, the FTMR pin capacitor pulls
down with 2µA from the 1.235V FTMR threshold until it
reaches0.2V.Then,itcompletes14coolingcyclesconsist-
ing of the FTMR pin capacitor charging to 1.235V with a
200µs/DIV
Figure 2. Overcurrent Fault on 12V Output
4235f
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LTC4235
applicaTions inForMaTion
100µAcurrentanddischargingto0.2Vwitha2µAcurrent.
At that point, the HGATE pin voltage is allowed to start up
if the fault has been cleared as described in the Resetting
Fault section. When the latched fault is cleared during the
cool-offperiod, theFAULTpinpullshigh. Thetotalcool-off
time for the MOSFET after an overcurrent fault is:
new cool-off cycle begins with FTMR ramping down with
a 2µA current. The whole process repeats itself until the
output short is removed. Since t and t
are a function
FT
COOL
of FTMR capacitance C , the auto-retry cycle is equal to
FT
0.15%, irrespective of C .
FT
Figure 4 shows an auto-retry sequence after an over-
current fault.
t
= C • 8 [s/µF]
FT
COOL
FTMR
After the cool-off period, the HGATE pin is only allowed
to pull up if the fault has been cleared for the latchoff
part. For the auto-retry part, the latched fault is cleared
automatically following the cool-off period and the HGATE
pin voltage is allowed to restart.
2V/DIV
FAULT
10V/DIV
HGATE
20V/DIV
Resetting Fault (LTC4235-1)
OUT
10V/DIV
For the latchoff part, an overcurrent fault is latched after
the fault timer expires and the FAULT pin is asserted low.
Only the Hot Swap MOSFET is turned off and the ideal
diode MOSFETs are not affected.
4235 F04
100ms/DIV
Figure 4. Auto-Retry Sequence After a Fault
To reset a latched fault and restart the output, pull the
ON pin below 0.6V for more than 100µs and then high
above 1.235V. The fault latch resets and the FAULT pin
de-asserts on the falling edge of the ON pin. When ON
goes high again and the cool-off cycle has completed, a
debounce timing cycle is initiated before the HGATE pin
voltage restarts. Toggling the EN pin high and then low
again also resets a fault, but the FAULT pin pulls high at
the end of the debounce cycle before the HGATE pin volt-
Monitor Undervoltage Fault
The ON pin functions as a turn-on control and an input
supply monitor. A resistive divider connected between
+
the supply diode-OR output (SENSE ) and GND at the
ON pin monitors the supply for undervoltage condition.
The undervoltage threshold is set by proper selection of
the resistors at the ON rising threshold voltage (1.235V).
age starts up. Bringing all the supplies below the INTV
CC
For Figure 1, if R1 = 2k, R2 = 13.7k, the input supply
undervoltage threshold is set to 9.7V.
undervoltage lockout threshold (2.2V) shuts off all the
MOSFETs and resets the fault latch. A debounce cycle is
initiated before a normal start-up when any of the supplies
An undervoltage fault occurs if the diode-OR output sup-
ply falls below its undervoltage threshold. If the ON pin
voltage falls below 1.155V but remains above 0.6V, the
Hot Swap MOSFET is turned off by a 2mA pull-down from
HGATE to ground. The Hot Swap MOSFET turns back on
instantly without the debounce cycle when the diode-OR
output supply rises above its undervoltage threshold.
However, if the ON pin voltage drops below 0.6V, it turns
off the Hot Swap MOSFET and clears the fault latch. The
Hot Swap MOSFET turns back on only after a debounce
cycle when the diode-OR output supply is restored above
its undervoltage threshold.
is restored above the INTV UVLO threshold.
CC
Auto-Retry after a Fault (LTC4235-2)
For the auto-retry part, the latched fault is reset automati-
cally at the end of the cool-off period as described in the
FTMR Pin Functions section. At the end of the cool-off
period, the fault latch is cleared and FAULT pulls high.
The HGATE pin voltage is allowed to start up and turn on
the Hot Swap MOSFET. If the output short persists, the
supply powers up into a short with active current limiting
until the fault timer expires and FAULT again pulls low. A
4235f
14
For more information www.linear.com/LTC4235
LTC4235
applicaTions inForMaTion
During the undervoltage fault condition, FAULT will not
be pulled low but PWRGD will be pulled high as HGATE
is pulled low. The ideal diode function controlled by the
ideal diode MOSFET is not affected by the undervoltage
(UV) fault condition.
frequency of the auto-zero clock is 10kHz. An internal
resistor R is connected between the amplifier’s negative
IN
+
input terminal and SENSE pin. The sense amplifier loop
forcesthenegativeinputterminaltohavethesamepotential
–
as SENSE and that develops a potential across R to be
IN
the same as the sense voltage V
. A corresponding
SENSE
Power Good Monitor
current, V
/R , will flow through R . The high
SENSE IN
IN
impedance inputs of the sense amplifier will not conduct
Internal circuitry monitors the MOSFET gate overdrive
between the HGATE and OUT pins. Also, an internal resis-
tive divider that connects to OUT is used to determine a
powergoodcondition.Thepowergoodcomparatordrives
high when the OUT pin rises above 10.5V, and drives low
when OUT falls below 10.33V. The power good status
for the input supply is reported via an open-drain output,
PWRGD. It is normally pulled high by an external pull-up
resistor or the internal 10µA pull-up.
this input current, allowing it to flow through an internal
MOSFET to a resistor R
connected between the IMON
OUT
and GND pins. The IMON output voltage is equal to (R
/
OUT
R )•V
IN
.TheresistorratioR /R definesthevoltage
SENSE
OUT IN
gain of the sense amplifier and is set to 100 with R
200Ω and R
=
IN
= 20k. Full scale input sense voltage to
OUT
the sense amplifier is 25mV, corresponding to an output
of 2.5V. The output clamps at 3.5V if the allowable input
sense voltage range is exceeded.
The PWRGD pin pulls low when the OUT power good
comparatorishighandtheHGATEdriveexceeds4.2V.The
PWRGDpingoeshighwhentheHGATEisturnedoffbythe
ON or EN pins, or when the OUT power good comparator
IMON Output Filtering
A capacitor connected in parallel with R
will give a
OUT
low pass response. This will reduce unwanted noise at
the output, and may also be useful as a charge reservoir
to keep the output steady while driving a switching circuit
such as an ADC (see Figure 5). This output capacitor
drives low, or when INTV enters undervoltage lockout.
CC
Current Sense Monitor
Thecurrentthroughtheexternalsenseresistorismonitored
C
in parallel with R
will create a pole in the output
OUT
response at:
OUT
+
by a LTC4235’s current sense amplifier at the SENSE
–
and SENSE pins (see Figure 5). The amplifier uses auto-
1
zeroing circuitry to achieve an offset below 150µV over
temperature, sense voltage and input supply voltage. The
fC =
2•π•ROUT •COUT
12V
0.1µF
LTC4235
REG
+
SENSE
R
IN
V
SENSE
200Ω
–
SENSE
HGATE
0.1µF
10µF
5V
+
REF
V
CC
SCL
SDA
2
IMON
V
OUT
2-WIRE I C
INTERFACE
I
LOAD
OUT
LOAD
IN
LTC2451
–
R
OUT
20k
REF
GND
GND
0.1µF
R
4235 F05
V
= ––––– • V
= 100 • V
SENSE SENSE
OUT
R
IN
Figure 5. High Side Current Monitor with LTC2451 ADC
4235f
15
For more information www.linear.com/LTC4235
LTC4235
applicaTions inForMaTion
REG Pin Bypassing
MOSFET Selection
The LTC4235 has an internally regulated supply near
The LTC4235 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
+
SENSE for internal bias of the current sense amplifier. It
is not intended for use as a supply or bias pin for external
circuitry. A 0.1µF capacitor should be connected between
on-resistanceR
,themaximumdrain-sourcevoltage
DS(ON)
BV
and the threshold voltage.
DSS
+
theREGandSENSE pins.Thiscapacitorshouldbelocated
The gate drive for the ideal diode and Hot Swap MOSFET
is guaranteed to be greater than 10V and is limited to 14V.
An external Zener diode can be used to clamp the potential
from the MOSFET’s gate to source if the rated breakdown
voltage is less than 14V.
very near to the device and close to the REG pin for the
best performance.
REG and IMON Start-Up
The start-up current of the current sense amplifier when
the LTC4235 is powered on consists of two parts: the
first is the current necessary to charge the REG bypass
capacitor,whichisnominally0.1µF.SincetheREGvoltage
The maximum allowable drain-source voltage BV
DSS
must be higher than the supply voltage including supply
transients as the full supply voltage can appear across the
MOSFET. If an input or output is connected to ground, the
full supply voltage will appear across the MOSFET. The
+
charges to approximately 4.1V below the SENSE voltage,
this can require a significant amount of start-up current.
The second source is the output current that flows into
R
should be small enough to conduct the maximum
DS(ON)
load current, and also stay within the MOSFET’s power
R , which upon start-up may temporarily drive the
OUT
rating.
IMON output high for less than 2ms. This is a temporary
conditionwhichwillceasewhenthesenseamplifiersettles
into normal closed-loop operation.
Supply Transient Protection
When the capacitances at the input and output are very
small, rapid changes in current during input or output
short-circuit events can cause transients that exceed the
24V absolute maximum ratings of the IN and OUT pins.
To minimize such spikes, use wider traces or heavier
trace plating to reduce the power trace inductance. Also,
bypass locally with a 10µF electrolytic and 0.1µF ceramic,
or alternatively clamp the input with a transient voltage
suppressor (Z1, Z2). A 100Ω, 0.1µF snubber damps the
response and eliminates ringing (See Figure 10).
CPO and DGATE Start-Up
The CPO and DGATE pin voltages are initially pulled up
to a diode below the IN pin when first powered up. CPO
starts ramping up 7µs after INTV clears its undervolt-
age lockout level. Another 40µs later, DGATE also starts
ramping up with CPO. The CPO ramp rate is determined
by the CPO pull-up current into the combined CPO and
DGATE pin capacitances. An internal clamp limits the CPO
pin voltage to 12V above the IN pin, while the final DGATE
pin voltage is determined by the gate drive amplifier. An
internal 12V clamp limits the DGATE pin voltage above IN.
CC
Design Example
Asa designexample forselectingcomponents, considera
12V system with a 7A maximum load current for the two
supplies (see Figure 1).
CPO Capacitor Selection
TherecommendedvalueofthecapacitorbetweentheCPO
and IN pins is approximately 10× the input capacitance
First, select the appropriate value of the current sense
C
ISS
of the ideal diode MOSFET. A larger capacitor takes
resistorR forthe12Vsupply. Calculatethesenseresistor
S
a correspondingly longer time to charge up by the internal
charge pump. A smaller capacitor suffers more voltage
drop during a fast gate turn-on event as it shares charge
with the MOSFET gate capacitance.
value based on the maximum load current I
and
LOAD(MAX)
4235f
16
For more information www.linear.com/LTC4235
LTC4235
applicaTions inForMaTion
thelowerlimitforthecurrentlimitsensevoltagethreshold
TheaveragepowerdissipatedintheMOSFETiscalculatedas:
∆V
.
SENSE(TH)(MIN)
2
ECL
tCHARGE
1
2
680µF • 12V
(
)
PAVG
=
=
•
= 6W
ΔVSENSE(TH)(MIN)
22.5mV
7A
8ms
RS =
=
= 3.2mΩ
ILOAD(MAX)
The MOSFET selected must be able to tolerate 6W for 8ms
duringpower-up.TheSOAcurvesoftheSiR158DPprovide
45W (1.5A at 30V) for 100ms. This is sufficient to satisfy
therequirement. Theincreaseinjunctiontemperaturedue
Choose a 3mΩ sense resistor with a 1% tolerance.
Next, calculate the R of the ideal diode MOSFET to
DS(ON)
achievethedesiredforwarddropatmaximumload.Assum-
tothepowerdissipatedintheMOSFETis∆T= P • Zth
AVG
JC
ing a forward drop, ∆V
of 30mV across the MOSFET:
FWD
where Zth is the junction-to-case thermal impedance.
JC
ΔV
ILOAD(MAX)
30mV
= 4.2mΩ
7A
FWD
Under this condition, the SiR158DP data sheet indicates
RDS(ON)
≤
=
that the junction temperature will increase by 3°C using
Zth = 0.5°C/W (single pulse).
JC
The SiR158DP offers a good choice with a maximum
of 1.8mΩ at V = 10V. The input capacitance
Next, the power dissipated in the MOSFET during an
overcurrent fault must be safely limited. The fault timer
R
ISS
DS(ON)
GS
C
of the SiR158DP is about 4980pF. Slightly exceeding
capacitor (C ) is used to prevent power dissipation in
FT
the 10× recommendation, a 0.1µF capacitor is selected
for C2 and C3 at the CPO pins.
the MOSFET from exceeding the SOA rating during active
current limit. A good way to determine a suitable value
Next, verify that the thermal ratings of the selected Hot
Swap MOSFET are not exceeded during power-up or an
overcurrent fault.
for C is to superimpose the foldback current limit profile
FT
shown in the Typical Performance Characteristics on the
MOSFET data sheet’s SOA curves.
Assuming the MOSFET dissipates power due to inrush
For the SiR158DP MOSFET, this exercise yields the plot
in Figure 6.
current charging the load capacitor C at power-up, the
L
energydissipatedintheMOSFETisthesameastheenergy
stored in the load capacitor, and is given by:
100
I
LIMITED
DM
1ms
1
2
2
ECL = • CL • V
IN
10
1
10ms
I
LIMITED
D
For C = 680µF, the time it takes to charge up C is cal-
culated as:
L
L
100ms
LIMITED BY R
*
DS(ON)
1s
CL • V
IINRUSH
680µF •12V
IN
tCHARGE
=
=
= 8ms
10s
1A
0.1
MOSFET POWER
DISSIPATION CURVE
RESULTING FROM
FOLDBACK ACTIVE
CURRENT LIMIT
DC
The inrush current is set to 1A by adding capacitance C
at the gate of the Hot Swap MOSFET.
HG
BVDSS LIMITED
10
0.01
0.01
0.1
1
100
CL •IHGATE(UP)
680µF •10µA
V
– DRAIN-TO-SOURCE VOLTAGE (V)
DS
4235 F06
CHG
=
=
= 6.8nF
IINRUSH
1A
* V > MINIMUM V AT WHICH R IS SPECIFIED
DS(ON)
GS
GS
Figure 6. SiR158DP SOA with Design Example
MOSFET Power Dissipation Superimposed
Choose a practical value of 10nF for C .
HG
4235f
17
For more information www.linear.com/LTC4235
LTC4235
applicaTions inForMaTion
Ascanbeseen,theLTC4235’sfoldbackcurrentlimitprofile
roughly coincides with the 100ms SOA contour. Since
this SOA plot is for an ambient temperature of 25°C only,
a maximum fault timer period of much less than 100ms
should be considered, such as 10ms or less. Selecting a
⎛
⎞
VON(TH)
1.235V
1µA
⎛
⎝
⎞
⎠
R1=
• 0.2% =
• 0.2% = 2.4k
⎜
⎟
⎜
⎟
I
⎝
⎠
IN(LEAK)
Choose R1 to be 2k to achieve less than 0.2% error and
calculating R2 yields:
0.1µF 10% value for C yields a maximum fault timer
FT
period of1.75mswhichshouldbesmallenoughtoprotect
the MOSFET during any overcurrent fault scenario.
⎛
⎞
V
IN(UV)
R2 =
R2 =
– 1 • R1
⎜
⎟
V
⎝
⎠
⎞
ON(TH)
Next, select the values for the resistive divider at the ON
pin that defines the undervoltage threshold of 9.7V for the
9.7V
1.235V
⎛
– 1 • 2k = 13.7k
⎜
⎝
⎟
+
12V supply at SENSE . Since the leakage current for the
⎠
ON pin can be as high as 1µA, the total resistance in the
divider should be low enough to minimize the resulting
offset error. Calculate the bottom resistor R1 based on
the following equation to obtain less than 0.2% error
due to leakage current.
The final components to consider are a 0.1µF bypass (C1)
at the INTV pin and a 0.1µF capacitor (C4) connected
CC
+
between the REG and SENSE pins.
VIA TO GND PLANE
•••
Z1
CURRENT FLOW
M
M
H
D1
TO LOAD
PowerPAK SO-8
PowerPAK SO-8
S
D
D
D
D
D
G
S
S
S
R
S
S
S
G
D
D
D
OUT
IN1
W
W
TRACK WIDTH W:
0.03" PER AMPERE
ON 1oz Cu FOIL
•
•
•
CURRENT FLOW
TO LOAD
R
H
•
VIA TO C2 (CPO1) VIA TO IN1
VIA TO DGATE1
M
D2
C2
•
PowerPAK SO-8
S
D
D
D
D
20 19 18 17
S
S
G
IN2
W
1
2
3
4
5
6
16
15
14
13
12
11
•
•
C1
VIA TO C4 (REG)
VIA TO DGATE2
LTC4235UFD
•
C4
•
Z2
+
VIA TO SENSE
VIA TO GND PLANE
•••
VIA TO GND PLANE
7
8
9
10
4235 F08
C3
•
Figure 7. Recommended PCB Layout for Power MOSFETs and Sense Resistor
4235f
18
For more information www.linear.com/LTC4235
LTC4235
applicaTions inForMaTion
PCB Layout Considerations
+
the CPO2 and IN2 pins, and C4 near the REG and SENSE
pins. The transient voltage suppressors Z1 and Z2, when
used, should be mounted close to the LTC4235 using
short lead lengths.
To achieve accurate current sensing, a Kelvin connection
for the sense resistor is recommended. The PCB layout
should be balanced and symmetrical to minimize wiring
errors. In addition, the PCB layout for the sense resistor
and the power MOSFET should include good thermal
managementtechniquesforoptimaldevicepowerdissipa-
tion. A recommended PCB layout is illustrated in Figure 7.
Prioritizing Supplies with D2OFF
Figure 8 shows an application where the IN1 supply
is passed to the output on the basis of priority, rather
than simply allowing the highest voltage to prevail. This
is achieved by connecting a resistive divider from IN1
at the D2OFF pin to suppress the turn-on of the ideal
Connect the IN and OUT pin traces as close as possible to
the MOSFETs’ terminals. Keep the traces to the MOSFETs
wideandshorttominimizeresistivelosses.ThePCBtraces
associated with the power path through the MOSFETs
should have low resistance. The suggested trace width for
1oz copper foil is 0.03" for each ampere of DC current to
keep PCB trace resistance, voltage drop and temperature
rise to a minimum. Note that the sheet resistance of 1oz
copper foil is approximately 0.5mΩ/square, and voltage
drops due to trace resistance add up quickly in high cur-
rent applications.
diode MOSFET M in the IN2 power path. When the IN1
D2
supply voltage falls below 11.4V, it allows the ideal diode
MOSFET M , to turn on, causing the diode-OR output
D2
to be switched from the main 12V supply at IN1 to the
auxiliary12VsupplyatIN2. Thisconfigurationpermitsthe
load to be supplied from a lower IN1 supply as compared
to IN2 until IN1 falls below the M turn-on threshold. The
D2
threshold value used should not allow the IN1 supply to
be operated at more than one diode voltage below IN2.
It is also important to place the bypass capacitor C1 for
Otherwise, M conducts through the MOSFET’s body
D2
+
the INTV pin, as close as possible between INTV and
diode. The resistive divider connected from SENSE at
CC
CC
GND. Also place C2 near the CPO1 and IN1 pins, C3 near
the ON pin provides the undervoltage threshold of 9.7V
for the diode-OR output supply.
M
D1
SiR818DP
V
MAIN
12V
Z1
SMAJ15A
C2
0.1µF
M
R
M
H
SiR818DP
D2
S
SiR818DP
0.004Ω
V
12V
5A
AUX
12V
+
Z2
SMAJ15A
C
L
470µF
R
H
10Ω
C3
0.1µF
R
HG
C4
0.1µF
1k
C
HG
10nF
V
+
SENSE
R2
+
–
CPO1
ON
IN1 DGATE1 CPO2
IN2 DGATE2
REG SENSE SENSE HGATE
OUT
13.7k
R6
R5
100k 100k
C5
0.1µF
R1
2k
FAULT
PWRGD
LTC4235
GND
EN
R4
IMON
ADC
21k
BACKPLANE CARD
CONNECTOR CONNECTOR
D2OFF
INTV
CC
FTMR
C6
0.1µF
R3
2.49k
4235 F08
C
FT
C1
0.1µF
0.1µF
Figure 8. Plug-In Card 12V Prioritized Power Supply at IN1
4235f
19
For more information www.linear.com/LTC4235
LTC4235
applicaTions inForMaTion
M
D1
SiR818DP
V
MAIN
12V
R7 100Ω
Z1
C2
SMAJ15A
0.1µF
M
M
R
M
H
SiR818DP
D2
D3
S
SiR818DP SiR818DP
0.004Ω
V
12V
5A
AUX
12V
+
Z2
SMAJ15A
C
L
470µF
R
H
10Ω
R
HG
1k
C
C3
0.1µF
C4
0.1µF
HG
10nF
V
+
SENSE
R2
+
–
CPO1
ON
IN1 DGATE1 CPO2
IN2 DGATE2
REG SENSE SENSE HGATE
OUT
13.7k
R6
R5
100k 100k
C5
0.1µF
R1
2k
FAULT
PWRGD
LTC4235
GND
EN
R4
IMON
ADC
20k
BACKPLANE CARD
CONNECTOR CONNECTOR
D2OFF
INTV
CC
FTMR
C6
0.1µF
R3
2.49k
4235 F09
C
FT
C1
0.1µF
0.1µF
Figure 9. 1V Supply Separation from IN2 for Prioritized Power Supply at IN1 Using Back-to-Back MOSFETs
M
D1
SiR158DP
V
IN1
12V
Z1
SMAJ15A
C2
0.1µF
R
SNUB1
100Ω
C
SNUB1
0.1µF
M
R
M
H
SiR158DP
D2
S
SiR158DP
0.002Ω
V
IN2
12V
10A
12V
+
Z2
SMAJ15A
R
100Ω
C
C
L
SNUB2
220µF
R
H
10Ω
C3
0.1µF
SNUB2
0.1µF
V
+
SENSE
R
HG
1k
R4
C
2.7k
HG
C4
0.1µF
10nF
R3
D2
2.7k
+
–
CPO1
ON
IN1 DGATE1 CPO2
IN2 DGATE2
REG SENSE SENSE HGATE
OUT
D1
PWREN
R1
10k
FAULT
PWRGD
LTC4235
EN
IMON
ADC
BACKPLANE CARD
CONNECTOR CONNECTOR
4235 F09
INTV
GND
D2OFF
FTMR
CC
C
FT
C1
0.1µF
D1: GREEN LED LN1351C
D2: RED LED LN1261CAL
0.1µF
Figure 10. 12V, 10A Card Resident Application
4235f
20
For more information www.linear.com/LTC4235
LTC4235
package DescripTion
Please refer to http://www.linear.com/product/LTC4235#packaging for the most recent package drawings.
UFD Package
20-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-ꢀ7ꢀꢀ Rev B)
0.70 0.05
2.65 0.05
3.65 0.05
4.50 0.05
3.ꢀ0 0.05
ꢀ.50 REF
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
2.50 REF
4.ꢀ0 0.05
5.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN ꢀ NOTCH
R = 0.20 OR
C = 0.35
0.75 0.05
ꢀ.50 REF
ꢀ9
4.00 0.ꢀ0
(2 SIDES)
R = 0.05 TYP
20
0.40 0.ꢀ0
PIN ꢀ
TOP MARK
(NOTE 6)
ꢀ
2
5.00 0.ꢀ0
(2 SIDES)
2.50 REF
3.65 0.ꢀ0
2.65 0.ꢀ0
(UFD20) QFN 0506 REV B
0.25 0.05
0.200 REF
R = 0.ꢀꢀ5
TYP
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4235f
21
For more information www.linear.com/LTC4235
LTC4235
Typical applicaTion
12V, 5A Backplane Resident Ideal Diode-OR Application with Inrush Current Limiting
M
D1
SiR158DP
V
IN1
12V
BULK
C2
0.1µF
SUPPLY
BYPASS
CAPACITOR
M
R
M
H
SiR158DP
D2
S
SiR158DP
0.004Ω
V
12V
5A
IN2
12V
+
BULK
C
L
SUPPLY
BYPASS
CAPACITOR
1000µF
R
H
10Ω
C3
0.1µF
R
HG
C4
0.1µF
1k
C
HG
10nF
+
–
CPO1
IN1 DGATE1 CPO2
IN2 DGATE2
REG SENSE SENSE HGATE
OUT
R2
FAULT
PWRGD
EN
13.7k
ON
C5
0.1µF
R1
2k
LTC4235
BACKPLANE PLUG-IN
CARD
IMON
ADC
INTV
CC
FTMR
D2OFF
GND
4235 TA02
C
FT
C1
0.1µF
0.1µF
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
Operates from 2.7V to 16.5V, Active Current Limiting, TSOT23-6
LTC4210
LTC4211
LTC4215
LTC4216
LTC4218
LTC4221
LTC4222
LTC4223
LTC4224
LTC4227
LTC4228
LTC4229
LTC4352
LTC4353
LTC4355
LTC4357
Single Channel Hot Swap Controller
Single Channel Hot Swap Controller
Single Channel Hot Swap Controller
Single Channel Hot Swap Controller
Single Channel Hot Swap Controller
Dual Channel Hot Swap Controller
Dual Channel Hot Swap Controller
Dual Supply Hot Swap Controller
Dual Channel Hot Swap Controller
Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8, SO-8 or MSOP-10
2
Operates from 2.9V to 15V, I C Compatible Monitoring, SSOP-16 or QFN-24
Operates from 0V to 6V, Active Current Limiting, MSOP-10 or DFN-12
Operates from 2.9V to 26.5V, Active Current Limiting, SSOP-16 or DFN-16
Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16
2
Operates from 2.9V to 29V, I C Compatible Monitoring, SSOP-36 or QFN-32
Controls 12V and 3.3V, Active Current Limiting, SSOP-16 or DFN-16
Operates from 1V to 6V, Active Current Limiting, MSOP-10 or DFN-10
Dual Ideal Diode and Single Hot Swap Controller Operates from 2.9V to 18V, Controls Three N-Channels, SSOP-16 or QFN-20
Dual Ideal Diode and Hot Swap Controller
Ideal Diode and Hot Swap Controller
Low Voltage Ideal Diode Controller
Dual Low Voltage Ideal Diode Controller
Operates from 2.9V to 18V, Controls Four N-Channels, SSOP-28 or QFN-28
Operates from 2.9V to 18V, Controls Two N-Channels, SSOP-24 or QFN-24
Operates from 0V to 18V, Controls N-Channel, MSOP-12 or DFN-12
Operates from 0V to 18V, Controls Two N-Channels, MSOP-16 or DFN-16
Positive High Voltage Ideal Diode-OR and Monitor Operates from 9V to 80V, Controls Two N-Channels, SO-16, DFN-14 or MSOP-16
Positive High Voltage Ideal Diode Controller
Operates from 9V to 80V, Controls N-Channel, MSOP-8 or DFN-6
4235f
LT 1115 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
22
●
●
LINEAR TECHNOLOGY CORPORATION 2015
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC4235
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