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LTC4240CGN#PBF [Linear]

LTC4240 - CompactPCI Hot Swap Controller with I<sup>2</sup>C Compatible Interface; Package: SSOP; Pins: 28; Temperature Range: 0&deg;C to 70&deg;C;
LTC4240CGN#PBF
型号： LTC4240CGN#PBF
厂家： Linear    Linear
描述：

LTC4240 - CompactPCI Hot Swap Controller with I<sup>2</sup>C Compatible Interface; Package: SSOP; Pins: 28; Temperature Range: 0&deg;C to 70&deg;C

PC 光电二极管
文件： 总28页 (文件大小：491K)
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LTC4240  
CompactPCI Hot Swap  
2
Controller with I C Compatible Interface  
U
FEATURES  
DESCRIPTIO  
TheLTC®4240isaHotSwapTM controllerthatallowsaboard  
to be safely inserted and removed from a live CompactPCI  
busslot. The LTC4240 has a built-in 2-wire I2C compatible  
interface to allow software control and monitoring of  
device function and power supply status. Two external  
N-channel transistors control the 3.3V and 5V supplies,  
while two internal switches control the –12V and 12V  
supplies.Electroniccircuitbreakersprotectallfoursupplies  
against overcurrent faults. The PWRGD output indicates  
when all of the supply voltages are within tolerance. The  
OFF/ON pin is used to cycle the board power or reset the  
circuitbreaker. The I2C interface allows the user to turn the  
device off or on, set RESETOUT, turn on the status LED  
driver and ignore 12V, –12V faults. It also allows the user  
to read the status of the FAULT, RESETIN, RESETOUT,  
PWRGD, PRSNT1# and PRSNT2# pins. Under a fault  
condition, the I2C interface can also be used to determine  
whichofthefoursuppliesgeneratedthefault.TheLTC4240  
is available in a 28-pin narrow SSOP package.  
■
Allows Safe Board Insertion and Removal from a  
Live CompactPCITM Bus  
I2CTM Compatible 2-Wire Interface  
PRECHARGE Output Biases I/O Pins During Card  
Insertion and Extraction  
■
■
■
■
■
■
■
■
■
■
Controls 3.3V, 5V, 12V and –12V Supplies  
Foldback Current Limit with Circuit Breaker  
LOCAL_PCI_RST# Logic On-Board  
QuickSwitch® Enable Output  
Status LED Driver  
User Programmable Supply Voltage Power-Up Rate  
Registers Individual Supply Faults  
Available in a 28-Pin Narrow SSOP Package  
U
APPLICATIO S  
■
Hot Board Insertion into CompactPCI Bus  
■
Electronic Circuit Breaker  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
Hot Swap is a trademark of Linear Technology Corporation.  
QuickSwitch is a registered trademark of Quality Semiconductor Corp.  
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.  
I2C is a trademark of Philips Electronics N.V.  
U
TYPICAL APPLICATIO  
CompactPCI CompactPCI  
BACKPLANE BACKPLANE  
C11  
10nF  
CONNECTOR CONNECTOR  
R2  
0.007Ω  
Q2  
Si7880DP  
(MALE)  
(FEMALE)  
Z4  
Z3  
5V  
IN  
5V  
OUT  
MEDIUM 5V  
LONG 5V  
MEDIUM 3.3V  
LONG 3.3V  
5V AT 5A  
R1  
0.005Ω  
+
Q1  
R22, 2.74Ω  
R21, 1.74Ω  
C
(5V )  
OUT  
LOAD  
Si7880DP  
3V  
IN  
3V  
OUT  
3.3V AT 7.6A  
+
C7  
0.01µF  
PER  
C8  
0.01µF  
PER  
R19  
2.55k  
1%  
C
LOAD  
(3V  
)
OUT  
C1  
0.047µF  
C10  
10nF  
R3  
10Ω  
R4  
10Ω  
R5  
1k  
5V  
IN  
PIN  
PIN  
R20  
1.91k  
1%  
LONG V(I/O)  
C9  
10nF  
3V  
IN  
ADDRIN  
SCL  
SDA  
PRSNT2#  
PRSNT1#  
3V  
GATE 3V  
5V  
5V  
5V  
OUT  
R12  
10k  
SENSE  
OUT  
IN  
SENSE  
R10  
100Ω  
DGND  
R25, 1.2k  
SCL  
SDA  
R28, 200Ω  
LED  
12V  
OUT  
12V AT 500mA  
(12V  
12V  
OUT  
+
+
12V  
IN  
12V  
C
C
)
OUT  
LOAD  
–12V  
V
EEIN  
V
LTC4240  
EEOUT  
–12V AT 100mA  
V
R18  
1k  
EEOUT  
5V  
IN  
R17, 1.2k  
TIMER  
(V  
)
C2  
0.1µF  
LOAD EEOUT  
OFF/ON  
FAULT  
BD_SEL#  
EARLY  
V(I/O)  
TO  
QUICKSWITCH®  
ENABLE  
Z1  
BE  
R15  
R29  
10Ω  
R16  
10k  
2k  
HEALTHY#  
PCI_RST#  
PWRGD  
RESETIN  
GND  
RESETOUT  
3V  
OUT  
R6  
10k  
C6  
0.01µF  
LOCAL_PCI_RST#  
R30  
1k  
PRECHARGE  
DRIVE  
Q3  
R13  
10Ω  
C4  
R14  
10Ω  
C5  
Z2  
TO PCI BRIDGE  
DEVICE OR  
EQUIVALENT  
R8, 1k  
R7, 12Ω  
R9  
24Ω  
R11  
18Ω  
Z1, Z2: SMAJ12CA  
Z3, Z4: IPMT5.0AT3  
C3, 4.7nF  
0.01µF  
0.01µF  
3V  
IN  
GROUND  
4240 TA01  
MMBT2222A  
4240f  
1
LTC4240  
W W U W  
U
W
U
ABSOLUTE AXI U RATI GS  
(Notes 1, 2)  
PACKAGE/ORDER I FOR ATIO  
ORDER PART  
TOP VIEW  
Supply Voltages  
NUMBER  
5VIN .................................................................... –0.3V to 12V  
12VIN ................................................................. –0.3V to 14V  
VEEIN ................................................................... 0.3V to –14V  
Input Voltages  
1
2
OFF/ON  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
PRSNT1#  
PRSNT2#  
RESETIN  
LTC4240CGN  
LTC4240IGN  
3
12V  
OUT  
12V  
IN  
4
V
V
EEIN  
EEOUT  
5
3V  
OUT  
TIMER  
PRSNT1#, PRSNT2#, SCL, RESETIN,  
OFF/ON ..................................................–0.3V to 12V  
5VOUT, 5VSENSE, 3VIN,  
6
3V  
SENSE  
5V  
OUT  
7
3V  
IN  
FAULT  
PWRGD  
BE  
8
5V  
IN  
3VSENSE, 3VOUT ............................ –0.3V to (5VIN + 0.3V)  
ADDRIN, PRECHARGE ......................... –0.3V to 5VIN  
Output Voltages  
TIMER, FAULT, PWRGD, SDA, RESETOUT,  
LED, DRIVE, GATE, 12VOUT ....................... –0.3V to 14V  
VEEOUT ................................................................ –14V to 0.3V  
BE............................................. 0.3V to (5VIN + 0.3V)  
Operating Temperature Range  
LTC4240C ............................................... 0°C to 70°C  
LTC4240I.............................................–40°C to 85°C  
Storage Temperature Range .................... 65°C to 150°C  
Lead Temperature (Soldering, 10 sec).................. 300°C  
9
5V  
SENSE  
10  
11  
12  
13  
14  
GATE  
GND  
PRECHARGE  
DRIVE  
DGND  
ADDRIN  
SDA  
SCL  
LED  
RESETOUT  
GN PACKAGE  
28-LEAD PLASTIC SSOP  
TJMAX = 140°C, θJA = 135°C/W  
Consult LTC Marketing for parts specified with wider operating temperature ranges.  
ELECTRICAL CHARACTERISTICS  
The ● denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. 12VIN = 12V, VEEIN = –12V, V3VIN = 3.3V, V5VIN = 5V unless otherwise noted.  
SYMBOL  
PARAMETER  
Supply Current  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
I
V
OFF/ON = 0V  
●
3
8
mA  
DD  
12VIN  
V
V
V
Undervoltage Lockout  
12V  
●
●
●
●
7.00  
4.10  
2.35  
8.00  
4.3  
2.45  
–9  
10.80  
4.45  
V
V
V
V
LKO  
IN  
5V  
3V  
EEIN  
IN  
IN  
2.55  
V
–10.5  
Foldback Current Limit Voltage  
Circuit Breaker Trip Voltage  
V
V
V
V
= (V  
– V  
– V  
– V  
– V  
), V  
), V  
), V  
), V  
= 0V, TIMER = 0V  
= 3V, TIMER = 0V  
= 0V, TIMER = 0V  
= 2V, TIMER = 0V  
●
●
●
●
15  
55  
15  
55  
25  
70  
25  
65  
35  
85  
35  
80  
mV  
mV  
mV  
mV  
FB  
FB  
FB  
FB  
FB  
5VIN  
5VIN  
3VIN  
3VIN  
5VSENSE  
5VSENSE  
3VSENSE  
3VSENSE  
5VOUT  
5VOUT  
3VOUT  
3VOUT  
= (V  
= (V  
= (V  
V
V
V
V
= (V  
= (V  
= (V  
= (V  
– V  
– V  
– V  
– V  
), V  
), V  
), V  
), V  
= 5V, TIMER = Open  
= 0V, TIMER = Open  
= 3.3V, TIMER = Open  
= 0V, TIMER = Open  
●
●
●
●
50  
6
50  
6
55  
11  
55  
11  
60  
16  
60  
16  
mV  
mV  
mV  
mV  
CB  
TV  
TV  
TV  
TV  
5VIN  
5VIN  
3VIN  
3VIN  
5VSENSE  
5VSENSE  
3VSENSE  
3VSENSE  
5VOUT  
5VOUT  
3VOUT  
3VOUT  
t
t
Overcurrent Fault Response Time (V  
Overcurrent Fault Response Time (V  
– V  
– V  
) = 100mV, TIMER = Open  
) = 100mV, TIMER = Open  
●
●
25  
25  
35  
35  
55  
55  
µs  
µs  
OC  
5VIN  
3VIN  
5VSENSE  
3VSENSE  
Short-Circuit Response Time  
(V  
5VIN  
(V  
3VIN  
– V  
– V  
) = 200mV, TIMER = Open  
5VSENSE  
) = 200mV, TIMER = Open  
3VSENSE  
●
●
25  
25  
35  
35  
55  
55  
µs  
µs  
SC  
I
I
I
GATE Pin Turn-On Current  
GATE Pin Turn-Off Current  
GATE Pin Fault-Off Current  
OFF/ON = 0V, V  
GATE  
= 0V, TIMER = 0V  
●
●
●
–20  
100  
2.5  
–65  
200  
6
–100  
300  
8.5  
µA  
µA  
mA  
GATE(UP)  
GATE(DN)  
GATE  
= 5V, (Note 3)  
V
OFF/ON = 0V, V  
= 2V, TIMER = Open, FAULT = 0V  
GATE(FAULT)  
GATE  
∆V  
GATE  
External Gate Voltage  
∆V  
GATE  
= (V  
– V ), I = 1µA  
GATE GATE  
●
600  
1000  
mV  
12VIN  
4240f  
2
LTC4240  
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. 12VIN = 12V, VEEIN = –12V, V3VIN = 3.3V, V5VIN = 5V unless otherwise noted.  
SYMBOL PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX UNITS  
∆V  
12V  
∆V  
VEE  
12V Switch Voltage Drop  
Switch Voltage Drop  
∆V = (V  
– V  
), I = 500mA  
), I = 100mA  
●
●
300  
125  
600  
250  
mV  
mV  
12V  
∆V = (V  
12VIN  
12VOUT  
– V  
V
EE  
VEE  
EEOUT EEIN  
I
Current Foldback  
12V = 12V, 12V  
= 0V  
= 0V  
●
●
–50  
50  
–350 –800  
250 350  
mA  
mA  
CL  
IN  
OUT  
V
= –12V, V  
EEIN  
EEOUT  
I
Current Fault Threshold  
12V = 12V  
EEIN  
●
●
–550  
225  
–1250 –1900  
mA  
mA  
TH  
IN  
V
= –12V  
500  
800  
T
Thermal Shutdown Temperature  
Power Good Threshold Voltage  
Note 4  
150  
°C  
TS  
V
12V  
●
●
●
●
10.8  
4.50  
2.8  
11.1  
4.65  
2.9  
11.4  
4.75  
3.0  
V
V
V
V
TH  
OUT  
5V  
3V  
OUT  
OUT  
V
– 10  
– 10.5 – 10.8  
EEOUT  
V
V
Input Low Voltage  
Input High Voltage  
OFF/ON, RESETIN, SCL, SDA, PRSNT1#, PRSNT2#  
OFF/ON, RESETIN, SCL, SDA, PRSNT1#, PRSNT2#  
●
●
0.8  
V
V
IL  
2
IH  
I
Input Current PRSNT1#, PRSNT2#,  
OFF/ON, RESETIN, SDA, SCL  
OFF/ON = RESETIN = SDA = SCL = 0V, 5V,  
PRSNT1#, PRSNT2# = 0V, 5V  
●
●
±0.08  
±0.08  
±2  
±2  
µA  
µA  
IN  
RESETOUT, FAULT Leakage Current  
PWRGD Leakage Current  
RESETOUT = FAULT = 12V, OFF/ON = 0V, RESETIN = 3.3V  
PWRGD = 12V, OFF/ON = 4V  
●
●
●
●
●
±0.08  
±0.08  
55  
±2  
±2  
µA  
µA  
5V  
3V  
Input Current  
Input Current  
5V  
SENSE  
3V  
SENSE  
= 5V, 5V = 0V, GATE = 0V  
OUT  
100  
100  
1.5  
µA  
SENSE  
SENSE  
= 3.3V, 3V  
= 0V, GATE = 0V  
55  
µA  
OUT  
5V Input Current  
IN  
5V = 5V, TIMER = 0V, OFF/ON = 0V  
IN  
0.8  
mA  
3V Input Current  
IN  
3V = 3.3V, TIMER = Open  
3V = 3.3V, TIMER = 0V  
IN  
●
●
250  
250  
600  
500  
µA  
µA  
IN  
5V  
3V  
Input Current  
Input Current  
5V  
3V  
= 5V, OFF/ON = 0V, TIMER = 0V, GATE = 0V  
= 3.3V, OFF/ON = 0V, TIMER = 0V, GATE = 0V  
●
●
●
●
●
237  
120  
400  
200  
µA  
µA  
µA  
µA  
µA  
OUT  
OUT  
OUT  
OUT  
V
Input Current  
TIMER = 0V, OFF/ON = 0V  
= 1V  
–950 –1200  
EEIN  
Precharge Input Current  
ADDRIN  
V
10  
PRECHARGE  
ADDRIN = 0V, 5V  
±0.1  
I
TIMER Pin Current  
OFF/ON = 0V, TIMER = 0V  
TIMER = 5V, OFF/ON = 2V  
●
●
–6  
15  
–11.5  
28  
–17  
55  
µA  
mA  
TIMER  
V
TIMER Threshold Voltages  
●
5
5.5  
6.5  
V
TIMER  
R
DIS  
12V  
Discharge Impedance  
OUT  
●
●
●
●
430  
50  
150  
650  
1000  
100  
300  
Ω
Ω
Ω
Ω
5V  
3V  
Discharge Impedance  
Discharge Impedance  
Discharge Impedance  
OUT  
OUT  
V
1000  
EEOUT  
5V – 0.4  
V
CMOS Output High Voltage  
BE, I = –100µA  
●
V
IN  
OH  
OL  
V
V
CMOS Output Low Voltage  
Output Low Voltage  
Output Low Voltage  
BE, I = 100µA  
PWRGD, RESETOUT, FAULT, SDA(I = 3mA)  
LED (I = 10mA)  
●
●
●
0.4  
0.4  
0.8  
V
V
V
PRECHARGE Reference Voltage  
V
= 5V  
5VIN  
●
0.9  
1
1.1  
V
PXG  
2
I C Timing (Note 4)  
f
t
t
t
SCL Clock Frequency  
100  
kHz  
µs  
SCL  
Start Condition Setup Time  
Bus Free Time Between Stop and Start  
Start Condition Hold Time  
4.7  
4.7  
4
SUSTA  
BUF  
µs  
µs  
HDSTA  
4240f  
3
LTC4240  
ELECTRICAL CHARACTERISTICS  
The ● denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. 12VIN = 12V, VEEIN = –12V, V3VIN = 3.3V, V5VIN = 5V unless otherwise noted.  
SYMBOL PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX UNITS  
t
t
t
t
t
t
t
Stop Condition Setup Time  
Data Hold Time  
4
µs  
ns  
ns  
µs  
µs  
SUSTP  
HDDAT  
SUDAT  
LOW  
HIGH  
f
300  
250  
Data Setup Time  
Clock Low Period  
4.7  
4.0  
Clock High Period  
Clock/Data Fall Time  
Clock/Data Rise Time  
300  
ns  
ns  
1000  
r
Note 1: Absolute Maximum Ratings are those values beyond which the life  
Note 3: OFF/ON pin pulled up to 5V by 1.2k resistor.  
Note 4: Parameters guaranteed by design and not tested.  
of a device may be impaired.  
Note 2: All currents into device pins are positive; all currents out of  
device pins are negative. All voltages are referenced to ground unless  
otherwise specified.  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
Gate Pin Fault Current  
vs Temperature  
Gate Pin Turn-Off Current  
vs Temperature  
Gate Pin Turn-On Current  
vs Temperature  
350  
300  
250  
200  
150  
100  
8
6
4
2
0
–20  
–40  
V
= 2V  
V
= 5V  
GATE  
GATE  
V
= 0V  
GATE  
FAULT = 0V  
OFF/ON = 2V  
OFF/ON = 0V  
–60  
–80  
–100  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
50  
75  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4240 G01  
4240 G02  
4240 G03  
12VIN Supply Current  
vs Temperature  
3VIN Supply Current  
vs Temperature  
5VIN Supply Current  
vs Temperature  
4.0  
3.6  
3.2  
2.8  
2.4  
280  
260  
240  
220  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
OFF/ON = 0V  
OFF/ON = 0V  
OFF/ON = 0V  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
50  
75  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4240 G05  
4240 G06  
4240 G04  
4240f  
4
LTC4240  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
VEEIN Supply Current  
vs Temperature  
12VIN Foldback Current Limit  
vs Temperature  
VEEIN Foldback Current Limit  
vs Temperature  
–0.8  
–0.9  
–1.0  
–1.1  
–1.2  
1.6  
1.2  
0.8  
0.4  
0
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
OFF/ON = 0V  
12V  
= 10V  
OUT  
V
= –10V  
EEOUT  
V
= 0V  
EEOUT  
12V  
= 0V  
50  
OUT  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
75  
100  
–50  
0
25  
50  
75  
100  
–25  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4240 G07  
4240 G08  
4240 G09  
12VOUT PWRGD Threshold  
Voltage vs Temperature  
12V Output Current  
–12V Output Current  
0.5  
0.4  
0.3  
0.2  
0.1  
0
1.6  
1.2  
0.8  
0.4  
0
11.4  
11.3  
11.2  
11.1  
11.0  
10.9  
10.8  
12V = 12V  
V
= –12V  
IN  
= 25°C  
EEIN  
T = 25°C  
A
T
A
0
–2  
–4  
–6  
–8  
–10  
–12  
–50  
0
25  
50  
75  
100  
–25  
0
2
4
6
8
10  
12  
OUTPUT VOLTAGE (V)  
TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
4240 G11  
4240 G12  
4240 G10  
3VOUT PWRGD Threshold Voltage  
vs Temperature  
VEEOUT PWRGD Threshold  
Voltage vs Temperature  
5VOUT PWRGD Threshold Voltage  
vs Temperature  
4.75  
4.70  
4.65  
4.60  
4.55  
4.50  
3.00  
2.95  
2.90  
2.85  
2.80  
–10.2  
–10.3  
–10.4  
–10.5  
–10.6  
–10.7  
–10.8  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
50  
75  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4240 G14  
4240 G13  
4240 G15  
4240f  
5
LTC4240  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
3VSENSE Input Current  
vs Temperature  
5VSENSE Input Current  
vs Temperature  
Timer Pin Turn-Off Current  
vs Temperature  
65  
60  
55  
50  
45  
65  
60  
55  
50  
45  
34  
32  
30  
28  
26  
24  
22  
20  
18  
5V  
= 5V  
3V  
= 3.3V  
SENSE  
OFF/ON = 2V  
= 5V  
SENSE  
V
TIMER  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
50  
75  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4240 G16  
4240 G17  
4240 G18  
5V/3.3V Circuit Breaker  
Overcurrent Fault Response Time  
vs Temperature  
Timer Threshold Voltage  
vs Temperature  
Timer Pin Turn-On Current vs  
Temperature  
40  
38  
36  
34  
32  
30  
–10.0  
–10.5  
–11.0  
–11.5  
–12.0  
–12.5  
–13.0  
6.0  
5.8  
5.6  
5.4  
5.2  
5.0  
OFF/ON = 0V  
TIMER  
TIMER PIN FLOATING  
V
= 0V  
V
– V  
= 0.1V  
IN  
SENSE  
–50  
0
25  
50  
75  
100  
–50  
0
25  
50  
75  
100  
–25  
–25  
–50  
0
25  
50  
75  
100  
–25  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4240 G21  
4240 G19  
4240 G20  
12VIN UVLO Threshold Voltage  
vs Temperature  
3VIN UVLO Threshold Voltage  
vs Temperature  
5VIN UVLO Threshold Voltage  
vs Temperature  
9.0  
8.5  
8.0  
7.5  
7.0  
2.55  
2.50  
2.45  
2.40  
2.35  
4.45  
4.40  
4.35  
4.30  
4.25  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
0
25  
50  
75  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4240 G22  
4240 G23  
4240 G24  
4240f  
6
LTC4240  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
VEEIN UVLO Threshold Voltage  
vs Temperature  
12VIN Internal Switch Voltage  
Drop vs Temperature  
VEEIN Internal Switch Voltage Drop  
vs Temperature  
–7.6  
–8.0  
–8.4  
–8.8  
–9.2  
–9.6  
–10.0  
500  
450  
400  
350  
300  
250  
200  
150  
200  
160  
120  
80  
I = 500mA  
I = 100mA  
40  
–50  
0
25  
50  
75  
100  
–25  
–50  
0
25  
50  
75  
100  
100  
100  
–25  
–50 –25  
0
25  
50  
75  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4240 G25  
4240 G26  
4240 G27  
3V Foldback Current Limit Voltage  
vs Temperature  
3V Circuit Breaker Trip Voltage  
vs Temperature  
5V Foldback Current Limit Voltage  
vs Temperature  
80  
60  
40  
20  
0
80  
60  
40  
20  
0
100  
80  
60  
40  
20  
0
3V  
= 2V  
OUT  
5V  
= 3V  
OUT  
3V  
= 3.3V  
OUT  
3V  
= 0V  
OUT  
5V  
= 0V  
OUT  
25  
3V  
= 0V  
OUT  
V = 0V  
TIMER  
V
= 0V  
V
= OPEN  
0
TIMER  
TIMER  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
25  
50  
75  
–50  
0
50  
75  
100  
–25  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4240 G31  
4240 G28  
4240 G29  
5V Circuit Breaker Trip Voltage  
vs Temperature  
3VOUT Input Current  
vs Temperature  
5VOUT Input Current  
vs Temperature  
160  
140  
120  
100  
80  
300  
280  
260  
240  
220  
200  
80  
60  
40  
20  
0
5V  
= 5V  
OUT  
3V  
= 3.3V  
OFF/ON = 0V  
OUT  
OFF/ON = 0V  
5V  
= 5V  
OUT  
5V  
= 0V  
OUT  
V
= OPEN  
0
TIMER  
–50 –25  
0
25  
50  
75  
–50 –25  
0
25  
50  
75  
100  
–50 –25  
25  
50  
75  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4240 G34  
4240 G33  
4240 G32  
4240f  
7
LTC4240  
U
U
U
PI FU CTIO S  
PRSNT1# (Pin 1): PCI Present Detect Input 1. PRSNT1#  
and PRSNT2# are readable over the I2C Bus. PRSNT1#  
and PRSNT2# indicate the maximum power used by the  
card. Do not float.  
PWRGD (Pin 8): Open-Drain Power Good Output. Con-  
nect the CPCI HEALTHY# signal to the PWRGD pin.  
PWRGD remains low while V12VOUT ≥ 11.1V, V3VOUT  
≥
2.9V, V5VOUT ≥ 4.65V and VEEOUT ≤ –10.5V. When any of  
the supplies drops below its power good threshold volt-  
age,PWRGDwillgohighaftera10µsdeglitchingtime.The  
switches will not be turned off when PWRGD goes high,  
unless a fault has occurred. The CPCI specification calls  
for a 0.01µF bypass capacitor on the backplane for  
HEALTHY#.  
PRSNT2#(Pin2):PCIPresentDetectInput2. Donotfloat.  
12VIN (Pin 3): 12V Supply Input. A 0.5Ω switch is inter-  
nally connected between 12VIN and 12VOUT with foldback  
current limit. An undervoltage lockout circuit prevents the  
switches from turning on while the 12VIN pin is below 8V.  
12VIN provides power to some of the LTC4240’s internal  
circuitry. SeeInputTransientProtectionsectiononhowto  
protect 12VIN from large voltage transients.  
BE(Pin9):QuickSwitchBusEnableOutput. TheBEoutput  
remains high until power is good on all supplies. This  
serves to isolate the I/O data lines during live  
insertion. This is a CMOS output powered by 5VIN.  
VEEIN (Pin 4): –12V Supply Input. A 1Ω internal switch is  
connected between VEEIN and VEEOUT with foldback cur-  
rent limit. An undervoltage lockout circuit prevents the  
switches from turning on while VEEIN is above –9V. See  
Connecting VEEIN section for more notes on VEEIN and  
VEEOUT. Also refer to Input Transient Protection section.  
GND (Pin 10): Analog Ground. Connect to analog ground  
plane.  
ADDRIN (Pin 11): I2C Address Programming Input. The  
I2C address is programmed by connecting the ADDRIN  
pintoaresistordividerbetweenthe5VIN pinandGND. See  
Table 1 for 1% resistor values and corresponding ad-  
dresses. Resistors must be placed close to the ADDRIN  
pin to minimize errors due to stray capacitance and  
resistance on the board trace. Connect this pin to ground  
if I2C is not used.  
SDA (Pin 12): I2C Data Input and Output. Note that TTL  
levels are used. Connect this pin to ground if I2C is not  
used.  
TIMER/AUX 12VIN (Pin 5): Current Fault Inhibit Timing  
Input. Connect a capacitor from TIMER to GND. With the  
LTC4240 turned off (OFF/ON = HIGH), the TIMER pin is  
internally held at GND. When the device is turned on, an  
11.5µA pull-up current source is connected to TIMER.  
Current limit faults will be ignored until the voltage at the  
TIMER pin rises above 5.5V. The Timer capacitor also  
serves as an auxiliary charge reservoir for internal VCC in  
theeventthe12VIN pinvoltageglitchesbelowtheLTC4240  
UVL threshold voltage.  
SCL (Pin 13): I2C Clock Input, 100kHz Maximum. Note  
that TTL levels are used. Do not float. Connect this pin to  
ground if I2C is not used.  
5VOUT (Pin 6): 5V Output Sense. The PWRGD pin will not  
pull low until the 5VOUT pin voltage exceeds 4.65V. When  
the power switches are turned off, a 50Ω resistor pulls  
5VOUT to ground.  
RESETOUT (Pin 14): Open-Drain Reset Output. Connect  
the CPCI LOCAL_PCI_RST# signal to the RESETOUT pin.  
RESETOUTisthelogicalcombinationofRESETIN, PWRGD,  
and I2C RESETOUT latch output.  
FAULT (Pin 7): Open-Drain Fault Output . FAULT is pulled  
low when a current limit fault is detected. Current limit  
faults are ignored until the voltage at the TIMER pin is  
above 5.5V. Once the TIMER cycle is complete, FAULT  
pulls low and the LTC4240 turns off (in the event of an  
overcurrent fault lasting longer than 35µs). The LTC4240  
will remain in the off state until the OFF/ON pin is cycled  
high then low or power is cycled. Note that the OFF/ON  
cycling can also be performed using I2C bus.  
LED (Pin 15): CPCI Status LED. Pulls low to light LED  
when RESETOUT is low or when the I2C LED latch is set.  
DGND (Pin 16): Digital Ground. Connect to ground plane.  
DRIVE (Pin 17):External transistor’s base drive output for  
bus precharge. Connects to the base of an external NPN  
emitter-follower which in turn biases the PRECHARGE  
4240f  
8
LTC4240  
U
U
U
PI FU CTIO S  
long pin must be connected to 3VIN to ensure precharge  
output. See Input Transient Protection section.  
node.Anexternal1kresistorbetweenthetransistor’sbase  
and 3VIN is needed.  
3VSENSE (Pin 23): 3.3V Current Limit Sense. A sense  
resistor placed between 3VIN and 3VSENSE determines the  
current limit for this supply. A foldback feature makes the  
current limit decrease as the voltage at the 3VOUT pin  
approaches 0V. To disable current limit, 3VSENSE and 3VIN  
must be tied together.  
PRECHARGE (Pin 18): Precharge Monitor Input. An inter-  
nalerroramplifierservostheDRIVEpinvoltagetokeepthe  
precharge node at 1V. Becomes valid when long 5V and  
3.3Vpowerpinsmakecontact.Tiepins17and18together  
if precharge function is unused.  
GATE (Pin 19): High Side Gate Drive for the External 3.3V  
and 5V N-Channel Power Transistors. An external series  
RC network is required for the current limit loop compen-  
sation and to set the maximum ramp-up rate. During  
power-up, the slope of the voltage rise at the GATE pin is  
setbythe65µAcurrentsourcechargingtheexternalGATE  
capacitor or by the 3.3V or 5V current limit and the  
associatedoutputcapacitor.Duringpower-down,a200µA  
current source pulls the GATE pin to GND.  
3VOUT (Pin 24): 3.3V Output Sense. The PWRGD pin  
cannot pull low until the 3VOUT pin voltage exceeds 2.9V.  
If no 3.3V input supply is available, tie the 3VOUT pin to the  
5VOUT pin. When the power switches are turned off, a  
150Ω resistor pulls 3VOUT to ground.  
VEEOUT (Pin 25): –12V Supply Output. An internal 1Ω  
switch is connected between VEEIN and VEEOUT. VEEOUT  
must exceed –10.5V before the PWRGD pin pulls low.  
When the power switches are turned off, a 650Ω resistor  
pulls VEEOUT to ground.  
The voltage at the GATE pin will be modulated to maintain  
a constant current when either the 3.3V or 5V supply goes  
intocurrentlimitandtheTIMERpinislessthan5.5V.Once  
the TIMER pin is above 5.5V, and in the event of a current  
fault condition lasting for longer than 35µs, the GATE pin  
is immediately pulled to GND.  
12VOUT (Pin 26): 12V Supply Output. A 0.5Ω switch is  
connected between 12VIN and 12VOUT. 12VOUT must  
exceed 11.1V before the PWRGD pin can pull low. When  
the power switches are turned off, a 430Ω resistor pulls  
12VOUT to ground.  
5VSENSE (Pin20):5VCurrentLimitSense.Asenseresistor  
placed between 5VIN and 5VSENSE determines the current  
limit for this supply. A foldback current feature makes the  
current limit decrease as the voltage at the 5VOUT pin  
approaches 0V. To disable the current limit, 5VSENSE and  
5VIN must be tied together.  
RESETIN (Pin 27): PCI Reset Input. Connect the CPCI  
PCI_RST#signaltotheRESETINpin.PullingRESETINlow  
will cause RESETOUT to pull low. Note that the I2C  
RESETIN latch output can also set RESETOUT. Do not  
float.  
5VIN (Pin 21): 5V Supply Sense Input. An undervoltage  
lockout circuit prevents the switches from turning on  
when the voltage at the 5VIN pin is less than 4.3V. At least  
onelongpinmustbeconnectedto5VINtoensureprecharge  
output. See Input Transient Protection section.  
OFF/ON (Pin 28): OFF/ON Input. Connect the CPCI  
BD_SEL# signal to the OFF/ON pin. When the OFF/ON pin  
ispulledlow, theGATEpinispulledhighbya65µAcurrent  
source and the internal 12V and –12V switches are turned  
on. When the OFF/ON pin is pulled high, the GATE pin will  
bepulledtogroundbya200µAcurrentsourceandthe12V  
and –12V switches turn off.  
3VIN (Pin 22): 3.3V Supply Sense Input. An undervoltage  
lockout circuit prevents the switches from turning on  
when the voltage at the 3VIN pin is less than 2.45V. If no  
3.3V input supply is available, connect two series diodes  
between 5VIN and 3VIN (tie anode of first diode to 5VIN and  
cathode of second diode to 3VIN, Figure 15). At least one  
Cycling the OFF/ON pin high and low will reset a tripped  
circuit breaker and start a new power-up sequence. The  
I2C OFF/ON latch output can also be used to reset the  
electronic circuit breaker. Do not float.  
4240f  
9
LTC4240  
W
BLOCK DIAGRA  
5V  
IN  
5V  
3V  
3V  
3V  
5V  
6
SENSE  
SENSE  
IN  
OUT  
24  
OUT  
GATE  
19  
21  
20  
23  
22  
5V  
OUT  
3V  
OUT  
12V  
in  
65mV,  
70mV,  
65µA  
Q2  
Q3  
TIMER LO  
165mV,  
+–  
+
+
+ – TIMER LO  
165mV,  
A1  
TIMER HI  
A2  
TIMER HI  
+–  
+ –  
–
–
1.2V  
Q1  
200µA  
1.2V  
–
+
+
–
+
+
–
CP3  
CP4  
CP2  
CP1  
55mV  
55mV  
+–  
+ –  
–
V
CB  
V
CB  
2.45V  
UVL  
4.3V  
UVL  
12 SDA  
Q4  
OFF/ON 28  
13  
11  
2
SCL  
FAULT  
7
ADDRIN  
PRSNT2#  
PRSNT1#  
Q13  
1
LOGIC  
PWRGD  
8
BE  
9
DGND  
16  
Q12  
RESETIN 27  
15 LED  
Q5  
Q6  
Q8  
Q11  
12V  
8V  
UVL  
IN  
14 RESETOUT  
1.2V  
Q10  
11.5µA  
Q14  
1V  
+
–
+
–
–
+
Q9  
Q7  
CP6  
CP5  
A3  
–9V  
UVL  
1.2V  
4240 BD  
3
26  
12V  
5
4
25  
10  
GND  
17  
DRIVE  
18  
PRECHARGE  
12V  
TIMER  
V
V
EEOUT  
IN  
OUT  
EEIN  
4240f  
10  
LTC4240  
W U U  
APPLICATIO S I FOR ATIO  
U
The LTC4240 is a Hot Swap controller that allows a board  
to be safely inserted and removed from a CompactPCI bus  
slot. The LTC4240 has built-in 2-wire I2C compatible  
interface hardware to allow software control and monitor-  
ing of device function and power supply status.  
• Adjustable 5Vand3.3Vcircuitbreakers:ifeithersupply  
exceeds current limit for more than 35µs, the circuit  
breaker will trip, the supplies will be turned off and the  
FAULTpinwillbepulledlow. Inaddition, ananalogloop  
willservotheGATEpintolimitthecurrenttothreetimes  
circuit breaker limit during transient conditions.  
• I2C interface: software control allows user to both write  
to and read from the device. The user can turn the  
device off and on, set the status LED, set RESETOUT  
anddisablefaultson12VIN andVEEIN. Theusercanalso  
read the device status: FAULT, RESETIN, RESETOUT  
PWRGD, PRSNT1#, PRSNT2#, FAULTCODE0 and  
FAULTCODE1. If a fault occurs, the FAULTCODE bits  
identify which supply generated the fault.  
Hot Circuit Insertion  
When a circuit board is inserted into a live CompactPCI  
(CPCI) backplane slot, supply bypass capacitors on the  
board can draw huge supply transient currents from the  
CPCI backplane power bus. The transient currents can  
cause glitches on the power bus, thus causing other  
boards in the system to reset.  
TheLTC4240isdesignedtoturnaboard’ssupplyvoltages  
on and off in a controlled manner, allowing the board to be  
safely inserted or removed from a live CPCI slot without  
disturbing the system power supplies. The device also  
protects the supplies from shorts, precharges the bus I/O  
pins during insertion and extraction and monitors the  
supply voltages. The LTC4240 includes an I2C compatible  
interface, which allows software control of device func-  
tions.  
• Current limit during power-up: the supplies are allowed  
topower-upincurrentlimit.ThisallowstheLTC4240 to  
power-up boards with widely varying capacitive loads  
without tripping the circuit breaker. The maximum  
allowable power-up time is programmable using an  
external capacitor connected to the TIMER pin. See  
TIMER section  
• Internal 12V and –12V power switches.  
The LTC4240 is specifically designed for CPCI applica-  
tions where it resides on the plug-in board. For best  
results, a well bypassed backplane is recommended.  
• PWRGD output: indicates the voltage status of the four  
supply voltages.  
• PCI_RST# is combined with HEALTHY# and  
with the I2C RESETIN latch output to create  
LOCAL_PCI_RST# output. If HEALTHY# asserts,  
LOCAL_PCI_RST#isassertedindependentoftheother  
two inputs.  
LTC4240 Feature Summary  
• Allows safe board insertion and removal from a CPCI  
backplane. Status LED visually identifies when a board  
is ready for removal.  
• Controls all four CPCI supplies: –12V, 12V, 3.3V and  
5V.  
• Precharge output: an internal reference and amplifier  
provide 1V for biasing bus I/O connector pins during  
CPCI card insertion and extraction.  
• Foldback current limit: An analog current limit with a  
value that depends on the output voltage. If the output  
is shorted to ground, the current limit drops to keep  
power dissipation and supply glitches to a minimum.  
• Space saving 28-pin SSOP package.  
I2C Interface  
TheLTC4240incorporatesanI2Ccompatible2-wire(clock  
and data) interface that allows the user to easily query and  
control the status of the LTC4240. A single analog input  
pin selects 1 of 32 allowed addresses. The I2C bus can be  
• 12V and –12V circuit breakers: if either supply remains  
in current limit for more than 35µs, the circuit breaker  
will trip, the supplies will turn off and the FAULT pin  
pulls low.  
4240f  
11  
LTC4240  
W U U  
U
APPLICATIO S I FOR ATIO  
Table 1. Suggested ADDRIN 1% Resistor Values  
used to turn off/on the power switches, turn on the status  
LED (alerting the user that its safe to remove the plug-in  
board), and assert the LOCAL_PCI_RST# signal. The I2C  
bus is also used to read the logic signals of several device  
pins: FAULT, PWRGD, RESETIN, and RESETOUT. Addi-  
tionally, when a supply generates a current fault, the I2C  
bus can be used to determine which supply generated the  
fault. See Send Byte and Receive Byte sections for a full  
description of all I2C features.  
ADDR RECOMMENDED ALLOWED ADDRIN  
R
R
20(BOT)  
19(TOP)  
CODE ADDRIN VOLTAGE VOLTAGE RANGE RESISTOR RESISTOR  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
0.108125  
0.264375  
0.420625  
0.576875  
0.733125  
0.889375  
1.045625  
1.201875  
1.358125  
1.514375  
1.670625  
1.826875  
1.983125  
2.139375  
2.295625  
2.451875  
2.608125  
2.764375  
2.920625  
3.076875  
3.233125  
3.389375  
3.545625  
3.701875  
3.858125  
4.014375  
4.170625  
4.326875  
4.483125  
4.639375  
4.795625  
4.951875  
0.080 to 0.136  
0.236 to 0.293  
0.393 to 0.449  
0.549 to 0.605  
0.705 to 0.761  
0.861 to 0.918  
1.018 to 1.074  
1.174 to 1.230  
1.330 to 1.386  
1.486 to 1.543  
1.643 to 1.699  
1.799 to 1.860  
1.955 to 2.021  
2.111 to 2.175  
2.268 to 2.330  
2.424 to 2.488  
2.580 to 2.644  
2.736 to 2.800  
2.888 to 2.950  
3.044 to 3.110  
3.200 to 3.262  
3.356 to 3.421  
3.513 to 3.574  
3.669 to 3.731  
3.825 to 3.886  
3.981 to 4.041  
4.138 to 4.190  
4.294 to 4.349  
4.450 to 4.499  
4.606 to 4.651  
4.763 to 4.805  
4.919 to 4.962  
8660  
2550  
2550  
2550  
2550  
2550  
3830  
2550  
2550  
1150  
1020  
8660  
2550  
2550  
1130  
1370  
2550  
2550  
2550  
715  
191  
140  
237  
332  
442  
549  
1020  
806  
The LTC4240 supports Send Byte and Receive Byte proto-  
cols. Communication is achieved using the SCL and SDA  
pins (TTL compatible input thresholds). The SCL pin is the  
clockinputfromtheI2Cbus(host)totheLTC4240(slave).  
The maximum SCL frequency is 100kHz. SDA is the  
bidirectionaldatatransferlinebetweentheI2Cbusandthe  
LTC4240. Send Byte and Receive Byte protocols are both  
comprised of 2 bytes. The first byte for both is the address  
byte. All communication begins with a START command.  
953  
499  
511  
4990  
1690  
1910  
1130  
1330  
2800  
3160  
3570  
1150  
2100  
2430  
2800  
1020  
8660  
1020  
5360  
1150  
1150  
1300  
2430  
10000  
Programming the I2C Address  
The voltage on the ADDRIN pin determines the I2C ad-  
dress. The ADDRIN voltage is set externally with a resistor  
divider from 5VIN to ground (resistor placement must be  
close to the pin, do not place a bypass capacitor on  
ADDRIN). This voltage is fed to a 5-bit A/D and compared  
against the address byte clocked in by the I2C bus. The 5-  
bitA/Dallows32uniqueLTC4240devicestobeconnected  
on the same I2C bus. 1% resistors should be used to place  
the voltage at ADDRIN approximately 0.5 LSB away from  
each code transition. Table 1 shows recommended resis-  
tor values for each of the address code segments. The  
resistor ratio for each code segment has been optimized  
forbestperformanceoverthespecifiedtemperaturerange.  
The parallel resistance for the address setting resistors  
should be kept under 10k.  
1150  
1150  
1150  
357  
2550  
249  
1070  
178  
133  
102  
105  
100  
4240f  
12  
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START and STOP Commands  
to acknowledge when there has been an address match.  
The only time the LTC4240 writes data onto the SDA bus  
during a send byte is to acknowledge the address and  
command bytes. The first 8 bits are referred to collectively  
as the address byte.  
The START command is defined as a high to low transition  
of the SDA line while the SCL line is high. It is an asynchro-  
nous event issued by the host, waking up all slave devices  
andalertingthemthataslaveaddressisbeingwrittenonto  
thebus.Onlytheslavedevicethatmatchestheaddresswill The command byte follows the address byte. The  
communicate with the host. The STOP command is de- command byte contains the information sent from the  
fined as a low to high transition on the SDA line while SCL hosttotheLTC4240. AftertheLTC4240acknowledgesthe  
is high. It is also an asynchronous event issued by the host address byte, each of the next 8 SCL rising edges shifts  
to signal the termination of the data transfer. Other than SDAfromthehostintoa shiftregisterinsidetheLTC4240.  
START and STOP commands, the SDA line is allowed to Thefirst2bitsclockedintotheshiftregister(2MSBsofthe  
change states only when SCL is low.  
command latch) are not used by the LTC4240. Only the 6  
LSBs are stored in the command latch on the falling edge  
of the 8th clock during the command byte. The output of  
the command latch remains fixed until the next Send Byte  
command overwrites it. Note that if power is turned off  
(5VIN <2V), thecommandanddatalatcheswillbecleared.  
Figure 1 shows the timing diagram of the entire send byte  
protocol. TransmissionendswhenthehostissuesaSTOP  
command.Table2definesthefunctionsofthe6command  
bits.Notethatsomeofthesefunctionscanoverride,orcan  
be overridden by, other circuitry and pins of the LTC4240.  
Figure 2 shows the relationship between bits C1 to C3 and  
other LTC4240 signals.  
Address Byte  
Once the LTC4240 has detected a START command, it  
clocks in the SDA line on the succeeding 9 SCL rising  
edges. The first 7 bits clocked in contain the address of the  
slave device targeted by the host. The first (MSB) address  
bit must be set to low and the second bit must be set to  
high. The next 5 bits are fed into a digital comparator and  
compared against the output of an internal 5-bit A/D. If the  
comparison is true, then there is an address match and the  
LTC4240 continues to communicate with the host device.  
TheLTC4240proceedstoacknowledgetheaddressmatch  
bypullingtheSDAlinelowwhileSCLislow, justbeforethe  
9th SCL rising edge. Figures 1 and 3 show a timing  
Receive Byte Protocol  
diagram of the START condition and address byte for both The Receive Byte protocol is used by the host to read data  
the Send Byte and Receive Byte protocols. Note that the from the LTC4240 data latch. This protocol begins with a  
SDA bit clocked in with the 8th SCL edge determines START command, issued by the host, followed by 7  
whether the host is sending or receiving information to/ address bits. The address bits are followed by the R/W bit,  
from the LTC4240.  
which is high for Receive Byte. The 9th bit is used by the  
LTC4240toacknowledgewhenthereisanaddressmatch.  
Send Byte Protocol  
The data byte then follows the address byte. This byte  
contains LTC4240 status information. After the LTC4240  
acknowledgestheaddressbyte, itshifts8bitsofdataonto  
theSDAline.Figure3showstheentireReceiveBytetiming  
diagram. Note that neither the host or the slave acknowl-  
edges the data byte (SDA line stays high during 9th clock  
edge of the data byte).  
The Send Byte protocol allows a host to write information  
into the LTC4240 and command the LTC4240 to perform  
certain predetermined functions. The host initiates com-  
munication with a START bit followed by 7 address bits.  
The address bits are followed by the R/W bit, which is low  
for Send Byte. The 9th bit is asserted low by the LTC4240  
4240f  
13  
LTC4240  
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LATCH  
COMMAND BYTE  
ADDRESS BYTE  
COMMAND BYTE  
SCL  
SDA  
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
STOP  
START  
0
1
R/WR=0  
XX  
XX  
C5  
C4  
C3  
C2  
C1  
XX  
ADDR 4 ADDR 3 ADDR 2 ADDR 1 ADDR 0  
ACK  
ACK  
4240 F01  
Figure 1. Send Byte Protocol  
Table 2. Command Byte Definitions  
HIGH  
LOW  
POWER-UP STATE  
C7  
C6  
C5  
C4  
C3  
C2  
Don’t care  
Don’t care  
Don’t care  
Don’t care  
N/A  
N/A  
Ignore V  
faults  
faults  
Don’t ignore V  
faults  
faults  
LOW  
LOW  
LOW  
LOW  
EEOUT  
EEOUT  
Ignore 12V  
Don’t ignore 12V  
OUT  
OUT  
Sets RESETOUT  
Does not set RESETOUT low  
Turns OFF/ON to OFF  
Overrides OFF/ON pin  
Does not set OFF/ON  
Does not override OFF/ON pin  
C1  
C0  
Turns on LED open drain  
Don’t care  
Does not turn on LED open drain  
Don’t care  
LOW  
N/A  
LED  
RESETOUT  
GATE  
C3  
C2  
C1  
RESETIN  
PWRGD  
OFF/ON  
RESETOUT  
C2 PULLS DOWN THE GATE OF THE  
EXTERNAL N-CHANNEL SWITCHES. IT  
C3 IS USED TO SET  
LOCAL_PCI_RST# (RESETOUT).  
C1 TURNS ON THE EXTERNAL STATUS  
LED INDEPENDENT OF RESETOUT.  
ALSO TURNS OFF THE 12V AND V  
IN  
EEIN  
4240 F02  
INTERNAL POWER SWITCHES.  
Figure 2. Send Byte Command Latch and Logic  
4240f  
14  
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Table 3 shows the definition for each data bit. PWRGD,  
FAULT, RESETIN, and RESETOUT external pins can be  
monitored. PRSNT1# and PRSNT2# are PCI signals that  
provide information on the power requirements of the  
board. Refer to PCI local bus specifications for a detailed  
description. FAULTCODE1 and FAULTCODE0 are two in-  
ternal binary encoded signals that, along with FAULT,  
indicate which of the four supplies generated a fault. Note  
that the FAULTCODE signals are valid only when FAULT  
has been asserted low. See Table 4 for description.  
to the LTC4240 before back-end power is allowed to ramp  
(BD_SEL# asserted low). The long pins, which include 5V,  
3.3V, V(I/O) and GND mate first. The short pins, which  
includes BD_SEL# (OFF/ON), mate last. At least one long  
5V power pin must be connected to the LTC4240 in order  
for the PRECHARGE voltage to be available during Early  
Power. The external components connected to the  
precharge pin require long 3.3V.  
The following is a typical hot plug sequence:  
1. ESD clips make contact.  
Status LED  
2. Long power and ground pins make contact and Early  
Power is established (see Early Power section). The 1V  
PRECHARGEvoltagebecomesvalidatthisstage.Power  
is applied to the pull-up resistors connected to FAULT,  
PWRGD and OFF/ON pins. The status LED is lit, indicat-  
ing that the plug-in board is in the process of being  
connected (LOCAL_PCI_RST# is asserted). All power  
switches are off.  
The main function of the LED is to alert the user when it is  
permissible to physically extract the board. The LED  
output of the LTC4240 is an open drain N-channel device  
capable of sinking 10mA from an externally connected  
LED. This LED lights up when RESETOUT  
(LOCAL_PCI_RST#)isasserted.UponapplicationofEarly  
Power, the long 5V pins will power up the LTC4240 and  
light up the Status LED. It will remain on until PWRGD  
(HEALTHY#) is asserted and RESETIN (PCI_RST#) is de-  
asserted,andtheboardentersnormaloperation.Notethat  
this LED can also be turned on via the I2C 2-wire interface.  
3. Mediumlengthpinsmakecontact. Therearesix 5Vand  
eight 3.3V medium length power pins, bringing the 5V  
total to 8 pins and the 3.3V total to 10 pins. The  
maximum DC current for the 3.3V and 5V supplies is  
10A and 8A, respectively. The I2C command latch is  
initialized to allow seamless CPCI Hot Swap operation.  
The LTC4240 can be used as a Hot Swap controller  
without ever establishing I2C communication. Both  
FAULTandPWRGDcontinuetobepulleduphighatthis  
CPCI Connection Pin Sequence  
The staggered length of the CPCI male connector pins  
ensures that all power supplies are physically connected  
Table 3. STATUS Byte Definitions  
S7  
S6  
S5  
S4  
S3  
S2  
S1  
S0  
Logic state of the PRSNT2# pin  
Logic state of the PRSNT1# pin  
Logic state of the PWRGD pin  
Logic state of the RESETOUT pin  
Logic state of the RESETIN pin  
FAULTCODE1 (see Table 4)  
FAULTCODE0 (see Table 4)  
Logic state of the FAULT pin  
Table 4. FAULTCODE Encoding Description for Receive Byte  
FAULTCODE0 FAULTCODE1  
FAULT  
LO  
Supply Causing Fault  
LO  
LO  
HI  
HI  
X
LO  
HI  
LO  
HI  
X
3V  
IN  
LO  
5V  
IN  
LO  
12V  
IN  
LO  
V
EEIN  
HI  
None  
ADDRESS BYTE  
DATA BYTE  
SCL  
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
STOP  
START  
0
1
R/WR=1  
S7  
S6  
S5  
S4  
S3  
S2  
S1  
S0  
ADDR 4 ADDR 3 ADDR 2 ADDR 1 ADDR 0  
SDA  
ACK  
ACK  
4240 F03  
Figure 3. Receive Byte Protocol  
4240f  
15  
LTC4240  
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A high to low transition on BD_SEL# causes the voltages  
on the TIMER, GATE, 3VOUT, 5VOUT, 12VOUT and VEEOUT  
pins to begin ramping (see Figure 4). The TIMER pin  
capacitance is charged by an 11.5µA current source while  
theGATEcapacitanceischargedbya65µAcurrentsource.  
Concurrently, an internal charge pump turns on the gates  
of the internal power switches that isolate the 12V and  
–12V supplies. All faults are ignored during the time that  
the voltage at the TIMER pin remains below 5.5V. In order  
to avoid faults due to the charging of the bulk output  
capacitors, all output voltages must settle before the  
TIMER pin reaches 5.5V. See TIMER section for more  
details.  
stage in the hot plug sequence, indicating that the  
LTC4240 is in reset mode with all power switches off  
(BD_SEL# is still pulled high to long 5V).  
The 12V and –12V supplies make contact at this stage.  
Zener clamps Z1 and Z2 plus shunt RC snubbers R13-  
C4 and R14-C5 help protect the 12VIN and VEEIN pins,  
respectively, from large transient voltages during hot  
insertion and short-circuit conditions.  
The signal pins also connect at this point. This includes  
the HEALTHY# signal connecting to the PWRGD pin  
and the PCI_RST# signal connecting to the RESETIN  
pin. The PWRGD and RESETIN signals are combined  
internally with Bit 3 (C3) of the I2C command latch (see  
Send Byte protocol) to generate the LOCAL_PCI_RST#  
signal, which is available at the RESETOUT pin.  
The 5VOUT and 3VOUT supply outputs will ramp up accord-  
ing to the slowest of the following slew rates:  
ILIMIT(5V)– ILOAD(5V)  
4. Short pins make contact. BD_SEL# signal connects to  
the OFF/ON pin. This starts the electrical part of the  
connection process. If the BD_SEL# signal is grounded  
on the backplane, then the electrical connection pro-  
cess starts immediately. Note that the electrical con-  
nection process can be interrupted with the Send Byte  
protocol of the I2C serial interface.  
dV 65µA  
=
,or =  
or =  
,
(1a)  
(1b)  
dt  
C1  
CLOAD(5VOUT)  
LIMIT(3V)– ILOAD(3V)  
CLOAD(3VOUT)  
I
TIMER  
10V/DIV  
System backplanes that do not ground the BD_SEL#  
signal will instead have circuitry that detects when  
BD_SEL# has made contact with the plug-in board. The  
backplane logic can then control the power up process  
by pulling BD_SEL# low. Figure 4 illustrates the power  
upsequence. ThematingofBD_SEL#isrepresentedby  
the high to low transition of the BD_SEL# signal.  
GATE  
10V/DIV  
12V  
OUT  
10V/DIV  
5V  
10V/DIV  
OUT  
3V  
OUT  
10V/DIV  
V
EEOUT  
10V/DIV  
BD_SEL#  
5V/DIV  
Power-Up Sequence  
Two external N-channel power MOSFETs isolate the 3.3V  
and 5V power paths, while two internal MOS switches  
isolate the 12V and –12V power paths. (See front page  
Application Circuit). Sense resistors R1 and R2 provide  
current limit and fault detection for the 3VIN and 5VIN  
supplies, while R5 and C1 provide current control loop  
compensation. Current fault detection for the 12V and  
–12V supplies is done internally.  
LCL_PCI_RST#  
5V/DIV  
HEALTHY#  
5V/DIV  
4240 F04  
10ms/DIV  
Figure 4. Normal Power-Up Sequence  
4240f  
16  
LTC4240  
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supply voltages. Internal switches are connected to each  
of the output supply voltage pins to discharge the output  
bulk capacitors to ground. When any one of the output  
voltagesdropsbelowitsPWRGDthreshold,theHEALTHY#  
signal pulls high, LOCAL_PCI_RST# (RESETOUT) is as-  
serted low, and the external status LED turns on.  
Note that capacitor C1 performs dual functions. In addi-  
tion to controlling the ramp up rates of the 5V and 3.3V  
outputs, it also compensates the current limit loop.  
Current limit faults are ignored while the TIMER voltage is  
less than 5.5V.  
Onceallfoursuppliesarewithintolerance,thePWRGDpin  
(HEALTHY#) will be pulled low and LOCAL_PCI_RESET#  
(RESETOUT) is free to follow PCI_RST#. Bit 3 of the I2C  
command latch powers up low, thus not asserting  
LOCAL_PCI_RST#.  
Once the power-down sequence is complete the status  
LED will light up and the CPCI card may be removed from  
the slot. During extraction, the precharge circuit will  
continue to bias the bus I/O pins at 1V until the long  
connector pin connections are broken.  
Power-Down Sequence  
Early Power  
When either BD_SEL# (OFF/ON) or Bit 2 of the command  
latch (C2) is set high, a power-down sequence begins  
(Figure 5).  
Early Power usage is restricted by the CompactPCI (CPCI)  
specification. It is intended to power up the precharge  
circuit and I/O cells. The CPCI specification allows any of  
the long power pins (5V, 3.3V, V(I/O)) to be used for Early  
Power. Since Early Power is not isolated, a resistor should  
beplacedinserieswitheachCPCIconnectorpin.Notethat  
if any Early Power pin is shorted on the inserted card, the  
current limiting resistor will dissipate the power.  
The TIMER pin is immediately pulled low. The GATE pin  
(Pin 19) is pulled down by a 200µA current source to  
preventtheloadcurrentsonthe3.3Vand5Vsuppliesfrom  
going to zero instantaneously and glitching the power  
TIMER  
10V/DIV  
In order to maximize the DC current available from the 5V  
supply, all eight 5V connector pins should be tied together  
ontheinsertedcard.Thesameappliestotheten3.3VCPCI  
connector pins. Early Power should then be drawn from  
either or both of the two V(I/O) long pins. If either or both  
of 5V and 3.3V is used for Early Power, then the 5V and  
3.3V sense resistor values must be chosen such that the  
1A/pin CPCI rule is not violated.  
GATE  
10V/DIV  
12V  
OUT  
10V/DIV  
5V  
OUT  
10V/DIV  
3V  
OUT  
10V/DIV  
V
EEOUT  
10V/DIV  
BD_SEL#  
5V/DIV  
Connecting VEEIN  
Tolessenthelikelihoodoffaultingonpowerup, theVEEOUT  
output pin should be bypassed with a capacitor that is only  
as large as necessary. A value of 10µF to 47µF is recom-  
mended. If a large value bypass capacitor is used (e.g.  
≥100µF) on VEEOUT, current limit faults may occur during  
power-up or during recovery from power failures.  
LCL_PCI_RST#  
5V/DIV  
HEALTHY#  
5V/DIV  
4240 F05  
10ms/DIV  
Figure 5. Normal Power-Down Sequence  
4240f  
17  
LTC4240  
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switches will be latched off and the FAULT pin (Pin 7) will  
be pulled low. Since there is no automatic retry, power will  
have to be cycled with the OFF/ON pin or the I2C command  
latch.  
Timer  
During a power-up sequence, an 11.5µA current source is  
connected to the TIMER pin (Pin 5) and charges up the  
external TIMER pin capacitor. Current limit faults are  
ignoreduntiltheTIMERvoltagerampsto5.5V.Thisfeature  
allows the LTC4240 to power-up CPCI boards with widely  
varying capacitive loads on the back end supplies. The  
power-up time for either of the two outputs under current  
limit conditions is given by the slower of:  
Short-Circuit Protection  
In order to lower power dissipation in the pass transistors  
and to mitigate voltage spikes on the supplies during  
short-circuit conditions, the current limit on each supply  
is designed to be a function of the output voltage. As the  
output voltage drops, the current limit decreases. Unlike a  
traditional circuit breaker function where huge currents  
can flow before the breaker trips, the current foldback  
feature lowers short-circuit current by at least 50% when  
powering up into a short.  
C
LOAD(XVOUT) • XVOUT  
tON(XVOUT ) = 2•  
or (2a)  
(2b)  
I
LIMIT(XVOUT) – ILOAD(XVOUT)  
C1(XVOUT + VTH)  
65µA  
tON(GATE) =  
If any supply is in current limit after the TIMER pin voltage  
has ramped to 5.5V, then all four pass transistors will be  
immediately turned off and FAULT will be asserted low  
(Figure 6).  
Where XVOUT = 5VOUT or 3VOUT. The timer period should  
be set longer than the maximum supply turn-on time but  
short enough to not exceed the maximum safe operating  
areaofthepasstransistorduringashort-circuit. VTH isthe  
threshold voltage of the external power FET (2V – 3V). The  
timer period will be:  
TIMER  
5V/DIV  
C
TIMER • 5.5V  
11.5µA  
GATE  
5V/DIV  
tTIMER  
=
(3)  
12V  
OUT  
10V/DIV  
5V  
10V/DIV  
OUT  
The TIMER pin is immediately pulled low when either  
OFF/ON(Pin28)orBit2ofcommandlatch(C2) goeshigh.  
3V  
OUT  
10V/DIV  
V
EEOUT  
The TIMER pin also functions as a temporary auxiliary  
supply for 12VIN. In the event of a large (greater than 1V)  
glitch on 12VIN, the energy stored on the timer capacitor  
is used as substitute 12VIN power. This improves the  
glitch immunity of the LTC4240.  
10V/DIV  
BD_SEL#  
5V/DIV  
FAULT  
5V/DIV  
Thermal Shutdown  
4240 F06  
10ms/DIV  
The internal switches for the 12V and –12V supplies are  
protected by current limit and thermal shutdown circuits.  
When the temperature of the die reaches 150°C, all four  
Figure 6. Power-Up into a Short on 3.3V Output  
4240f  
18  
LTC4240  
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The current limit and the foldback current level for the 5V  
and 3.3V outputs are both a function of the external sense  
resistor (R1 for 3VOUT and R2 for 5VOUT, see front page).  
A sense resistor is connected between 5VIN (Pin 21) and  
5VSENSE (Pin 20) for the 5V supply. For the 3.3V supply, a  
sense resistor is connected between 3VIN (Pin 22) and  
3VSENSE (Pin23).Thecurrentlimitandthecurrentfoldback  
current level are given by Equations 4 and 5:  
Once the TIMER voltage has reached 5.5V, all of the  
supplies will be latched off if any supply enters current  
limit for at least 35µs. The 35µs delay prevents quick  
current spikes—for example, from a fan turning on—  
from causing false trips of the circuit breaker.  
During normal operation, the 5V and 3.3V supplies are  
protected from overcurrent and short-circuit conditions  
by dual-level circuit breakers. In the event that either  
supplycurrent exceedsthenominallimit, aninternaltimer  
is started. If the supply is still overcurrent after 35µs, the  
circuit breaker trips and all the supplies are turned off  
(Figure 7). If a short-circuit occurs on 5VOUT or 3VOUT and  
the supply current exceeds three times the set limit, an  
analog loop will limit the current to 3 times the value set  
by RSENSE and 55mV. If the short persists for more than  
35µs, the LTC4240 latches off (Figure 8). It will stay in the  
latched off state until it is reset using the OFF/ON pin or by  
using the I2C interface. The LTC4240 can also be reset by  
cycling any of the power supplies.  
55mV  
RSENSE(XVOUT)  
11mV  
ILIMIT(XVOUT)  
=
(4)  
(5)  
IFOLDBACK(XVOUT)  
=
RSENSE(XVOUT)  
where XVOUT = 5VOUT or 3VOUT  
.
Equation 4 is the current limit for XVOUT ≈ XVIN. Equation  
5 shows the ILIMIT for shorted outputs. Both equations  
assume voltage on TIMER pin is greater than 5.5V.  
XVOUT = 3VOUT or 5VOUT. Note that since there are only 8  
pins connecting 5VIN, RSENSE ≥ 0.007Ω for 5VIN.  
5V –5V  
IN  
SENSE  
100mV/DIV  
The current limit for the internal 12V switch is set at  
–1200mA folding back to –350mA and the –12V switch at  
500mA folding back to 250mA.  
GATE  
5V/DIV  
Selecting RSENSE  
FAULT  
5V/DIV  
An equivalent circuit for the 5V and 3.3V circuit breakers  
is shown in Figure 9. The sense resistor and the circuit  
breaker threshold voltage determine the fault current that  
turns off the external FETs. Sense resistors with a 1%  
tolerance are recommended. Due to part to part and  
temperature variations for both the sense resistor value  
and the circuit breaker threshold voltage, the actual cur-  
rent limit threshold will exhibit some variation. To calcu-  
late the smallest value of current that will trip the fault  
comparator, usethelargestvalueofthesenseresistorand  
the smallest value of the threshold voltage. A 0.005Ω 1%  
sense resistor (on the 3.3V supply, for example) with  
typical temperature coefficients would increase to ap-  
proximately0.0051Ω(nominalvaluemultipliedbythe1%  
tolerance and the TC at 70°C). Since the minimum value of  
the threshold voltage is 50mV, this implies a current limit  
of 9.8A. To arrive at the largest value of the current limit  
4240 F07  
20µs/DIV  
Figure 7. Overcurrent Fault on 5V  
5V –5V  
IN  
SENSE  
100mV/DIV  
GATE  
5V/DIV  
FAULT  
5V/DIV  
4240 F08  
20µs/DIV  
Figure 8. Short-Circuit Fault on 5V  
that will turn off the external FETs, the nominal value of the  
4240f  
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On Resistance  
sense resistor drops to 0.0049Ω and the largest value of  
threshold voltage increases to 60mV. This results in a trip  
current of 12.2A.  
The CompactPCI specification limits the total IR drop of  
the FET plus the IR drop of the sense resistor to 100mV.  
For a nominal sense resistor of 0.005Ω, if the user limits  
the 3.3V supply load current to 8.7A, then the maximum  
FET resistance should be less than 0.0063Ω. Similarly, for  
a 6.2A load current on the 5V supply and a 0.007Ω sense  
resistor, the maximum 5V FET resistance should be  
0.0088Ω. Note that above values of FET resistance are  
worst case over temperature (on the FET’s datasheet, find  
the resistance vs temperature curve and de-rate the room  
temperature maximum value).  
I
LOAD(MAX)  
R
SENSE  
5V  
IN  
21  
5V  
20  
5V  
SENSE  
IN  
+
V
CB  
LTC4240*  
–
–
+
V
V
V
= 60mV  
= 55mV  
= 50mV  
CB(MAX)  
CB(NOM)  
CB(MIN)  
*ADDITIONAL DETAILS  
OMITTED FOR CLARITY  
4240 F09  
Figure 9. Circuit Breaker Equivalent  
Circuit for Calculating RSENSE  
Breakdown Voltage  
The maximum DC voltage that can appear across the  
drain/sourceoftheexternalpowerFETis5V+10%.During  
transient events and hot swap conditions, parasitic induc-  
tances could cause ringing up to 3 times the supply  
voltage. Theuseofvoltagetransientsuppressorsatthe5V  
and 3.3V inputs can limit these voltage swings to less than  
10V (see front page schematic). Similarly, the largest DC  
voltage that is likely to appear across the gate is 12V  
+10%. Voltage suppressors on the 12VIN node will also  
limit the transient spikes on that node. Additionally, the  
total capacitance on the GATE node will serve to filter fast  
voltage noise spikes. FETs with a minimum rating of ±20V  
on both the drain/source and the gate/source are recom-  
mended.  
Plug-inboarddesignersarethuslimitedtousinglessthan  
9.8A when a nominal 0.005Ω resistor is used. Using more  
than 9.8A runs the risk of turning off the external FET.  
Since the CompactPCI specification allows a maximum  
1A/pin, at least 10 pins must be used to supply 9.8A. This  
implies that only the 3.3V supply can use a 0.005Ω  
resistor, since the 5V supply has a maximum of 8 pins  
available. To adhere to the 1A/pin specification, the 5V  
sense resistor should be larger than the 3.3V sense  
resistor. Typical applications show a nominal 0.007Ω  
resistor, which results in a 7.04A maximum deliverable  
current to the plug-in board loads. The 7.04A current  
implies at least 7 pins on the 5V connector. Note that the  
thermal considerations of the external FET will also place  
limitations on the maximum allowable current.  
Steady State Power Dissipation  
For a user selected maximum load current of 8.7A on the  
3.3V power supply and a 0.0063Ω maximum FET resis-  
tance, the DC power dissipation is:  
5V and 3.3V External FET Selection  
The LTC4240 uses external power FETs to limit and  
modulate the current delivered by the 3.3V and 5V sup-  
plies. There are several parameters to consider when  
selecting the FET:  
(IMAX)2(RDSON,MAX) = (8.7)(8.7)(0.0063) = 0.477W  
This is within the SOA limits of most power FETs.  
1. On resistance.  
2. Gate and drain breakdown voltage.  
3. Steady state and transient power dissipation.  
4240f  
20  
LTC4240  
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APPLICATIO S I FOR ATIO  
Transient Power Dissipation  
When the LTC4240 is turned on and the large 5VOUT  
output capacitor (2000µF or more) is charged, it is pos-  
sible that the 5V FET will dissipate as much as the 35.1W  
described above. If there is no DC load at 5VOUT, then 8.8A  
will charge the 2000µF in less than 2ms, which should not  
pose any thermal problems for the Si7880DP. If the DC  
load at 5VOUT approaches the current limit, then the above  
analysis should be used to calculate the internal junction  
temperature of the FET.  
There are certain transient events that can significantly  
increase the power dissipated by the external FET. If the  
LTC4240 5V supply (at 5V + 10%) powers up into a 1.5V  
short (potentially manifested as a short to two diodes in  
series), then the FET can potentially have 4V across it with  
8.8A flowing. This implies a power dissipation of 35.1W.  
The amount of time the FET will dissipate 35.1W will  
depend on the relative values of the TIMER and GATE  
capacitances. For the values specified on the front page  
application circuit, the GATE pin will ramp high signifi-  
cantly faster than the TIMER pin, hence transient power  
dissipation will be set by the TIMER pin capacitance.  
Output Voltage Monitor  
The DC level of all four supply outputs is monitored by the  
powergoodcircuitry. Whenanyofthefoursupplyoutputs  
falls below its specified level (see DC electrical specifica-  
tions) for longer than 10µs, the PWRGD (HEALTHY#)  
opendrainpinwillbedeassertedandtheLOCAL_PCI_RST#  
signal will be asserted low. This does not generate a fault  
condition.  
The dissipated 35.1W, the ramp time of the TIMER pin  
(50ms will be used for this example), and the FET thermal  
resistance will determine the internal junction tempera-  
ture of the FET. Most FETs will specify a maximum internal  
junctiontemperatureof150°C.TheFETdatasheetsshould  
have a transient thermal impedance graph. This graph has  
a family of curves listing the FET transient thermal imped-  
ance as a function of duty cycle. The duty cycle refers to  
what percentage of the time the FET is in the short circuit  
condition. If we choose the Si7880DP FET and assume  
that the board on which the FET is placed has minimal heat  
sinking capability, and further assume that the user will  
turn on the board every 2.5 seconds (0.02 duty cycle:  
50ms on, 2450ms off), then by looking at the junction-to-  
ambient curve we note that with a 70°C ambient tempera-  
ture, the Si7880DP internal junction temperature will be  
172°C. This is above the absolute maximum rating of the  
FET, and although operating at this temperature will not  
damage the FET immediately, it does affect its long term  
reliability. Conversely, if we assume that there is a perfect  
heatsinkfortheSi7880DPpackage,thenwewouldusethe  
junction-to-case curve and calculate a value of 117°C with  
a 70°C ambient temperature. The Si7880DP comes in a  
thermally enhanced package whose drain lead is a large  
pieceofmetalthatcanconductheatawayfromtheinternal  
junctionoftheFET.Toachievebestperformance,thedrain  
of the Si7880DP should be connected to a piece of copper  
(as large as possible) on the board. Note that if the output  
is shorted to ground, the current foldback feature will cut  
the power dissipation by at least a factor of two.  
The LOCAL_PCI_RST# signal (RESETOUT pin) is derived  
from the HEALTHY# (PWRGD pin), PCI_RST# (RESETIN  
pin), and Bit 3 of the command latch (see Table 5).  
Table 5. LOCAL_PCI_RST# Truth Table  
Bit 3 (C3 )  
PCI_RST#  
HEALTHY#  
Command Latch  
LOCAL_PCI_RST#  
LO  
X
X
HI  
X
X
X
LO  
LO  
LO  
HI  
X
HI  
LO  
HI  
LO  
Precharge  
The PRECHARGE input and DRIVE output pins are used to  
generate the 1V precharge voltage that biases the bus I/O  
connector pins during board insertion and extraction  
(Figure 10). The LTC4240 is capable of generating  
precharge voltages other than 1V. Figure 11 shows a  
circuitthatcanbeusedinapplicationsrequiringaprecharge  
voltage less than 1V. The circuit in Figure 12 can be used  
for applications that need precharge voltages greater than  
1V. Table 6 lists suggested resistor values for R11A and  
R11B vs precharge voltage for the application circuits  
shown in Figures 11 and 12.  
4240f  
21  
LTC4240  
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APPLICATIO S I FOR ATIO  
Table 6. R1 and R2 Resistor Values vs Precharge Voltages  
Precharge resistors are used to connect the 1V bias  
voltagetotheCompactPCIconnectorI/Olines.Thisallows  
live insertion of the I/O lines with minimal disturbance.  
Figure 13 shows the precharge application circuit for 5V  
signaling environments. The precharge resistor require-  
mentsaremorestringentfor3.3VandUniversalHotSwap  
signaling. If the total leakage current on the I/O line is less  
V
R11A  
18Ω  
18Ω  
18Ω  
18Ω  
18Ω  
18Ω  
R11B  
9.09Ω  
7.15Ω  
5.36Ω  
3.65Ω  
1.78Ω  
0Ω  
V
R11A  
16.2Ω  
14.7Ω  
12.1Ω  
11Ω  
R11B  
1.78Ω  
3.65Ω  
5.11Ω  
7.15Ω  
9.09Ω  
PRECHARGE  
PRECHARGE  
1.5V  
1.4V  
1.3V  
1.2V  
1.1V  
1V  
0.9V  
0.8V  
0.7V  
0.6V  
0.5V  
9.09Ω  
CompactPCI CompactPCI  
BACKPLANE BACKPLANE  
CONNECTOR CONNECTOR  
(MALE)  
(FEMALE)  
5V  
IN 21  
5V  
MEDIUM 5V  
IN  
IN  
R22  
2.74Ω  
LTC4240*  
LONG 5V  
3.3V  
3V  
22  
IN  
3V  
R21  
1.74Ω  
GND  
10  
PRECHARGE  
18  
DRIVE  
17  
LONG 3.3V  
GROUND  
R8  
1k, 5%  
R9  
24Ω, 5%  
R11  
18Ω, 5%  
C3  
4.7nF  
3V  
Q3  
IN  
R7  
12Ω, 5%  
MMBT2222A  
PRECHARGE OUT  
R
10k  
5%  
R
10k  
5%  
PRE1  
PRE128  
1V ±20%  
R
I01  
I
= ±55mA  
OUT  
10Ω, 5%  
I/O  
I/O PIN 1  
PCI  
BRIDGE  
(21154)  
UP TO 128  
I/O LINES  
DATA BUS  
I/O  
I/O PIN 128  
R
I0128  
10Ω, 5%  
*ADDITIONAL DETAILS OMITTED FOR CLARITY  
4240 F10  
Figure 10. Precharge Application Circuit  
LTC4240*  
GND PRECHARGE  
LTC4240*  
DRIVE  
17  
GND  
10  
PRECHARGE  
18  
DRIVE  
17  
R8  
1k, 5%  
R8  
1k, 5%  
10  
18  
R9  
24Ω, 5%  
R9  
24Ω, 5%  
R7  
12Ω, 5%  
C3  
4.7nF  
C3  
4.7nF  
R7  
12Ω, 5%  
Q3  
Q3  
R11A  
R11B  
PRECHARGE OUT  
R11A  
R11B  
MMBT2222A  
MMBT2222A  
3V  
IN  
PRECHARGE OUT  
R11A  
• 1V  
3V  
IN  
R11A + R11B  
*ADDITIONAL DETAILS  
OMITTED FOR CLARITY 4240 F12  
*ADDITIONAL DETAILS  
OMITTED FOR CLARITY  
V
=
• 1V  
V
=
PRECHARGE  
PRECHARGE  
R11A  
4240 F11  
R11A + R11B  
Figure 11. Precharge Voltage Less Than 1V  
Figure 12. Precharge Voltage Greater Than 1V  
4240f  
22  
LTC4240  
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APPLICATIO S I FOR ATIO  
than 2µA, then a 50K resistor can be connected directly  
fromthe1VbiasvoltagetotheI/Oline. However, manyICs  
connected to the I/O lines can have leakage currents up to  
10µA. For these applications, a 10k resistor is used but  
must be disconnected when the board has been seated as  
determined by the state of the BD_SEL# signal. Figure 14  
shows a precharge circuit that uses a bus switch to  
connect the individual 10k precharge resistors to the  
LTC42401VPRECHARGEpin. Theelectricalconnectionis  
made (bus switches close) when the voltage on the  
BD_SEL# pin of the plug-in card is above 4.4V, which  
occurs just after the long pins have made contact. The bus  
switchesaresubsequentlyelectricallydisconnectedwhen  
the board connector makes contact with the BD_SEL# pin  
(bus switch OE pin is pulled high by Q4).  
CompactPCI CompactPCI  
BACKPLANE BACKPLANE  
CONNECTOR CONNECTOR  
(MALE)  
(FEMALE)  
5V  
IN  
21  
28  
5V  
IN  
MEDIUM 5V  
R22  
2.74Ω  
LTC4240*  
LONG 5V  
BD_SEL#  
R18  
1k, 5%  
OFF/ON  
GND  
R17  
1.2k  
5%  
PRECHARGE  
18  
DRIVE  
17  
R8  
1k, 5%  
Z4  
R9  
24Ω  
R11  
18Ω, 5%  
LONG  
5V  
C3, 4.7nF  
3V  
IN  
GROUND  
I/O PIN 1  
Q3  
R
PRECHARGE OUT  
R
R7  
R
I01  
PRE1  
10k  
5%  
PRE128  
10k  
5%  
MMBT2222A  
10Ω  
1V ±10%  
12Ω, 5%  
5%  
I
= ±55mA  
OUT  
I/O  
R
PCI  
BRIDGE  
CHIP  
I0128  
DATA BUS  
UP TO 128 I/O LINES  
10Ω  
5%  
I/O  
I/O PIN 128  
Z4: 1PMT5.0AT3  
*ADDITIONAL DETAILS OMITTED FOR CLARITY  
4240 F13  
Figure 13.Precharge Application Circuit for 5V Signaling Systems  
CompactPCI CompactPCI  
BACKPLANE BACKPLANE  
CONNECTOR CONNECTOR  
(MALE)  
(FEMALE)  
5V  
21  
28  
IN  
5V  
IN  
MEDIUM 5V  
R22  
2.74Ω  
R17  
1.2k  
5%  
LTC4240*  
LONG 5V  
BD_SEL#  
R18  
1k, 5%  
OFF/ON  
GND  
10  
PRECHARGE  
18  
DRIVE  
17  
R8  
1k, 5%  
Z4  
R9  
24Ω  
R11  
18Ω, 5%  
C3, 4.7nF  
3V  
GROUND  
IN  
Q3  
LONG  
5V  
R7  
R26  
51.1k, 5%  
MMBT2222A  
12Ω, 5%  
100Ω  
0.1µF  
Q4  
PRECHARGE OUT  
V
IN  
DD  
MMBT3906  
1V ±10%  
BUS SWITCH  
I
= ±55mA  
OE  
OUT  
R27  
75k  
5%  
OUT  
OUT  
R
R
10k  
5%  
I01  
R
10k  
5%  
PRE1  
PRE128  
10Ω  
5%  
I/O  
I/O  
I/O PIN 1  
R
PCI  
I0128  
DATA BUS  
UP TO 128 I/O LINES  
10Ω  
BRIDGE  
CHIP  
5%  
I/O PIN 128  
Z4: 1PMT5.0AT3  
*ADDITIONAL DETAILS OMITTED FOR CLARITY  
4240 F14  
Figure 14. Precharge Bus Switch Application Circuit for 3.3V and Universal Hot Swap Boards  
4240f  
23  
LTC4240  
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APPLICATIO S I FOR ATIO  
The assumption by the CompactPCI specification is that  
there is a diode to 3.3V on the circuit that is driving the  
BD_SEL#pin.The1.2kresistorpullupto5VIN ontheplug-  
in card will thus be clamped by the diode to 3.3V. If the  
BD_SEL#pinisbeingdrivenhigh,theactualvoltageonthe  
pin will be approximately 3.9V. This is still above the high  
TTLthresholdoftheLTC4240OFF/ONpin, butlowenough  
forQ4todisablethebusswitchesandthusremovethe10k  
resistors from the I/O lines. Note that BD_SEL# is ordi-  
narily connected to V(I/O), which in turn is allowed to be  
driven by either 3.3V or 5V. For applications such as  
shown in Figure 14, the pull up on BD_SEL# is restricted  
to the long 5V pins. A bus switch with no internal diode to  
VDD is preferred. Since the power to the bus switch is  
derived from one of the unswitched power planes, a 100Ω  
resistor plus a 0.1µF bypass capacitor should be placed in  
series with its power supply.  
PRSNT1#  
Open  
PRSNT2#  
Open  
Expansion Configuration  
No plug in board present  
Ground  
10k Pull-Up  
Plug-in board present,  
maximum power consumption  
10k Pull-Up  
Ground  
Ground  
Ground  
Plug-in board present,  
nominal power consumption  
Plug-in board present,  
minimum power consumption  
Other CompactPCI Applications  
If no 3.3V supply input is required, Figure 15 illustrates  
how the LTC4240 should be configured.  
For applications where the BD_SEL# connector pin is  
grounded on the backplane, the circuit in Figure 16 allows  
the LTC4240 to be reset simply by pressing a pushbutton  
switch on the CPCI plug-in board. This arrangement  
allowsformanualresettingoftheLTC4240’scircuitbreak-  
ers.  
When the plug-in card is removed from the connector, the  
BD_SEL# connection is broken first, and the BD_SEL#  
voltagepullsupto5V. ThiscausesQ4toturnoff, whichre-  
enables the bus switch, and the precharge resistors are  
again connected to the LTC4240 PRECHARGE pin for the  
remainder of the board extraction process.  
Input Transient Protection  
Hot-plugging a board into a backplane generates inrush  
currentsfromthebackplanepowersupplies. Thisisdueto  
the charging of the plug-in board bulk capacitance. To  
reduce this transient current to a safe level, the CPCI Hot  
Swap specification restricts the amount of unswitched  
capacitance used on the input side of the plug-in board.  
Each pin connected to the CPCI female connector on the  
plug-in board is allowed at most 0.01µF/pin. Bulk capaci-  
tors are only allowed on the switched output side of the  
LTC4240 (5VOUT, 3VOUT, 12VOUT, VEEOUT). Some bulk  
capacitance is allowed on the Early Power planes, but only  
because a current limiting resistor is assumed to separate  
the connector from the bulk capacitor. Circuits normally  
placed on the unswitched Early Power (PCI Bridge, for  
example) need to have a current limiting resistor.  
The LTC4240 BE pin can alternatively be used to drive the  
enable input of the bus switch. The BE signal would then  
keep the I/O lines precharged until all supplies reached  
power good status. The resistor in series with the  
PRECHARGE pin protects the internal circuitry from large  
voltage transients during live insertion.  
PRSNT1#, PRSNT2#  
PRSNT1# and PRSNT2# are PCI signals that convey the  
plug-in board’s power consumption information. These  
pins should either be shorted to ground or be connected  
toEarlyPowerwitha10kresistor. Thevoltagelevels(TTL)  
at the PRSNT#1, 2 pins can be read using the I2C 2-wire  
interface.  
4240f  
24  
LTC4240  
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APPLICATIO S I FOR ATIO  
Disallowing bulk capacitors on the input power pins  
mitigates the inrush current during hot plug. However, it  
also tends to create a resonant circuit formed by the  
inductance of the backplane power supply trace and the  
parasitic capacitance of the plug-in board (mainly due to  
the large power FET). Upon board insertion, the ringing of  
this circuit will exhibit peak overshoot as high as 2.5 times  
the steady state voltage (>30V for 12V).  
networks. Snubbers are RC networks whose time  
constants are large enough to damp the inductance of the  
parasitic resonant circuit. The snubber capacitor should  
be 10X to 100X the value of the plug-in board parasitic  
capacitance. The value of the series snubber resistor  
should be large enough to damp the resulting  
R-L-C circuit and is typically between 1Ω and 50Ω. These  
protection networks should be mounted very close to the  
LTC4240 in order to minimize parasitic inductance. This is  
shown in Figure 17 for the 3.3V and 5V supplies.  
Therearetwomethodsforabatingtheeffectsofthesehigh  
voltagetransients:usingzenerclamps,andusingsnubber  
CompactPCI  
BACKPLANE  
CONNECTOR  
(FEMALE)  
CompactPCI  
BACKPLANE  
CONNECTOR  
(MALE)  
R2  
0.007Ω  
Q2  
Si7880DP  
5V  
IN  
5V  
OUT  
MEDIUM 5V  
C
L(5VOUT)  
Z4  
LONG  
5V  
D1  
D2  
C1  
0.047µF  
R4  
10Ω  
R22  
2.74Ω  
R5  
1k  
22  
23  
21  
20  
19  
GATE  
6
24  
3V  
IN  
3V  
5V  
IN  
5V  
5V  
OUT  
3V  
OUT  
SENSE  
SENSE  
10  
LTC4240*  
*ADDITIONAL DETAILS OMITTED FOR CLARITY  
GND  
GND  
4240 F15  
D1, D2: BAV99  
Z4: 1PMT5.0AT3  
Figure 15. 5V Supply Only Application Circuit  
V(I/O)  
CompactPCI CompactPCI  
BACKPLANE BACKPLANE  
CONNECTOR CONNECTOR  
PUSHBUTTON  
SWITICH  
(MALE)  
(FEMALE)  
1.2k  
1k  
100Ω  
BD_SEL#  
GND  
28  
10  
OFF/ON  
LTC4240*  
GND  
4240 F16  
*ADDITIONAL DETAILS OMITTED FOR CLARITY  
Figure 16. BD_SEL# Pushbutton Toggle Switch  
R2  
0.007Ω  
Q2  
Si7880DP  
5V  
OUT  
AT 5A  
MEDIUM 5V  
R22, 2.74Ω  
R21, 1.74Ω  
R1  
0.005Ω  
Q1  
LONG 5V  
Si7880DP  
3V  
OUT  
AT 7.6A  
MEDIUM 3.3V  
LONG 3.3V  
C1  
0.047µF  
R3  
10Ω  
R4  
10Ω  
R5  
1k  
22  
23  
19  
24  
21  
20  
6
R23  
2.7Ω  
2.7Ω  
3V  
3V  
GATE 3V  
5V  
IN  
5V  
5V  
OUT  
IN  
SENSE  
OUT  
SENSE  
LTC4240*  
GND  
Z3  
Z4  
C7  
0.1µF  
0.1µF  
1644 F17  
10  
Z3, Z4: 1PMT5.0AT3  
*ADDITIONAL DETAILS OMITTED FOR CLARITY  
Figure 17. Place Transient Protection Device Close to the LTC4240  
4240f  
25  
LTC4240  
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APPLICATIO S I FOR ATIO  
Note (see front page schematic) that the 12V and –12V PCB Layout Considerations  
show 0.01µF snubber capacitors. This is consistent with  
For proper operation of the LTC4240’s circuit breaker  
the CPCI specification since we also recommend a 10Ω  
snubber resistor. The 12VIN pin is the most sensitive to  
high energy large voltage transients. A transient voltage  
suppressor with a breakdown voltage between 13.2V and  
15V is advisable. The TVS should also be able to dissipate  
at least 150W. The SMAJ12CA can be used for both 12VIN  
and VEEIN. Place the TVS close to the LTC4240. See front  
page schematic.  
function, a 4-wire Kelvin connection to the sense resistors  
is highly recommended. A recommended PCB layout for  
thesenseresistor, thepowerMOSFET, andtheGATEdrive  
components around the LTC4240 is illustrated in  
Figure 18. The drawing is not to scale and is only intended  
to show the low resistance, external high current path. In  
hot swap applications where load currents can reach 10A,  
narrow PCB tracks exhibit more resistance than wider  
tracks and operate at more elevated temperatures. Since  
the sheet resistance of 1 ounce copper is approximately  
0.5mΩ/square, track resistances add up quickly in high-  
current applications. Thus, to keep PCB track resistance  
and temperature rise to a minimum, the suggested trace  
width in these applications for 1 ounce copper is 0.03" for  
each ampere of DC current.  
CURRENT FLOW  
TO LOAD  
POWER  
MOSFET  
CURRENT FLOW  
TO LOAD  
SENSE  
RESISTOR  
D
D
D
D
G
S
S
S
5V  
OUT  
5V  
5V  
IN  
W
W
5V  
VIA/PATH  
TO GND  
R4  
R5  
TRACK WIDTH W:  
0.03" PER AMPERE  
ON 1OZ Cu FOIL  
GATE  
In order to help dissipate the heat generated by the power  
MOSFET, the copper trace connected to the drain should  
be made as large as possible.  
C1  
In the majority of applications, it will be necessary to use  
plated-through vias to make circuit connections from  
component layers to power and ground layers internal to  
the PC board. For 1 ounce copper plating, a general rule is  
1A of DC current per via, making sure the via is properly  
dimensioned so that solder completely fills any void. For  
otherplatingthicknesses, checkwithyourPCBfabrication  
facility.  
LTC4240CGN*  
SIMILAR LAYOUT  
FOR 3.3V RAIL  
NOT SHOWN  
CURRENT FLOW  
TO SOURCE  
VIA TO  
GND PLANE  
C
TIMER  
GND  
GND  
W
Power MOSFET and Sense Resistor Selection  
4240 F18  
*ADDITIONAL DETAILS OMITTED FOR CLARITY. DRAWING IS NOT TO SCALE!  
Table 7 lists some current MOSFET transistors that are  
available. Table 8 lists some current sense resistors that  
can be used with the LTC4240’s circuit breakers. Table 9  
lists supplier web site addresses for discrete components  
mentioned throughout the LTC4240 data sheet. High  
current applications should select a MOSFET with very  
low on-resistance and good transient thermal character-  
istics.  
Figure 18. Recommended Layout for Power MOSFET,  
Sense Resistor and GATE Components for the 5V Rail.  
Similar Layout for 3.3V Rail Not Shown  
4240f  
26  
LTC4240  
U
W U U  
APPLICATIO S I FOR ATIO  
Table 7. N-Channel Power MOSFET Selection Guide  
CURRENT LEVEL (A)  
PART NUMBER  
DESCRIPTION  
MANUFACTURER  
0 to 2  
MMDF3N02HD  
Dual N-Channel SO-8  
ON Semiconductor  
R
= 0.1Ω  
DS(ON)  
2 to 5  
MMSF5N02HD  
MTB50N06V  
IRF7457  
Single N-Channel SO-8  
= 0.025Ω  
ON Semiconductor  
ON Semiconductor  
International Rectifier  
Vishay-Siliconix  
R
DS(ON)  
5 to 10  
5 to 10  
5 to 10  
Single N-Channel DD-Pak  
= 0.028Ω  
R
DS(ON)  
Single N-Channel SO-8  
= 0.007Ω  
R
DS(ON)  
TM  
Si7880DP  
Single N-Channel PowerPAK  
= 0.003Ω  
R
DS(ON)  
Table 8. Sense Resistor Selection Guide  
CURRENT LIMIT VALUE  
PART NUMBER  
DESCRIPTION  
MANUFACTURER  
1A  
LR120601R055F  
WSL1206R055  
0.055Ω, 0.5W, 1% Resistor  
IRC-TT  
Vishay-Dale  
2A  
5A  
LR120601R028F  
WSL1206R028  
0.028Ω, 0.5W, 1% Resistor  
0.011Ω, 0.5W, 1% Resistor  
IRC-TT  
Vishay-Dale  
LR120601R011F  
WSL2010R011  
IRC-TT  
Vishay-Dale  
7.9A  
11A  
WSL2512R007  
WSL2512R005  
0.007Ω, 1W, 1% Resistor  
0.005Ω, 1W, 1% Resistor  
Vishay-Dale  
Vishay-Dale  
PowerPAK is a trademark of Vishay-Siliconix  
Table 9. Manufacturers’ Web Site  
MANUFACTURER  
International Rectifier  
ON Semiconductor  
IRC-TT  
WEB SITE  
www.irf.com  
www.onsemi.com  
www.irctt.com  
www.vishay.com  
www.vishay.com  
www.diodes.com  
Vishay-Dale  
Vishay-Siliconix  
Diodes, Inc.  
4240f  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-  
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.  
27  
LTC4240  
U
PACKAGE DESCRIPTIO  
GN Package  
28-Lead Plastic SSOP (Narrow .150 Inch)  
(Reference LTC DWG # 05-08-1641)  
.386 – .393*  
(9.804 – 9.982)  
.045 ±.005  
.033  
(0.838)  
REF  
28 27 26 25 24 23 22 21 20 19 18 17 1615  
.254 MIN  
.150 – .165  
.229 – .244  
.150 – .157**  
(5.817 – 6.198)  
(3.810 – 3.988)  
.0165 ±.0015  
.0250 TYP  
1
2
3
4
5
6
7
8
9
10 11 12 13 14  
.004 – .009  
RECOMMENDED SOLDER PAD LAYOUT  
.015 ± .004  
(0.38 ± 0.10)  
.053 – .069  
(1.351 – 1.748)  
× 45°  
(0.102 – 0.249)  
.0075 – .0098  
(0.191 – 0.249)  
0° – 8° TYP  
.016 – .050  
(0.406 – 1.270)  
.008 – .012  
(0.203 – 0.305)  
.0250  
(0.635)  
BSC  
NOTE:  
1. CONTROLLING DIMENSION: INCHES  
INCHES  
2. DIMENSIONS ARE IN  
(MILLIMETERS)  
GN28 (SSOP) 0502  
3. DRAWING NOT TO SCALE  
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH  
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE  
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD  
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
COMMENTS  
LTC1421  
Hot Swap Controller  
Dual Supplies for 3V to 12V, Additionally –12V  
Single Supply from 3V to 12V  
LTC1422  
Hot Swap Controller in SO-8  
LT1641-1/LT1641-2  
LTC1642  
Positive Voltage Hot Swap Controller in SO-8  
Fault Protected Hot Swap Controller  
Supplies from 9V to 80V, Latched Off/Auto Retry  
3V to 15V, Overvoltage Protection Up to 33V  
3.3V, 5V, 12V, –12V Supplies for PCI Bus  
LTC1643AL/LTC1643AL-1/ PCI Bus Hot Swap Controllers  
LTC1643AH  
LTC1644  
LTC1645  
LTC1646  
LTC1647  
LTC4211  
LTC4230  
LTC4241  
LT4250L/LT4250H  
LTC4251  
LTC4252  
LTC4350  
CompactPCI Hot Swap Controller  
2-Channel Hot Swap Controller  
3.3V, 5V, ±12V, I/O Precharge and Local Reset Logic  
Operates from 1.2V to 12V, Power Sequencing  
3.3V and 5V only, I/O Precharge and Local Reset Logic  
Dual ON Pins for Supplies from 3V to 15V  
CompactPCI Hot Swap Controller for 3.3V and 5V  
Dual Hot Swap Controller  
Single Hot Swap Controller with Multifunction Current Control 2.5V to 16.5V, Dual Level Circuit Breaker, No Gate Capacitor  
Triple Hot Swap Controller with Multifunction Current Control 1.7V to 16.5V, Dual Level Circuit Breaker, No Gate Capacitor  
PCI Hot Swap Controller with 3.3V Auxiliary  
–48 Hot Swap Controllers in SO-8  
–48 Hot Swap Controller in SOT-23  
–48 Hot Swap Controller in MSOP  
Hot Swappable Load Share Controller  
3.3V, 5V, ±12V and 3.3VAux Supplies for PCI Bus  
Active Current Limiting, Supplies from –20V to –80V  
Floating Topology, Active Current Limiting  
Floating Topology, Active Current Limiting, PWRGD Output  
Eliminates ORing Diodes, Identifies and Localizes Faults  
4240f  
LT/TP 0403 2K • PRINTED IN USA  
28 LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
●
●
LINEAR TECHNOLOGY CORPORATION 2003  
(408) 432-1900 FAX: (408) 434-0507 www.linear.com  

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