LTC4236 [Linear]
Dual Ideal Diode-OR and Single Hot Swap Controller with Current Monitor;
| 型号： | LTC4236 |
| 厂家： | 
Linear |
| 描述： | Dual Ideal Diode-OR and Single Hot Swap Controller with Current Monitor |
| 文件： | 总24页 (文件大小：563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4236
Dual Ideal Diode-OR and
Single Hot Swap Controller
with Current Monitor
DescripTion
The LTC®4236 offers ideal diode-OR and Hot Swap func-
tions for two power rails by controlling external N-channel
MOSFETs. MOSFETs acting as ideal diodes replace two
highpowerSchottkydiodesandtheassociatedheatsinks,
savingpowerandboardarea.AHotSwapcontrolMOSFET
allows a board to be safely inserted and removed from a
livebackplanebylimitinginrushcurrent.Thesupplyoutput
is also protected against short-circuit faults with a fast
actingfoldbackcurrentlimitandelectroniccircuitbreaker.
FeaTures
n
Ideal Diode-OR and Inrush Current Control for
Redundant Supplies
Low Loss Replacement for Power Schottky Diodes
Enables Safe Board Insertion into a Live Backplane
2.9V to 18V Operating Range
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Current Monitor Output
Controls N-Channel MOSFETs
Limits Peak Fault Current in ≤ 1µs
Adjustable Current Limit with Foldback
Adjustable Start-Up and Current Limit Fault Delay
0.5µs Ideal Diode Turn-On and Turn-Off Time
Smooth Switchover without Oscillation
Fault, Power Good and Diode Status Outputs
LTC4236-1: Latch Off After Fault
The LTC4236 regulates the forward voltage drop across
theidealdiodeMOSFETstoensuresmoothcurrenttransfer
from one supply to the other without oscillation. The ideal
diode MOSFETs turn on quickly to reduce the load voltage
droop during supply switchover. If the input supply fails
or is shorted, a fast turn-off minimizes reverse current
transients.
LTC4236-2: Automatic Retry After Fault
28-Pin 4mm x 5mm QFN Package
A current sense amplifier translates the voltage across the
senseresistortoagroundreferencedsignal.TheLTC4236
provides adjustable start-up delay, turn-on/-off control,
and reports fault and power good status for the supply.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 7920013, 8022679.
applicaTions
n
Redundant Power Supplies
High Availability Systems and Servers
n
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Telecom and Network Infrastructure
Typical applicaTion
Ideal Diode-OR with Hot Swap Application
SiR158DP
Smooth Supply Switchover
12V
12V
IN2
0.1µF
SiR158DP
0.003Ω
SiR158DP
12V
7A
IN1
+
IN1
1V/DIV
0.1µF
0.1µF
C
LOAD
IN2
1V/DIV
+
+
–
13.7k
2k
CPO1 IN1 DGATE1 CPO2 D2SRC IN2 DGATE2
ON
REG SENSE CS
SENSE HGATE OUT
15k
2k
I
IN1
FB
2A/DIV
I
IN2
2A/DIV
LTC4236
FAULT
PWRGD
DSTAT1
DSTAT2
4236 TA01b
200ms/DIV
EN
IMON
FTMR
ADC
INTV
CC
0.1µF
GND
D2OFF
DTMR
0.1µF
0.1µF
4236 TA01a
4236f
1
For more information www.linear.com/LTC4236
LTC4236
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
Supply Voltages
TOP VIEW
IN1, IN2.................................................. –0.3V to 24V
INTV ..................................................... –0.3V to 7V
CC
+
+
REG ...........................SENSE – 5V to SENSE + 0.3V
28 27 26 25 24 23
–
Input Voltages
SENSE
SENSE
CS
1
2
3
4
5
6
7
8
22
21
FAULT
+
+
ON, D2OFF, EN ...................................... –0.3V to 24V
DSTAT1
20 DSTAT2
FTMR, DTMR.........................–0.3V to INTV + 0.3V
CC
IN1
19
18
17
16
15
ON
FB ............................................................ –0.3V to 7V
29
INTV
D2OFF
NC
+
–
+
CC
SENSE , SENSE , CS , D2SRC .............. –0.3V to 24V
Output Voltages
GND
IN2
NC
IMON ....................................................... –0.3V to 7V
FAULT, PWRGD, DSTAT1, DSTAT2........... –0.3V to 24V
CPO1, CPO2 (Notes 3, 4) ....................... –0.3V to 35V
DGATE1, DGATE2 (Notes 3, 4)............... –0.3V to 35V
HGATE (Note 5) ..................................... –0.3V to 35V
OUT ....................................................... –0.3V to 24V
Average Currents
D2SRC
REG
9
10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
T
= 125°C, θ = 43°C/W (NOTE 6)
JMAX
JA
EXPOSED PAD (PIN 29) PCB GND CONNECTION OPTIONAL
FAULT, PWRGD, DSTAT1, DSTAT2.........................5mA
INTV ...............................................................10mA
CC
Operating Ambient Temperature Range
LTC4236C................................................ 0°C to 70°C
LTC4236I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
orDer inForMaTion
LEAD FREE FINISH
LTC4236CUFD-1#PBF
LTC4236CUFD-2#PBF
LTC4236IUFD-1#PBF
LTC4236IUFD-2#PBF
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4236CUFD-1#TRPBF 42361
LTC4236CUFD-2#TRPBF 42362
28-Lead (4mm x 5mm) Plastic QFN
28-Lead (4mm x 5mm) Plastic QFN
28-Lead (4mm x 5mm) Plastic QFN
28-Lead (4mm x 5mm) Plastic QFN
0°C to 70°C
0°C to 70°C
LTC4236IUFD-1#TRPBF
LTC4236IUFD-2#TRPBF
42361
42362
–40°C to 85°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
4236f
2
For more information www.linear.com/LTC4236
LTC4236
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
V
Input Supply Range
2.9
18
4
V
mA
V
IN
I
Input Supply Current
Internal Regulator Voltage
2.7
5
IN
V
V
I = 0, –500µA
4.5
2.1
30
5.5
2.3
90
INTVCC
Internal V Undervoltage Lockout
INTV Rising
2.2
60
V
INTVCC(UVL)
CC
CC
∆V
Internal V Undervoltage Lockout Hysteresis
mV
INTVCC(HYST)
CC
Ideal Diode Control
l
∆V
∆V
∆V
Forward Regulation Voltage
(V – V +)
2
15
28
mV
FWD(REG)
INn
SENSE
l
l
External N-Channel Gate Drive
(V – V ) and (V
IN < 7V, ∆V
= 0.15V; I = 0, –1µA
5
10
7
12
14
14
V
V
DGATE
FWD
– V
)
IN = 7V to 18V, ∆V = 0.15V; I = 0, –1µA
FWD
DGATE1
IN1
DGATE2
D2SRC
l
Diode MOSFET On Detect Threshold
(V – V ) and (V – V )
D2SRC
DSTAT Pulls Low, ∆V
= 50mV
0.3
0.7
1.1
V
DGATE(ST)
FWD
DGATE1
IN1
DGATE2
l
I
I
D2SRC Pin Current
D2SRC = 0V
–90
–130
µA
D2SRC
l
l
CPOn Pull-Up Current
CPO = IN = D2SRC = 2.9V
CPO = IN = D2SRC = 18V
–60
–50
–100
–90
–130
–120
µA
µA
CPO(UP)
I
I
I
t
t
t
DGATEn Fast Pull-Up Current
∆V
∆V
= 0.2V, ∆V = 0V, CPO = 17V
DGATE
–1.5
1.5
A
A
DGATE(FPU)
DGATE(FPD)
DGATE2(DN)
ON(DGATE)
OFF(DGATE)
PLH(DGATE2)
FWD
FWD
DGATEn Fast Pull-Down Current
DGATE2 Off Pull-Down Current
DGATEn Turn-On Delay
= –0.2V, ∆V
= 5V
DGATE
l
l
l
l
D2OFF = 2V, ∆V
= 2.5V
= 10nF
= 10nF
50
100
0.25
0.2
200
0.5
µA
µs
µs
µs
DGATE2
∆V
FWD
∆V
FWD
= 0.2V , C
DGATE
DGATEn Turn-Off Delay
= –0.2V, C
0.5
DGATE
D2OFF Low to DGATE2 High
50
100
Hot Swap Control
∆V Current Limit Sense Voltage Threshold
l
l
FB = 1.3V
FB = 0V
22.5
5.8
25
27.5
10.8
mV
mV
SENSE(TH)
(V
+ – V
–)
SENSE
8.3
SENSE
+
+
l
l
l
l
l
V
+
SENSE Undervoltage Lockout
SENSE Rising
1.8
10
1.9
50
2
90
1.3
100
1
V
mV
mA
µA
SENSE (UVL)
+
∆V
+
SENSE Undervoltage Lockout Hysteresis
SENSE (HYST)
+
+
I
I
I
+
–
SENSE Pin Current
SENSE = 12V
0.3
10
0.8
40
SENSE
SENSE
–
–
SENSE Pin Current
SENSE = 12V
+
+
+
CS Pin Current
CS = 12V, ∆V
= 0V
µA
CS
SENSE
l
l
∆V
External N-Channel Gate Drive
IN < 7V, I = 0, –1µA
IN = 7V to 18V, I = 0, –1µA
5
10
7
12
14
14
V
V
HGATE
(V
– V
)
HGATE
OUT
l
l
l
∆V
Gate High Threshold (V
– V )
OUT
3.6
–7
1
4.2
–10
2
4.8
–13
4
V
µA
HGATE(H)
HGATE(UP)
HGATE(DN)
HGATE
I
I
External N-Channel Gate Pull-Up Current
Gate Drive On, HGATE = 0V
External N-Channel Gate Pull-Down Current Gate Drive Off, OUT = 12V,
HGATE = OUT + 5V
mA
l
l
I
t
t
External N-Channel Gate Fast Pull-Down
Current
Fast Turn-Off, OUT = 12V,
HGATE = OUT + 5V
100
200
0.5
350
1
mA
µs
HGATE(FPD)
PHL(SENSE)
OFF(HGATE)
+
–
Sense Voltage (SENSE – SENSE )
High to HGATE Low
∆V
SENSE
= 200mV, C
= 10nF
HGATE
l
l
l
ON Low to HGATE Low
10
20
10
20
40
20
µs
µs
µs
EN High to HGATE Low
+
+
SENSE Low to HGATE Low
SENSE UVLO
l
l
t
t
ON High, EN Low to HGATE Turn-On Delay DTMR = INTV
50
100
10
150
20
ms
D(HGATE)
P(HGATE)
CC
ON to HGATE Propagation Delay
ON = Step 0.8V to 2V
µs
4236f
3
For more information www.linear.com/LTC4236
LTC4236
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.
SYMBOL
Inputs
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
V
V
D2OFF Pin High Threshold
D2OFF Pin Low Threshold
D2OFF Pin Hysteresis
D2OFF Rising
D2OFF Falling
1.21
1.19
10
1.235
1.215
20
1.26
1.24
30
V
V
D2OFF(H,TH)
D2OFF(L,TH)
∆V
mV
V
D2OFF(HYST)
V
ON, FB Pin Threshold Voltage
ON Pin Hysteresis
Voltage Rising
1.21
40
1.235
80
1.26
120
30
IN(TH)
∆V
∆V
mV
mV
V
ON(HYST)
FB(HYST)
FB Pin Hysteresis
10
20
V
ON Pin Fault Reset Threshold Voltage
Input Leakage Current (ON, FB, D2OFF)
EN Pin Threshold Voltage
EN Pin Hysteresis
ON Falling
V = 5V
0.57
0.6
0.63
1
ON(RESET)
IN(LEAK)
I
0
µA
V
V
EN Rising
1.185
60
1.235
110
–10
1.235
0.2
1.284
200
–13
1.272
0.25
–120
2.7
EN(TH)
∆V
mV
µA
V
EN(HYST)
I
EN Pull-Up Current
EN = 1V
–7
EN(UP)
V
V
FTMR, DTMR Pin High Threshold
FTMR, DTMR Pin Low Threshold
FTMR Pull-Up Current
1.198
0.15
–80
1.3
TMR(H)
TMR(L)
V
I
I
FTMR = 1V, In Fault Mode
FTMR = 2V, No Faults
–100
2
µA
µA
%
FTMR(UP)
FTMR(DN)
FTMR Pull-Down Current
Auto-Retry Duty Cycle
D
0.07
–8
0.15
–10
5
0.23
–12
10
RETRY
I
I
DTMR Pull-Up Current
DTMR = 0.6V
DTMR = 1.5V
µA
mA
V
DTMR(UP)
DTMR(DN)
DTMR Pull-Down Current
DTMR Pin Threshold Voltage
1
∆V
t
Start-Up Delay
–0.1
–0.3
–0.5
DTMR(TH)
D(HGATE)
(V
DTMR
– V
)
INTVCC
l
l
t
t
ON Low to FAULT High
FB Low to PWRGD High
20
20
40
40
µs
µs
RST(ON)
PG(FB)
Outputs
l
l
I
OUT Pin Current
OUT = 11V, IN = 12V, ON = 2V
OUT = 13V, IN = 12V, ON = 2V
40
2.5
100
4
µA
mA
OUT
l
l
V
Output Low Voltage
(FAULT, PWRGD, DSTAT1, DSTAT2)
I = 1mA
I = 3mA
0.15
0.4
0.4
1.2
V
V
OL
l
l
V
Output High Voltage (FAULT, PWRGD)
I = –1µA
V = 18V
INTV – 1 INTV – 0.5
V
OH
CC
CC
I
I
Input Leakage Current
(FAULT, PWRGD, DSTAT1, DSTAT2)
0
1
µA
OH
l
Output Pull-Up Current (FAULT, PWRGD)
V = 1.5V
–7
–10
4.1
–13
µA
PU
Current Monitor
l
l
∆V
Floating Regulator Voltage
I
= 1µA
3.6
25
4.6
V
REG
REG
(V + – V
SENSE
)
REG
+
∆V
Input Sense Voltage Full Scale
(V + – V –)
SENSE = 12V
mV
SENSE(FS)
SENSE
SENSE
l
l
V
IMON Input Offset Voltage
IMON Voltage Gain
∆V
∆V
= 0V
150
101
µV
IMON(OS)
SENSE
G
= 20mV and 5mV
99
100
20
V/V
IMON
SENSE
+
l
l
V
IMON Maximum Output Voltage
∆V
SENSE
∆V
SENSE
= 70mV, 5V ≤ SENSE ≤ 18V
= 35mV, SENSE = 2.9V
3.5
2.7
5.5
2.9
V
V
IMON(MAX)
+
l
l
V
IMON Minimum Output Voltage
IMON Output Resistance
∆V
SENSE
∆V
SENSE
= 200µV
= 200µV
40
27
mV
kΩ
IMON(MIN)
R
15
IMON(OUT)
4236f
4
For more information www.linear.com/LTC4236
LTC4236
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 4: An internal clamp limits the DGATE2 and CPO2 pins to a minimum
of 10V above and a diode below D2SRC. Driving these pins to voltages
beyond the clamp may damage the device.
Note 5: An internal clamp limits the HGATE pin to a minimum of 10V
above and a diode below OUT. Driving this pin to voltages beyond the
clamp may damage the device.
Note 6: Thermal resistance is specified when the exposed pad is soldered
Note 3: An internal clamp limits the DGATE1 and CPO1 pins to a minimum
of 10V above and a diode below IN1. Driving these pins to voltages beyond
the clamp may damage the device.
to a 3" x 5" , four layer, FR4 board.
4236f
5
For more information www.linear.com/LTC4236
LTC4236
TA = 25°C, VIN = 12V, unless otherwise noted.
Typical perForMance characTerisTics
IN Supply Current vs Voltage
SENSE+ Current vs Voltage
OUT Current vs Voltage
3.5
3
1.4
1.2
1
3.5
V + = V – 0.5V
SENSE IN
V
= 12V, V
+ = 11.5V
SENSE
IN
3
2.5
2
2.5
2
0.8
0.6
0.4
0.2
0
V
OUT
= 0V
1.5
1
1.5
1
V
OUT
= 3.3V
0.5
0
V
OUT
= 12V
0.5
0
–0.5
0
3
6
9
12
15
18
0
3
6
9
12
15
18
0
3
6
9
12
15
18
V
(V)
V
+ (V)
SENSE
V
(V)
OUT
IN
4236 G01
4236 G02
4236 G03
Hot Swap Gate Voltage vs IN
Voltage
Hot Swap Gate Voltage vs Current
CPO Voltage vs Current
14
12
10
8
14
12
10
8
12
10
8
V
OUT
= V
V = V
OUT IN
IN
V
IN
= 12V
V
IN
= 18V
6
V
IN
= 2.9V
6
4
V
IN
= 2.9V
4
2
6
2
0
0
4
–2
0
–2
–4
–6
–8
–10
–12
0
3
6
9
12
15
18
0
–20 –40 –60 –80 –100 –120 –140
(µA)
I
(µA)
V
(V)
I
CPO
HGATE
IN
4236 G04
4236 G05
4236 G06
FAULT, PWRGD, DSTAT1, DSTAT2
Output Low Voltage vs Current
Diode Gate Voltage vs Current
Diode Gate Voltage vs IN Voltage
12
10
8
14
12
10
8
1
0.8
0.6
0.4
0.2
0
V
+ = V – 0.15V
V
+ = V – 0.15V
SENSE
IN
SENSE IN
V
IN
= 18V
6
V
IN
= 2.9V
4
V
IN
= 2.9V
V
IN
= 12V
2
6
0
–2
4
0
–20 –40 –60 –80 –100 –120 –140
(µA)
0
3
6
9
12
15
18
0
1
2
3
4
5
I
V
(V)
IN
CURRENT (mA)
DGATE
4236 G07
4236 G08
4236 G09
4236f
6
For more information www.linear.com/LTC4236
LTC4236
TA = 25°C, VIN = 12V, unless otherwise noted.
Typical perForMance characTerisTics
Current Limit Delay vs Sense
Voltage
Current Sense Amplifier Input
Offset Voltage vs Temperature
Current Limit Threshold Foldback
30
25
20
15
10
5
100
10
1
40
30
C
= 10nF
HGATE
V
= 2.9V
= 12V
IN
20
10
V
IN
0
–10
–20
–30
–40
0
0.1
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
0
40
80
120
+ – V
160
–) (mV)
SENSE
200
–50
–25
0
25
50
75
100
FB VOLTAGE (V)
SENSE VOLTAGE (V
TEMPERATURE (°C)
SENSE
4236 G10
4236 G11
4236 G12
IMON Voltage Gain vs
Temperature
IMON Propagation Delay vs
Sense Voltage
IMON Voltage vs Sense Voltage
5
4
3
2
1
0
101
100.5
100
120
100
80
60
40
20
0
V
IN
= 12V
V
IN
= 2.9V
V
IN
= 2.9V
V
IN
= 12V
99.5
99
0
10
20
30
+ – V
40
–) (mV)
50
–50
–25
0
25
50
75
100
0
1
2
3
4
5
SENSE VOLTAGE (V
TEMPERATURE (°C)
SENSE VOLTAGE (V
+ – V
–) (mV)
SENSE
4236 G15
SENSE
SENSE
SENSE
4236 G13
4236 G14
Ideal Diode Start-Up Waveform
on IN Power-Up
100ms HGATE Start-Up Delay with
DTMR Pin Connected to INTVcc
Adjustable HGATE Start-Up Delay
with 0.1µF Capacitor at DTMR pin
IN
10V/DIV
ON
5V/DIV
ON
5V/DIV
+
HGATE
10V/DIV
OUT
HGATE
10V/DIV
OUT
SENSE
10V/DIV
CPO
10V/DIV
10V/DIV
DGATE
10V/DIV
PWRGD
10V/DIV
PWRGD
10V/DIV
4236 G16
4236 G17
4236 G18
10ms/DIV
20ms/DIV
20ms/DIV
4236f
7
For more information www.linear.com/LTC4236
LTC4236
pin FuncTions
CPO1, CPO2: Charge Pump Output. Connect a capacitor
from CPO1 or CPO2 to the corresponding IN1 or D2SRC
pin. The value of this capacitor is approximately 10×
DSTAT2: Diode MOSFET Status Output. Open drain out-
put that pulls low when the MOSFET gate drive voltage
between DGATE2 and D2SRC exceeds 0.7V indicating
that the MOSFET diode path is on. Otherwise it goes high
impedance. It requires an external pull-up resistor to a
positive supply. Leave open if unused.
the gate capacitance (C ) of the external MOSFET for
ISS
ideal diode control. The charge stored on this capacitor
is used to pull up the ideal diode MOSFET gate during a
fast turn-on. Leave this pin open if fast ideal diode turn-
on is not needed.
DTMR: Debounce Timer Capacitor Terminal. Connect
this pin to either INTV for fixed 100ms delay or an
CC
+
CS : Positive Current Sense Input for Current Sense Am-
external capacitor to ground for adjustable start-up delay
plifier. Connect this pin to the input of the current sense
(123ms/µF) when EN toggles low.
+
–
resistor.ThevoltagebetweenCS andSENSE istranslated
to a ground referenced signal at IMON pin.
EN: Enable Input. Ground this pin to enable Hot Swap
control. If this pin is pulled high, the Hot Swap MOSFET
is not allowed to turn on. A 10µA current source pulls this
DGATE1, DGATE2: Ideal Diode MOSFET Gate Drive Out-
put. Connect this pin to the gate of an external N-channel
MOSFET for ideal diode control. An internal clamp limits
the gate voltage to 12V above and a diode voltage below
IN1 or D2SRC. During fast turn-on, a 1.5A pull-up charges
DGATE from CPO. During fast turn-off, a 1.5A pull-down
discharges DGATE1 to IN1 and DGATE2 to D2SRC.
pin up to a diode below INTV . Upon EN going low when
CC
ON is high, there is a start-up delay for debounce as con-
figured at the DTMR pin, after which the fault is cleared.
FAULT: Overcurrent Fault Status Output. Output that pulls
low when the fault timer expires during an overcurrent
fault. Otherwise it is pulled high by a 10µA current source
D2OFF: Control Input. A rising edge above 1.235V turns
off the external ideal diode MOSFET in the IN2 supply path
and a falling edge below 1.215V allows the MOSFET to be
turned on. Connect this pin to an external resistive divider
fromIN1tomakeIN1thehigherpriorityinputsupplywhen
IN1 and IN2 are equal.
to a diode below INTV . It may be pulled above INTV
CC
CC
using an external pull-up. Leave open if unused.
FB:FoldbackandPowerGoodComparatorInput. Connect
this pin to an external resistive divider from OUT. If the
voltage falls below 1.215V, the PWRGD pin pulls high to
indicate the power is bad. If the voltage falls below 0.9V,
the output power is considered bad and the current limit
D2SRC: Ideal Diode MOSFET Gate Drive Return. Connect
this pin to the source of the external N-channel MOSFET
switch in the IN2 power path. The gate fast pull-down cur-
rent returns through this pin when DGATE2 is discharged.
is reduced. Tie to INTV to disable foldback.
CC
FTMR:FaultTimerCapacitorTerminal.Connectacapacitor
between this pin and ground to set a 12ms/µF duration
for current limit before the external Hot Swap MOSFET is
turned off. The duration of the off time is 8s/µF, resulting
in a 0.15% duty cycle.
DSTAT1: Diode MOSFET Status Output. Open drain out-
put that pulls low when the MOSFET gate drive voltage
between DGATE1 and IN1 exceeds 0.7V indicating that the
MOSFET diode path is on. Otherwise it goes high imped-
ance. It requires an external pull-up resistor to a positive
supply. Leave open if unused.
GND: Device Ground.
4236f
8
For more information www.linear.com/LTC4236
LTC4236
pin FuncTions
HGATE: Hot Swap MOSFET Gate Drive Output. Connect
this pin to the gate of the external N-channel MOSFET for
HotSwapcontrol.Aninternal10µAcurrentsourcecharges
the MOSFET gate. An internal clamp limits the gate volt-
age to 12V above and a diode voltage below OUT. During
an undervoltage generated turn-off, a 2mA pull-down
discharges HGATE to ground. During an output short or
OUT: Hot Swap MOSFET Gate Drive Return. Connect this
pin to the output side of the external MOSFET. The gate
fast pull-down current returns through this pin when
HGATE is discharged.
PWRGD:PowerStatusOutput. Outputthatpullslowwhen
the FB pin rises above 1.235V and the MOSFET gate drive
between HGATE and OUT exceeds 4.2V. Otherwise it is
pulled high by a 10µA current source to a diode below
INTV undervoltage lockout, a fast 200mA pull-down
CC
discharges HGATE to OUT.
INTV . It may be pulled above INTV using an external
CC
CC
IN1, IN2: Positive Supply Input and Ideal Diode MOSFET
pull-up. Leave open if unused.
Gate Drive Return. Connect this pin to the power input
REG: Internal Regulated Supply for Current Sense Ampli-
side of the external ideal diode MOSFET. The 5V INTV
CC
fier. A 0.1µF or larger capacitor should be tied from REGto
supply is generated from IN1, IN2 and OUT via an internal
diode-OR. The voltage sensed at this pin is used to control
DGATE. The gate fast pull-down current returns through
IN1 pin when DGATE1 is discharged.
+
SENSE . This pin is not designed to drive external circuits.
+
SENSE : Positive Current Sense Input. Connect this pin
to the diode-OR output of the external ideal diode MOS-
FETs and input of the current sense resistor. The voltage
sensed at this pin is used for monitoring the current limit
and also to control DGATE for forward voltage regulation
and reverse turn-off. This pin has an undervoltage lockout
threshold of 1.9V that will turn off the Hot Swap MOSFET.
INTV : Internal 5V Supply Decoupling Output. This pin
CC
must have a 0.1µF or larger capacitor to GND. An external
load of less than 500µA can be connected at this pin. An
undervoltage lockout threshold of 2.2V will turn off both
MOSFETs.
–
SENSE : Negative Current Sense Input. Connect this pin
IMON: Current Sense Monitoring Output. This pin voltage
is proportional to the sense voltage across the current
sense resistor with a voltage gain of 100. An internal 20k
resistor is connected from this pin to ground.
to the output of the current sense resistor. The current
limit circuit controls HGATE to limit the voltage between
+
–
SENSE and SENSE to 25mV or less depending on the
voltage at the FB pin.
ON: ON Control Input. A rising edge above 1.235V turns
ontheexternalHotSwapMOSFETandafallingedgebelow
1.155Vturnsitoff. Connectthispintoanexternalresistive
+
divider from SENSE to monitor the supply undervoltage
condition. Pulling the ON pin below 0.6V resets the fault
latch after an overcurrent fault. Tie to INTV if unused.
CC
4236f
9
For more information www.linear.com/LTC4236
LTC4236
block DiagraM
+
–
+
IN1 SENSE
SENSE
IN2 CS
REG
4.1V
FOLDBACK
FB
0.9V
200Ω
HGATE
–
CM
+
+
CL
–
GATE
DRIVER
12V
IMON
20k
OUT
10µA
100µA
CHARGE
PUMP 1
f = 2MHz
CHARGE
PUMP 2
f = 2MHz
CPO2
CPO1
100µA
+
–
+
–
DGATE1
DGATE2
GD1
GD2
12V
12V
15mV
15mV
D2SRC
INTV
CC
5V LDO
UVLO1
UVLO2
PG1
DOFF
+
–
D2OFF
+
–
DGATE2 OFF
2.2V
1.235V
ON
+
–
+
SENSE
1.9V
1.235V
–
+
HGATE ON
–
+
ON
+
–
RST
FB
INTV
CC
–
+
FAULT RESET
–
+
1.235V
4.2V
10µA
0.6V
PG2
+
–
EN
EN
HGATE
+
–
OUT
0.7V
1.235V
1.235V
INTV
CC
100µA
DSTAT1
+
–
DGATE1
DGATE2
TM1
TM2
–
+
–
+
IN1
LOGIC
FTMR
0.7V
DSTAT2
INTV
+
–
–
+
–
+
0.2V
D2SRC
INTV
CC
2µA
INTV
CC
10µA
10µA
CC
PWRGD
FAULT
10µA
DTMR
GND
0.3V
TM3
TM4
–
–
+
1.235V
0.2V
–
+
DSTAT1
DSTAT2
EXPOSED PAD
4236 BD
4236f
10
For more information www.linear.com/LTC4236
LTC4236
operaTion
The LTC4236 functions as an input supply diode-OR with
rises above 1.235V and the MOSFET’s gate drive (HGATE
inrush current limiting and overcurrent protection by
to OUT voltage) exceeds 4.2V, the PWRGD pin pulls low.
controlling the external N-channel MOSFETs (M , M
D1
D2
The high side current sense amplifier (CM) provides ac-
curate monitoring of current through the current sense
resistor. The sense voltage is amplified by 100 times and
level shifted from the positive rail to a ground-referred
output at the IMON pin. The output signal is analog and
may be used as is or measured with an ADC.
and M ) on a supply path. This allows boards to be safely
H
insertedandremovedinsystemswithabackplanepowered
byredundantsupplies.TheLTC4236hasasingleHotSwap
controller and two separate ideal diode controllers, each
providing independent control for the two input supplies.
When the LTC4236 is first powered up, the gates of the
external MOSFETs are held low, keeping them off. As the
DGATE2pull-upcanbedisabledbytheD2OFFpin,DGATE2
will pull high only when the D2OFF pin is pulled low. The
gate drive amplifier (GD1, GD2) monitors the voltage be-
When the ideal diode MOSFET is turned on, the gate drive
amplifier controls DGATE to servo the forward voltage
drop (V – V
+) across the MOSFET to 15mV. If the
IN
SENSE
load current causes more than 15mV of voltage drop,
the gate voltage rises to enhance the MOSFET. For large
output currents, the MOSFET’s gate is driven fully on and
+
tween the IN and SENSE pins and drives the respective
DGATE pin. The amplifier quickly pulls up the DGATE pin,
turning on the MOSFET for ideal diode control, when it
senses a large forward voltage drop. With the ideal diode
the voltage drop is equal to I
•R
of the MOSFET.
LOAD DS(ON)
In the case of an input supply short-circuit when the
MOSFETs are conducting, a large reverse current starts
flowing from the load towards the input. The gate drive
amplifier detects this failure condition and turns off the
ideal diode MOSFET by pulling down the DGATE pin.
+
MOSFETs acting as input supply diode-OR, the SENSE
pin voltage rises to the highest of the supplies at the IN1
and IN2 pins. An external capacitor connected at the CPO
pin provides the charge needed to quickly turn on the
ideal diode MOSFET. An internal charge pump charges
up this capacitor at device power-up. The DGATE pin
sources current from the CPO pin and sinks current into
the IN1, D2SRC and GND pins. When the DGATE1 to IN1
or DGATE2 to D2SRC voltage exceeds 0.7V, the respec-
tive DSTAT pin pulls low to indicate that the ideal diode
MOSFET is turned on.
Inthecasewhereanovercurrentfaultoccursonthesupply
output, the current is limited with foldback. After a delay
set by 100µA charging the FTMR pin capacitor, the fault
timer expires and pulls the HGATE pin low, turning off the
Hot Swap MOSFET. The FAULT pin is also latched low. At
this point, the DGATE pin continues to pull high and keeps
the ideal diode MOSFET on.
PullingtheONpinhighandENpinlowinitiatesadebounce
timing cycle that can be a fixed 100ms or adjustable delay
as configured at the DTMR pin. After this timing cycle, a
10µA current source from the charge pump ramps up
the HGATE pin. When the Hot Swap MOSFET turns on,
Internal clamps limit both the DGATE1 and CPO1 to IN1,
and DGATE2 and CPO2 to D2SRC voltages to 12V. The
same clamps also limit the DGATE and CPO pins to a diode
voltage below the IN1 or D2SRC pins. Another internal
clamp limits the HGATE to OUT voltage to 12V and also
clampstheHGATEpintoadiodevoltagebelowtheOUTpin.
the inrush current is limited at a level set by an external
+
sense resistor (R ) connected between the SENSE and
S
–
Power to the LTC4236 is supplied from either the IN or
OUT pins, through an internal diode-OR circuit to a low
dropout regulator (LDO). That LDO generates a 5V supply
SENSE pins. An active current limit amplifier (CL) servos
the gate of the MOSFET to 25mV or less across the cur-
rent sense resistor depending on the voltage at the FB
pin. Inrush current can be further reduced, if desired, by
adding a capacitor from HGATE to GND. When FB voltage
at the INTV pin and powers the LTC4236’s internal low
CC
voltage circuitry.
4236f
11
For more information www.linear.com/LTC4236
LTC4236
applicaTions inForMaTion
High availability systems often employ parallel-connected
powersuppliesorbatteryfeedstoachieveredundancyand
enhance system reliability. Power ORing diodes are com-
monlyusedtoconnectthesesuppliesatthepointofloadat
theexpenseofpowerlossduetosignificantdiodeforward
voltage drop. The LTC4236 minimizes this power loss by
using external N-channel MOSFETs as the pass elements,
allowing for a low voltage drop from the supply to the load
when the MOSFETs are turned on. When an input source
voltage drops below the output common supply voltage,
the appropriate MOSFET is turned off, thereby matching
the function and performance of an ideal diode. By adding
a current sense resistor and a Hot Swap MOSFET after
theparallel-connectedidealdiodeMOSFETs, theLTC4236
enhances the ideal diode performance with inrush current
limiting and overcurrent protection (see Figure 1). This
allows the board to be safely inserted and removed from
a live backplane without damaging the connector.
Internal V Supply
CC
The LTC4236 operates with an input supply from 2.9V to
18V. Thepowersupplytothedeviceisinternallyregulated
at 5V by a low dropout regulator (LDO) with an output at
the INTV pin. An internal diode-OR circuit selects the
CC
highest of the supplies at the IN and OUT pins to power the
devicethroughtheLDO.Thediode-ORschemepermitsthe
device’s power to be kept alive by the OUT voltage when
the IN supplies have collapsed or shut off.
AnundervoltagelockoutcircuitpreventsalloftheMOSFETs
from turning on until the INTV voltage exceeds 2.2V. A
CC
0.1µF capacitor is recommended between the INTV and
CC
GND pins, close to the device for bypassing. No external
supply should be connected at the INTV pin so as not
CC
to affect the LDO’s operation. A small external load of less
than 500µA can be connected at the INTV pin.
CC
M
D1
SiR158DP
V
IN1
12V
Z1
SMAJ15A
M
R
M
H
SiR158DP
D2
SiR158DP
S
0.003Ω
V
12V
7A
IN2
12V
Z2
SMAJ15A
+
R
H
10Ω
C
L
680µF
R
1k
C
HG
R4
15k
C2
0.1µF
C3
0.1µF
C4
0.1µF
V
+
HG
SENSE
10nF
R2
R5
100k
13.7k
+
+
–
CPO1 IN1 DGATE1 CPO2 D2SRC IN2 DGATE2 REG SENSE CS
ON
SENSE
HGATE OUT
R6
100k
FB
C5
0.1µF
R3
2k
R7
100k
R1
2k
R8
100k
LTC4236
FAULT
PWRGD
DSTAT1
DSTAT2
EN
ADC
IMON
INTV
GND
D2OFF
DTMR
FTMR
CC
BACKPLANE CARD
CONNECTOR CONNECTOR
4236 F01
C1
0.1µF
C
DT
0.1µF
C
FT
0.1µF
Figure 1. Card Resident Diode-OR with Hot Swap Application
4236f
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For more information www.linear.com/LTC4236
LTC4236
applicaTions inForMaTion
Turn-On Sequence
Once OUT reaches the input supply voltage, HGATE con-
tinues to ramp up. An internal 12V clamp limits the HGATE
voltage above OUT.
The board power supply at the OUT pin is controlled
with external N-channel MOSFETs (M , M and M ) in
D1
D2
H
Figure 1. The ideal diode MOSFETs connected in parallel
When the ideal diode MOSFET is turned on, the gate
drive amplifier controls the gate of the MOSFET to servo
the forward voltage drop across the MOSFET to 15mV.
If the load current causes more than 15mV of drop, the
MOSFET gate is driven fully on and the voltage drop is
on the supply side function as a diode-OR, while M on
H
the load side acts as a Hot Swap MOSFET controlling the
power supplied to the output load. The sense resistor R
S
monitors the load current for overcurrent detection. The
HGATE capacitor C controls the gate slew rate to limit
equal to I
• R
.
HG
LOAD
DS(ON)
the inrush current. Resistor R with C compensates
HG
HG
Turn-Off Sequence
thecurrentcontrolloop, whileR preventshighfrequency
H
oscillations in the Hot Swap MOSFET.
The external MOSFETs can be turned off by a variety of
conditions. A normal turn-off for the Hot Swap MOSFET is
initiated by pulling the ON pin below its 1.155V threshold
(80mV ON pin hysteresis), or pulling the EN pin above its
1.235V threshold. Additionally, an overcurrent fault that
exceeds the fault timer period also turns off the Hot Swap
MOSFET. Normally, the LTC4236 turns off the MOSFET by
pulling the HGATE pin to ground with a 2mA current sink.
During a normal power-up, the ideal diode MOSFETs turn
onfirst.Assoonastheinternallygeneratedsupply,INTV ,
CC
rises above its 2.2V undervoltage lockout threshold, the
internal charge pump is allowed to charge up the CPO
pins. Because the ideal diode MOSFETs are connected in
+
parallelasadiode-OR,theSENSE pinvoltageapproaches
the highest of the supplies at the IN1 and IN2 pins. The
MOSFET associated with the lower input supply voltage
willbeturnedoffbythecorrespondinggatedriveamplifier.
All of the MOSFETs turn off when INTV falls below its
CC
undervoltage lockout threshold (2.2V). The DGATE pin is
pulled down with a 100µA current to one diode voltage
belowtheIN1orD2SRCpins,whiletheHGATEpinispulled
down to the OUT pin by a 200mA current. When D2OFF
is pulled high above 1.235V, the ideal diode MOSFET in
the IN2 power path is turned off with DGATE2 pulled low
by a 100µA current.
Before the Hot Swap MOSFET can be turned on, EN must
remainlow and ONmustremain high fora debounce cycle
as configured at the DTMR pin, to ensure that any contact
bounces during the insertion have ceased. At the end of
the debounce cycle, the internal fault latch is cleared. The
Hot Swap MOSFET is then allowed to turn on by charging
up HGATE with a 10µA current source from the charge
pump. The voltage at the HGATE pin rises with a slope
The gate drive amplifier controls the ideal diode MOSFET
to prevent reverse current when the input supply falls
+
equal to 10µA/C and the supply inrush current flowing
HG
below SENSE . If the input supply collapses quickly, the
into the load capacitor C is limited to:
L
gate drive amplifier turns off the ideal diode MOSFET with
a fast pull-down circuit. If the input supply falls at a more
modest rate, the gate drive amplifier controls the MOSFET
CL
CHG
IINRUSH
=
•10µA
+
to maintain SENSE at 15mV below IN.
The OUT voltage follows the HGATE voltage when the Hot
Swap MOSFET turns on. If the voltage across the current
Board Presence Detect with EN
sense resistor R becomes too high based on the FB pin
If ON is high when the EN pin goes low, indicating a board
presence,theLTC4236initiatesatimingcycleasconfigured
at the DTMR pin for contact debounce. It defaults to inter-
S
voltage, the inrush current will be limited by the internal
currentlimitingcircuitry.OncetheMOSFETgateoverdrive
exceeds 4.2V and the FB pin voltage is above 1.235V, the
PWRGD pin pulls low to indicate that the power is good.
nal 100ms delay if DTMR is tied to INTV . If an external
CC
capacitor C is connected from the DTMR pin to GND,
DT
the delay is given by charging the capacitor to 1.235V with
4236f
13
For more information www.linear.com/LTC4236
LTC4236
applicaTions inForMaTion
a 10µA current. Thereafter, the capacitor is discharged to
ground by a 5mA current. For a given debounce delay, the
OUT
10V/DIV
equation for setting the external capacitor C value is:
DT
C
= t •0.0081 [µF/ms]
DB
DT
HGATE
10V/DIV
Upon board insertion, any bounces on the EN pin restart
the timing cycle. When the debounce timing cycle is done,
the internal fault latch is cleared. If the EN pin remains low
at the end of the timing cycle, HGATE is charged up with
a 10µA current source to turn on the Hot Swap MOSFET.
I
LOAD
20A/DIV
4236 F02
200µs/DIV
If the EN pin goes high, indicating a board removal, the
HGATE pin is pulled low with a 2mA current sink after a
20µs delay, turning off the Hot Swap MOSFET without
clearing any latched fault.
Figure 2. Overcurrent Fault on 12V Output
OUT
10V/DIV
Overcurrent Fault
The LTC4236 features an adjustable current limit with
foldback that protects the external MOSFET against short
circuits or excessive load current. The voltage across the
HGATE
10V/DIV
externalsenseresistorR ismonitoredbyanactivecurrent
S
I
LOAD
20A/DIV
limit amplifier. The amplifier controls the gate of the Hot
Swap MOSFET to reduce the load current as a function of
theoutputvoltagesensedbytheFBpinduringactivecurrent
limit. A graph in the Typical Performance Characteristics
shows the current limit sense voltage versus FB voltage.
4236 F03
5µs/DIV
Figure 3. Severe Short-Circuit on 12V Output
An overcurrent fault occurs when the output has been in
currentlimitforlongerthanthefaulttimerperiodconfigured
at the FTMR pin. Current limiting begins when the sense
Intheeventofasevereshort-circuitfaultonthe12Voutput
as shown in Figure 3, the output current can surge to tens
ofamperes.TheLTC4236respondswithin1µstobringthe
currentundercontrolbypullingtheHGATEtoOUTvoltage
downtozerovolts.Almostimmediately,thegateoftheHot
Swap MOSFET recovers rapidly due to the charge stored
+
–
voltage between the SENSE and SENSE pins reaches
8.3mV to 25mV depending on the FB pin voltage. The gate
of the Hot Swap MOSFET is brought under control by the
current limit amplifier and the output current is regulated
to limit the sense voltage to less than 25mV. At this point,
the fault timer starts with a 100µA current charging the
FTMR pin capacitor. If the FTMR pin voltage exceeds its
1.235V threshold, the external MOSFET turns off with
HGATE pulled to ground by 2mA and FAULT pulls low.
in the R and C network and current is actively limited
HG
HG
until the fault timer expires. Due to parasitic supply lead
inductance, an input supply without any bypass capaci-
tor may collapse during the high current surge and then
spike upwards when the current is interrupted. Figure 9
shows the input supply transient suppressors comprising
of Z1, R
, C
and Z2, R
, C
for the two
SNUB1 SNUB1
supplies if there is no input capacitance.
SNUB2 SNUB2
After the Hot Swap MOSFET turns off, the FTMR pin ca-
pacitor is discharged with a 2µA pull-down current until
its threshold reaches 0.2V. This is followed by a cool-off
period of 14 timing cycles as described in the FTMR Pin
Functions. Figure 2 shows an overcurrent fault on the
12V output.
FTMR Pin Functions
An external capacitor C connected from the FTMR pin
FT
to GND serves as fault timing when the supply output is
4236f
14
For more information www.linear.com/LTC4236
LTC4236
applicaTions inForMaTion
in active current limit. When the voltage across the sense
resistorexceedsthefoldbackcurrentlimitthreshold(from
25mV to 8.3mV), FTMR pulls up with 100µA. Otherwise,
it pulls down with 2µA. The fault timer expires when the
1.235V FTMR threshold is exceeded, causing the FAULT
pin to pull low. For a given fault timer period, the equation
initiated before a normal start-up when any of the supplies
is restored above the INTV UVLO threshold.
CC
Auto-Retry after a Fault (LTC4236-2)
For the auto-retry part, the latched fault is reset automati-
cally at the end of the cool-off period as described in the
FTMR Pin Functions section. At the end of the cool-off
period, the fault latch is cleared and FAULT pulls high.
The HGATE pin voltage is allowed to start up and turn on
the Hot Swap MOSFET. If the output short persists, the
supply powers up into a short with active current limiting
until the fault timer expires and FAULT again pulls low. A
new cool-off cycle begins with FTMR ramping down with
a 2µA current. The whole process repeats itself until the
for setting the external capacitor C value is:
FT
C = t • 0.083 [µF/ms]
FT
FT
After the fault timer expires, the FTMR pin capacitor pulls
down with 2µA from the 1.235V FTMR threshold until it
reaches0.2V.Then,itcompletes14coolingcyclesconsist-
ing of the FTMR pin capacitor charging to 1.235V with a
100µAcurrentanddischargingto0.2Vwitha2µAcurrent.
At that point, the HGATE pin voltage is allowed to start up
if the fault has been cleared as described in the Resetting
Fault section. When the latched fault is cleared during the
cool-offperiod, theFAULTpinpullshigh. Thetotalcool-off
time for the MOSFET after an overcurrent fault is:
output short is removed. Since t and t
are a function
FT
COOL
of FTMR capacitance C , the auto-retry cycle is equal to
FT
0.15%, irrespective of C .
FT
Figure 4 shows an auto-retry sequence after an overcur-
rent fault.
t
= C • 8 [s/µF]
FT
COOL
FTMR
2V/DIV
After the cool-off period, the HGATE pin is only allowed
to pull up if the fault has been cleared for the latchoff
part. For the auto-retry part, the latched fault is cleared
automatically following the cool-off period and the HGATE
pin voltage is allowed to restart.
FAULT
10V/DIV
HGATE
20V/DIV
Resetting Fault (LTC4236-1)
OUT
10V/DIV
For the latchoff part, an overcurrent fault is latched after
the fault timer expires and the FAULT pin is asserted low.
Only the Hot Swap MOSFET is turned off and the ideal
diode MOSFETs are not affected.
4236 F04
100ms/DIV
Figure 4. Auto-Retry Sequence After a Fault
To reset a latched fault and restart the output, pull the
ON pin below 0.6V for more than 100µs and then high
above 1.235V. The fault latch resets and the FAULT pin
de-asserts on the falling edge of the ON pin. When ON
goes high again and the cool-off cycle has completed, a
debounce timing cycle is initiated before the HGATE pin
voltage restarts. Toggling the EN pin high and then low
again also resets a fault, but the FAULT pin pulls high at
the end of the debounce cycle before the HGATE pin volt-
Monitor Undervoltage Fault
The ON pin functions as a turn-on control and an input
supply monitor. A resistive divider connected between
the supply diode-OR output (SENSE ) and GND at the
ON pin monitors the supply for undervoltage condition.
The undervoltage threshold is set by proper selection of
the resistors at the ON rising threshold voltage (1.235V).
+
For Figure 1, if R1 = 2k, R2 = 13.7k, the input supply
undervoltage threshold is set to 9.7V.
age starts up. Bringing all the supplies below the INTV
CC
undervoltage lockout threshold (2.2V) shuts off all the
MOSFETs and resets the fault latch. A debounce cycle is
4236f
15
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LTC4236
applicaTions inForMaTion
An undervoltage fault occurs if the diode-OR output sup-
ply falls below its undervoltage threshold. If the ON pin
voltage falls below 1.155V but remains above 0.6V, the
Hot Swap MOSFET is turned off by a 2mA pull-down from
HGATE to ground. The Hot Swap MOSFET turns back on
instantly without the debounce cycle when the diode-OR
output supply rises above its undervoltage threshold.
However, if the ON pin voltage drops below 0.6V, it turns
off the Hot Swap MOSFET and clears the fault latch. The
Hot Swap MOSFET turns back on only after a debounce
cycle when the diode-OR output supply is restored above
its undervoltage threshold.
The PWRGD pin pulls low when the FB power good com-
parator is high and the HGATE drive exceeds 4.2V. The
PWRGD pin goes high when the HGATE is turned off by
theONorENpins, orwhentheFBpowergoodcomparator
drives low, or when INTV enters undervoltage lockout.
CC
Current Sense Monitor
The current through the external sense resistor is moni-
+
tored by LTC4236’s current sense amplifier at the CS
–
and SENSE pins (see Figure 5). The amplifier uses
auto-zeroing circuitry to achieve an offset below 150µV
over temperature, sense voltage and input supply volt-
age. The frequency of the auto-zero clock is 10kHz. An
During the undervoltage fault condition, FAULT will not
be pulled low but PWRGD will be pulled high as HGATE
is pulled low. The ideal diode function controlled by the
ideal diode MOSFET is not affected by the undervoltage
(UV) fault condition.
internal resistor R is connected between the amplifier’s
IN
+
negative input terminal and CS pin. The sense amplifier
loop forces the negative input terminal to have the same
–
potential as SENSE and that develops a potential across
R
IN
to be the same as the sense voltage V
responding current, V
. A cor-
SENSE
Power Good Monitor
/R , will flow through R .
SENSE IN IN
The high impedance inputs of the sense amplifier will not
conduct this input current, allowing it to flow through an
Internal circuitry monitors the MOSFET gate overdrive
between the HGATE and OUT pins. Also, the FB pin that
connects to OUT through a resistive divider is used to
determine a power good condition. The power good
comparator drives high when the FB pin rises above
1.235V, and drives low when FB falls below 1.215V. The
power good status for the input supply is reported via an
open-drain output, PWRGD. It is normally pulled high by
an external pull-up resistor or the internal 10µA pull-up.
internalMOSFETtoaresistorR
connectedbetweenthe
OUT
IMON and GND pins. The IMON output voltage is equal to
(R /R ) • V . The resistor ratio R /R defines
OUT IN
SENSE
OUT IN
the voltage gain of the sense amplifier and is set to 100
with R = 200Ω and R = 20k. Full scale input sense
IN
OUT
voltage to the sense amplifier is 25mV, corresponding to
an output of 2.5V. For input supply voltages greater than
12V
0.1µF
REG
LTC4236
+
SENSE
CS
+
R
IN
V
SENSE
200Ω
–
SENSE
HGATE
0.1µF
10µF
5V
+
REF
V
CC
SCL
SDA
2
IMON
V
OUT
2-WIRE I C
INTERFACE
I
LOAD
OUT
LOAD
IN
LTC2451
–
R
OUT
20k
REF
GND
GND
0.1µF
R
4236 F05
V
= ––––– • V
= 100 • V
SENSE SENSE
OUT
R
IN
Figure 5. High Side Current Monitor with LTC2451 ADC
4236f
16
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LTC4236
applicaTions inForMaTion
5V, the output clamps at 3.5V if the allowable input sense
voltage range is exceeded.
near ground (see Figure 8). CPO starts ramping up 7µs
after INTV clears its undervoltage lockout level. Another
CC
40µs later, DGATE also starts ramping up with CPO. The
CPO ramp rate is determined by the CPO pull-up current
into the combined CPO and DGATE pin capacitances. An
internal clamp limits the CPO pin voltage to 12V above
the IN1 or D2SRC pin, while the final DGATE pin voltage
is determined by the gate drive amplifier. An internal 12V
clamp limits the DGATE1 and DGATE2 pin voltages above
IN1 and D2SRC respectively.
IMON Output Filtering
A capacitor connected in parallel with R
will give a
OUT
low pass response. This will reduce unwanted noise at
the output, and may also be useful as a charge reservoir
to keep the output steady while driving a switching circuit
such as an ADC (see Figure 5). This output capacitor
C
in parallel with R
will create a pole in the output
OUT
response at:
OUT
CPO Capacitor Selection
1
fC =
TherecommendedvalueofthecapacitorbetweentheCPO1
and IN1, and CP02 and D2SRC pins is approximately 10×
2•π•ROUT •COUT
the input capacitance C of the ideal diode MOSFET. A
ISS
REG Pin Bypassing
larger capacitor takes a correspondingly longer time to
chargeupbytheinternalchargepump.Asmallercapacitor
suffers more voltage drop during a fast gate turn-on event
as it shares charge with the MOSFET gate capacitance.
The LTC4236 has an internally regulated supply near
+
SENSE for internal bias of the current sense amplifier. It
is not intended for use as a supply or bias pin for external
circuitry. A 0.1µF capacitor should be connected between
MOSFET Selection
+
theREGandSENSE pins.Thiscapacitorshouldbelocated
The LTC4236 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
very near to the device and close to the REG pin for the
best performance.
on-resistanceR
,themaximumdrain-sourcevoltage
DS(ON)
REG and IMON Start-Up
BV
and the threshold voltage.
DSS
The start-up current of the current sense amplifier when
the LTC4236 is powered on consists of two parts: the
first is the current necessary to charge the REG bypass
capacitor,whichisnominally0.1µF.SincetheREGvoltage
The gate drive for the ideal diode and Hot Swap MOSFET
is guaranteed to be greater than 5V when the supply
voltages at IN1 and IN2 are between 2.9V and 7V. When
the supply voltages at IN1 and IN2 are greater than 7V,
the gate drive is guaranteed to be greater than 10V. The
gate drive is limited to 14V. An external Zener diode can
be used to clamp the potential from the MOSFET’s gate
to source if the rated breakdown voltage is less than 14V.
+
charges to approximately 4.1V below the SENSE voltage,
this can require a significant amount of start-up current.
The second source is the output current that flows into
R , which upon start-up may temporarily drive the
OUT
IMON output high for less than 2ms. This is a temporary
conditionwhichwillceasewhenthesenseamplifiersettles
into normal closed-loop operation.
The maximum allowable drain-source voltage BV
DSS
must be higher than the supply voltage including supply
transientsasthefullsupplyvoltagecanappearacrossthe
MOSFET. If an input or output is connected to ground,
the full supply voltage will appear across the MOSFET.
CPO and DGATE Start-Up
The CPO pin voltage is initially pulled up to a diode below
theIN1orD2SRCpinwhenfirstpoweredup(seeFigure1).
However, for application with back-to-back MOSFETs in
IN2 power path, CPO2 starts off at 0V since D2SRC is
The R
should be small enough to conduct the
DS(ON)
maximumloadcurrent,andalsostaywithintheMOSFET’s
power rating.
4236f
17
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LTC4236
applicaTions inForMaTion
Supply Transient Protection
Assuming the MOSFET dissipates power due to inrush
current charging the load capacitor C at power-up, the
L
When the capacitances at the input and output are very
small, rapid changes in current during input or output
short-circuit events can cause transients that exceed the
24V absolute maximum ratings of the IN and OUT pins.
To minimize such spikes, use wider traces or heavier
trace plating to reduce the power trace inductance. Also,
bypass locally with a 10µF electrolytic and 0.1µF ceramic,
or alternatively clamp the input with a transient voltage
suppressor (Z1, Z2). A 100Ω, 0.1µF snubber damps the
response and eliminates ringing (See Figure 9).
energydissipatedintheMOSFETisthesameastheenergy
stored in the load capacitor, and is given by:
1
2
ECL = • CL • V
IN
2
For C = 680µF, the time it takes to charge up C is cal-
L
L
culated as:
CL • V
IINRUSH
680µF •12V
IN
tCHARGE
=
=
= 8ms
1A
Design Example
The inrush current is set to 1A by adding capacitance C
at the gate of the Hot Swap MOSFET.
HG
As adesignexampleforselecting components, considera
12V system with a 7A maximum load current for the two
supplies (see Figure 1).
CL •IHGATE(UP)
680µF •10µA
CHG
=
=
= 6.8nF
IINRUSH
1A
First, select the appropriate value of the current sense
resistorR forthe12Vsupply. Calculatethesenseresistor
Choose a practical value of 10nF for C .
S
HG
value based on the maximum load current I
and
LOAD(MAX)
TheaveragepowerdissipatedintheMOSFETiscalculatedas:
thelowerlimitforthecurrentlimitsensevoltagethreshold
2
∆V
.
SENSE(TH)(MIN)
ECL
tCHARGE
1
2
680µF • 12V
(
)
PAVG
=
=
•
= 6W
ΔVSENSE(TH)(MIN)
22.5mV
7A
8ms
RS =
=
= 3.2mΩ
ILOAD(MAX)
The MOSFET selected must be able to tolerate 6W for 8ms
duringpower-up.TheSOAcurvesoftheSiR158DPprovide
45W (1.5A at 30V) for 100ms. This is sufficient to satisfy
therequirement. Theincreaseinjunctiontemperaturedue
Choose a 3mΩ sense resistor with a 1% tolerance.
Next, calculate the R of the ideal diode MOSFET to
achievethedesiredforwarddropatmaximumload.Assum-
ing a forward drop, ∆V
DS(ON)
tothepowerdissipatedintheMOSFETis∆T= P • Zth
AVG
JC
of 30mV across the MOSFET:
FWD
where Zth is the junction-to-case thermal impedance.
JC
Under this condition, the SiR158DP data sheet indicates
ΔV
ILOAD(MAX)
30mV
= 4.2mΩ
7A
FWD
RDS(ON)
≤
=
that the junction temperature will increase by 3°C using
Zth = 0.5°C/W (single pulse).
JC
The SiR158DP offers a good choice with a maximum
Next, the power dissipated in the MOSFET during an
overcurrent fault must be safely limited. The fault timer
R
C
of 1.8mΩ at V = 10V. The input capacitance
DS(ON)
GS
of the SiR158DP is about 4980pF. Slightly exceeding
capacitor (C ) is used to prevent power dissipation in
ISS
FT
the 10× recommendation, a 0.1µF capacitor is selected
the MOSFET from exceeding the SOA rating during active
for C2 and C3 at the CPO pins.
current limit. A good way to determine a suitable value
for C is to superimpose the foldback current limit profile
FT
Next, verify that the thermal ratings of the selected Hot
Swap MOSFET are not exceeded during power-up or an
overcurrent fault.
shown in the Typical Performance Characteristics on the
MOSFET data sheet’s SOA curves.
4236f
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LTC4236
applicaTions inForMaTion
For the SiR158DP MOSFET, this exercise yields the plot
⎛
⎞
V
IN(UV)
in Figure 6.
R2 =
R2 =
– 1 • R1
⎜
⎟
V
⎝
⎠
⎞
ON(TH)
100
I
LIMITED
DM
9.7V
1.235V
⎛
– 1 • 2k = 13.7k
⎜
⎝
⎟
1ms
⎠
I
D
LIMITED
10
1
10ms
It remains to select the values for the FB pin resistive
divider in order to set a power good threshold of 10.5V.
KeepinginmindtheFBpin’s 1µAleakagecurrent,choose
a value of 2k for the bottom resistor R3. Calculating the
top resistor R4 value yields:
LIMITED BY R
*
DS(ON)
100ms
1s
10s
TA = 25°C, SINGLE PULSE
MOSFET POWER
0.1
0.01
DISSIPATION CURVE
RESULTING FROM
FOLDBACK ACTIVE
CURRENT LIMIT
DC
⎛
⎞
⎟
VOUT(PG)
R4 =
R4 =
– 1 • R3
⎜
BVDSS LIMITED
10
V
⎝
⎠
⎞
FB(TH)
0.01
0.1
1
100
10.5V
1.235V
⎛
V
– DRAIN-TO-SOURCE VOLTAGE (V)
DS
– 1 • 2k = 15k
⎜
⎝
⎟
4236 F06
⎠
* V > MINIMUM V AT WHICH R IS SPECIFIED
DS(ON)
GS
GS
The subsequent offset error due to the FB pin leakage
current will be less than 0.2%.
Figure 6. SiR158DP SOA with Design Example
MOSFET Power Dissipation Superimposed
The final components to consider are a 0.1µF bypass (C1)
Ascanbeseen,theLTC4236’sfoldbackcurrentlimitprofile
roughly coincides with the 100ms SOA contour. Since
this SOA plot is for an ambient temperature of 25°C only,
a maximum fault timer period of much less than 100ms
should be considered, such as 10ms or less. Selecting a
at the INTV pin and a 0.1µF capacitor (C4) connected
CC
+
between the REG and SENSE pins.
PCB Layout Considerations
To achieve accurate current sensing, a Kelvin connection
for the sense resistor is recommended. The PCB layout
should be balanced and symmetrical to minimize wiring
errors. In addition, the PCB layout for the sense resistor
and the power MOSFET should include good thermal
managementtechniquesforoptimaldevicepowerdissipa-
tion. A recommended PCB layout is illustrated in Figure 7.
0.1µF 10% value for C yields a maximum fault timer
FT
periodof1.75mswhichshouldbesmallenoughtoprotect
the MOSFET during any overcurrent fault scenario.
Next, select the values for the resistive divider at the ON
pin that defines the undervoltage threshold of 9.7V for the
+
12V supply at SENSE . Since the leakage current for the
ON pin can be as high as 1µA, the total resistance in the
divider should be low enough to minimize the resulting
offset error. Calculate the bottom resistor R1 based on
the following equation to obtain less than 0.2% error
due to leakage current.
Connect the IN and OUT pin traces as close as possible to
the MOSFETs’ terminals. Keep the traces to the MOSFETs
wideandshorttominimizeresistivelosses.ThePCBtraces
associated with the power path through the MOSFETs
should have low resistance. The suggested trace width for
1oz copper foil is 0.03" for each ampere of DC current to
keep PCB trace resistance, voltage drop and temperature
rise to a minimum. Note that the sheet resistance of 1oz
copper foil is approximately 0.5mΩ/square, and voltage
drops due to trace resistance add up quickly in high cur-
rent applications.
⎛
⎞
VON(TH)
1.235V
1µA
⎛
⎝
⎞
⎠
R1=
• 0.2% =
• 0.2% = 2.4k
⎜
⎟
⎜
⎟
I
⎝
⎠
IN(LEAK)
Choose R1 to be 2k to achieve less than 0.2% error and
calculating R2 yields:
4236f
19
For more information www.linear.com/LTC4236
LTC4236
applicaTions inForMaTion
VIA TO GND PLANE
•••
Z1
CURRENT FLOW
TO LOAD
M
M
H
D1
PowerPAK SO-8
PowerPAK SO-8
S
D
D
D
D
D
G
S
S
S
R
S
S
S
G
D
D
D
OUT
IN1
W
W
TRACK WIDTH W:
0.03" PER AMPERE
ON 1oz Cu FOIL
•
•
•
CURRENT FLOW
TO LOAD
R
H
•
VIA TO C2 (CPO1) VIA TO IN1
VIA TO DGATE1
M
D2
PowerPAK SO-8
C2
•
S
D
D
D
D
28 27 26 25 24 23
S
S
G
IN2
W
1
2
3
4
5
6
7
8
22
21
20
19
18
17
•
VIA TO C4 (REG)
VIA TO DGATE2
•
•
C1
LTC4236UFD
Z2
•
VIA TO GND PLANE
•••
VIA TO GND PLANE
16
C4
15
+
VIA TO SENSE
9
10 11 12 13 14
C3
4236 F07
•
Figure 7. Recommended PCB Layout for Power MOSFETs and Sense Resistor
It is also important to place the bypass capacitor C1 for
from the 12V backup supply (V ) only when the primary
IN2
the INTV pin, as close as possible between INTV and
supply is unavailable. As long as V is above the 4.7V
CC
CC
IN1
GND. Also place C2 near the CPO1 and IN1 pins, C3 near
threshold set by the R6-R7 divider at the D2OFF pin, M
D2
the CPO2 and D2SRC pins, and C4 near the REG and
and M are turned off, allowing V to be connected to
D3
IN1
+
SENSE pins. The transient voltage suppressors Z1 and
the output through M . The common source terminals of
D1
Z2, when used, should be mounted close to the LTC4236
using short lead lengths.
M
and M are connected to D2SRC pin, which allows
D2 D3
the body-diode of M to reverse block the current flow
D2
from the higher backup supply (V ) to the output. If the
IN2
Power Prioritizer
primary supply fails and V drops below 4.3V, D2OFF is
IN1
allowed to turn on M and M , and connect the V to
D2
D3
IN2
D2
Figure 8 shows an application where the IN1 supply is
passed to the output on the basis of priority, rather than
simply allowing the highest voltage to prevail. This is
achieved by connecting a resistive divider from IN1 at the
D2OFF pin to suppress the turn-on of the back-to-back
the output. When V returns to a viable voltage, M and
IN1
M
D3
turn off, and the output is connected to V . Adding
IN1
R5 in the R6-R7 divider and bypassing it with DSTAT2 pin
control allows the D2OFF pin hysteresis to be increased
from 20mV to 100mV. The resistive divider at the ON pin
ideal diodeMOSFETs, M and M intheIN2 powerpath.
D2
D3
+
sets the SENSE undervoltage threshold to 4.1V.
In this application, the 5V primary supply (V ) is passed
IN1
to the output whenever it is available; power is drawn
4236f
20
For more information www.linear.com/LTC4236
LTC4236
applicaTions inForMaTion
M
D1
SiR818DP
V
IN1
5V
PRIMARY
SUPPLY
Z1
SMAJ15A
M
M
R
M
H
D2
SiR818DP
D3
SiR818DP
S
0.004Ω
SiR818DP
12V
5A
V
IN2
Z2
SMAJ15A
+
12V
BACKUP
BATTERY
+
C
L
470µF
R
H
10Ω
R
HG
1k
C
HG
10nF
C2
0.1µF
R4
4.87k
C3
0.1µF
C4
0.1µF
R2
4.64k
+
+
–
CPO1 IN1 DGATE1 IN2 CPO2 D2SRC DGATE2 REG SENSE CS
SENSE HGATE
OUT
FB
ON
R3
2k
R1
2k
LTC4236
FAULT
PWRGD
DSTAT1
R7
56.2k
D2OFF
ADC
IMON
EN
INTV
CC
GND
DTMR
FTMR
DSTAT2
R6
20k
C5
0.1µF
C1
0.1µF
C
DT
0.1µF
C
FT
0.1µF
R5
2.2k
4236 F08
Figure 8. 2-Channel Power Prioritizer
M
D1
SiR158DP
V
IN1
12V
Z1
SMAJ15A
R
SNUB1
100Ω
C
SNUB1
0.1µF
M
R
M
H
SiR158DP
D2
S
SiR158DP
0.002Ω
V
IN2
12V
10A
12V
Z2
SMAJ15A
R
100Ω
C
SNUB2
+
R
H
10Ω
C
L
SNUB2
0.1µF
220µF
R
1k
C
HG
C2
C3
0.1µF
C4
0.1µF
HG
V
+
SENSE
R4
15k
0.1µF
10nF
R5
2.7k
+
+
–
REG SENSE CS
SENSE
CPO1 IN1 DGATE1
ON
CPO2 D2SRC
IN2 DGATE2
HGATE
OUT
FB
PWREN
R6
D4
R1
10k
R3
2k
2.7k
R7
D3
2.7k
R8
2.7k
FAULT
D2
LTC4236
EN
PWRGD
DSTAT1
DSTAT2
D1
BACKPLANE CARD
CONNECTOR CONNECTOR
ADC
IMON
INTV
GND
D2OFF
DTMR
FTMR
CC
4236 F09
C1
0.1µF
C
DT
0.1µF
C
FT
0.1µF
D1, D2, D3: GREEN LED LN1351C
D4: RED LED LN1261CAL
Figure 9. 12V, 10A Card Resident Application
4236f
21
For more information www.linear.com/LTC4236
LTC4236
Typical applicaTion
Plug-In Card 3.3V Prioritized Power Supply at IN1
M
D1
SiR818DP
V
MAIN
3.3V
Z1
SMAJ13A
M
R
M
H
SiR818DP
D2
SiR818DP
S
0.004Ω
V
3.3V
5A
AUX
3.3V
Z2
SMAJ13A
+
R
H
10Ω
C
L
100µF
R
1k
C
HG
C2
0.1µF
C3
0.1µF
C4
0.1µF
HG
R4
2.37k
10nF
V
+
SENSE
R2
2.21k
+
+
–
CPO1 IN1 DGATE1 CPO2 D2SRC IN2 DGATE2 REG SENSE CS
ON
SENSE
HGATE OUT
R5
10k
FB
R6
10k
R1
2k
R3
2k
C5
0.1µF
R7
10k
LTC4236
FAULT
PWRGD
DSTAT1
EN
R10
28.7k
BACKPLANE CARD
CONNECTOR CONNECTOR
ADC
IMON
D2OFF
GND
INTV
DTMR
FTMR
DSTAT2
CC
R9
20k
C6
0.1µF
C
FT
0.1µF
C1
0.1µF
4236 TA02
R8
2.2k
4236f
22
For more information www.linear.com/LTC4236
LTC4236
package DescripTion
Please refer to http://www.linear.com/product/LTC4236#packaging for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 ±0.05
4.00 ±0.10
(2 SIDES)
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0506 REV B
0.25 ±0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4236f
23
For more information www.linear.com/LTC4236
LTC4236
Typical applicaTion
12V, 5A Backplane Resident Ideal Diode-OR Application with Inrush Current Limiting
M
D1
SiR158DP
V
IN1
12V
BULK
SUPPLY
BYPASS
CAPACITOR
M
R
M
H
D2
S
SiR158DP
0.004Ω
SiR158DP
V
12V
5A
IN2
12V
BULK
+
C
SUPPLY
BYPASS
CAPACITOR
L
R
H
1000µF
10Ω
R
1k
C
HG
C2
0.1µF
C3
0.1µF
C4
0.1µF
HG
10nF
R4
15k
+
–
+
CPO1 IN1 DGATE1 CPO2 D2SRC IN2 DGATE2 REG SENSE
SENSE
HGATE OUT
FB
CS
R2
13.7k
R3
2k
FAULT
PWRGD
DSTAT1
DSTAT2
EN
ON
R1
2k
C5
0.1µF
LTC4236
BACKPLANE PLUG-IN
CARD
ADC
IMON
D2OFF
GND
INTV
DTMR
FTMR
CC
4236 TA03
C
FT
0.1µF
C1
0.1µF
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
Operates from 2.7V to 16.5V, Active Current Limiting, TSOT23-6
LTC4210
LTC4211
LTC4215
LTC4216
LTC4218
LTC4221
LTC4222
LTC4223
LTC4224
LTC4227
LTC4228
LTC4229
LTC4235
Single Channel Hot Swap Controller
Single Channel Hot Swap Controller
Single Channel Hot Swap Controller
Single Channel Hot Swap Controller
Single Channel Hot Swap Controller
Dual Channel Hot Swap Controller
Dual Channel Hot Swap Controller
Dual Supply Hot Swap Controller
Dual Channel Hot Swap Controller
Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8, SO-8 or MSOP-10
2
Operates from 2.9V to 15V, I C Compatible Monitoring, SSOP-16 or QFN-24
Operates from 0V to 6V, Active Current Limiting, MSOP-10 or DFN-12
Operates from 2.9V to 26.5V, Active Current Limiting, SSOP-16 or DFN-16
Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16
2
Operates from 2.9V to 29V, I C Compatible Monitoring, SSOP-36 or QFN-32
Controls 12V and 3.3V, Active Current Limiting, SSOP-16 or DFN-16
Operates from 1V to 6V, Active Current Limiting, MSOP-10 or DFN-10
Dual Ideal Diode and Single Hot Swap Controller Operates from 2.9V to 18V, Controls Three N-Channels, SSOP-16 or QFN-20
Dual Ideal Diode and Hot Swap Controller
Ideal Diode and Hot Swap Controller
Operates from 2.9V to 18V, Controls Four N-Channels, SSOP-28 or QFN-28
Operates from 2.9V to 18V, Controls Two N-Channels, SSOP-24 or QFN-24
Operates from 9V to 14V, Controls Three N-Channels, QFN-20
Dual 12V Ideal Diode-OR and Single Hot Swap
Controller with Current Monitor
LTC4352
LTC4353
LTC4355
LTC4357
Low Voltage Ideal Diode Controller
Operates from 0V to 18V, Controls N-Channel, MSOP-12 or DFN-12
Operates from 0V to 18V, Controls Two N-Channels, MSOP-16 or DFN-16
Dual Low Voltage Ideal Diode Controller
Positive High Voltage Ideal Diode-OR and Monitor Operates from 9V to 80V, Controls Two N-Channels, SO-16, DFN-14 or MSOP-16
Positive High Voltage Ideal Diode Controller
Operates from 9V to 80V, Controls N-Channel, MSOP-8 or DFN-6
4236f
LT 1215 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
LINEAR TECHNOLOGY CORPORATION 2015
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC4236
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