LTC4233 [Linear]
20A Guaranteed SOA Hot Swap Controller;
| 型号： | LTC4233 |
| 厂家： | 
Linear |
| 描述： | 20A Guaranteed SOA Hot Swap Controller |
| 文件： | 总20页 (文件大小：678K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4234
20A Guaranteed SOA
Hot Swap Controller
FEATURES
DESCRIPTION
The LTC®4234 is an integrated solution for Hot Swap™
applications that allows a board to be safely inserted and
removed from a live backplane. The part integrates a
Hot Swap controller, power MOSFET and current sense
resistor in a single package for small form factor applica-
tions.TheMOSFETSafeOperatingAreaisproductiontested
and guaranteed for the stresses in Hot Swap applications.
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Allows Safe Board Insertion into Live Backplane
Small Footprint
4mΩ MOSFET Including R
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SENSE
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Safe Operating Area Guaranteed at 81W, 30ms
Wide Operating Voltage Range: 2.9V to 15V
Adjustable, 11% Accurate Current Limit
Current and Temperature Monitor Outputs
Overtemperature Protection
Adjustable Current Limit Timer Before Fault
Power Good and Fault Outputs
Adjustable Inrush Current Control
2.5% Accurate Undervoltage and Overvoltage Protection
Pin Compatible with LTC4233
The LTC4234 provides separate inrush current control
and an 11% accurate 22.5A current limit with output
dependent foldback. The current limit threshold can be
adjusteddynamicallyusingtheI pin.Additionalfeatures
SET
include a current monitor output that amplifies the sense
resistor voltage for ground referenced current sensing
andaMOSFETtemperaturemonitoroutput.Thermallimit,
overvoltage,undervoltageandpowergoodmonitoringare
alsoprovided.Fora10Acompatibleversion,seeLTC4233.
Available in a 38-Pin (5mm × 9mm) QFN Package
APPLICATIONS
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap and PowerPath are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
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High Availability Servers
Solid State Drives
Industrial
240W, 12V Systems
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TYPICAL APPLICATION
12V, 20A Card Resident Application with Auto-Retry
V
12V
20A
OUT
Power-Up Waveform
V
OUT
FB
12V
DD
+
150k
20k
*
1000µF
107k
UV
V
IN
CONTACT
BOUNCE
10V/DIV
10k
FLT
I
LTC4234
IN
5.23k
10k
0.2A/DIV
OV
PG
–
SENSE
SENSE
GATE
V
OUT
10V/DIV
I
TIMER
INTV
SET
PG
10V/DIV
I
ADC
MON
CC
1µF
GND
20k
4234 TA01a
4234 TA01b
20ms/DIV
*TVS: DIODES INC. SMAJ17A
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For more information www.linear.com/LTC4234
LTC4234
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Supply Voltage (V )................................. –0.3V to 28V
DD
Input Voltages
UV
OV
1
2
38 I
SET
FB, OV, UV ..............................................–0.3V to 12V
37 FB
36 FLT
35 PG
39
I
3
TIMER................................................... –0.3V to 3.5V
MON
V
DD
−
TIMER
4
SENSE , SENSE.....V − 10V or –0.3V to V + 0.3V
DD
DD
–
5
34
33
32
31
30
29
28
27
26
25
24
23
INTV
SENSE
V (DNC)
DD
CC
Output Voltages
V
(DNC)
GND
6
DD
I
, I ................................................. –0.3V to 3V
SET MON
GATE
SENSE
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
7
PG, FLT ................................................. –0.3V to 35V
SENSE (DNC)
OUT
8
OUT ............................................ –0.3V to V + 0.3V
DD
9
INTV .................................................. –0.3V to 3.5V
OUT
10
11
12
13
14
15
16
CC
40
SENSE
GATE (Note 3)........................................ –0.3V to 33V
OUT
OUT
Operating Ambient Temperature Range
OUT
LTC4234C................................................ 0°C to 70°C
LTC4234I .............................................–40°C to 85°C
LTC4234H.......................................... –40°C to 125°C
Junction Temperature (Notes 4, 5)........................ 150°C
Storage Temperature Range .................. –65°C to 150°C
OUT
OUT
OUT
17 18 19 20 21 22
WHH PACKAGE
38-LEAD (5mm × 9mm) PLASTIC QFN
T
= 150°C, θ = 15°C/W
JMAX
JA
EXPOSED PADS (PINS 39 and 40) ARE V AND SENSE
DD
θ
= 15°C/W SOLDERED, OTHERWISE θ = 50°C/W
JA
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC4234CWHH#PBF
LTC4234IWHH#PBF
LTC4234HWHH#PBF
TAPE AND REEL
PART MARKING
4234
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4234CWHH#TRPBF
LTC4234IWHH#TRPBF
LTC4234HWHH#TRPBF
38-Lead (5mm × 9mm) Plastic QFN
38-Lead (5mm × 9mm) Plastic QFN
38-Lead (5mm × 9mm) Plastic QFN
4234
–40°C to 85°C
4234
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4234fa
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LTC4234
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
2.9
TYP
MAX
UNITS
DC Characteristics
l
l
l
V
Input Supply Range
15
3
V
mA
V
DD
I
Input Supply Current
MOSFET On, No Load
1.6
DD
V
Input Supply Undervoltage Lockout
OUT Leakage Current
V
Rising
2.63
2.73
2.85
DD(UVL)
OUT
DD
l
l
I
V
V
= V
= V
= 0V, V = 15V
0
2
700
4
µA
µA
OUT
OUT
GATE
GATE
DD
= 12V
1
l
dV
/dt
OUT Turn-On Ramp Rate
GATE Open
0.15
0.35
0.6
V/ms
GATE
l
l
R
MOSFET + Sense Resistor On-Resistance C-Grade, I-Grade
H-Grade
2.3
2.3
4.0
4.0
7.2
8.2
mΩ
mΩ
ON
l
l
l
I
Current Limit Threshold
V
V
V
= 1.35V, I Open
20
4
22.5
5.7
11.1
25
7.4
12.8
A
A
A
LIM(TH)
FB
FB
FB
SET
= 0V, I Open
SET
= 1.35V, R = 20k
9.4
SET
2
SOA
MOSFET Safe Operating Area
13.5V, 6A Folded Back, 200W s (Note 6)
7.5V, 22A Onset of Foldback, 200W s (Note 7)
30
7
ms
ms
2
Inputs
l
l
l
l
l
l
l
l
I
I
OV, UV, FB Input Current
V = 1.2V
0
4
1
10
µA
µA
V
IN
SENSE (IN)
−
−
−
SENSE Input Current
V
V
= 12V
SENSE
V
OV, UV, FB Threshold Voltage
OV Hysteresis
Rising
1.205
10
1.235
20
1.265
30
TH
PIN
mV
mV
V
∆V
∆V
V
OV(HYST)
UV(HYST)
UV(RTH)
UV Hysteresis
50
80
110
0.7
30
UV Reset Threshold Voltage
FB Power Good Hysteresis
V
Falling
0.55
10
0.62
20
UV
mV
kΩ
∆V
R
FB(HYST)
I
Internal Resistor
SET
19
20
21
ISET
Outputs
l
l
l
l
l
l
l
l
l
V
V
INTV Output Voltage
V
= 5V,15V, I = 0mA, –10mA
LOAD
2.8
3.1
0.4
0
3.3
0.8
V
V
INTVCC
OL
CC
DD
PG, FLT Output Low Voltage
PG , FLT Input Leakage Current
TIMER High Threshold
I = 2mA
V = 30V
I
10
µA
V
OH
V
V
V
V
V
V
Rising
Falling
= 0V
1.2
0.1
–80
1.4
1.6
4.5
1.235
0.21
–100
2
1.28
0.3
TIMER(H)
TIMER(L)
TIMER
TIMER
TIMER
TIMER
TIMER Low Threshold
V
I
I
I
TIMER Pull-Up Current
–120
2.6
µA
µA
%
TIMER(UP)
TIMER(DN)
TIMER(RATIO)
TIMER Pull-Down Current
= 1.2V
TIMER Current Ratio I
/I
2
2.7
TIMER(DN) TIMER(UP)
A
I
I
I
Current Gain
Bandwidth
5
5.25
µA/A
kHz
µA
µA
µA
mA
IMON
MON
MON
MON
BW
250
0
IMON
l
l
l
I
I
I
I
Offset Current
I
= 600mA
OUT
9
OFF(IMON)
GATE(UP)
GATE(DN)
GATE(FST)
Gate Pull-Up Current
Gate Drive On, V
Gate Drive Off, V
= V
= 12V
OUT
–18
180
–24
250
140
–29
500
GATE
Gate Pull-Down Current
= 18V, V
= 12V
GATE
OUT
Gate Fast Pull-Down Current
Fast Turn Off, V
= 18V, V
= 12V
GATE
OUT
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LTC4234
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC Characteristics
l
l
l
t
t
Input High (OV), Input Low (UV) to GATE
Low Propagation Delay
V
< 17.8V Falling
8
1
20
5
µs
µs
PHL(GATE)
PHL(ILIM)
GATE
−
Short Circuit to GATE Low
V
= 0, Step V − SENSE to 50mV, V
<
GATE
FB
DD
15V Falling
Step V to 2V, V > 13V
GATE
t
t
t
t
Turn-On Delay
24
48
1
72
ms
µs
D(ON)
UV
UV Low to Clear Fault Latch Delay
Circuit Breaker Filter Delay Time (Internal)
Cool Down Delay (Internal)
D(FAULT)
D(CB)
−
l
l
V
= 0, Step V − SENSE to 50mV
1.2
2
2.7
ms
ms
FB
DD
600
900
1200
D(COOL_DOWN)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: T is calculated from the ambient temperature, T , and power
J
A
dissipation, P , according to the formula:
D
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
T = T + (P • 15°C/W)
Note 6: SOA tested at room temperature. SOA (i.e. P t), is reduced at
elevated temperatures according to the following formula:
J
A
D
2
Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V
above OUT. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
2
150°C–TJ
150°C–25°C
2
P2t T = 200 W s •
(
)
J
2
2
Note 7: Guaranteed by design and extrapolated from P t limit of 200W s.
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LTC4234
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 12V unless otherwise noted.
UV Low-High Threshold
vs Temperature
IDD vs VDD
INTVCC Load Regulation
2.2
1.8
1.4
1.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.240
1.236
1.232
1.228
V
= 5V
DD
125°C
25°C
V
= 3.3V
DD
–40°C
1.224
0
5
10
15
(V)
20
25
30
0
–2
–4
–6
–8 –10 –12 –14
(mA)
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
V
I
DD
LOAD
4234 G02
4234 G01
4234 G03
Timer Pull-Up Current
vs Temperature
Current Limit Delay
UV Hysteresis vs Temperature
(tPHL(ILIM) vs Overdrive)
1000
100
10
0.10
0.08
0.06
0.04
–110
–105
–100
–95
1
0.1
–90
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
20
40
60
80
100
120
OUTPUT CURRENT (A)
4234 G06
4234 G04
4234 G05
Current Limit Adjustment
(IOUT vs RSET
Current Limit Threshold Foldback
)
RISET vs Temperature
25
20
15
10
25
20
15
10
5
22
21
20
19
5
0
>30ms SOA GUARANTEED
0
18
0
0.4
0.6
0.8
1.0
1.2
1k
10k
100k
(Ω)
1M
10M
0.2
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
R
SET
FB VOLTAGE (V)
4234 G08
4234 G07
4234 G09
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LTC4234
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 12V unless otherwise noted.
SOA Constant vs Junction
RON vs VDD and Temperature
Temperature
Guaranteed MOSFET SOA Curve
1.0
0.8
0.6
0.4
0.2
0
100
8
6
4
2
T = 25°C
A
SINGLE PULSE
V
= 3.3V TO 12V
DD
3ms
>30ms SOA
GUARANTEED
10
1
30ms
DC
0
0.1
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
25
50
75
100
125
150
0.1
1
10
100
V
(V)
JUNCTION TEMPERATURE (°C)
DS
4234 G11
4234 G10
4234 G17
GATE Pull-Up Current
vs Temperature
PG, FLT VOUT Low vs ILOAD
I
MON vs Temperature and VDD
14
12
10
8
105
–25.0
–24.5
–24.0
–23.5
V
LOAD
= 3.3V TO 12V
DD
I
= 20A
100
95
6
90
85
80
4
2
0
–23.0
50
TEMPERATURE (°C)
8
12
–50 –25
0
25
75 100 125 150
0
2
4
6
10
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
CURRENT (mA)
4234 G13
4234 G12
4234 G14
Gate Drive vs GATE Pull-Up
Current
Gate Drive vs VDD
VISET vs Temperature
7
6.2
6.0
5.8
5.6
5.4
5.2
0.9
0.8
0.7
0.6
0.5
0.4
0.2
V
= 12V
DD
6
5
4
3
2
1
0
V
= 3.3V
DD
75 100
0
–5
–10
–15
–20
–25
–30
0
5
10
15
(V)
20
25
30
–50 –25
0
25 50
125 150
I
(µA)
V
TEMPERATURE (°C)
GATE
DD
4234 G15
4234 G16
4234 G18
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LTC4234
PIN FUNCTIONS
DNC: Do Not Connect. Leave open.
OV: Overvoltage Comparator Input. Connect this pin to an
external resistive divider from V . If the voltage at this
DD
FB: Foldback and Power Good Input. Connect this pin to
an external resistive divider from OUT. If the voltage falls
below 0.6V, the current limit is reduced using a foldback
profile (see the Typical Performance Characteristics sec-
tion). If the voltage falls below 1.21V, the PG pin will pull
low to indicate the power is bad
pin rises above 1.235V, an overvoltage is detected and
the switch turns off. Tie to GND if unused.
PG: Power Good Indicator. Open-drain output pulls low
when the FB pin drops below 1.21V indicating the power
is bad. If the voltage at FB rises above 1.235V and the
GATE-to-OUT voltage exceeds 4.2V, the open-drain pull-
down releases the PG pin to go high.
FLT: Overcurrent Fault Indicator. Open-drain output pulls
low when an overcurrent fault has occurred and the circuit
breaker trips. For overcurrent auto-retry tie to UV pin (see
Applications Information section for details).
SENSE: Current Sense Node and MOSFET Drain. One
exposed pad on the UH package is connected to SENSE
and should be soldered to an electrically isolated printed
circuit board trace to properly transfer the heat out of the
GATE: Gate Drive for Internal N-Channel MOSFET. An
internal 24µA current source charges the gate of the
N-channel MOSFET. At start-up the GATE pin ramps up
at a 0.35V/ms rate determined by internal circuitry. Dur-
ing an undervoltage or overvoltage condition a 250µA
pull-down current turns the MOSFET off. During a short
circuit or undervoltage lockout condition, a 140mA pull-
down current source between GATE and OUT is activated.
–
package. Connect the SENSE pin 31 to the SENSE pin 34.
−
SENSE : Current Limit and Current Monitor Amplifier
Input. The current limit circuit controls the GATE pin to
–
limit the voltage between the V and SENSE pins to
DD
15mV (22.5A) or less depending on the voltage at the FB
pin. This pin must be connected to SENSE pin on the right
side (connect Pin 34 to Pin 31).
GND: Device Ground.
TIMER: Current Limit Timer Input. Connect a capacitor
between this pin and ground to set a 12ms/µF duration for
current limit before the switch is turned off. If the UV pin
is toggled low while the MOSFET switch is off, the switch
will turn on again following cool down time of 4.14s/µF
I
: Current Monitor Output. The current in the internal
MON
MOSFET switch is divided by 200,000 and sourced from
this pin. Placing a 20k resistor on this pin allows a 0V to
2V voltage swing when current ranges from 0A to 20A.
INTV : Internal 3.1V Supply Decoupling Output. This pin
duration. Tie thispintoINTV forafixed2msovercurrent
CC
CC
musthavea1.0µForlargerbypasscapacitor. Overloading
delay and 900ms cool down time.
this pin can disrupt internal operation.
UV: Undervoltage Comparator Input. Tie high to INTV
CC
I
:CurrentLimitAdjustmentPin. For 22.5Acurrentlimit
if unused. Connect this pin to an external resistive divider
SET
value, open this pin. This pin is driven by a 20k resistor
in series with a voltage source. The pin voltage is used
to generate the current limit threshold. The internal 20k
resistor (R ) and an external resistor (R ) between
from V . If the UV pin voltage falls below 1.15V, an un-
DD
dervoltageisdetectedandtheswitchturnsoff.Pullingthis
pin below 0.62V resets the overcurrent fault and allows
the switch to turn back on (see Application Information
section for details). If overcurrent auto-retry is desired
then tie this pin to the FLT pin.
ISET
SET
I
and ground create an attenuator that lowers the
SET
current limit value. Due to circuit tolerance R
should
SET
not be less than 2k. In order to match the temperature
variation of the sense resistor, the voltage on this pin is
made proportional to temperature of the MOSFET switch.
V : Supply Voltage and Current Sense Input. This ex-
DD
posed pad must be soldered to input power. V has an
DD
undervoltage lockout threshold of 2.73V.
OUT: Output of Internal MOSFET Switch. Connect this pin
directly to the load.
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LTC4234
FUNCTIONAL BLOCK DIAGRAM
SENSE
(EXPOSED PAD)
GATE
0.7mΩ
SENSE RESISTOR
3.3mΩ
MOSFET
6.1V
V
DD
OUT
(EXPOSED PAD)
I
I
MON
SET
CLAMP
–
SENSE
CHARGE
PUMP
AND GATE
DRIVER
f = 2MHz
–
+
R
ISET
20k
CS
INRUSH
0.6V POSITIVE
+–
0.35V/ms
TEMPERATURE
COEFFICIENT
REFERENCE
X1
FB
CM
FOLDBACK
0.6V
+
–
1.235V
0.62V
+
–
UV
RST
OV
PG
UV
1.235V
LOGIC
PG
+
–
0.21V
+
FLT
TM1
INTV
CC
–
OV
+
–
100µA
1.235V
2µA
+
V
DD
TM2
V
–
DD
1.235V
–
3.1V
GEN
INTV
UVLO1
CC
2.73V
+
–
+
UVLO2
TIMER
2.65V
4234 BD
GND
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LTC4234
OPERATION
The Functional Diagram displays the main circuits of the
device. The LTC4234 is designed to turn a board’s supply
voltageonandoffinacontrolledmannerallowingtheboard
to be safely inserted and removed from a live backplane.
The LTC4234 includes a 3.3mΩ MOSFET and a 0.7mΩ
currentsenseresistor. Duringnormaloperation,thecharge
pump and gate driver turn on the pass MOSFET’s gate to
provide power to the load. The inrush current control is
accomplished by the INRUSH circuit. This circuit limits
the GATE ramp rate to 0.35V/ms and hence controls the
voltage ramp rate of the output capacitor.
0.21V(ComparatorTM1)whichcompletesonetimercycle.
After eight TIMER pin cycles (ramping to 1.235V and then
below 0.21V) the logic starts the internal 48ms timer. At
this point, the pass transistor has cooled and it is safe
to turn it on again. It is suitable in many applications to
use an internal 2ms overcurrent timer with a 900ms cool
down period. Tying the TIMER pin to INTV sets this
CC
default timing. Latchoff is the normal operating condition
following overcurrent turnoff. Retry is initiated by pulling
the UV pin low for a minimum of 1µs then high. Auto-retry
is implemented by tying the FLT to the UV pin.
Thecurrentsense(CS)amplifiermonitorstheloadcurrent
usingthevoltagesensedacrossthecurrentsenseresistor.
The CS amplifier limits the current in the load by reduc-
ing the GATE-to-OUT voltage in an active control loop. It
is simple to adjust the current limit threshold using the
The output voltage is monitored using the FB pin and the
PG comparator to determine if power is available for the
load. The power good condition is signaled by the PG pin
using an open-drain pull-down transistor.
The Functional Diagram shows the monitoring blocks of
theLTC4234. Thetwocomparatorsontheleftsideinclude
the UV and OV comparators. These comparators are used
to determine if the external conditions are valid prior to
turning on the MOSFET. But first the undervoltage lockout
circuits UVLO1 and UVLO2 must validate the input supply
current limit adjustment (I ) pin. This allows a different
SET
threshold during other times such as start-up. Note there
−
must be a connection between SENSE to SENSE (Pin 34
to Pin 31) in order to monitor current.
A short circuit on the output to ground causes significant
power dissipation during active current limiting. To limit
this power, the foldback amplifier reduces the current
limit value from 22.5A to 5.7A in a linear manner as the
FB pin drops below 0.6V (see the Typical Performance
Characteristics).
and the internally generated 3.1V supply (INTV ) and
CC
generate the power up initialization to the logic circuits. If
theexternalconditionsremainvalidfor48mstheMOSFET
is allowed to turn on.
Other monitoring features include MOSFET current and
temperaturemonitoring.Thecurrentmonitor(CM)outputs
a current proportional to the sense resistor current. This
current can drive an external resistor or other circuits for
monitoring purposes. A voltage proportional to the MOS-
If an overcurrent condition persists, the TIMER pin ramps
up with a 100µA current source until the pin voltage
exceeds 1.235V (comparator TM2). This indicates to the
logic that it is time to turn off the pass MOSFET to prevent
overheating. At this point the TIMER pin ramps down
usingthe2µAcurrentsourceuntilthevoltagedropsbelow
FET temperature is output to the I pin. The MOSFET is
SET
protected by a thermal shutdown circuit.
4234fa
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LTC4234
APPLICATIONS INFORMATION
The typical LTC4234 application is in a high availability
system that uses a positive voltage supply to distribute
powertoindividualcards.Thecompleteapplicationcircuit
is shown in Figure 1. External component selection is
discussed in detail in the following sections.
range. All of these conditions must be satisfied for a du-
ration of 48ms to ensure that any contact bounce during
the insertion has ended.
The MOSFET is turned on by charging up the GATE with a
charge pump generated 24µA current source whose value
is adjusted by shunting a portion of the pull-up current to
ground. The charging current is controlled by the INRUSH
circuit that maintains a constant slope of GATE voltage
versus time (Figure 2). The voltage at the GATE pin rises
with a slope of 0.35[V/ms] and the supply inrush current
is set at:
Turn-On Sequence
Several conditions must be present before the internal
pass MOSFET can be turned on. First the supply V must
DD
exceed its undervoltage lockout level. Next the internally
generated supply INTV must cross its 2.65V undervolt-
CC
agethreshold.Thisgeneratesa25µspower-on-resetpulse
I
= C • 0.35[V/ms]
INRUSH L
whichclearsthefaultregisterandinitializesinternallatches.
This gate slope is designed to charge up a 1000µF capaci-
tor to 12V in 34ms, with an inrush current of 350mA. This
After the power-on-reset pulse, the UV and OV pins must
indicate that the input voltage is within the acceptable
V
12V
10A
OUT
V
OUT
12V
DD
+
R5
C
COMP
C
Z1*
L
150k
3.3nF
R3
680µF
FB
140k
R6
20k
UV
FLT
OV
GATE
R
R1
GATE
100k
C
0.1µF
226k
R7
10k
UV = 9.88V
OV = 15.2V
PG = 10.5V
GATE
R2
20k
R4
20k
LTC4234
PG
ISET
–
SENSE
SENSE
R
SET
20k
TIMER
INTV
IMON
ADC
CC
C
C1
1µF
T
R
GND
MON
0.1µF
20k
4234 F01
*TVS Z1: DIODES INC. SMAJ17A
Figure 1. 10A, 12V Card Resident Application
V
DD
+ 6.15V
GATE
SLOPE = 0.35[V/ms]
V
DD
OUT
4234 F02
t
1
t
2
Figure 2. Supply Turn-On
4234fa
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For more information www.linear.com/LTC4234
LTC4234
APPLICATIONS INFORMATION
allows the inrush current to stay under the folded back
currentlimitthreshold(5.7A)forcapacitorslessthan10mF.
IncludedintheTypicalPerformanceCharacteristicssection
is a graph of the Safe Operating Area for the MOSFET. It
is evident from this graph that the power dissipation at
12V, 350mA for 34ms is in the safe region.
GATE
OPTIONAL
C
P
RC TO LOWER
2.2nF
INRUSH CURRENT
LTC4234
4234 F03
Figure 3. Compensation for Small CLOAD
Addingacapacitoranda100kseriesresistorfromGATEto
groundwilllowertheinrushcurrentbelowthedefaultvalue
Turn-Off Sequence
set by the INRUSH circuit. The 3.3nF capacitor, C
, is
COMP
necessary to compensate the current limit regulation loop
when the R and C network is on the GATE pin.
The switch can be turned off by a variety of conditions. A
normal turn-off is initiated by the UV pin going below its
1.235V threshold. Additionally, several fault conditions
will turn off the switch. These include an input overvolt-
GATE
GATE
The GATE is charged with a 24µA current source (when
the INRUSH circuit is not driving the GATE). The voltage
–
at the GATE pin rises with a slope equal to 24µA/C
and the supply inrush current is set at:
GATE
age (OV pin), overcurrent circuit breaker (SENSE pin) or
overtemperature. Normally the switch is turned off with a
250µA current pulling down the GATE pin to ground. With
the switch turned off, the OUT voltage drops which pulls
the FB pin below its threshold. The PG then pulls low to
indicate output power is no longer good.
CL
CGATE
I
=
•24µA
INRUSH
When the GATE voltage reaches the MOSFET threshold
voltage, the switch begins to turn on and the OUT volt-
age follows the GATE voltage as it increases. Once OUT
If V drops below 2.65V for greater than 5µs or INTV
DD
CC
drops below 2.5V for greater than 1µs, a fast shut down
of the switch is initiated. The GATE is pulled down with a
140mA current to the OUT pin.
reaches V , the GATE will ramp up until clamped by the
DD
6.1V Zener between GATE and OUT.
As the OUT voltage rises, so will the FB pin which is moni-
toring it. Once the FB pin crosses its 1.235V threshold
and the GATE to OUT voltage exceeds 4.2V, the PG pin
will cease to pull low and indicate that the power is good.
Overcurrent Fault
The LTC4234 features an adjustable current limit with
foldback that protects against short circuits and exces-
sive load current. To protect against excessive power
dissipation in the switch during active current limit, the
available current is reduced as a function of the output
voltage sensed by the FB pin. A graph in the Typical Per-
formance Characteristics curves shows the Current Limit
Threshold Foldback.
Parasitic MOSFET Oscillation
When the N-channel MOSFET ramps up the output during
power-up it operates as a source follower. The source fol-
lowerconfigurationmayself-oscillateintherangeof25kHz
to 300kHz when the load capacitance is less than 10µF,
especially if the wiring inductance from the supply to V
DD
Anovercurrentfaultoccurswhenthecurrentlimitcircuitry
has been engaged for longer than the timeout delay set
by the TIMER. Current limiting begins when the MOSFET
currentreaches5.7Ato22.5A(dependingonthefoldback).
The GATE pin is then brought down with a 140mA GATE-
to-OUT current. The voltage on the GATE is regulated in
order to limit the current to 22.5A. At this point, a circuit
breaker time delay starts by charging the external timing
capacitor with a 100µA pull-up current from the TIMER
pin is greater than 3µH. The possibility of oscillations will
increase as the load current (during power-up) increases.
There are two ways to prevent this type of oscillation. The
simplest way is to avoid load capacitances below 10µF.
For wiring inductances larger than 20µH, the minimum
load capacitance may extend to 100µF. A second choice
is to connect an external gate capacitor C > 1.5nF as
P
shown in Figure 3.
4234fa
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For more information www.linear.com/LTC4234
LTC4234
APPLICATIONS INFORMATION
pin. If the TIMER pin reaches its 1.235V threshold, the
internal switch turns off (with a 250µA current from
GATE to ground). Included in the Typical Performance
Characteristics curves is a graph of the Safe Operating
Area for the MOSFET. From this graph one can determine
the MOSFET’s maximum time in current limit for a given
output power.
V
OUT
10V/DIV
I
OUT
5A/DIV
∆V
GATE
10V/DIV
TIMER
2V/DIV
Tying the TIMER pin to INTV will force the part to use
CC
the internally generated (circuit breaker) delay of 2ms.
In either case the FLT pin is pulled low to indicate an
overcurrent fault has turned off the pass MOSFET. For a
given circuit breaker time delay, the equation for setting
the timing capacitor’s value is as follows:
4234 F04
1ms/DIV
Figure 4. Short-Circuit Waveform
Current Limit Adjustment
The default value of the active current limit is 22.5A. The
current limit threshold can be adjusted lower by placing
C = t • 0.083[µF/ms]
T
CB
After the switch is turned off, the TIMER pin begins dis-
charging the timing capacitor with a 2µA pull-down cur-
rent. When the TIMER pin reaches its 0.21V threshold, it
completes one timer cycle. After eight TIMER pin cycles
(ramping to 1.235V and then below 0.21V) plus the 48ms
debounce time, the switch is allowed to turn on again if
the overcurrent fault latch has been cleared. Bringing the
UV pin below 0.6V for a minimum of 1µs and then high
a resistor between the I pin and ground. As shown in
SET
the Functional Block Diagram the voltage at the I
pin
SET
(viatheclampcircuit)setstheCSamplifier’sbuilt-inoffset
voltage. This offset voltage directly determines the active
current limit value. With the I
pin open, the voltage
pin is determined by a positive temperature
SET
at the I
SET
coefficient reference. This voltage is set to 0.618V which
corresponds to a 22.5A current limit at room temperature.
will clear the fault latch. If the TIMER pin is tied to INTV
CC
An external resistor R placed between the I pin and
SET
SET
thentheswitchisallowedtoturnonagain(afteraninternal
900ms cool down time plus the 48ms debounce time), if
the overcurrent fault latch is cleared.
groundformsaresistivedividerwiththeinternal20kR
ISET
sourcing resistor. The divider acts to lower the voltage at
theI pinandthereforelowerthecurrentlimitthreshold.
SET
Tying the FLT pin to the UV pin allows the part to self-clear
the fault and turn the MOSFET on as soon as TIMER pin
has ramped below 0.21V for the eighth time followed by
the 48ms debounce time. In this auto-retry mode the
LTC4234 repeatedly tries to turn on after an overcurrent
at a period determined by the capacitor on the TIMER pin.
The auto retry mode also functions when the TIMER pin
The overall current limit threshold precision is reduced to
15% when using a 20k resistor to halve the threshold.
Using a switch (connected to ground) in series with R
SET
allows the active current limit to change only when the
switch is closed. This feature can be used to program a
reduced running current while the maximum available
current limit is used at start-up.
is tied to INTV .
CC
Monitor MOSFET Temperature
The waveform in Figure 4 shows how the output latches
off following a short-circuit. The current in the MOSFET
is 5.7A as the TIMER pin ramps up.
The voltage at the I pin increases linearly with increas-
SET
ing temperature. The temperature profile of the I pin is
SET
shownintheTypicalPerformanceCharacteristicssection.
4234fa
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For more information www.linear.com/LTC4234
LTC4234
APPLICATIONS INFORMATION
Using a comparator or ADC to measure the I
voltage
to turn off the MOSFET when the V voltage exceeds
DD
SET
providesanaccurateindicationoftheMOSFETtemperature.
15.2V. If the V pin subsequently falls back below 14.9V,
DD
The I voltage follows the formula:
the switch will be allowed to turn on immediately. In the
LTC4234 the OV pin threshold is 1.235V when rising, and
1.215V when falling out of overvoltage.
SET
RSET
V
=
•(T+273°C)•2.093[mV/°C]
ISET
RSET +RISET
TheMOSFETtemperatureiscalculatedusingR
The UV pin functions as an undervoltage protection pin
or as an “ON” pin. In the Figure 1 application the MOS-
of20k.
ISET
FET turns off when V falls below 9.23V. If the V pin
DD
DD
R
+20k •V
(
)
SET
ISET
subsequently rises above 9.88V for 48ms, the switch will
be allowed to turn on again. The LTC4234 UV turn-on/off
threshold are 1.235V (rising) and 1.155V (falling).
T =
–273°C
RSET •2.093[mV/°C]
When R is not present, T becomes:
SET
Inthecaseofanundervoltageorovervoltage,theMOSFET
turnsoffandthereisindicationonthePGstatuspin. When
the overvoltage is removed, the MOSFET’s gate ramps up
immediately at the rate determined by the INRUSH circuit.
V
ISET
T =
–273°C
2.093[mV/°C]
There is an overtemperature circuit in the LTC4234 that
monitorsaninternalvoltagesimilartotheI pinvoltage.
SET
Power Good Indication
When the die temperature exceeds 155°C the circuit turns
In addition to setting the foldback current limit threshold,
the FB pin is used to determine a power good condition.
The Figure 1 application uses an external resistive divider
on the OUT pin to drive the FB pin. On the LTC4234 the
PG comparator drives high when the FB pin rises above
1.235V and low when it falls below 1.215V.
off the MOSFET until the temperature drops to 135°C.
Monitor MOSFET Current
The current in the MOSFET passes through an internal
0.7mΩsense resistor. The voltageon thesense resistoris
converted to a current that is sourced out of the I
pin.
MON
Once the PG comparator is high the GATE pin voltage is
monitored with respect to the OUT pin. Once the GATE
minus OUT voltage exceeds 4.2V the PG pin goes high.
This indicates to the system that it is safe to load the OUT
pin while the MOSFET is completely turned “on”. The PG
pin goes low when the GATE is commanded off (using
The gain of I
amplifier is 5µA/A referenced from the
SENSE
MOSFET current. This output current can be converted to
a voltage using an external resistor to drive a comparator
or ADC. The voltage compliance for the I
pin is from
MON
0V to INTV − 0.7V.
CC
A microcontroller with a built-in comparator can build a
simple integrating single-slope ADC by resetting a capaci-
tor that is charged with this current. When the capacitor
voltage trips the comparator and the capacitor is reset, a
timer is started. The time between resets will indicate the
MOSFET current.
–
the UV, OV or SENSE pins) or when the PG comparator
drives low.
Design Example
Consider the following design example (Figure 5):
T = 60°C, V = 12V, I
= 20A. I = 350mA,
OVOFF PGTHRESHOLD
A
IN
MAX
=9.88V,V
INRUSH
=15.2V,V
C =1000µF,V
L
UVON
Monitor OV and UV Faults
= 10.5V. A current limit fault triggers an automatic restart
of the power-up sequence.
Protecting the load from an overvoltage condition is the
main function of the OV pin. In Figure 1 an external resis-
tive divider (driving the OV pin) connects to a comparator
4234fa
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For more information www.linear.com/LTC4234
LTC4234
APPLICATIONS INFORMATION
V
12V
20A
OUT
The maximum power for 34ms can be calculated from
the derated constant:
V
OUT
12V
DD
+
Z1*
140k
R5
150k
C
L
LTC4234
1000µF
UV
FB
2
P2t T = 60°C
104 W s
R1
226k
R6
20k
FLT
(
)
=
R
J
T
PMAX
=
= 55W
10k
OV
τ
34ms
UV = 9.88V
OV = 15.2V
PG = 10.5V
R2
R4
PG
–
20k 20k
SENSE GATE
I
Therefore the power dissipation at charge-up is within
the MOSFET SOA.
SENSE
TIMER
SET
INTV
CC
I
MON
ADC
Next the power dissipated in the MOSFET during overcur-
rent must be limited. The active current limit uses a timer
to prevent excessive energy dissipation in the MOSFET.
Theworst-casepowerdissipationoccurswhenthevoltage
versus current profile of the foldback current limit is at the
maximum. This occurs when the current is 25A and the
C
C1
R
T
GND
MON
68nF
1µF
20k
4234 F05
*TVS Z1: DIODES INC. SMAJ17A
Figure 5. 20A, 12V Card Resident Application
The inrush current is defined by the current required to
chargetheoutputcapacitorusingthefixed0.35V/msGATE
charge up rate. The inrush current is defined as:
voltage is one-half of the V or 6V. See the Current Limit
IN
Threshold Foldback in the Typical Performance Charac-
teristics section to view this profile. In order to survive
150W, theMOSFETSOAdictatesamaximumcurrentlimit
timeout. If the MOSFET operating temperature is elevated
prior to current limit the SOA constant must be derated
according to the formula:
0.35V
ms
0.35V
ms
I
INRUSH =CL •
=1000µF •
=350mA
As mentioned previously the charge-up time is the output
voltage (12V) divided by the output rate of 0.35V/ms
resulting in 34ms. The peak power dissipation of 12V at
350mA (or 4.2W) must not exceed the SOA of the pass
MOSFET for 34ms (see MOSFET SOA graph in the Typical
PerformanceCharacteristics).OntheSOAgraphthe30ms
150°C–TJ
150°C–25°C
2
P2t T =P2t 25°C •
(
)
( )
J
T is calculated from the ambient temperature, package
J
2
thermal impedance (θ ) and the I R heating:
JA
line crosses the 10V V vertical line at 8A. This verifies
DS
2
2
that the 80W for 30ms is safe at room temperature. Each
T = (θ • I • R ) + T = 15°C/W • (20A) • 7.2mΩ
J
JA
ON
A
single point on the 8ms and 30ms lines represent a power
+ 60°C = 103˚C
2
(voltage times current) and time that follow a constant P t
Use the SOA derating formula:
2
2
relationship of 200W s. This constant P t number is valid
2
2
2
for power pulses less than 50ms. Beyond 50ms the P t
P t T =103°C =200 W S •
(
)
J
number will depend on the thermal characteristics of the
board. If the MOSFET junction temperature is elevated,
2
2
150°C–103°C
150°C–25°C
2
then the P t constant must be derated. At T = 60°C the
J
= 28 W S
new constant becomes:
2
2
150°C–60°C
150°C–25°C
So the SOA constant is derated to 28 W s. The maximum
currentlimittimeoutiscalculatedfromtherevisedconstant
and the 150 W dissipated in current limit:
2
2
P t T = 60°C = 200 W s •
=
(
)
J
2
104 W s
2
P2t T =103°C
28 W S
(
)
=
J
tMAX
=
=1.2ms
2
P2
150W
4234fa
14
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LTC4234
APPLICATIONS INFORMATION
Therefore it is acceptable to set the current limit timeout
using C to be 0.8ms:
T
0.8ms
CT =
= 68nF
12 ms/µF
[
]
To configure the LTC4234 for auto retry after overcurrent
SENSE
OUT
fault, connect the FLT to the UV pin.
V
V
DD
DD
C1
After the 0.8ms timeout the FLT pin pulls down on the UV
pin restart the power-up sequence.
The values for overvoltage, undervoltage and power good
thresholds using the resistive dividers on the UV, OV and
FB pins match the requirements of turn-on at 9.88V and
turn-off at 15.2V.
GND
The final schematic in Figure 5 results in very few external
components. The pull-up resistor, R7, connects to the PG
4234 F06
pin while the 20k (R
voltage at a ratio:
) converts the I
current to a
MON
MON
Figure 6. Recommended Layout
V
= 5[µA/A] • 20k • I
= 0.1[V/A] • I
During normal operation the power dissipated in the
MOSFET could be as high as 2.9W. To remove this heat
solder the SENSE exposed pad to a copper trace that
contains vias underneath the pad. The OUT pins conduct
substantial heat from the MOSFET. Connect all the OUT
pinstoaplaneof1ozcopper. Sincethetracethatconnects
OUT pins must accommodate high current, this area of
copper is usually present. It is also important to put C1,
IMON
OUT
OUT
In addition there is a 1µF bypass (C1) on the INTV pin
CC
−
andnotetheconnectionbetweenSENSEtoSENSE (Pin34
to Pin 31).
Layout Considerations
In Hot Swap applications where load currents can be 20A,
narrowPCBtracksexhibitmoreresistancethanwidertracks
and operate at elevated temperatures. The minimum trace
width requirement for 1oz copper foil is 0.02" per amp to
make sure the trace stays at a reasonable temperature.
Using 0.03" per amp or wider is recommended. Note that
1oz copper exhibits a sheet resistance of about 0.5mΩ/
square. Small resistances add up quickly in high current
applications.
the bypass capacitor for the INTV pin as close as pos-
CC
sible between INTV and GND.
CC
Thermal Considerations
The LTC4234 junction to board temperature rise in still air
when the load current is 10A, 15A and 20A is shown in
curves of Figure 7 and Figure 8. The junction temperature
was measured at the package and the board temperature
was measured at the board edge. This temperature rise
TheinputsupplyshouldbetiedtoV exposedpadthrough
DD
2
a PCB trace that enters between Pin 1 and Pin 38. The V
DD
falls as the board area is increases from 6.45cm to
2
pad connects to the sense resistor and MOSFET. Globally
103cm . Two different SENSE pad areas are shown as
there are three DNC pins that are unconnected and left
separate figures.
–
open (pins 6, 8, 33). Connect the SENSE pin (pin 34) to
This thermal test board uses 2oz copper on the top layer
the SENSE pin (pin 31). Figure 6 shows a recommended
layout for the LTC4234.
divided equally between V and OUT traces similar to
DD
4234fa
15
For more information www.linear.com/LTC4234
LTC4234
APPLICATIONS INFORMATION
120
120
100
100
80
80
60
10A
15A
20A
10A 15A 20A
60
40
20
0
40
20
0
0
20
40
60
80
100
0
20
40
60
80
100
∆T
JB
∆T
JB
4234 F07
SMALL SENSE PAD (2ND LAYER)
LARGE SENSE PAD (2ND LAYER)
4234 F08
4234 F07
Figure 7. Temperature Rise for Small SENSE Pad
Figure 8. Temperature Rise for Large SENSE Pad
Figure 6. The second layer is 1oz copper connected to
the vias to the SENSE pad on the top layer. Two versions
of the second layer are considered. One uses a minimum
sized SENSE pad that only covers the vias for the top
layer while the remainder of the second layer is empty
(see Figure 7). The other version fills the second layer
with SENSE connected copper (see Figure 8). The third
layer is 1oz copper tied to ground while the bottom layer
is 2oz copper tied to ground except for a few signal traces.
Additional Applications
TheLTC4234hasawideoperatingrangefrom2.9Vto15V.
The UV, OV and PG thresholds are set with few resistors.
All other functions are independent of supply voltage.
In addition to Hot Swap applications, the LTC4234 also
functions as a backplane resident switch for removable
load cards (see Figure 9).
Figure 10 shows a 3.3V application with a UV threshold
of 2.87V, an OV threshold of 3.77V and a PG threshold
of 3.05V.
The curves demonstrate that the heat from the MOSFET
can be effectively transferred out of the package through
the OUT pins and only requires a minimum sized SENSE
pad under the package. However for small boards the
larger SENSE area does reduce the junction temperature
when sourcing higher currents.
The last page shows a 40A parallel application where the
two LTC4234 parts each provide 20A to the load. The
PNPs prevent one LTC4234 from faulting off in current
limit until both parts hit the 22.5A limit. The PNPs are
disconnected when power good is false via the series
MOSFETs M1 and M2
4234fa
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For more information www.linear.com/LTC4234
LTC4234
APPLICATIONS INFORMATION
V
12V
20A
OUT
12V
V
OUT
DD
R7
R5
12V
Z1*
LTC4234
10k
150k
R1
FB
PG
OV
226k
R6
20k
GATE
FLT
UV = 9.88V
OV = 15.2V
PG = 10.5V
R4
20k
R2
20k
LOAD
–
SENSE
SENSE
R3
140k
UV
TIMER
INTV
I
SET
4234 F09
I
ADC
CC
MON
C1
1µF
R
MON
GND
20k
*TVS Z1: DIODES INC. SMAJ17A
Figure 9. 12V, 20A Backplane Resident Application with Insertion Activated Turn-On
V
3.3V
5A
OUT
V
OUT
FB
3.3V
DD
+
R5
Z1*
C
LTC4234
L
14.7k
R1
1000µF
17.4k
R6
10k
R7
10k
UV
FLT
OV
SENSE
SENSE
R2
3.16k
UV = 2.87V
OV = 3.77V
PG = 3.05V
PG
GATE
R3
10k
–
I
SET
TIMER
INTV
CC
I
ADC
MON
C1
1µF
R
MON
GND
20k
4234 F10
*TVS Z1: DIODES INC. SMAJ17A
Figure 10. 3.3V, 20A Card Resident Application with Auto-Retry
4234fa
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For more information www.linear.com/LTC4234
LTC4234
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
WHH Package
Variation: WHH38MA
38-Lead Plastic QFN (5mm × 9mm)
(Reference LTC DWG # 05-08-1934 Rev Ø)
0.70 ±0.05
1.22 REF
0.72 REF
5.5 ±0.05
3.59 ±0.05
3.59 ±0.05
4.1 ±0.05
2.7 ±0.05
0.35 REF
0.7
BSC
0.5 REF
2.93 0.05
4.14 0.05
PACKAGE
OUTLINE
0.70 ±0.05
0.25 ±0.05
0.5 BSC
7.5 REF (2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30
0.9 0.10
0.350 REF
5.00 ±0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
2.93 0.10
0.50 REF
3.59 ±0.10
9.00 ±0.10
(2 SIDES)
7.50
REF
1.22 0.72
REF REF
0.25 0.05
4.14 0.10
3.59 ±0.10
0.5 BSC
(WHH36MA) QFN 1212 REV Ø
0.7 BSC
0.40 0.10
2.7 REF
0.203 REF
0.00 – 0.05
0.90 ±0.10
BOTTOM VIEW—EXPOSED PAD
SEATING PLANE
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4234fa
18
For more information www.linear.com/LTC4234
LTC4234
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
10/15
Changed input clamp to SMAJ17A in application circuit.
1, 10, 17
Updated SOA specification; added BW
and t
specifications.
3, 4
IMON
D(FAULT)
Added SOA Constant vs Junction Temperature curve; updated MOSFET SOA curve.
Updated INTV , SENSE and V pin functions.
6
7
CC
DD
Clarified latchoff and auto-retry behavior.
9
13
Added equations to calculate MOSFET temperature from V
.
ISET
Updated sections: Design Example, Layout Considerations, Typical Application.
14, 15, 20
4234fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC4234
TYPICAL APPLICATION
12V, 40A Parallel Application
V
12V
40A
OUT
V
OUT
FB
12V
DD
+
150k
20k
107k
Z1*
Z2
UV
2200µF
FLT
100k
5.23k
LTC4234
–
OV
PG
TIMER
GATE
10k
SENSE
SENSE
0.1µF
I
SET
INTV
I
CC
MON
1µF
GND
V
OUT
FB
DD
150k
20k
107k
UV
FLT
5.23k
LTC4234
–
OV
PG
10k
SENSE
SENSE
TIMER
GATE
0.1µF
I
M2
VN2222LLG
M1
VN2222LLG
Q1
2N5087
SET
INTV
CC
I
MON
Q2
2N5087
1µF
GND
*TVS Z1, Z2: DIODES INC: SMBJ8V5(C)A
4234 TA02
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Operates from 2.9V to 15V, Adjustable 10% Accurate Current Limit
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10A Guaranteed SOA Hot Swap Controller
4234fa
LT 1015 REV A • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2015
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC4234
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