ICE65L01F-LCB81C_技术文档

iCE65^™Ultra Low-Power

mobileFPGA^™Family

March 30, 2012 (2.42)

Data Sheet

 First high-density, ultra low-power

single-chip, SRAM mobileFPGA family

specifically designed for hand-held

applications and long battery life

Figure 1: iCE65 Family Architectural Features

Programmable

Logic Block (PLB)

12 µA at f =0 kHz (Typical)

 12 µA in static mode

I/O Bank 0

 Two power/speed options

–L: Low Power

Programmable Interconnect

–T: High speed

 Up to 256 MHz internal performance

 Reprogrammable from a variety of

sources and methods

 Processor-like mode self-configures from

external, commodity SPI serial Flash PROM

 Downloaded by processor using SPI-like serial

interface in as little as 20 µs

 In-system programmable, ASIC-like mode loads

from secure, internal Nonvolatile Configuration

Memory (NVCM)

NVCM

Programmable Interconnect

 Ideal for volume production

SPI

I/O Bank 2

Config

 Superior design and intellectual property

protection; no exposed data

Carry logic

Four-input

Look-Up Table

(LUT4)

Nonvolatile Configuration

Memory (NVCM)

 Proven, high-volume 65 nm, low-power

CMOS technology

Flip-flop with enable

and reset controls

 Low leakage, µW static power

 Lower core voltage, lowest dynamic power

 Plentiful, fast, on-chip 4Kbit RAM blocks

 Flexible programmable logic and programmable

 Low-cost, space-efficient packaging options

 Known-good die (KGD) options available

interconnect fabric

 Over 7,600 look-up tables (LUT4) and flip-flops

 Low-power logic and interconnect

 Complete iCEcube^™development system

 Windows^®and Linux^®support

 Flexible I/O pins to simplify system interfaces

 Up to 222 programmable I/O pins

 VHDL and Verilog logic synthesis

 Place and route software

 Four independently-powered I/O banks; support for 3.3V,

 Design and IP core libraries

2.5V, 1.8V, and 1.5V voltage standards

 Low-cost iCEman65 development board

 LVCMOS, MDDR, LVDS, and SubLVDS I/O standards

Table 1: iCE65 Ultra Low-Power Programmable Logic Family Summary

iCE65L01

1,280

16

iCE65L04

3,520

20

iCE65L08

7,680

32

Logic Cells (LUT + Flip-Flop)

RAM4K Memory Blocks

RAM4K RAM bits

64K

80K

128K

Configuration bits (maximum)

Typical Current at 0 kHz, 1.0 V

Maximum Programmable I/O Pins

Maximum Differential Input Pairs

245 Kb

12 µA

95

533 Kb

26 µA

176

1,057 Kb

54 µA

222

0

20

25

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iCE65 Ultra Low-Power mobileFPGA^™Family

Overview

The Lattice Semiconductor iCE65 programmable logic family is specifically designed to deliver the lowest static and

dynamic power consumption of any comparable CPLD or FPGA device. iCE65 devices are designed for cost-

sensitive, high-volume applications and provide on-chip, nonvolatile configuration memory (NVCM) to customize

for a specific application. iCE65 devices can self-configure from a configuration image stored in an external

commodity SPI serial Flash PROM or be downloaded from an external processor over an SPI-like serial port.

The three iCE65 components, highlighted in Table 1, deliver from approximately 1K to nearly 8K logic cells and flip-

flops while consuming a fraction of the power of comparable programmable logic devices. Each iCE65 device

includes between 16 to 32 RAM blocks, each with 4Kbits of storage, for on-chip data storage and data buffering.

As pictured in Figure 1, each iCE65 device consists of four primary architectural elements.

 An array of Programmable Logic Blocks (PLBs)

 Each PLB contains eight Logic Cells (LCs); each Logic Cell consists of …

 A fast, four-input look-up table (LUT4) capable of implementing any combinational logic function of

up to four inputs, regardless of complexity

 A ‘D’-type flip-flop with an optional clock-enable and set/reset control

 Fast carry logic to accelerate arithmetic functions such as adders, subtracters, comparators, and

counters.

 Common clock input with polarity control, clock-enable input, and optional set/reset control input to

the PLB is shared among all eight Logic Cells

 Two-port, 4Kbit RAM blocks (RAM4K)

 256x16 default configuration; selectable data width using programmable logic resources

 Simultaneous read and write access; ideal for FIFO memory and data buffering applications

 RAM contents pre-loadable during configuration

 Four I/O banks with independent supply voltage, each with multiple Programmable Input/Output (PIO)

blocks

 LVCMOS I/O standards and LVDS outputs supported in all banks

 I/O Bank 3 supports additional SSTL, MDDR, LVDS, and SubLVDS I/O standards

 Programmable interconnections between the blocks

 Flexible connections between all programmable logic functions

 Eight dedicated low-skew, high-fanout clock distribution networks

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Packaging Options

iCE65 components are available in a variety of package options to support specific application requirements. The

available options, including the number of available user-programmable I/O pins (PIOs), are listed in Table 2. Fully-

tested Known-Good Die (KGD) DiePlus^™are available for die stacking and highly space-conscious applications. All

iCE65 devices are provided exclusively in Pb-free, RoHS-compliant packages.

Table 2: iCE65 Family Packaging Options, Maximum I/O per Package

Package

Body

(mm)

5 x 5

7 x 7

14 x 14

6 x 6

8 x 8

Ball/Lead

Pitch

(mm)

0.5

Package

Code

CB81

Package

81-ball chip-scale BGA

84-pin quad flat no-lead package

100-pin very thin quad flat package

121-ball chip-scale BGA

132-ball chip-scale BGA

196-ball chip-scale BGA

284-ball chip-scale BGA

65L01

63 (0)

67 (0)

72 (0)

92 (0)

93 (0)

—

65L04

—

72 (9)

—

95 (11)

150 (18)

176 (20)

65L08

—

QN84

0.5

—

VQ100

CB121

CB132

CB196

CB284

95 (12)

150 (18)

222 (25)

0.5

8 x 8

12 x 12

See DiePlus

data sheet

—

Known Good Die

DI

—

95 (0)

176 (20)

222 (25)

= Common footprint allows each density migration on the same printed circuit board. (Differential input count).

The iCE65L04 and the iCE65L08 are both available in the CB196 package and have similar footprints but are not completely pin

compatible. See “Pinout Differences between iCE65L04 and iCE65L08 in CB196 Package” on page 73 for more information.

When iCE65 components are supplied in the same package style, devices of different gate densities share a common

footprint. The common footprint improves manufacturing flexibility. Different models of the same product can

share a common circuit board. Feature-rich versions of the end application mount a larger iCE65 device on the

circuit board. Low-end versions mount a smaller iCE65 device.

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iCE65 Ultra Low-Power mobileFPGA^™Family

Ordering Information

Figure 2 describes the iCE65 ordering codes for all packaged, non-NVCM Programed components. See the separate

DiePlus data sheets when ordering die-based products.

Figure 2: iCE65 Ordering Codes Standard Device

iCE65L 04 F -L CB 132 C

Logic Cells (x1,000)

Temperature Range

C= Commercial

04, 08

01, 04, 08

(T_A_J= 0° to 70° Celsius)

I= Industrial

Configuration Memory

(T_A_J= –40° to 85° Celsius)

F= NVCM + reprogrammable

Package Leads

Package Style

Power Consumption/

Speed

-L= Low power

-T= High speed

CB= chip-scale ball grid

CS= wafer level chip-scale package (0.4 mm pitch)

VQ= very-thin quad flat pack package

QN = quad flat no-lead package

iCE65 devices offer two power consumption, speed options. Standard products (“-L” ordering code) have low

standby and dynamic power consumption. The “-T” provides higher-speed logic.

Similarly, iCE65 devices are available in two operating temperature ranges, one for typical commercial applications,

the other with an extended temperature range for industrial and telecommunications applications. The ordering

code also specifies the device package option, as described further in Table 2.

Figure 3 describes the iCE65 ordering codes for all packaged, NVCM Programmed components.

Figure 3: iCE65 Ordering Codes NVCM Programmed Device

iCE65L 01 F – ZZZ ZZZZ

Logic Cells (x1000)

NVCM Program Code Revision

01, 04, 08

Customer Program Code

Configuration Memory

F = NVCM + reprogrammable

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Programmable Logic Block (PLB)

Generally, a logic design for an iCE65 component is created using a high-level hardware description language such

as Verilog or VHDL. The Lattice Semiconductor development software then synthesizes the high-level description

into equivalent functions built using the programmable logic resources within each iCE65 device. Both sequential

and combinational functions are constructed from an array of Programmable Logic Blocks (PLBs). Each PLB

contains eight Logic Cells (LCs), as pictured in Figure 4, and share common control inputs, such as clocks, reset, and

enable controls.

PLBs are connected to one another and other logic functions using the rich Programmable Interconnect resources.

Logic Cell (LC)

Each iCE65 device contains thousands of Logic Cells (LCs), as listed in Table 1. Each Logic Cell includes three

primary logic elements, shown in Figure 4.

 A four-input Look-Up Table (LUT4) builds any combinational logic function, of any complexity, of up to

four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory (ROM). Combine and

cascade multiple LUT4s to create wider logic functions.

Figure 4: Programmable Logic Block and Logic Cell

 A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic

functions. Each DFF also connects to a global reset signal that is automatically asserted immediately

following device configuration.

 Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders,

subtracters, comparators, binary counters and some wide, cascaded logic functions.

The output from a Logic Cell is available to all inputs to all eight Logic Cells within the Programmable Logic Block.

Similarly, the Logic Cell output feeds into fabric to connect to other features on the iCE65 device.

Shared Block-Level Controls

Clock

Programmable Logic

Block (PLB)

Enable

1

Set/Reset₀

Logic Cell

Carry Logic

DFF

O

I0

I1

I2

I3

D

EN

Q

LUT4

SR

Four-input

Flip-flop with

Look-Up Table

(LUT4)

optional enable and

set or reset controls

= Statically defined by configuration program

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Look-Up Table (LUT4)

The four-input Look-Up Table (LUT4) function implements any and all combinational logic functions, regardless of

complexity, of between zero and four inputs. Zero-input functions include “High” (1) and “Low” (0). The LUT4

function has four inputs, labeled I0, I1, I2, and I3. Three of the four inputs are shared with the Carry Logic function,

as shown in Figure 4. The bottom-most LUT4 input connects either to the I3 input or to the Carry Logic output

from the previous Logic Cell.

The output from the LUT4 function connects to the flip-flop within the same Logic Cell. The LUT4 output or the

flip-flop output then connects to the programmable interconnect.

For detailed LUT4 internal timing, see Table 54.

‘D’-style Flip-Flop (DFF)

The ‘D’-style flip-flop (DFF) optionally stores state information for the application.

The flip-flop has a data input, ‘D’, and a data output, ‘Q’. Additionally, each flip-flop has up to three control signals

that are shared among all flip-flops in all Logic Cells within the PLB, as shown in Figure 4. Table 3 describes the

behavior of the flip-flop based on inputs and upon the specific DFF design primitive used or synthesized.

Table 3: ‘D’-Style Flip-Flop Behavior

Inputs

Output

DFF

Primitive

Flip-Flop

Mode

X

Operation

Cleared Immediately after

Configuration

Hold Present Value

(Disabled)

D

X

EN

SR

CLK

X

Q

0

All

X

0

X

Q

Hold Present Value (Static

Clock)

1 or 0

↑

Load with Input Data

Asynchronous Reset

D

X

1*

X

0*

1

D

0

SB_DFFR

SB_DFFS

SB_DFFSR

SB_DFFSS

Asynchronous

Reset

X

Asynchronous Set

Synchronous Reset

Synchronous Set

Asynchronous

Set

Synchronous

Reset

Synchronous

Set

X

1

X

↑

1

0

1

1*

X = don’t care, ↑ = rising clock edge (default polarity), 1* = High or unused, 0* = Low or unused

The CLK clock signal is not optional and is shared among all flip-flops in a Programmable Logic Block. By default,

flip-flops are clocked by the rising edge of the PLB clock input, although the clock polarity can be inverted for all the

flip-flops in the PLB.

The CLK input optionally connects to one of the following clock sources.

 The output from any one of the eight Global Buffers, or

 A connection from the general-purpose interconnect fabric

The EN clock-enable signal is common to all Logic Cells in a Programmable Logic Block. If the enable signal is not

used, then the flip-flop is always enabled. This condition is indicated as “1*” in Table 3. The asterisk indicates that

this is the default state if the control signal is not connected in the application.

Similarly, the SR set/reset signal is common to all Logic Cells in a Programmable Logic Block. If not used, then the

flip-flop is never set/reset, except when cleared immediately after configuration or by the Global Reset signal. This

condition is indicated as “0*” in Table 3. The asterisk indicates that this is the default state if the control signal is

not connected in the application.

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Each flip-flop has an additional control that defines its set or reset behavior. As defined in the configuration image,

the control defines whether the set or reset operation is synchronized to the active CLK clock edge or whether it is

completely asynchronous.

 The SB_DFFR and SB_DFFS primitives are asynchronously controlled, solely by the SR input. If the SR

input is High, then an SB_DFFR primitive is asynchronously reset and an SB_DFFS primitive is

asynchronously set.

 The SB_DFFSR and SB_DFFRSS primitives are synchronously controlled by both the SR input and the clock

input. If the SR input is High at a rising edge of the clock input, then an SB_DFFSR primitive is

synchronously reset and an SB_DFFSS primitive is synchronously set.

The LUT4 output or the flip-flop output then connects to the programmable interconnect.

Because of the shared control signals, the design software can pack flip-flops with common control inputs into a

single PLB block, as described by Table 4. There are eight total packing options.

Table 4: Flip-flop Packing/Sharing within a PLB

Set or Reset Control

Group

Active Clock Edge

Clock Enable

(Sync. or Async)

















1

2

3

4

5

6

7

8

None

None (always enabled)

PLB set/reset control

None

Selective (controlled by

PLB clock enable)

PLB set/reset control

For detailed flip-flop internal timing, see Table 54.

Carry Logic

The dedicated Carry Logic within each Logic Cell primarily accelerates and improves the efficiency of arithmetic

logic such as adders, accumulators, subtracters, incrementers, decrementers, counters, ALUs, and comparators. The

Carry Logic also supports wide combinational logic functions.

COUT = I1 ● I2 + CIN ●I1 + CIN ● I2

[Equation 1]

Equation 1 and Figure 5 describe the Carry Logic structure within a Logic Cell. The Carry Logic shares inputs with

the associated Look-Up Table (LUT4). The LUT4’s I1 and I2 inputs directly feed the Carry Logic; inputs I0 and I3

do not. A signal cascades between Logic Cells within the Programmable Logic Block. The carry input from the

previous adjacent Logic Cell optionally provides an alternate input to the LUT4 function, supplanting the I3 input.

Low-Power Disable

To save power and prevent unnecessary signal switching, the Carry Logic function within a Logic Cell is disabled if

not used. The output of a Logic Cell’s Carry Logic is forced High.

PLB Carry Input and Carry Output Connections

As shown in Figure 5, each Programmable Logic Block has a carry input signal that can be initialized High, Low, or

come from the carry output signal from PLB immediately below.

Similarly, the Carry Logic output from the Programmable Logic Block connects to the PLB immediately above,

which allows the Carry Logic to span across multiple PLBs in a column. As shown in Figure 6, the Carry Logic chain

can be tapped mid-way through a chain or a PLB by feeding the value through a LUT4 function.

Adder Example

Figure 6 shows an example design that uses the Carry Logic. The example is a 2-bit adder, which can be expanded

into an adder of arbitrary size. The LUT4 function within a Logic Cell is programmed to calculate the sum of the

two input values and the carry input, A[i] + B[i] + CARRY_IN[i-1] = SUM[i].

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iCE65 Ultra Low-Power mobileFPGA^™Family

The Carry Logic generates the carry value to feed the next bit in the adder. The calculated carry value replaces the I3

input to the next LUT4 in the upper Logic Cell.

If required by the application, the carry output from the final stage of the adder is available by passing it through the

final LUT4.

Figure 5: Carry Logic Structure within a Logic Cell and between PLBs

Adjacent PLB

To upper adjacent Logic Cell

Carry

Logic

I0

I1

LUT4

I2

I3

From lower adjacent Logic Cell

Carry Logic

initialization into

Programmable Logic

Block (PLB)

1

0

Adjacent PLB

= Statically defined by

configuration program

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Implementing Subtracters, Decrementers

As mentioned earlier, the Carry Logic generates a High output whenever the sum of I1 + I2 + CARRY_IN

generates a carry. The Carry Logic does not specifically have a subtract mode. To implement a subtract function or

decrement function, logically invert either the I1 or I2 input and invert the initial carry input. This performs a 2s

complement subtract operation.

Figure 6: Two-bit Adder Example

LUT4

I0

GND I1

GND I2

I3

CARRY_OUT

Carry

Logic

LUT4

I0

A[1]

B[1]

I1

I2

I3

SUM[1]

Carry

Logic

LUT4

I0

I1

I2

I3

A[0]

B[0]

SUM[0]

CARRY_IN

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Programmable Input/Output Block (PIO)

Programmable Input/Output (PIO) blocks surround the periphery of the device and connect external components to

the Programmable Logic Blocks (PLBs) and RAM4K blocks via programmable interconnect. Individual PIO pins are

grouped into one of four I/O banks, as shown in Figure 7. I/O Bank 3 has additional capabilities, including LVDS

differential I/O and the ability to interface to Mobile DDR memories.

Figure 7 also shows the logic within a PIO pin. When used in an application, a PIO pin becomes a signal input, an

output, or a bidirectional I/O pin with a separate direction control input.

Figure 7: Programmable Input/Output (PIO) Pin

VCCIO

I/O Bank 0, 1, or 2

1.5V to 3.3V

Voltage Supply

0 = Hi-Z

Enabled

Disabled

‘1’

‘0’

1 = Output

Enabled

Pull-up

not in I/O

Bank 3

OE

VCCIO_0

VCC

Internal Core

Pull-up

Enable

I/O Bank 0

General-Purpose I/O

OUT

PIO

PAD

Latch inhibits

switching for

lowest power

iCEGATE

HOLD

HD

IN

GBIN pins optionally

connect directly to an

associated GBUF global

buffer

I/O Bank 2

SPI

Config

General-Purpose I/O

Programmable Input/Output

= Statically defined by configuration program

SPI_VCC

VCCIO_2

I/O Banks

PIO blocks are organized into four separate I/O banks, each with its own voltage supply input, as shown in Table 5.

The voltage applied to the VCCIO pin on a bank defines the I/O standard used within the bank. Table 50 and Table

51 describe the I/O drive capabilities and switching thresholds by I/O standard. On iCE65L04 and iCE65L08

devices, I/O Bank 3, along the left edge of the die, is different than the others and supports specialized I/O standards.

I/O Bank Voltage Supply Inputs Support Different I/O Standards

Because each I/O bank has its own voltage supply, iCE65 components become the ideal bridging device between

different interface standards. For example, the iCE65 device allows a 1.8V-only processor to interface cleanly with a

3.3V bus interface. The iCE65 device replaces external voltage translators.

Table 5: Supported Voltages by I/O Bank

Bank

Device Edge

Top

Supply Input

VCCIO_0

VCCIO_1

VCCIO_2

VCCIO_3

3.3V

Yes

2.5V

Yes

1.8V

Yes

1.5V

Outputs only

iCE65L01: Outputs only

iCE65L04/08: Yes

No

0

1

2

3

Right

Bottom

Left

SPI

Bottom Right

SPI_VCC

Yes

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If not connected to an external SPI PROM, the four pins associated with the SPI Master Configuration Interface can

be used as PIO pins, supplied by the SPI_VCC input, essentially forming a fifth “mini” I/O bank. If using an SPI

Flash PROM, then connect SPI_VCC to 3.3V.

I/O Banks 0, 1, 2, SPI and Bank 3 of iCE65L01

Table 6 highlights the available I/O standards when using an iCE65 device, indicating the drive current options, and

in which bank(s) the standard is supported. I/O Banks 0, 1, 2 and SPI interface support the same standards. I/O

Bank 3 has additional capabilities in iCE65L04 and iCE65L08, including support for MDDR memory standards and

LVDS differential I/O.

Table 6: I/O Standards for I/O Banks 0, 1, 2, SPI Interface Bank, and Bank 3 of iCE65L01

I/O Standard

5V Input Tolerance

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15 outputs

Supply Voltage

Drive Current (mA)

Attribute Name

N/A

3.3V

2.5V

1.8V

1.5V

N/A

±11

±8

±5

±4

SB_LVCMOS

IBIS Models for I/O Banks 0, 1, 2 and the SPI Bank

The IBIS (I/O Buffer Information Specification) file that describes the output buffers used in I/O Banks 0, 1, 2, SPI

Bank and Bank 3 of iCE65L01 is available from the following link.

 IBIS Models for I/O Banks 0, 1, 2, SPI Bank and Bank 3 of iCE65L01

I/O Bank 3 of iCE65L04 and iCE65L08

I/O Bank 3, located along the left edge of the die, has additional special I/O capabilities to support memory

components and differential I/O signaling (LVDS). Table 7 lists the various I/O standards supported by I/O Bank 3.

The SSTL2 and SSTL18 I/O standards require the VREF voltage reference input pin which is only available on the

CB284 package. Also see Table 51 for electrical characteristics.

Table 7: I/O Standards for I/O Bank 3 Only of iCE65L04 and iCE65L08

Supply

Voltage

3.3V

VREF Pin (CB284 or

DiePlus) Required?

No

Target

Drive Current (mA)

±8

I/O Standard

LVCMOS33

Attribute Name

SB_LVCMOS33_8

No

±16

±12

±8

SB_LVCMOS25_16

SB_LVCMOS25_12

SB_LVCMOS25_8

SB_LVCMOS25_4

LVCMOS25

2.5V

1.8V

±4

No

±10

±8

±4

SB_LVCMOS18_10

SB_LVCMOS18_8

SB_LVCMOS18_4

SB_LVCMOS18_2

LVCMOS18

LVCMOS15

±2

No

Yes

No

±4

±2

SB_LVCMOS15_4

SB_LVCMOS15_2

1.5V

2.5V

1.8V

SSTL2_II

SSTL2_I

±16.2

±8.1

SB_SSTL2_CLASS_2

SB_SSTL2_CLASS_1

SSTL18_II

SSTL18_I

±13.4

±6.7

SB_SSTL18_FULL

SB_SSTL18_HALF

±10

±8

±4

SB_MDDR10

SB_MDDR8

SB_MDDR4

SB_MDDR2

MDDR

LVDS

1.8V

2.5V

±2

No

N/A

SB_LVDS_INPUT

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iCE65 Ultra Low-Power mobileFPGA^™Family

Table 8 lists the I/O standards that can co-exist in I/O Bank 3, depending on the VCCIO_3 voltage.

Table 8: Compatible I/O Standards in I/O Bank 3 of iCE65L04 and iCE65L08

VCCIO_3 Voltage

Compatible I/O

Standards

3.3V

SB_LVCMOS33_8

2.5V

1.8V

1.5V

Any SB_LVCMOS15

Any SB_LVCMOS25

SB_SSTL2_Class_2

SB_SSTL2_Class_1

SB_LVDS_INPUT

Any SB_LVCMOS18

SB_SSTL18_FULL

SB_SSTL18_HALF

SB_MDDR10

SB_MDDR8

SB_MDDR4

SB_MDDR2

SB_LVDS_INPUT

Programmable Output Drive Strength

Each PIO in I/O Bank 3 offers programmable output drive strength, as listed in Table 8. For the LVCMOS and

MDDR I/O standards, the output driver has settings for static drive currents ranging from 2 mA to 16 mA output

drive current, depending on the I/O standard and supply voltage.

The SSTL18 and SSTL2 I/O standards offer full- and half-strength drive current options

Differential Inputs and Outputs

All PIO pins support “single-ended” I/O standards, such as LVCMOS. However, iCE65 FPGAs also support

differential I/O standards where a single data value is represented by two complementary signals transmitted or

received using a pair of PIO pins. The PIO pins in I/O Bank 3 of iCE65L04 and iCE65L08L08 support Low-Voltage

Differential Swing (LVDS) and SubLVDS inputs as shown in Figure 8. Differential outputs are available in all four

I/O banks.

Differential Inputs Only on I/O Bank 3 of iCE65L04 and iCE65L08

Differential receivers are required for popular applications such as LVDS and LVPECL clock inputs, camera

interfaces, and for various telecommunications standards.

Specific pairs of PIO pins in I/O Bank 3 form a differential input. Each pair consists of a DPxxA and DPxxB pin,

where “xx” represents the pair number. The DPxxB receives the true version of the signal while the DPxxA receives

the complement of the signal. Typically, the resulting signal pair is routed on the printed circuit board (PCB) with

matched 50Ω signal impedance. The differential signaling, the low voltage swing, and the matched signal routing

are ideal for communicating very-high frequency signals. Differential signals are generally also more tolerant of

system noise and generate little EMI themselves.

The LVDS input circuitry requires 2.5V on the VCCIO_3 voltage supply. Similarly, the SubLVDS input circuitry

requires 1.8V on the VCCIO_3 voltage supply. For electrical specifications, see “Differential Inputs” on page 100.

Each differential input pair requires an external 100 Ω termination resistor, as shown in Figure 8.

The PIO pins that make up a differential input pair are indicated with a blue bounding box in the footprint diagrams

and in the pinout tables.

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Figure 8: Differential Inputs in iCE65L04 and iC65L08 I/O Bank 3

Impedance-matched

signal traces

VCCIO_3 = 1.8V or 2.5V

DPxxB

50Ω

DPxxA

iC65 Differential

Input

External 100Ω

termination resistor

1

0

1

0

Noise pulse affects both traces

similarly. Difference between

signals remains nearly constant.

Differential Outputs in Any Bank

Differential outputs are built using a pair of single-ended PIO pins as shown in Figure 9. Each differential I/O pair

requires a three-resistor termination network to adjust output characteristic to match those for the specific

differential I/O standard. The output characteristics depend on the values of the parallel resistors (RP) and series

resistor (RS). Differential outputs must be located in the same I/O tile.

Figure 9: Differential Output Pair

External output

compensation

Impedance-matched

signal traces

resistor network

VCCIO_x

R_S

50Ω

R_P

iC65 Differential Output Pair

1

0

1

0

Noise pulse affects both traces

similarly. Difference is signals

remains nearly constant.

For electrical characteristics, see “Differential Outputs” on page 100.

The PIO pins that make up a differential output pair are indicated with a blue bounding box in the in the tables in

“Die Cross Reference” starting on page 84.

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iCE65 Ultra Low-Power mobileFPGA^™Family

Input Signal Path

As shown in Figure 7, a signal from a package pin optionally feeds directly into the device, or is held in an input

register. The input signal connects to the programmable interconnect resources through the IN signal. Table 9

describes the input behavior, assuming that the output path is not used or if a bidirectional I/O, that the output

driver is in its high-impedance state (Hi-Z). Table 9 also indicates the effect of the Power-Saving I/O Bank iCEgate

Latch and the Input Pull-Up Resistors on I/O Banks 0, 1, and 2.

See Input and Output Register Control per PIO Pair for information about the registered input path.

Power-Saving I/O Bank iCEgate Latch

To save power, the optional iCEgate latch can selectively freeze the state of individual, non-registered inputs within

an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-enable control. As shown in

Figure 10, the iCEgate HOLD control signal captures the external value from the associated asynchronous input.

The HOLD signal prevents switching activity on the PIO pad from affecting internal logic or programmable

interconnect. Minimum power consumption occurs when there is no switching. However, individual pins within

the I/O bank can bypass the iCEgate latch and directly feed into the programmable interconnect, remaining active

during low-power operation. This behavior is described in Table 9. The decision on which asynchronous inputs use

the iCEgate feature and which inputs bypass it is determined during system design. In other words, the iCEgate

function is part of the source design used to create the iCE65 configuration image.

Figure 10: Power-Saving iCEgate Latch

Controlled by configuration

image; allows pin-by-pin

PIO

PAD

option to freeze input with

iCEgate

D

Q

LE

HOLD

PAD

Optional iCEgate Latch

HOLD

Input

Follow value

on PAD

Follow value

on PAD

Freeze last

value

Table 9: PIO Non-Registered Input Operations

HOLD Bitstream Setting

Controlled Input Pull-

iCEgate Latch by iCEgate? Up Enabled? Pin Value

PAD

IN

Input Value to

Interconnect

PAD Value

(Undefined)

1

Operation

Data Input

Pad Floating, No Pull-up

Pad Floating, Pull-up

Data Input, Latch

Bypassed

0

X

No

Yes

X

PAD

Z

No

PAD

PAD Value

Pad Floating, No Pull-up,

Latch Bypassed

Pad Floating, Pull-up,

Latch Bypassed

Low Power Mode, Hold

Last Value

X

1

No

Yes

X

Z

X

(Undefined)

1

Yes

Last Captured

PAD Value

There are four iCEgate HOLD controls, one per each I/O bank. The iCEgate HOLD control input originates within

the interconnect fabric, near the middle of the I/O edge. Consequently, the HOLD signal is optionally controlled

externally through a PIO pin or from other logic within the iCE65 device.

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For best possible performance, the global buffer inputs (GBIN[7:-0]) connect directly to the their associated

global buffers (GBUF[7:0]), bypassing the PIO logic and iCEgate circuitry as shown in Figure 7.

Consequently, the direct GBIN-to-GBUF connection cannot be blocked by the iCEgate circuitry. However,

it is possible to use iCEgate to block PIO-to-GBUF clock connections.

i

For additional information on using the iCEgate feature, please refer to the following application note.

AN002: Using iCEgate Blocking for Ultra-Low Power

Input Pull-Up Resistors on I/O Banks 0, 1, and 2

The PIO pins in I/O Banks 0, 1, and 2 have an optional input pull-up resistor. Pull-up resistors are not provided in

iCE65L04 and iCE65L08 I/O Bank 3. During the iCE65 configuration process, the input pull-up resistor is

unconditionally enabled and pulls the input to within a diode drop of the associated I/O bank supply voltage

(VCCIO_#). This prevents any signals from floating on the circuit board during configuration.

After iCE65 configuration is complete, the input pull-up resistor is optional, defined by a configuration bit. The

pull-up resistor is also useful to tie off unused PIO pins. The Lattice iCEcube development software defines all

unused PIO pins in I/O Banks 0, 1 and 2 as inputs with the pull-up resistor turned on. The pull-up resistor value

depends on the VCCIO voltage applied to the bank, as shown in Table 49.

Note: JTAG inputs TCK, TDI and TMS do not have the input pull-up resistor and must be tied off to GND

when unused, else VCCIO_1 draws current.

!

No Input Pull-up Resistors on I/O Bank 3 of iCE65L04 and iCE65L08

The PIO pins in I/O Bank 3 do not have an internal pull-up resistor. To minimize power consumption, tie unused

PIO pins in Bank 3 to a known logic level or drive them as a disabled high-impedance output.

Input Hysteresis

Inputs typically have about 50 mV of hysteresis, as indicated in Table 49.

Output and Output Enable Signal Path

As shown in Figure 7, a signal from programmable interconnect feeds the OUT signal on a Programmable I/O pad.

This output connects either directly to the associated package pin or is held in an optional output flip-flop. Because

all flip-flops are automatically reset after configuration, the output from the output flip-flop can be optionally

inverted so that an active-Low output signal is held in the disabled (High) state immediately after configuration.

Similarly, each Programmable I/O pin has an output enable or three-state control called OE. When OE = High, the

OUT output signal drives the associated pad, as described in Table 10. When OE = Low, the output driver is in the

high-impedance (Hi-Z) state. The OE output enable control signal itself connects either directly to the output

buffer or is held in an optional register. The output buffer is optionally permanently enabled or permanently

disabled, either to unconditionally drive output signals, or to allow input-only signals.

Table 10: PIO Output Operations (non-registered operation, no inversions)

OUT

Data Output

OE

Enable

0

Operation

PAD

Hi-Z

OUT

Three-State

Drive Output Data

X

OUT

1*

X = don’t care, 1* = High or unused, Hi-Z = high-impedance, three-stated, floating.

See Input and Output Register Control per PIO Pair for information about the registered input path.

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iCE65 Ultra Low-Power mobileFPGA^™Family

Input and Output Register Control per PIO Pair

PIO pins are grouped into pairs for synchronous control. Registers within pairs of PIO pins share common input

clock, output clock, and I/O clock enable control signals, as illustrated in Figure 11. The combinational logic paths

are removed from the drawing for clarity.

The INCLK clock signal only controls the input flip-flops within the PIO pair.

The OUTCLK clock signal controls the output flip-flops and the output-enable flip-flops within the PIO pair.

If desired in the iCE65 application, the INCLK and OUTCLK signals can be connected together.

The IOENA clock-enable input, if used, enables all registers in the PIO pair, as shown in Figure 11. By default, the

registers are always enabled.

Before laying out your printed-circuit board, run the design through the iCEcube development software to

verify that your selected pinout complies with these I/O register pairing requirements. See tables in “Die

Cross Reference” starting on page 84.

!

Figure 11: PIO Pairs Share Clock and Clock Enable Controls (only registered paths shown for clarity)

PIO Pair

OUTCLK

IOENA

1

INCLK

0 = Hi-Z

OE

1 = Output Enabled

EN

PAD

OUT

IN

EN

0 = Hi-Z

OE

1 = Output Enabled

EN

PAD

OUT

IN

EN

= Statically defined by configuration program

The pairing of PIO pairs is most evident in the tables in “Die Cross Reference” starting on page 84.

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Double Data Rate (DDR) Flip-Flops

Each individual PIO pin optionally has two sets of double data rate (DDR) flip-flops; one input pair and one output

pair. Figure 12 demonstrates the functionality of the output DDR flip-flop. Two signals from within the iCE65

device drive the DDR output flip-flop. The D_OUT_0 signal is clocked by the rising edge of the OUTCLK signal

while the D_OUT_1 signal is clocked by the falling edge of the OUTCLK signal, assuming no optional clock polarity

inversion. Internally, the two individual flip-flops are multiplexed together before the data appears at the pad,

effectively doubling the output data rate.

Figure 12: DDR Output Flip-Flop

OE

IOENA

D

Q

D_OUT_1

D_OUT_0

OUTCLK

0

1

PAD

PIO

D0

EN

S

D

EN

OUTCLK

PAD

D0

D1

D0

D1

Similarly, Figure 13 demonstrates the DDR input flip-flop functionality. A double data rate (DDR) signal arrives at

the pad. Internally, one value is clocked by the rising edge of the INCLK signal and another value is clocked by the

falling edge of the INCLK signal. The DDR data stream is effectively de-multiplexed within the PIO pin and

presented to the programmable interconnect on D_IN_0 and D_IN_1.

Figure 13: DDR Input Flip-Flop

IOENA

PIO

D

Q

D_IN_1

D_IN_0

EN

PAD

D

EN

INCLK

PAD

D0

D1

D0

D1

D0

D1

D0

D1

D_IN_0

D_IN_1

The DDR flip-flops provide several design advantages. Internally within the iCE65 device, the clock frequency is

half the effective external data rate. The lower clock frequency eases internal timing, doubling the clock period, and

slashes the clock-related power in half.

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iCE65 Ultra Low-Power mobileFPGA^™Family

Global Routing Resources

Global Buffers

Each iCE65 component has eight global buffer routing connections, illustrated in Figure 14. There are eight high-

drive buffers, connected to the eight low-skew, global lines. These lines are designed primarily for clock distribution

but are also useful for other high-fanout signals such as set/reset and enable signals. The global buffers originate

either from the Global Buffer Inputs (GBINx) or from programmable interconnect. The associated GBINx pin

represents the best pin to drive a global buffer from an external source. However, the application with an iCE65

FPGA can also drive a global buffer via any other PIO pin or from internal logic using the programmable

interconnect.

If not used in an application, individual global buffers are turned off to save power.

Figure 14: High-drive, Low-skew, High-fanout Global Buffer Routing Resources

I/O Bank 0

GBIN7

GBIN2

Global

Buffer

GBUF7

Global

Buffer

GBUF2

GBUF7 and its associated

PIO are best for direct

differential clock inputs

GBUF6

Global

Buffer

GBUF3

Global

Buffer

GBIN6

GBIN3

I/O Bank 2

Table 11 lists the connections between a specific global buffer and the inputs on a Programmable Logic Block (PLB).

All global buffers optionally connect to all clock inputs. Any four of the eight global buffers can drive logic inputs to

a PLB. Even-numbered global buffers optionally drive the Reset input to a PLB. Similarly, odd-numbered buffers

optionally drive the PLB clock-enable input.

Table 11: Global Buffer (GBUF) Connections to Programmable Logic Block (PLB)

Global Buffer

GBUF0

GBUF1

GBUF2

GBUF3

GBUF4

GBUF5

GBUF6

GBUF7

LUT Inputs

Yes, any 4 of 8

GBUF buffers

Clock

Yes

Clock Enable

Reset

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

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Table 12 and Table 13 list the connections between a specific global buffer and the inputs on a Programmable I/O

(PIO) pair. Although there is no direct connection between a global buffer and a PIO output, such a connection is

possible by first connecting through a PLB LUT4 function. Again, all global buffers optionally drive all clock inputs.

However, even-numbered global buffers optionally drive the clock-enable input on a PIO pair.

The PIO clock enable connect is different between the iCE65L01/iCE65L04 and iCE65L08.

!

Table 12: iCE65L01 & iCE65L04: Global Buffer (GBUF) Connections to Programmable I/O (PIO) Pair

Output

Global Buffer

GBUF0

GBUF1

GBUF2

GBUF3

GBUF4

GBUF5

GBUF6

GBUF7

Connections

No (connect through

PLB LUT)

Input Clock

Yes

Output Clock

Clock Enable

Yes

No

Yes

No

Yes

No

Yes

No

Yes

Table 13: iCE64L08: Global Buffer (GBUF) Connections to Programmable I/O (PIO) Pair

Output

Global Buffer

GBUF0

GBUF1

GBUF2

GBUF3

GBUF4

GBUF5

GBUF6

GBUF7

Connections

No (connect through

PLB LUT)

Input Clock

Yes

Output Clock

Clock Enable

Yes

No

Yes

No

Yes

No

Yes

No

Global Buffer Inputs

The iCE65 component has eight specialized GBIN/PIO pins that are optionally direct inputs to the global buffers,

offering the best overall clock characteristics. As shown in Figure 15, each GBIN/PIO pin is a full-featured I/O pin

but also provides a direct connection to its associated global buffer. The direct connection to the global buffer

bypasses the iCEgate input-blocking latch and other PIO input logic. These special PIO pins are allocated two to an

I/O Bank, a total of eight. These pins are labeled GBIN0 through GBIN7, as shown in Figure 14 and the pin locations

for each GBIN input appear in Table 14.

Table 14: Global Buffer Input Ball/Pin Number by Package

Global Buffer

Input (GBIN)

GBIN0

‘L04

CB196

A7

‘L08

CB196

A7

I/O

VQ100

90

CB132

A6

CB284

E10

E11

Bank

0

1

2

3

GBIN1

E7

89

A7

E7

GBIN2

GBIN3

F10

G12

63

62

G14

F14

F10

G12

L18

K18

GBIN4

GBIN5

34

33

P8

P7

L7

P5

N8

M7

V12

V11

GBIN6

GBIN7

H1

H3

15

13

H1

G1

H1

G1

M5

L5

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iCE65 Ultra Low-Power mobileFPGA^™Family

Note the clock differences between the iCE65L04 and iCE65L08 in the CB196 package.

!

Figure 15: GBIN/PIO Pin

GBIN/PIO Pin

VCCIO

0 = Hi-Z

1 = Output

Enabled

Disabled

‘1’

‘0’

Pull-up

not in I/O

Bank 3

OE

Pull-up

Enable

OUT

PAD

Latch inhibits

switching for

lowest power

iCEGATE

HOLD

HD

IN

GBIN pins optionally

connect directly to an

associated GBUF global

buffer

Optional connection from internal

programmable interconnect.

GBUF

Differential Global Buffer Input

All eight global buffer inputs support single-ended I/O standards such as LVCMOS. Global buffer GBUF7 in I/O

Bank 3 also provides an optional direct SubLVDS, LVDS, or LVPECL differential clock input, as shown in Figure 16.

The GBIN7 and its associated differential I/O pad accept a differential clock signal. A 100 Ω termination resistor is

required across the two pads. Optionally, swap the outputs from the LVDS or LVPECL clock driver to invert the

clock as it enters the iCE65 device.

Figure 16: LVDS or LVPECL Clock Input

GBIN7/DP##B

LVDS/

LVPECL

Clock

Driver

GBUF7

DP##A

Table 15 lists the pin or ball numbers for the differential global buffer input by package style. Although this

differential input is the only one that connects directly to a global buffer, other differential inputs can connect to a

global buffer using general-purpose interconnect, with slightly more signal delay.

Table 15: Differential Global Buffer Input Ball/Pin Number by Package

Differential Global

Buffer Input

‘L04

CB196

G1

‘L08

CB196

H3

I/O

(GBIN)

GBIN7/DPxxB

DPxxA

VQ100

13

CB132

N/A

CB284

L5

Bank

3

H4

12

G2

L3

The differential global buffer input is not available for iCE65 devices in the CB132 package. This

restriction is an artifact of the pin compatibility between the CB132 and CB284 package.

!

Note the clock differences between the iCE65L04 and iCE65L08 in the CB196 package.

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Automatic Global Buffer Insertion, Manual Insertion

The iCEcube development software automatically assigns high-fanout signals to a global buffer. However, to

manual insert a global buffer input/global buffer (GBIN/GBUF) combination, use the SB_IO_GB primitive. To

insert just a global buffer (GBUF), use the SB_GBprimitive.

Global Hi-Z Control

The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE65 device. This GHIZ signal is

automatically asserted throughout the configuration process, forcing all user-I/O pins into their high-impedance

state. Similarly, the PIO pins can be forced into their high-impedance state via the JTAG controller.

Global Reset Control

The global reset control signal connects to all PLB and PIO flip-flops on the iCE65 device. The global reset signal is

automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state.

For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application.

See Table 3 for more information.

The PIO flip-flops are always reset during configuration, although the output flip-flop can be inverted before leaving

the iCE65 device, as shown in Figure 11.

RAM

Each iCE65 device includes multiple high-speed synchronous RAM blocks (RAM4K), each 4Kbit in size. As shown

in Table 16 a single iCE65 integrates between 16 to 96 such blocks. Each RAM4K block is generically a 256-word

deep by 16-bit wide, two-port register file, as illustrated in Figure 17. The input and output connections, to and

from a RAM4K block, feed into the programmable interconnect resources.

Figure 17: RAM4K Memory Block

Write Port

Read Port

WDATA[15:0]

MASK[15:0]

WADDR[7:0]

RDATA[15:0]

RADDR[7:0]

RAM4K

RAM Block

(256x16)

WE

RE

WCLKE

WCLK

RCLKE

RCLK

Table 16: RAM4K Blocks per Device

Default

Configuration

Device

RAM4K Blocks

16

RAM Bits per Block

Block RAM Bits

64K

iCE65L01

4K

(4,096)

iCE65L04

iCE65L08

20

32

256 x 16

80K

128K

Using programmable logic resources, a RAM4K block implements a variety of logic functions, each with

configurable input and output data width.

 Random-access memory (RAM)

 Single-port RAM with a common address, enable, and clock control lines

 Two-port RAM with separate read and write control lines, address inputs, and enable

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iCE65 Ultra Low-Power mobileFPGA^™Family

 Register file and scratchpad RAM

 First-In, First-Out (FIFO) memory for data buffering applications

 Circuit buffer

 A 256-deep by 16-wide ROM with registered outputs, contents loaded during configuration

 Sixteen different 8-input look-up tables

 Function or waveform tables such as sine, cosine, etc.

 Correlators or pattern matching operations

 Counters, sequencers

As pictured in Figure 17, a RAM4K block has separate write and read ports, each with independent control signals.

Table 17 lists the signals for both ports. Additionally, the write port has an active-Low bit-line write-enable control;

optionally mask write operations on individual bits. By default, input and output data is 16 bits wide, although the

data width is configurable using programmable logic and, if needed, multiple RAM4K blocks.

The WCLK and RCLK inputs optionally connect to one of the following clock sources.

 The output from any one of the eight Global Buffers, or

 A connection from the general-purpose interconnect fabric

The data contents of the RAM4K block are optionally pre-loaded during iCE65 device configuration. If the RAM4K

blocks are not pre-loaded during configuration, then the resulting configuration bitstream image is smaller.

However, if an uninitialized RAM4K block is used in the application, then the application must initialize the RAM

contents to guarantee the data value.

See Table 56 for detailed timing information.

Signals

Table 17 lists the signal names, direction, and function of each connection to the RAM4K block. See also Figure 17.

Table 17: RAM4K Block RAM Signals

Signal Name

WDATA[15:0]

MASK[15:0]

Direction

Input

Description

Write Data input.

Masks write operations for individual data bit-lines.

0 = Write bit; 1 = Don’t write bit

WADDR[7:0]

WE

WCLKE

WCLK

RDATA[15:0]

RADDR[7:0]

RE

Input

Output

Input

Write Address input. Selects one of 256 possible RAM locations.

Write Enable input.

Write Clock Enable input.

Write Clock input. Default rising-edge, but with falling-edge option.

Read Data output.

Read Address input. Selects one of 256 possible RAM locations.

Read Enable input.

RCLKE

RCLK

Read Clock Enable input.

Read Clock input. Default rising-edge, but with falling-edge option.

Write Operations

Figure 18 shows the logic involved in writing a data bit to a RAM location. Table 18 describes various write

operations for a RAM4K block. By default, all RAM4K write operations are synchronized to the rising edge of

WCLK although the clock is invertible as shown in Figure 18.

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Figure 18: RAM4K Bit Write Logic

RAM[LOCATION][BIT]

WDATA[BIT]

MASK[BIT]

WE

D

EN

WADDR[7:0]

WCLKE

WCLK

When the WCLKE signal is Low, the clock to the RAM4K block is disabled, keeping the RAM in its lowest power

mode.

Table 18: RAM4K Write Operations

WDATA[15:0] MASK[15:0] WADDR[7:0]

WE

Write

WCLKE WCLK

Clock

Operation

Disabled

Write

Data

Masked

Write

Data

X

Mask Bit

Address

Enable Enable Clock

RAM Location

No change

X

0

X

1

0

X

↑

No change

RAM[WADDR][i]

= WDATA[i]

RAM[WADDR][i]

= No change

X

0

1

WDATA[i]

MASK[i] = 0

WADDR

1

↑

X

MASK[i] = 1

WADDR

1

To write data into the RAM4K block, perform the following operations.

 Supply a valid address on the WADDR[7:0] address input port

 Supply valid data on the WDATA[15:0] data input port

 To write or mask selected data bits, set the associated MASK input port accordingly. For example, write

operations on data bit D[i] are controlled by the associated MASK[i] input.

 MASK[i] = 0: Write operations are enabled for data line WDATA[i]

 MASK[i] = 1: Mask write operations are disabled for data line WDATA[i]

 Enable the RAM4K write port (WE = 1)

 Enable the RAM4K write clock (WCLKE = 1)

 Apply a rising clock edge on WCLK (assuming that the clock is not inverted)

Read Operations

Figure 19 shows the logic involved in reading a location from RAM. Table 19 describes various read operations for a

RAM4K block. By default, all RAM4K read operations are synchronized to the rising edge of RCLK although the

clock is invertible as shown in Figure 19.

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iCE65 Ultra Low-Power mobileFPGA^™Family

Figure 19: RAM4K Read Logic

Select

Location

RAM[LOCATION]

Output Register

RDATA[15:0]

Q

D

Q

EN

RADDR[7:0]

RE

RCLKE

RCLK

Table 19: RAM4K Read Operations

RADDR[7:0]

RE

RCLKE

RCLK

Read

Enable

Clock

Enabe

Operation

After configuration, before first

valid Read Data operation

Disabled

Read Data

Address

Clock

RDATA[15:0]

X

Undefined

X

0

1

X

0

X

1

0

X

↑

No Change

No change

X

RADDR

RAM[RADDR]

To read data from the RAM4K block, perform the following operations.

 Supply a valid address on the RADDR[7:0] address input port

 Enable the RAM4K read port (RE = 1)

 Enable the RAM4K read clock (RCLKE = 1)

 Apply a rising clock edge on RCLK

 After the clock edge, the RAM contents located at the specified address (RADDR) appear on the RDATA

output port

Read Data Register Undefined Immediately after Configuration

Unlike the flip-flops in the Programmable Logic Blocks and Programmable I/O pins, the RDATA[15:0] read data

output register is not automatically reset after configuration. Consequently, immediately following configuration

and before the first valid Read Data operation, the initial RDATA[15:0] read value is undefined.

Pre-loading RAM Data

The data contents for a RAM4K block can be optionally pre-loaded during iCE65 configuration. If not pre-loaded

during configuration, then the RAM contents must be initialized by the iCE65 application before the RAM contents

are valid.

Pre-loading the RAM data in the configuration bitstream increases the size of the configuration image accordingly.

RAM Contents Preserved during Configuration

RAM contents are preserved (write protected) during configuration, assuming that voltage supplies are maintained

throughout. Consequently, data can be passed between multiple iCE65 configurations by leaving it in a RAM4K

block and then skipping pre-loading during the subsequent reconfiguration. See “Cold Boot Configuration Option”

and “Warm Boot Configuration Option” for more information.

Low-Power Setting

To place a RAM4K block in its lowest power mode, keep WCLKE = 0 and RCLKE = 0. In other words, when not

actively using a RAM4K block, disable the clock inputs.

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Device Configuration

As described in Table 20, iCE65 components are configured for a specific application by loading a binary

configuration bitstream image, generated by the Lattice development system. For high-volume applications, the

bitstream image is usually permanently programmed in the on-chip NVCM, However, the bitstream image can also

be stored external in a standard, low-cost commodity SPI serial Flash PROM. The iCE65 component can

automatically load the image using the SPI Master Configuration Interface. Similarly, the iCE65 configuration data

can be downloaded from an external processor, microcontroller, or DSP processor using an SPI-like serial interface

or an IEEE 1149 JTAG interface.

Table 20: iCE65 Device Configuration Modes

Mode

NVCM

Analogy

ASIC

Configuration Data Source

Internal, lowest-cost, secure, one-time programmable Nonvolatile Configuration

Memory (NVCM)

SPI Flash

Microprocessor External, low-cost, commodity, SPI serial Flash PROM

SPI

Peripheral

Processor

Peripheral

Configured by external device, such as a processor, microcontroller, or DSP using

practically any data source, such as system Flash, a disk image, or over a network

connection.

JTAG

JTAG configuration requires sending a special command sequence on the SPI

interface to enable JTAG configuration. Configuration is controlled by and external

device.

Configuration Mode Selection

The iCE65 configuration mode is selected according to the following priority described below and illustrated in

Figure 20.

 After exiting the Power-On Reset (POR) state or when CRESET_B returns High after being held Low for

250 ns or more, the iCE65 FPGA samples the logical value on its SPI_SS_B pin. Like other programmable I/O

pins, the SPI_SS_B pin has an internal pull-up resistor (see Input Pull-Up Resistors on I/O Banks 0, 1, and 2).

 If the SPI_SS_B pin is sampled as a logic ‘1’ (High), then …

 Check if the iCE65 is enabled to configure from the Nonvolatile Configuration Memory (NVCM). If the

iCE65 device has NVCM memory (‘F’ ordering code) but the NVCM is yet unprogrammed, then the

iCE65 device is not enabled to configure from NVCM. Conversely, if the NVCM is programmed, the

iCE65 device will configure from NVCM.

 If enabled to configure from NVCM, the iCE65 device configures itself using NVCM.

 If not enabled to configure from NVCM, then the iCE65 FPGA configures using the SPI Master

Configuration Interface.

 If the SPI_SS_B pin is sampled as a logic ‘0’ (Low), then the iCE65 device waits to be configured from an

external controller or from another iCE65 device in SPI Master Configuration Mode using an SPI-like

interface.

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iCE65 Ultra Low-Power mobileFPGA^™Family

Figure 20: Device Configuration Control Flow

Power-Up

CDONE = 0

iCE65 checks that all

required supply voltages

are within acceptable

range

Is Power-On

Reset (POR)

Released?

No

Yes

Holding CRESET_B Low

delays the start of

configuration

CRESET_B = High?

State of SPI_SS_B

Yes

SPI_SS_B = High?

Yes

pin sampled

No

CCoonnfifgiguurreeafsroSmPI

PNerVipChMal

A device with an

unprogrammed NVCM is not

enabled for configuration.

Yes

NVCM Enabled for

Configuration?

Configure from

NVCM

No

Configure from

SPI Flash PROM

CDONE = 1

After configuration ends,

pulse the CRESET_B pin

Low for 250 ns or longer to

restart configuration process

or cycle the power

No

CRESET_B = Low?

Yes

Configuration Image Size

Table 23 shows the number of memory bits required to configure an iCE65 device. Two values are provided for each

device. The “Logic Only” value indicates the minimum configuration size, the number of bits required to configure

only the logic fabric, leaving the RAM4K blocks uninitialized. The “Logic + RAM4K” column indicates the

maximum configuration size, the number of bits to configure the logic fabric and to pre-initialize all the RAM4K

blocks.

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Table 21: iCE65 Configuration Image Size (Kbits)

MINIMUM

Logic Only

MAXIUM

Logic + RAM4K

Device

(RAM4K not initialized)

(RAM4K pre-initialized)

iCE65L01

181 Kbits

245 Kbits*

iCE65L04

iCE65L08

453 Kbits

929 Kbits

533 Kbits

1,057 Kbits

* Note: only 14 of the 16 RAM4K Memory Blocks may be pre-initialized in the iCE65L01.

Nonvolatile Configuration Memory (NVCM)

All standard iCE65 devices have an internal, nonvolatile configuration memory (NVCM). The NVCM is large

enough to program a complete iCE65 device, including initializing all RAM4K block locations (MAXIMUM column

in Table 23. The NVCM memory also has very high programming yield due to extensive error checking and

correction (ECC) circuitry.

The NVCM is ideal for cost-sensitive, high-volume production applications, saving the cost and board space

associated with an external configuration PROM. Furthermore, the NVCM provides exceptional design security,

protecting critical intellectual property (IP). The NVCM contents are entirely contained within the iCE65 device

and are not readable once protected by the one-time programmable Security bits. Furthermore, there is no

observable difference between a programmed or un-programmed memory cell using optical or electron microscopy.

The NVCM memory has a programming interface similar to a 25-series SPI serial Flash PROM. Consequently, it can

be programmed using standard device programmers before or after circuit board assembly or programmed in-system

from a microprocessor or other intelligent controller. NVCM programming requires VCCIO_1, Bank 1 voltage to be

applied on power-up, at the same time as other voltage supplies.

Configuration Control Signals

The iCE65 configuration process is self-timed and controlled by a few internal signals and device I/O pins, as

described in Table 22.

Table 22: iCE65 Configuration Control Signals

Signal

Name

POR

OSC

CRESET_B

CDONE

Direction

Internal control

Input

Description

Internal Power-On Reset (POR) circuit.

Internal configuration oscillator.

Configuration Reset input. Active-Low. No internal pull-up resistor.

Open-drain Output Configuration Done output. Permanent, weak pull-up resistor to VCCIO_2.

The Power-On Reset circuit, POR, automatically resets the iCE65 component to a known state during power-up

(cold boot). The POR circuit monitors the relevant voltage supply inputs, as shown in Figure 22. Once all supplies

exceed their minimum thresholds, the configuration controller can start the configuration process.

The configuration controller begins configuring the iCE65 device, clocked by the Internal Oscillator, OSC. The OSC

oscillator continues controlling configuration unless the iCE65 device is configured using the SPI Peripheral

Configuration Interface.

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iCE65 Ultra Low-Power mobileFPGA^™Family

Figure 21: iCE65 Configuration Control Pins

Optional Pull-up

Required if driven by

Recommended if

SiliconBlue

iCE65

open-drain output

driving another device

VCCIO_2

I/O Bank 2

10 kΩ

CRESET_B

CDONE

Rising edge starts

Pulse

Configured

configuration process.

CRESET_B

Low for 200

ns to restart

configuration

PIOs activate 49

configuration clock

cycles after CDONE

goes High

Low resets iCE65

Unconfigured

Figure 21 shows the two iCE65 configuration control pins, CRESET_B and CDONE. Table 23 lists the ball/pin

numbers for the configuration control pins by package. When driven Low for at least 200 ns, the dedicated

Configuration Reset input, CRESET_B, resets the iCE65 device. When CRESET_B returns High, the iCE65 FPGA

restarts the configuration process from its power-on conditions (Cold Boot). The CRESET_B pin is a pure input

with no internal pull-up resistor. If driven by open-drain driver or un-driven, then connect the CRESET_B pin to a

10 kΩ pull-up resistor connected to the VCCIO_2 supply.

Table 23: Configuration Control Ball/Pin Numbers by Package

Configuration

Control Pins

CRESET_B

CDONE

CB81

J6

H6

QN84

A21

B16

VQ100

44

CB132

L10

M10

CB196

L10

M10

CB284

R14

T14

43

The iCE65 device signals the end of the configuration process by actively turning off the internal pull-down

transistor on the Configuration Done output pin, CDONE. The pin has a permanent, weak internal pull-up resistor

to the VCCIO_2 rail. If the iCE65 device drives other devices, then optionally connect the CDONE pin to a 10 kΩ

pull-up resistor connected to the VCCIO_2 supply.

The PIO pins activate according to their configured function after 49 configuration clock cycles. The internal

oscillator is the configuration clock source for the SPI Master Configuration Interface and when configuring from

* Note: only 14 of the 16 RAM4K Memory Blocks may be pre-initialized in the iCE65L01.

Nonvolatile Configuration Memory (NVCM). When using the SPI Peripheral Configuration Interface, the

configuration clock source is the SPI_SCK clock input pin.

Internal Oscillator

During SPI Master or NVCM configuration mode, the controlling clock signal is generated from an internal

oscillator. The oscillator starts operating at the Default frequency. During the configuration process, however, bit

settings within the configuration bitstream can specify a higher-frequency mode in order to maximize SPI

bandwidth and reduce overall configuration time. See Table 57: Internal Oscillator Frequency on page 105 for the

specified oscillator frequency range.

Using the SPI Master Configuration Interface, internal oscillator controls all the interface timing and clocks the SPI

serial Flash PROM via the SPI_SCK clock output pin.

The oscillator output, which also supplies the SPI SCK clock output during the SPI Flash configuration process, has

a 50% duty cycle.

Internal Device Reset

Figure 22 presents the various signals that internally reset the iCE65 internal logic.

 Power-On Reset (POR)

 CRESET_B Pin

 JTAG Interface

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Figure 22: iCE65 Internal Reset Circuitry

Internal

Voltage

Thresholds

Power-on

Device Pins

Reset (POR)

SPI_VCC

Time-out

Delay

SPI_VCCT

VCCT

VCC

VCCIO_2

VPP_2V5

VCCIO_2T

VPP_2V5T

Internal Reset

Glitch Filter

CRESET_B

TDI

TMS

TCK

JTAG

TDO

TRST_B

Power-On Reset (POR)

The Power-on Reset (POR) circuit monitors specific voltage supply inputs and holds the device in reset until all the

relevant supplies exceed the internal voltage thresholds. The SPI_VCC supply also has an additional time-out delay

to allow an attached SPI serial PROM to power up properly. Table 24 shows the POR supply inputs. The

Nonvolatile Configuration Memory (NVCM) requires that the VPP_2V5 supply be connected, even if the

application does not use the NVCM.

Table 24: Power-on Reset (POR) Voltage Resources

Supply Rail

VCC

SPI_VCC

VCCIO_1

VCCIO_2

VPP_2V5

iCE65 Production Devices

Yes

No

Yes

CRESET_B Pin

The CRESET_B pin resets the iCE65 internal logic when Low.

JTAG Interface

Specific command sequences also reset the iCE65 internal logic.

SPI Master Configuration Interface

All iCE65 devices, including those with NVCM, can be configured from an external, commodity SPI serial Flash

PROM, as shown in Figure 23. The SPI configuration interface is essentially its own independent I/O bank, powered

by the VCC_SPI supply input. Presently, most commercially-available SPI serial Flash PROMs require a 3.3V

supply.

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iCE65 Ultra Low-Power mobileFPGA^™Family

Figure 23: iCE65 SPI Master Configuration Interface

+3.3V

SPI_VCC

10 kΩ

SPI_SO

SiliconBlue

iCE65

(SPI bank)

SPI_SI

Commodity SPI

Serial Flash

PROM

SPI_SS_B

SPI_SCK

The SPI configuration interface is used primarily during development before mass production, where the

configuration is then permanently programmed in the NVCM configuration memory. However, the SPI interface

can also be the primary configuration interface allowing easy in-system upgrades and support for multiple

configuration images.

The SPI control signals are defined in Table 25. Table 26 lists the SPI interface ball or pins numbers by package.

Table 25: SPI Master Configuration Interface Pins (SPI_SS_B High before Configuration)

Signal Name

SPI_VCC

SPI_SO

SPI_SI

SPI_SS_B

SPI_SCK

Direction

Supply

Output

Input

Output

Description

SPI Flash PROM voltage supply input.

SPI Serial Output from the iCE65 device.

SPI Serial Input to the iCE65 device, driven by the select SPI serial Flash PROM.

SPI Slave Select output from the iCE65 device. Active Low.

SPI Slave Clock output from the iCE65 device.

After configuration, the SPI port pins are available to the user-application as additional PIO pins, supplied by the

SPI_VCC input voltage, essentially providing a fifth “mini” I/O bank.

Table 26: SPI Interface Ball/Pin Numbers by Package

SPI Interface

SPI_VCC

VQ100

50

CB132

L11

CB196

L11

CB284

R15

PIOS/SPI_SO

PIOS/SPI_SI

PIOS/SPI_SS_B

PIOS/SPI_SCK

45

46

49

48

M11

P11

P13

M11

P11

P13

T15

V15

V17

V16

P12

SPI PROM Requirements

The iCE65 mobileFPGA SPI Flash configuration interface supports a variety of SPI Flash memory vendors and

product families. However, Lattice Semiconductor does not specifically test, qualify, or otherwise endorse any

specific SPI Flash vendor or product family. The iCE65 SPI interface supports SPI PROMs that they meet the

following requirements.

 The PROM must operate at 3.3V or 2.5V in order to trigger the iCE65 FPGA’s power-on reset circuit.

 The PROM must support the 0x0BFast Read command, using a 24-bit start address and has 8 dummy bits

before the PROM provides first data (see Figure 25: SPI Fast Read Command).

 The PROM must have enough bits to program the iCE65 device (see Table 27: Smallest SPI PROM Size

(bits), by Device, by Number of Images).

 The PROM must support data operations at the upper frequency range for the selected iCE65 internal

oscillator frequency (see Table 57). The oscillator frequency is selectable when creating the FPGA bitstream

image.

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 For lowest possible power consumption after configuration, the PROM should also support the 0xB9Deep

Power Down command and the 0xABRelease from Deep Power-down Command (see Figure 24 and Figure

26). The low-power mode is optional.

 The PROM must be ready to accept commands 10 µs after meeting its power-on conditions. In the PROM

data sheet, this may be specified as t_VSLor t_VCSL. It is possible to use slower PROMs by holding the

CRESET_B input Low until the PROM is ready, then releasing CRESET_B, either under program control or

using an external power-on reset circuit.

The Lattice iCEman65 development board and associated programming software uses an ST Micro/Numonyx

M25Pxx SPI serial Flash PROM.

SPI PROM Size Requirements

Table 27 lists the minimum SPI PROM size required to configure an iCE65 device. Larger PROM sizes are allowed,

but not required unless the end application uses the additional space. SPI serial PROM sizes are specified in bits.

For each device size, the table shows the required minimum PROM size for “Logic Only” (no BRAM initialization)

and “Logic + RAM4K” (RAM4K blocks pre-initialized). Furthermore, the table shows the PROM size for varying

numbers of configuration images. Most applications will use a single image. Applications that use the Cold Boot or

Warm Boot features may use more than one image.

Table 27: Smallest SPI PROM Size (bits), by Device, by Number of Images

1 Image

2 Images

3 Images

4 Images

Logic

Only

Logic +

RAM4K

Logic

Only

Logic +

RAM4K

Logic

Only

Logic +

RAM4K

Logic

Only

Logic +

RAM4K

Device

iCE65L01

256K

512K

1M

2M

4M

1M

4M

8M

iCE65L04

iCE65L08

512K

1M

2M

4M

2M

4M

2M

4M

Enabling SPI Configuration Interface

To enable the SPI configuration mode, the SPI_SS_B pin must be allowed to float High. The SPI_SS_B pin has an

internal pull-up resistor. If SPI_SS_B is Low, then the iCE65 component defaults to the SPI Slave configuration

mode.

SPI Master Configuration Process

The iCE65 SPI Master Configuration Interface supports a variety of modern, high-density, low-cost SPI serial Flash

PROMs. Most modern SPI PROMs include a power-saving Deep Power-down mode. The iCE65 component

exploits this mode for additional system power savings.

The iCE65 SPI interface starts by driving SPI_SS_B Low, and then sends a Release from Power-down command to

the SPI PROM, hexadecimal command code 0xAB. Figure 24 provides an example waveform. This initial command

wakes up the SPI PROM if it is already in Deep Power-down mode. If the PROM is not in Deep Power-down mode,

the extra command has no adverse affect other than that it requires a few additional microseconds during the

configuration process. The iCE65 device transmits data on the SPI_SO output, on the falling edge of the SPI_SCK

output. The SPI PROM does not provide any data to the iCE65 device’s SPI_SI input. After sending the last

command bit, the iCE65 device de-asserts SPI_SS_B High, completing the command. The iCE65 device then waits a

minimum of 10 µS before sending the next SPI PROM command.

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iCE65 Ultra Low-Power mobileFPGA^™Family

Figure 24: SPI Release from Deep Power-down Command

SPI_SCK

SPI_SS_B

SPI_SO

1

0 1 0 1 0 1 1

0xAB

Release from Deep Power-down

Figure 25 illustrates the next command issued by the iCE65 device. The iCE65 SPI interface again drives SPI_SS_B

Low, followed by a Fast Read command, hexadecimal command code 0x0B, followed by a 24-bit start address,

transmitted on the SPI_SO output. The iCE65 device provides data on the falling edge of SPI_SS_B. Upon initial

power-up, the start address is always 0x00_0000. After waiting eight additional clock cycles, the iCE65 device

begins reading serial data from the SPI PROM. Before presenting data, the SPI PROM’s serial data output is high-

impedance. The SPI_SI input pin has an internal pull-up resistor and sees high-impedance as logic ‘1’.

Figure 25: SPI Fast Read Command

SPI_SCK

SPI_SS_B

SPI_SO

SPI_SI

0

1

0

1

X X X X X X X X

0x0B

Fast Read

24-bit Start Address

Don’t Care

Dummy Byte

PROM output is Hi-Z. Pulled High in SPI_SI pin via internal pull-up resistor.

Data Byte 0

The external SPI PROM supplies data on the falling edge of the iCE65 device’s SPI_SCK clock output. The iCE65

device captures each PROM data value on the SPI_SI input, using the rising edge of the SPI_SCK clock signal. The

SPI PROM data starts at the 24-bit address presented by the iCE65 device. PROM data is serially output, byte by

byte, with most-significant bit, D7, presented first. The PROM automatically increments an internal byte counter as

long as the PROM is selected and clocked.

After transferring the required number configuration data bits, the iCE65 device ends the Fast Read command by

de-asserting its SPI_SS_B PROM select output, as shown in Figure 26. To conserve power, the iCE65 device then

optionally issues a final Deep Power-down command, hexadecimal command code 0xB9. After de-asserting the

SPI_SS_B output, the SPI PROM enters its Deep Power-down mode. The final power-down step is optional; the

application may use the SPI PROM and can skip this step, controlled by a configuration option.

Figure 26: Final Configuration Data, SPI Deep Power-down Command

SPI_SCK

SPI_SS_B

SPI_SO

SPI_SI

1 0 1 1 1 0 0 1

0xB9

Deep Power-down

Last Data Byte

Fast Read data

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Cold Boot Configuration Option

By default, the iCE65 FPGA is programmed with a single configuration image, either from internal NVCM memory,

from an external SPI Flash PROM, or externally from a processor or microcontroller.

Figure 27: ColdBoot and WarmBoot Configuration

At power-up or

after reset

CBSEL1

0

Jump based

on settings

Enable/Disable Cold Boot

Enable/Disable Warm Boot

Jump vector addresses (4)

Cold/Warm Boot

Applet

CBSEL0

CRESET_B

Cold Boot

Control

Vector Address 0

Vector Address 1

Vector Address 2

Vector Address 3

Configuration

Image 0

Power-On

Reset

(0,0)

(0,1)

(1,0)

(1,1)

SB_WARMBOOT

S1

S0

Configuration

Image 1

Warm

Boot

Control

BOOT

Configuration

Image 2

Controlled by

currently loaded

iCE65 application

Configuration

Image 3

SPI PROM

When self loading from NVCM or from an SPI Flash PROM, there is an additional configuration option called Cold

Boot mode. When this option is enabled in the configuration bitstream, the iCE65 FPGA boots normally from

power-on or a master reset (CRESET_B = Low pulse), but monitors the value on two PIO pins that are borrowed

during configuration, as shown in Figure 27. These pins, labeled PIO2/CBSEL0 and PIO2/CBSEL1, tell the FPGA

which of the four possible SPI configurations to load into the device. Table 30 provides the pin or ball locations for

these pins.

 Load from initial location, either from NVCM or from address 0 in SPI Flash PROM. For Cold Boot or

Warm Boot applications, the initial configuration image contains the cold boot/warm boot applet.

 Check if Cold Boot configuration feature is enabled in the bitstream.

 If not enabled, FPGA configures normally.

 If Cold Boot is enabled, then the FPGA reads the logic values on pins CBSEL[1:0]. The FPGA uses the

value as a vector and then reads from the indicated vector address.

 At the selected CBSEL[1:0] vector address, there is a starting address for the selected configuration

image.

 For SPI Flash PROMs, the new address is a 24-bit start address in Flash.

 If the selected bitstream is in NVCM, then the address points to the internal NVCM.

 Using the new start address, the FPGA restarts reading configuration memory from the new location.

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Table 28: ColdBoot Select Ball/Pin Numbers by Package

ColdBoot Select

PIO2/CBSEL0

PIO2/CBSEL1

CB81

G5

H5

QN84

B15

A20

VQ100

41

CB132

L9

P10

CB196

L9

P10

CB284

R13

V14

42

When creating the initial configuration image, the Lattice development software loads the start address for up to

four configuration images in the bitstream. The value on the CBSEL[1:0] pins tell the configuration controller to

read a specific start address, then to load the configuration image stored at the selected address. The multiple

bitstreams are stored either in the SPI Flash or in the internal NVCM.

After configuration, the CBSEL[1:0] pins become normal PIO pins available to the application.

The Cold Boot feature allows the iCE65 to be reprogrammed for special application requirements such as the

following.

 A normal operating mode and a self-test or diagnostics mode.

 Different applications based on switch settings.

 Different applications based on a card-slot ID number.

Warm Boot Configuration Option

The Warm Boot configuration is similar to the Cold Boot feature, but is completely under the control of the FPGA

application.

A special design primitive, SB_WARMBOOT, allows an FPGA application to choose between four configuration

images using two internal signal ports, S1 and S0, as shown in Figure 27. These internal signal ports connect to

programmable interconnect, which in turn can connect to PLB logic and/or PIO pins.

After selecting the desired configuration image, the application then asserts the internal signal BOOT port High to

force the FPGA to restart the configuration process from the specified vector address stored in PROM.

A Warm Boot application can only jump to another configuration image that DOES NOT have Warm

Boot enabled. There is no such restriction for Cold Boot applications.

!

Time-Out and Retry

When configuring from external SPI Flash, the iCE65 device looks for a synchronization word. If the device does

not find a synchronization word within its timeout period, the device automatically attempts to restart the

configuration process from the very beginning. This feature is designed to address any potential power-sequencing

issues that may occur between the iCE65 device and the external PROM.

The iCE65 device attempts to reconfigure six times. If not successful after six attempts, the iCE65 FPGA

automatically goes into low-power mode.

SPI Peripheral Configuration Interface

Using the SPI peripheral configuration interface, an application processor (AP) serially writes a configuration image

to an iCE65 FPGA using the iCE65’s SPI interface, as shown in Figure 23. The iCE65’s SPI configuration interface is

a separate, independent I/O bank, powered by the VCC_SPI supply input. Typically, VCC_SPI is the same voltage as

the application processor’s I/O. The configuration control signals, CDONE and CRESET_B, are supplied by the

separate I/O Bank 2 voltage input, VCCIO_2.

This same SPI peripheral interface supports programming for the iCE65’s Nonvolatile Configuration Memory

(NVCM).

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Figure 28: iCE65 SPI Peripheral Configuration Interface

AP_VCCIO VCCIO_2

VCCIO_2

SPI_VCC

10 kΩ

CDONE

AP_VCCIO

iCE65

CRESET_B (I/O Bank 2)

Application

Processor

SPI_SI

SPI_SO

iCE65

(SPI Bank)

SPI_SS_B

SPI_SCK

10 kΩ

The SPI control signals are defined in Table 25.

Table 29: SPI Peripheral Configuration Interface Pins (SPI_SS_B Low when CRESET_B Released)

Signal

Name

iCE65 I/O

Supply

Direction

Description

CDONE

AP  iCE65

VCCIO_2

Configuration Done output from iCE65. Connect to a 10kΩ pull-up

resistor to the application processor I/O voltage, AP_VCC.

Configuration Reset input on iCE65. Typically driven by AP using an

open-drain driver, which also requires a 10kΩ pull-up resistor to

VCCIO_2.

CRESET_B

AP  iCE65

SPI_VCC

SPI_SI

SPI_SO

Supply

AP  iCE65

AP  iCE65

SPI_VCC

SPI Flash PROM voltage supply input.

SPI Serial Input to the iCE65 FPGA, driven by the application processor.

SPI Serial Output from CE65 device to the application processor. Not

actually used during SPI peripheral mode configuration but required if

the SPI interface is also used to program the NVCM.

SPI Slave Select output from the application processor. Active Low.

Optionally hold Low prior to configuration using a 10kΩ pull-down

resistor to ground.

SPI_SS_B

SPI_SCK

AP  iCE65

SPI Slave Clock output from the application processor.

After configuration, the SPI port pins are available to the user-application as additional PIO pins, supplied by the

SPI_VCC input voltage, essentially providing a fifth “mini” I/O bank.

Enabling SPI Configuration Interface

The optional 10 kΩ pull-down resistor on the SPI_SS_B signal ensures that the iCE65 FPGA powers up in the SPI

peripheral mode. Optionally, the application processor drives the SPI_SS_B pin Low when CRESET_B is released,

forcing the iCE65 FPGA into SPI peripheral mode.

SPI Peripheral Configuration Process

Figure 29 illustrates the interface timing for the SPI peripheral mode and Figure 30 outlines the resulting

configuration process. The actual timing specifications appear in Table 60. The application processor (AP) begins

by driving the iCE65 CRESET_B pin Low, resetting the iCE65 FPGA. Similarly, the AP holds the iCE65’s SPI_SS_B

pin Low. The AP must hold the CRESET_B pin Low for at least 200 ns. Ultimately, the AP either releases the

CRESET_B pin and allows it to float High via the 10 kΩ pull-up resistor to VCCIO_2 or drives CRESET_B High. The

iCE65 FPGA enters SPI peripheral mode when the CRESET_B pin returns High while the SPI_SS_B pin is Low.

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iCE65 Ultra Low-Power mobileFPGA^™Family

After driving CRESET_B High or allowing it to float High, the AP must wait a minimum of t_{CR_SCK}µs, (see Table 60)

allowing the iCE65 FPGA to clear its internal configuration memory.

After waiting for the configuration memory to clear, the AP sends the configuration image generated by the iCEcube

development system. An SPI peripheral mode configuration image must not use the ColdBoot or WarmBoot

options. Send the entire configuration image, without interruption, serially to the iCE65’s SPI_SI input on the falling

edge of the SPI_SCK clock input. Once the AP sends the 0x7EAA997Esynchronization pattern, the generated

SPI_SCK clock frequency must be within the specified 1 MHz to 25 MHz range (40 ns to 1 µs clock period) while

sending the configuration image. Send each byte of the configuration image with most-significant bit (msb) first.

The AP sends data to the iCE65 FPGA on the falling edge of the SPI_SCK clock. The iCE65 FPGA internally

captures each incoming SPI_SI data bit on the rising edge of the SPI_SCK clock. The iCE65’s SPI_SO output pin is

not used during SPI peripheral mode but must connect to the AP if the AP also programs the iCE65’s Nonvolatile

Configuration Memory (NVCM).

Prior to sending the iCE65 configuration image , an SPI NVCM shut-off sequence must be sent.

See AN014 for details.

The iCE65 configuration image must be sent as one contiguous stream without interruption.

!

The SPI_SCK clock period must be between 40 ns to 1 µs (1 MHz to 25 MHz).

After sending the entire image, the iCE65 FPGA releases the CDONE output allowing it to float High via the 10 kΩ

pull-up resistor to AP_VCC. If the CDONE pin remains Low, then an error occurred during configuration and the

AP should handle the error accordingly for the application.

After the CDONE output pin goes High, send at least 49 additional dummy bits, effectively 49 additional SPI_SCK

clock cycles measured from rising-edge to rising-edge.

After the additional SPI_CLK cycles, the SPI interface pins then become available to the user application loaded in

FPGA.

To reconfigure the iCE65 FPGA or to load a different configuration image, merely restart the configuration process

by pulsing CRESET_B Low or power-cycling the FPGA.

Figure 29: Application Processor Waveforms for SPI Peripheral Mode Configuration Process

CDONE

49 SPI_SCK Cycles

Rising edge to rising edge

≥ 200 ns

CRESET_B

iCE65L01: ≥ 800 µs

iCE65L04: ≥ 800 µs

iCE65L08: ≥ 1200 µs

iCE65 clears internal

configuration memory

iCE65 enters SPI Peripheral

mode with SPI_SS_B = Low on

SPI_SCK

rising edge of CRESET_B

iCE65 captures SPI_SI data on SPI_SCK rising edge.

SPI_SS_B

Configuration image always starts with 0x7EAA997Esynchronization word.

SPI_SI

SPI_SO

X

Entire Configuration Images

Don’t Care

Send most-significant bit of each byte first

49 dummy bits

Pulled High in SPI_SO pin via internal pull-up resistor. Not used for SPI Peripheral mode configuration. Used when programming NVCM via SPI itnterface.

The iCE65 configuration image must be sent as one contiguous stream without interruption.

The SPI_SCK clock period must be between 40 ns to 1 µs (1 MHz to 25 MHz).

!

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Figure 30: SPI Peripheral Configuration Process

SPI Peripheral Configuration

Drive CRESET_B = 0

Drive SPI_SS_B = 0, SPI_SCK = 1

Wait a minimum of 200 ns

Release CRESET_B or drive

CRESET_B = 1

Wait a minimum of

iC65L01: 800 µs

iC65L04: 800 µs

iC65L08: 1200 µs

to clear internal config. memory

Send NVCM shut-off sequence

Send configuration image serially

on SPI_SI to iCE65, most-

significant bit first, on falling edge

of SPI_SCK. Send the entire

image, without interruption.

Ensure that SPI_SCK frequency is

between 1 MHz and 25 MHz.

NO

CDONE = 1?

YES

ERROR!

Send a minimum of 49 additional

dummy bits and 49 additional

SPI_SCK clock cycles (rising-edge

to rising-edge) to active the

user-I/O pins.

SPI interface pins available as user-

defined I/O pins in application

NO

Reconfigure?

YES

Voltage Compatibility

As shown in Figure 23, there are potentially three different supply voltages involved in the SPI Peripheral interface,

described in Table 30.

Table 30: SPI Peripheral Mode Supply Voltages

Supply Voltage

AP_VCCIO

Description

I/O supply to the Application Processor (AP)

VCC_SPI

VCCIO_2

Voltage supply for the iCE65 SPI interface.

Supply voltage for the iCE65 I/O Bank 2.

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iCE65 Ultra Low-Power mobileFPGA^™Family

Table 31 describes how to maintain voltage compatibility for two interface scenarios. The easiest interface is when

the Application Processor’s (AP) I/O supply rail and the iCE65’s SPI and VCCIO_2 bank supply rails all connect to

the same voltage. The second scenario is when the AP’s I/O supply voltage is greater than the iCE65’s VCCIO_2

supply voltage.

Table 31: CRESET_B and CDONE Voltage Compatibility

CRESET_B

Open-

Drain

OK with

pull-up

CDONE Pull-

up

Condition

VCCIO_AP

= VCC_SPI

Direct

Pull-up

Requirement

OK

Required if Recommended AP can directly drive CRESET_B High and

using

open-drain

output

Low although an open-drain output

recommended is if multiple devices control

CRESET_B. If using an open-drain driver,

the CRESET_B input must include a 10 kΩ

pull-up resistor to VCCIO_2. The 10 kΩ

pull-up resistor to AP_VCCIO is also

recommended.

VCCIO_AP

= VCCIO_2

AP_VCCIO

> VCCIO_2

N/A

Required,

requires

pull-up

Required

The AP must control CRESET_B with an

open-drain output, which requires a 10 kΩ

pull-up resistor to VCCIO_2. The 10 kΩ

pull-up resistor to AP_VCCIO is required.

JTAG Boundary Scan Port

Overview

Each iCE65 device includes an IEEE 1149.1-compatible JTAG boundary-scan port. The port supports printed-circuit

board (PCB) testing and debugging. It also provides an alternate means to configure the iCE65 device.

Signal Connections

The JTAG port connections are listed in Table 32.

Table 32: iCE65 JTAG Boundary Scan Signals

Signal

Name

TDI

TMS

TCK

TDO

TRST_B

Direction

Input

Output

Input

Description

Test Data Input. Must be tied off to GND when unused. (no pull-up resistor)*

Test Mode Select. Must be tied off to GND when unused. (no pull-up resistor)*

Test Clock. Must be tied off to GND when unused. (no pull-up resistor)*

Test Data Output.

Test Reset, active Low. Must be Low during normal device operation. Must be High

to enable JTAG operations.*

* Must be tied off to GND or VCCIO_1, else VCCIO_1 draws current.

Table 33 lists the ball/pin numbers for the JTAG interface by package code. The JTAG interface is available in select

package types. The JTAG port is located in I/O Bank 1 along the right edge of the iCE65 device and powered by the

VCCIO_1 supply inputs. Consequently, the JTAG interface uses the associated I/O standards for I/O Bank 1.

Table 33: JTAG Interface Ball/Pin Numbers by Package

JTAG Interface

TDI

VQ100

CB132

M12

P14

CB196

M12

P14

CB284

T16

V18

TMS

N/A

TCK

L12

R16

TDO

N14

U18

TRST_B

M14

T18

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Supported JTAG Commands

The JTAG interface supports the IEEE 1149.1 mandatory instructions, including EXTEST, SAMPLE/PRELOAD, and

BYPASS.

Package and Pinout Information

Maximum User I/O Pins by Package and by I/O Bank

Table 34 lists the maximum number of user-programmable I/O pins by package, with additional detail showing user

I/O pins by I/O bank. In some cases, a smaller iCE65 device is packaged in a larger package with unconnected (N.C.)

pins or balls, resulting in fewer overall I/O pins. See Table 35 for device-specific I/O counts by package.

Table 34: User I/O by Package, by I/O Bank

CB81

81

QN84

84

VQ100

100

CB132

132

CB196

196

CB284

284

Package Leads

Package Body (mm)

5 x 5

9 x 9

0.5

7 x 7

N/A

0.5

14 x 14

N/A

0.5

8 x 8

14 x 14

0.5

8 x 8

14 x 14

0.5

12 x 12

22 x 22

0.5

Ball Array (balls)

Ball/Lead Pitch (mm)

Maximum user I/O,

all I/O banks

63

67

72

95

150

222

PIO Pins in Bank 0

PIO Pins in Bank 1

PIO Pins in Bank 2

PIO Pins in Bank 3

PIO Pins in SPI

Interface

17

16

12

18

17

11

18

19

12

18

26

21

20

24

37

38

35

36

60

55

53

50

4

Printed Circuit Board Layout Information

For information on how to use the iCE65 packages on a printed circuit board (PCB) design, consult the following

application note.

 AN010: iCE65 Printed Circuit Board (PCB Layout) Guidelines

Maximum User I/O by Device and Package

Table 35 lists the maximum available user I/O by device and by and package type. Not all devices are available in all

packages. Similarly, smaller iCE65 devices may have unconnected balls in some packages. Devices sharing a

common package have similar footprints.

Table 35: Maximum User I/O by Device and Package

Device

Package

CB81

QN84

VQ100

CB132

CB196

CB284

iCE65L01

iCE65L04

iCE65L08

63

67

72

93

—

72

95

150

176

—

150

222

—

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39

iCE65 Ultra Low-Power mobileFPGA^™Family

iCE65 Pin Descriptions

Table 36 lists the various iCE65 pins, alphabetically by name. The table indicates the directionality of the signal and

the associated I/O bank. The table also indicates if the signal has an internal pull-up resistor enabled during

configuration. Finally, the table describes the function of the pin.

Table 36: iCE65 Pin Description

Pull-up

I/O

during

Config

Signal Name

CDONE

Bank

Description

Direction

Configuration Done. Dedicated output. Includes a permanent

weak pull-up resistor to VCCIO_2.. If driving external devices

with CDONE output, connect a 10 kΩ pull-up resistor to

VCCIO_2.

Configuration Reset, active Low. Dedicated input. No internal

pull-up resistor. Either actively drive externally or connect a

10 kΩ pull-up resistor to VCCIO_2.

Global buffer input from I/O Bank 0. Optionally, a full-featured

PIO pin.

Global buffer input from I/O Bank 1. Optionally, a full-featured

PIO pin.

Output

2

Yes

No

CRESET_B

Input

2

0

1

2

GBIN0/PIO0

GBIN1/PIO0

GBIN2/PIO1

GBIN3/PIO1

GBIN4/PIO2

GBIN5/PIO2

Input/IO

Yes

No

Global buffer input from I/O Bank 2. Optionally, a full-featured

PIO pin.

Global buffer input from I/O Bank 3. Optionally, a full-featured

PIO pin.

GBIN6/PIO3

3

Global buffer input from I/O Bank 3. Optionally, a full-featured

PIO pin. Optionally, a differential clock input using the

associated differential input pin.

GBIN7/PIO3

GND

Input/IO

Supply

3

No

All

N/A

Ground. All must be connected.

Programmable I/O pin defined by the iCE65 configuration

bitstream. The ‘x’ number specifies the I/O bank number in

which the I/O pin resides. The “yy’ number specifies the I/O

number in that bank.

PIOx_yy

I/O

0,1,2

Yes

Optional ColdBoot configuration SELect input, if ColdBoot mode

is enabled. A full-featured PIO pin after configuration.

Optional ColdBoot configuration SELect input, if ColdBoot mode

is enabled. A full-featured PIO pin after configuration.

Programmable I/O pin that is also half of a differential I/O pair.

Only available in I/O Bank 3. The “yy” number specifies the I/O

number in that bank. The “ww” number indicates the

differential I/O pair. The ‘z’ indicates the polarity of the pin in

the differential pair. ‘A’=negative input. ‘B’=positive input.

SPI Serial Output. A full-featured PIO pin after configuration.

SPI Serial Input. A full-featured PIO pin after configuration.

SPI Slave Select. Active Low. Includes an internal weak pull-up

resistor to SPI_VCC during configuration. During configuration,

the logic level sampled on this pin determines the configuration

mode used by the iCE65 device, as shown in Figure 20. An

input when sampled at the start of configuration. An input when

in SPI Peripheral configuration mode (SPI_SS_B = Low). An

output when in SPI Flash configuration mode. A full-featured

PIO pin after configuration.

PIO2/CBSEL0 Input/IO

PIO2/CBSEL1 Input/IO

2

Yes

PIO3_yy/

I/O

3

No

DPwwz

PIOS/SPI_SO

PIOS /SPI_SI

I/O

SPI

Yes

PIOS /

SPI_SS_B

I/O

SPI

Yes

SPI Slave Clock. An input when in SPI Peripheral configuration

mode (SPI_SS_B = Low). An output when in SPI Flash

configuration mode. A full-featured PIO pin after configuration.

JTAG Test Data Input. If using the JTAG interface, use a 10kΩ

pull-up resistor to VCCIO_1. Tie off to GND when unused.

PIOS/

SPI_SCK

I/O

SPI

1

Yes

No

TDI

Input

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Pull-up

during

Config

I/O

Bank

Signal Name

TMS

Description

Direction

JTAG Test Mode Select. If using the JTAG interface, use a 10kΩ

pull-up resistor to VCCIO_1. Tie off to GND when unused.

JTAG Test Clock. If using the JTAG interface, use a 10kΩ pull-

up resistor to VCCIO_1. Tie off to GND when unused.

JTAG Test Data Output.

Input

1

No

TCK

Input

Output

Input

1

No

TDO

JTAG Test Reset, active Low. Keep Low during normal

operation; High for JTAG operation.

TRST_B

VCC

1

No

Supply

All

N/A

Internal core voltage supply. All must be connected.

Voltage supply to I/O Bank 0. All such pins or balls on the

package must be connected. Can be disconnected or turned off

without affecting the Power-On Reset (POR) circuit.

Voltage supply to I/O Bank 1. All such pins or balls on the

package must be connected. Required to guarantee a valid

input voltage on TRST_B JTAG pin.

Voltage supply to I/O Bank 2. All such pins or balls on the

package must be connected. Required input to the Power-On

Reset (POR) circuit.

Voltage supply to I/O Bank 3. All such pins or balls on the

package must be connected. Can be disconnected or turned off

without affecting the Power-On Reset (POR) circuit.

SPI interface voltage supply input. Must have a valid voltage

even if configuring from NVCM. Required input to the Power-On

Reset (POR) circuit.

VCCIO_0

VCCIO_1

VCCIO_2

VCCIO_3

Supply

0

1

2

3

N/A

SPI_VCC

Supply

SPI

All

N/A

Direct programming voltage supply. If unused, leave floating or

unconnected during normal operation.

VPP_FAST

Programming supply voltage. When the iCE65 device is active,

VPP_2V5 must be in the valid range between 2.3 V to 3.47 V to

release the Power-On Reset circuit, even if the application is not

using the NVCM.

VPP_2V5

Supply

All

N/A

Input reference voltage in I/O Bank 3 for the SSTL I/O standard.

This pin only appears on the CB284 package and for die-based

products.

Voltage

Reference

VREF

3

N/A

N/A = Not Applicable

iCE65 Package Footprint Diagram Conventions

Figure 31 illustrates the naming conventions used in the following footprint diagrams. Each PIO pin is associated

with an I/O Bank. PIO pins in I/O Bank 3 that support differential inputs are also numbered by differential input

pair.

Figure 31: CB Package Footprint Diagram Conventions

Ball column number

1

Ball row number

Single-ended PIO Numbering

PIO0

A PIO0

Ball number A1

I/O bank number

PIO3/

DP07A

Differential Input Pair Numbering

_DifferentialB

PIO0/

DP07A

Input Pair

Indicators

Pair pin polarity

Pair number

PIO3/

DP07B

C

Differential Pair

Dot indicates unconnected pin

for iCE65L04 in CB284 package

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iCE65 Ultra Low-Power mobileFPGA^™Family

CB81 Chip-Scale Ball-Grid Array

The CB81 package is a full ball grid array with 0.5 mm ball pitch. The iCE65L01 device is available in this package.

Footprint Diagram

Figure 32 shows the iCE65 footprint diagram for the CB81 package.

Figure 31 shows the conventions used in the diagram.

Also see Table 37 for a complete, detailed pinout for the 81-ball BGA package.

The signal pins are also grouped into the four I/O Banks and the SPI interface.

Figure 32: iCE65L01 CB81 Chip-Scale BGA Footprint (Top View)

I/O Bank 0

1

2

3

4

5

6

7

8

9

GBIN0

/PIO0

VCCIO_0

GND

PIO0 PIO0

PIO0

VCC

PIO0 PIO0 GND

A

B

C

D

VPP_

2V5

PIO3

PIO3 PIO3 PIO0 PIO0 PIO0 PIO0 PIO0

B

C

PIO3 PIO3 PIO3 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1

GBIN1

D ^GBIN7

PIO3

VCCIO_1

PIO3

PIO0

PIO1 PIO1

/PIO3

/PIO0

E ^GBIN6

PIO0 PIO1 PIO1 PIO1 E

GND

PIO3 PIO3

/PIO3

GBIN2GBIN3

/PIO1 /PIO1

PIO3

GND GND

PIO3

VCCIO_3

F

G

H

J

PIO1

PIO2/

SEL0

PIO2 PIO2

PIO1 PIO1

G

H

J

PIO3 PIO3

GBIN5 PIO2/

/PIO2 SEL1

SPI_

VCC

PIOS/ PIOS/

CDONE

PIO3 PIO3 PIO2

SPI_SO SPI_SS_B

GBIN4

_{CRESET_B}PIOS/ PIOS/

/PIO2 ^VCCIO_2

GND PIO2

VCC

GND

SPI_SI SPI_SCK

1

2

3

4

5

6

7

8

9

I/O Bank 2

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Pinout Table

Table 37 provides a detailed pinout table for the CB81 package. Pins are generally arranged by I/O bank, then by ball

function.

Table 37: iCE65 CB81 Chip-scale BGA Pinout Table

Ball Function

PIO0

GBIN0/PIO0

PIO0

Ball Number

Pin Type

PIO

GBIN

PIO

Bank

0

A2

A3

A4

A7

A8

B4

B5

B6

B7

B8

C4

C5

C6

D4

D5

D6

E6

A6

PIO0

PIO

GBIN

PIO

PIO0

GBIN1/PIO0

PIO0

VCCIO_0

0

VCCIO

PIO1

C7

C8

C9

D7

D8

E7

E8

E9

F6

F7

F8

F9

G6

G7

G8

G9

D9

PIO

GBIN

PIO

VCCIO

1

GBIN2/PIO1

GBIN3/PIO1

PIO1

VCCIO_1

CDONE

CRESET_B

PIO2

PIO2/CBSEL0

PIO2

GBIN5/PIO2

PIO2/CBSEL1

PIO2

GBIN4/PIO2

VCCIO_2

H6

J6

CONFIG

PIO

2

G3

G4

G5

H3

H4

H5

J2

J3

J4

PIO

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iCE65 Ultra Low-Power mobileFPGA^™Family

Ball Function

Ball Number

Pin Type

Bank

PIO3

B1

B2

B3

C1

C2

C3

D1

D2

D3

E1

E2

E3

F2

F3

G1

G2

H1

H2

F1

PIO

GBIN

PIO

GBIN

PIO

VCCIO

3

PIO3

GBIN7/PIO3

PIO3

GBIN6/PIO3

PIO3

VCCIO_3

PIOS/SPI_SO

PIOS/SPI_SI

PIOS/SPI_SCK

PIOS/SPI_SS_B

SPI_VCC

H7

J7

J8

H8

H9

SPI

GND

VCC

A1

A9

J9

GND

VCC

GND

VCC

J1

E4

E5

F4

F5

A5

J5

VCC

VPP_2V5

B9

VPP

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Package Mechanical Drawing

Figure 33: CB81 Package Mechanical Drawing

CB81: 5 x 5 mm, 81-ball, 0.5 mm ball-pitch, chip-scale ball grid array

Top View

Bottom View

Mark pin 1 dot

A

B

C

D

E

F

A

B

C

D

E

F

SiliconBlue

iCE65L01F-T

CB81C

NXXXX YYWW

G

H

J

G

H

J

b

e

E1

E

Side View

Description

Symbol

Min.

Nominal

Max.

Units

Number of Ball Columns

Number of Ball Rows

Number of Signal Balls

X

Y

9

Columns

Rows

9

n

E

81

Balls

X

Y

4.90

—

5.00

0.50

—

5.10

—

Body Size

D

Ball Pitch

e

Ball Diameter

b

0.2

—

0.3

—

mm

X

Y

E1

D1

A

4.00

—

Edge Ball Center to

Center

—

Package Height

Stand Off

—

1.00

0.25

A1

0.15

—

Top Marking Format

Thermal Resistance

Line Content

Description

Logo

Junction-to-Ambient

θ

0 LFM

67

(⁰C/W)

200 LFM

57

1

Logo

iCE65P01F Part number

2

-T

CB81C

ENG

NXXXX

YYWW

Power/Speed

Package type

Engineering

Lot Number

Date Code

3

4

5

6

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45

iCE65 Ultra Low-Power mobileFPGA^™Family

QN84 Quad Flat Pack No-Lead

The QN84 is a Quad Flat Pack No-Lead package with a 0.5 mm pad pitch.

Footprint Diagram

Figure 34 shows the iCE65 footprint diagram for the QN84 package.

Also see Table 38 for a complete, detailed pinout for the QN84 package.

The signal pins are also grouped into the four I/O Banks and the SPI interface.

Figure 34: iCE65 QN84 Quad Flat Pack No-Lead Footprint (Top View)

I/O Bank 0

PIO3 A1

A36 VPP_2V5

A35 PIO1

A34 PIO1

A33 PIO1

A32 PIO1

A31 PIO1

A30 GND

A29 GBIN3/PIO1

A28 VCC

PIO3 A2

B1 PIO3

B2 PIO3

B3 PIO3

B4 PIO3

B5 PIO3

B6 VCCIO_3

B7 PIO3

B8 PIO3

B9 PIO3

PIO1 B27

PIO1 B26

PIO3 A3

PIO3 A4

VCCIO_1 B25

PIO1 B24

SILICONBLUE

iCE65L01F-T

QN84

0948

PIO3 A5

GND A6

PIO1 B23

VCC A7

GBIN2/PIO1 B22

PIO1 B21

GBIN7/PIO3 A8

GBIN6/PIO3 A9

PIO3 A10

PIO1 B20

A27 PIO1

A26 PIO1

A25 PIO1

PIO1 B19

PIO3 A11

PIO3 A12

I/O Bank 2

SPI Bank

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Pinout Table

Table 38 provides a detailed pinout table for the QN84 package. Pins are generally arranged by I/O bank, then by

ball function. The QN84 package has no JTAG pins.

Table 38: iCE65 QN84 Chip-scale BGA Pinout Table

Ball Function

GBIN0/PIO0

GBIN1/PIO0

PIO0

Ball Number

B32

Pin Type

GBIN

PIO

Bank

0

A43

A38

0

PIO0

A39

PIO

0

PIO0

A40

PIO

0

PIO0

A41

PIO

0

PIO0

A44

PIO

0

PIO0

A45

PIO

0

PIO0

A46

PIO

0

PIO0

A47

PIO

0

PIO0

A48

PIO

0

PIO0

B29

PIO

0

PIO0

B30

PIO

0

PIO0

B31

PIO

0

PIO0

B34

PIO

0

PIO0

B35

PIO

0

PIO0

B36

PIO

0

VCCIO_0

A42

VCCIO

0

GBIN2/PIO1

GBIN3/PIO1

PIO1

B22

A29

A25

A26

A27

A31

A32

A33

A34

A35

B19

B20

B21

B23

B24

B26

B27

B25

GBIN

PIO

VCCIO

1

PIO1

VCCIO_1

CDONE

CRESET_B

GBIN4/PIO2

GBIN5/PIO2

PIO2

B16

A21

A14

A16

A13

B12

A19

B10

B11

B13

CONFIG

GBIN

PIO

2

PIO2

PIO

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47

iCE65 Ultra Low-Power mobileFPGA^™Family

Ball Function

PIO2

PIO2/CBSEL0

PIO2/CBSEL1

VCCIO_2

Ball Number

B14

Pin Type

PIO

Bank

2

B15

A20

A17

PIO

GBIN6/PIO3

GBIN7/PIO3

PIO3

A9

A8

A1

A2

A3

A4

A5

A10

A11

A12

B1

B2

B3

B4

B5

B7

B8

B9

B6

GBIN

PIO

VCCIO

3

PIO3

VCCIO_3

PIOS/SPI_SO

PIOS/SPI_SI

PIOS/SPI_SCK

PIOS/SPI_SS_B

SPI_VCC

B17

A22

A23

B18

A24

SPI

GND

VCC

A6

GND

VCC

GND

VCC

A18

A30

B33

A7

A15

A28

B28

VPP_2V5

VPP_FAST

A36

A37

VPP

(2.42, 30-MAR-2012)

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Package Mechanical Drawing

Figure 35: QN84 Package Mechanical Drawing

Top View

BottomView

7.00

Underside metal is at

ground potential

Mark pin 1 dot

A36

A35

A34

A33

A32

A31

A30

A29

A28

A27

A26

A25

A1

A2

B27

B26

B25

B24

B23

B22

B21

B20

B19

B1

A3

B2

A4

4.40 0.10

B3

B4

B5

B6

B7

B8

B9

A5

A6

iCE65L01F-T

QN84C

A7

A8

A9

NXXXXXXX

YYWW

A10

A11

A12

0.40 0.10

0.65

0.50

0.22 0.05

Side View

Notes:

1. All dimensions are in millimeters

Top Marking Format

Thermal Resistance

Line Content

Description

Logo

Junction-to-Ambient *

θ

0 LFM

45

(⁰C/W)

200 LFM

44

1

Logo

iCE65L01F Part number

2

-T

Power/Speed

Package type

Engineering

QN84C

ENG

3

* With PCB thermal vias

4

5

6

NXXXXXXX Lot Number

YYWW Date Code

Lattice Semiconductor Corporation

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49

iCE65 Ultra Low-Power mobileFPGA^™Family

VQ100 Very-thin Quad Flat Package

The VQ100 package is a very-thin quad-flat package with 0.5 mm lead pitch. The iCE65L01 and iCE65L04 devices

are available in this package.

Footprint Diagram

Figure 36 shows the footprint diagram for the 100-lead very-thin quad-flat package (VQ100). See Table 40 for a

complete, detailed pinout for the 100-lead very-thin quad-flat package. The signal pins are also grouped into the

four I/O Banks and the SPI interface.

Figure 36: iCE65 VQ100 Footprint (Top View)

1

2

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PIO3/DP00A

PIO3/DP00B

PIO3/DP01A

PIO3/DP01B

GND

VPP_2V5

PIO1

I/O Bank 0

3

PIO1

Pin 1 indicator

4

PIO1

5

PIO1

R

6

VCCIO_3

GND

7

PIO3/DP02A

PIO3/DP02B

PIO3/DP03A

PIO3/DP03B

PIO1

8

PIO1

SiliconBlue

9

VCCIO_1

PIO1

10

VCC 11

PIO1

12

PIO3/DP04A

PIO1

13

14

15

16

17

18

19

20

21

22

23

24

25

GBIN7/PIO3/DP04B

VCCIO_3

GBIN2/PIO1

GBIN3/PIO1

VCC

iCE65L04F-L

VQ100

GBIN6/PIO3/DP05A

PIO3/DP05B

GND

PIO1

PIO3/DP06A

PIO3/DP06B

PIO3/DP07A

PIO3/DP07B

VCCIO_3

VCCIO_1

PIO1

GND

PIO1

GND

PIO1

PIO3/DP08A

PIO3/DP08B

PIO1

I/O Bank 2

SPI Bank

PIO1

(L01 only, see Table 39)

(L01 only, see Table 40)

Pinout Table

Table 39 provides a detailed pinout table for the VQ100 package. Pins are generally arranged by I/O bank, then by

pin function. The table also highlights the differential I/O pairs in I/O Bank 3. The VQ100 package has no JTAG

pins.

(2.42, 30-MAR-2012)

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Table 39: iCE65 VQ100 Pinout Table

Pin Function

GBIN0/PIO0

GBIN1/PIO0

PIO0

Pin Number

Type

GBIN

PIO

Bank

0

90

89

78

79

80

81

82

83

85

86

87

91

93

94

95

96

97

99

100

88

92

PIO0

0

PIO

VCCIO

VCCIO_0

0

GBIN2/PIO1

GBIN3/PIO1

PIO1

63

62

51

52

53

54

56

57

59

60

64

65

66

68

69

71

72

73

74

58

67

GBIN

PIO

1

PIO1

PIO

VCCIO

VCCIO_1

CDONE

CRESET_B

GBIN4/PIO2

43

44

CONFIG

GBIN

2

iCE65L01: 33

iCE65L04: 34

iCE65L01: 36

iCE65L04: 33

26

GBIN5/PIO2

GBIN

2

PIO2

PIO

2

27

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iCE65 Ultra Low-Power mobileFPGA^™Family

Pin Function

PIO2

Pin Number

Type

PIO

Bank

28

29

30

2

PIO2

iCE65L01: 34

iCE65L04: 36

PIO2

PIO2/CBSEL0

PIO2/CBSEL1

VCCIO_2

37

40

41

42

31

38

PIO

VCCIO

2

VCCIO_2

PIO3/DP00A

PIO3/DP00B

1

2

PIO/DPIO

3

PIO3/DP01A

PIO3/DP01B

3

4

PIO/DPIO

3

PIO3/DP02A

PIO3/DP02B

7

8

PIO/DPIO

3

PIO3/DP03A

PIO3/DP03B

9

10

PIO/DPIO

3

PIO3/DP04A

GBIN7/PIO3/DP04B

12

13

PIO/DPIO

GBIN/DPIO

3

GBIN6/PIO3/DP05A

PIO3/DP05B

15

16

GBIN/DPIO

PIO/DPIO

3

PIO3/DP06A

PIO3/DP06B

18

19

PIO/DPIO

3

PIO3/DP07A

PIO3/DP07B

20

21

PIO/DPIO

3

PIO3/DP08A

PIO3/DP08B

24

25

PIO/DPIO

3

VCCIO_3

6

14

22

VCCIO

3

PIOS/SPI_SO

PIOS/SPI_SI

PIOS/SPI_SCK

PIOS/SPI_SS_B

SPI_VCC

45

46

48

49

50

SPI

GND

5

GND

17

23

32

39

47

55

70

84

98

VCC

11

35

VCC

(2.42, 30-MAR-2012)

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Pin Function

VCC

Pin Number

Type

VCC

Bank

VCC

61

VCC

77

VCC

VPP_2V5

VPP_FAST

75

76

VPP

Package Mechanical Drawing

Figure 37: VQ100 Package Mechanical Drawing: Standard Device Marking

Top View

Mark pin 1 dot

100

76

1

75

Pin 1 indicator

iCE65L01F-T ENG

VQ100C NXXXXXXX

YYWW

25

26

51

50

E2

E1

E

Side View

c

L1

Description

Symbol

Min.

Nominal

Max.

Units

X

Y

25

Leads per Edge

Top Marking Format

25

Leads

Line Content

Description

Logo

Number of Signal Leads

n

E

100

16.0

14.0

12.0

0.50

0.20

1.20

—

1

2

3

Logo

X

Y

X

Y

X

Y

—

Maximum Size

(lead tip to lead tip)

iCE65L01F Part number

D

-T

ENG

Power/Speed

Engineering

E1

D1

E2

D2

e

—

Body Size

—

VQ100C

Package type and

—

Edge Pin Center to

Center

NXXXXXXX Lot number

—

4

5

6

YYWW

N/A

Date Code

Blank

Lead Pitch

Lead Width

—

mm

b

0.17

—

0.27

—

Total Package Height

Stand Off

A

A1

A2

L1

c

0.05

0.95

—

0.15

1.05

—

Thermal Resistance

Body Thickness

Lead Length

1.00

—

Junction-to-Ambient

θ (⁰C/W)

Lead Thickness

Coplanarity

0.09

—

0.20

—

0 LFM

38

200 LFM

32

0.08

Lattice Semiconductor Corporation

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53

iCE65 Ultra Low-Power mobileFPGA^™Family

Figure 38: VQ100 Package Mechanical Drawing: NVCM Programmed Device Marking

Top View

Mark pin 1 dot

100

76

1

75

Pin 1 indicator

iCE65L01F-T ENG

VQ100C NXXXXXXX

ZZZZZZZZ

YYWW

25

26

51

50

E2

E1

E

Side View

c

L1

Description

Symbol

Min.

Nominal

Max.

Units

X

Y

25

Top Marking Format

Leads per Edge

25

Leads

Line Content

Description

Logo

Number of Signal Leads

n

E

100

16.0

14.0

12.0

0.50

0.20

1.20

—

1

2

3

Logo

X

Y

X

Y

X

Y

—

Maximum Size

(lead tip to lead tip)

iCE65L01F Part number

D

-T

ENG

Power/Speed

Engineering

E1

D1

E2

D2

e

—

Body Size

—

VQ100C

Package type and

NXXXXXXX Lot number

ZZZZZZZZ NVCM Program. code

—

Edge Pin Center to

Center

4

5

6

—

YYWW

Date Code

Lead Pitch

Lead Width

—

mm

b

0.17

—

0.27

—

Total Package Height

Stand Off

A

Thermal Resistance

A1

A2

L1

c

0.05

0.95

—

0.15

1.05

—

Junction-to-Ambient

Body Thickness

Lead Length

1.00

—

θ (⁰C/W)

0 LFM

38

200 LFM

32

Lead Thickness

Coplanarity

0.09

—

0.20

—

0.08

(2.42, 30-MAR-2012)

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CB121 Chip-Scale Ball-Grid Array

The CB121 package is a chip-scale, fully-populated, ball-grid array with 0.5 mm ball pitch.

Footprint Diagram

Figure 39 shows the iCE65L01 chip-scale BGA footprint for the 6 x 6 mm CB121 package.

Also see Table 40 for a complete, detailed pinout for the 121-ball chip-scale BGA packages.

The signal pins are also grouped into the four I/O Banks and the SPI interface.

Figure 39: iCE65L01 CB121 Chip-Scale BGA Footprint (Top View)

I/O Bank 0

1

2

3

4

5

6

7

8

9 10 11

VPP_

VCCIO_3

PIO0 PIO0

PIO1 PIO1

PIO0 PIO0

NC PIO0

PIO0

A

B

C

D

E

F

A

B

C

D

E

F

FAST

VCCIO_0

PIO3

GND PIO0 PIO0 PIO0 VCC

PIO0 PIO0 GND PIO1

GBIN1/

PIO0

VPP_

2V5

PIO3 PIO3

PIO3

PIO0

PIO0 PIO0

PIO1

GBIN0/

PIO0

GBIN7/

PIO3

PIO1

PIO0 PIO1

PIO1 PIO1

VCCIO_1

PIO3 PIO3

PIO0 PIO0

GND GND

PIO0 PIO1 PIO1

PIO1

GND

VCC

GBIN3/ GBIN2/

PIO1 PIO1

GBIN6/

PIO3

VCC

GND

PIO0

PIO1

PIO3

VCCIO_3

PIO1 PIO1 PIO1

PIO3

PIO3 PIO3

PIO1

G

H

J

G

H

J

PIO2/

PIO2

PIO1 PIO1 PIO1

PIO1 PIO2

PIO3 PIO3

PIO2

CBSEL0

SPI_

PIO2

VCC

PIO2/

CBSEL1

PIOS/ PIOS/

SPI_SO SPI_SS_B

CDONE

PIO3 PIO3 PIO3

PIO2 PIO2

_{CRESET_B}PIOS/ PIOS/

VCCIO_2

NC GND PIO2 PIO2

VCC

GND PIO2

K

L

K

L

SPI_SI SPI_SCK

GBIN4/ GBIN5/



NC PIO2 PIO2 PIO2 PIO2 NC NC

PIO2 PIO2

1

2

3

4

5

6

7

8

9 10 11

I/O Bank 2

SPI Bank

Pinout Table

Table 40 provides a detailed pinout table for the iCE65L01 in the CB121 chip-scale BGA package. Pins are generally

arranged by I/O bank, then by ball function.

Table 40: iCE65L01 CB121 Chip-scale BGA Pinout Table

Ball Function

GBIN0/PIO0

GBIN1/PIO0

PIO0

Ball Number

Pin Type

GBIN

PIO

Bank

D6

C6

A2

A3

A4

0

PIO0

PIO

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iCE65 Ultra Low-Power mobileFPGA^™Family

Ball Function

PIO0

Ball Number

Pin Type

PIO

Bank

A5

A6

A8

A10

B3

B4

B5

B8

B9

C5

C7

C8

C9

D5

D7

E5

E6

E7

F7

0

PIO0

PIO

PIO0

VCCIO_0

PIO

VCCIO

B7

GBIN2/PIO1

GBIN3/PIO1

PIO1

F9

F8

A11

B11

C11

D8

GBIN

PIO

VCCIO

1

PIO1

D9

D10

D11

E8

E9

E11

F10

G7

G8

G9

G10

H7

H8

H9

H10

E10

PIO1

VCCIO_1

CDONE

CRESET_B

GBIN4/PIO2

GBIN5/PIO2

PIO2

J7

K7

L8

CONFIG

GBIN

PIO

2

L9

H4

H5

H11

J4

PIO2

J5

(2.42, 30-MAR-2012)

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Lattice Semiconductor Corporation

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Ball Function

PIO2

Ball Number

Pin Type

PIO

Bank

J11

K3

K4

K11

L2

L3

L4

L5

L10

L11

H6

J6

2

PIO2

PIO

VCCIO

PIO2

PIO2/CBSEL0

PIO2/CBSEL1

VCCIO_2

K5

PIO3

C1

B1

D1

E2

C2

D2

C3

C4

E4

D4

F3

G3

G4

F4

D3

E3

F2

G1

H1

J1

3

PIO

GBIN

PIO

VCCIO

GBIN6/PIO3

GBIN7/PIO3

PIO3

H2

H3

J3

J2

A1

G2

VCCIO_3

PIOS/SPI_SO

PIOS/SPI_SI

PIOS/SPI_SCK

PIOS/SPI_SS_B

SPI_VCC

J8

K8

K9

J9

SPI

J10

GND

B2

B10

E1

F5

F6

G5

G6

G11

GND

Lattice Semiconductor Corporation

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iCE65 Ultra Low-Power mobileFPGA^™Family

Ball Function

GND

Ball Number

Pin Type

GND

Bank

GND

K2

K10

GND

VCC

B6

F1

F11

K6

VCC

VPP_2V5

VPP_FAST

C10

A9

VPP

(2.42, 30-MAR-2012)

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Package Mechanical Drawing

Figure 40: CB121 Package Mechanical Drawing

CB121: 6 x 6 mm, 121-ball, 0.5 mm ball-pitch, fully-populated,

chip-scale ball grid array

Top View

Bottom View

Mark pin 1 dot

A

B

C

D

E

F

G

H

J

A

B

C

D

E

F

G

H

J

SiliconBlue

iCE65L01F-T

CB121I

NXXXX YYWW

K

L

K

L

b

e

E1

E

Side View

Description

Symbol

Min.

Nominal

Max.

Units

Number of Ball Columns

Number of Ball Rows

Number of Signal Balls

X

Y

11

Columns

Rows

n

E

121

6.00

0.50

—

Balls

X

Y

5.90

—

6.10

—

Body Size

D

Ball Pitch

e

Ball Diameter

b

0.2

—

0.3

—

mm

X

Y

E1

D1

A

5.00

—

Edge Ball Center to

Center

—

Package Height

Stand Off

—

1.00

0.20

A1

0.12

—

Top Marking Format

Thermal Resistance

Line Content

Description

Logo

Junction-to-Ambient

θ_JA

(ꢀC/W)

200 LFM

55

1

Logo

0 LFM

64

iCE65L01F Part number

2

-T

CB121I

ENG

NXXXX

YYWW

Power/Speed

Package type

Engineering

LotNumber

Date Code

3

4

5

6

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

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59

iCE65 Ultra Low-Power mobileFPGA^™Family

CB132 Chip-Scale Ball-Grid Array

The CB132 package is a partially-populated ball grid array with 0.5 mm ball pitch. The empty ball rings simplify

PCB layout. The iCE65L01, iCE65L04 and iCE65L08 devices are available in this package.

Footprint Diagram

Figure 41, Figure 42 and

Figure 43 show the iCE65 footprint diagrams for the CB132 package in iCE65L01, iCE65L04 and iCE65L08 devices.

See Figure 48 for the “universal” chip-scale BGA footprint for the CB132 and CB284 packages. The 8 x 8 mm CB132

package fits within the same ball pattern as the 12 x 12 mm CB284 package.

Figure 31 shows the conventions used in the diagram.

Also see Table 41 for a complete, detailed pinout for the 132-ball BGA package.

The signal pins are also grouped into the four I/O Banks and the SPI interface.

Figure 41: iCE65L01 CB132 Chip-Scale BGA Footprint (Top View)

I/O Bank 0

1

2

3

4

5

6

7

8

9 10 11 12 13 14

VPP_ VPP_

GND PIO0 NC PIO0

FAST 2V5

GBIN1/ GBIN0/

VCCIO_0

PIO0 PIO0 NC PIO0 PIO0

A

B

C

D

E

PIO0 PIO0

PIO3

PIO1

B

C

D

E

F

PIO3

GND

PIO3

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0

PIO1

PIO3 PIO3

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1

PIO1 PIO1

VCCIO_3

PIO3

^GBIN3/F

VCCIO_0

VCCIO_1

PIO3 PIO3

GND VCC

PIO1 PIO1

PIO1

^GBIN2/G

GBIN7/

PIO3

VCC GND GND GND

GND GND GND VCC

G

H

J

PIO1

GBIN6/

PIO3

VCCIO_1

H

VCCIO_3

VCCIO_2

PIO3

VCCIO_3

PIO3

VCC

VCC GND

GND

J

PIO3 PIO3

PIO1

K

L

K

SPI_

TCK

VCC

PIO2/ _{CRESET_B}

CBSEL0

GND PIO2 PIO2 PIO2 PIO2 PIO2

PIO1

L

PIOS/

TDI

VCCIO_2

CDONE

TRST_B

PIO3

PIO2 PIO2

PIO2 PIO2 PIO2 PIO2

M

N

P

M

SPI_SO

PIO3

TDO

N

SPI Bank

GBIN5/ GBIN4/

PIO2 PIO2

PIO2/

PIO2

PIOS/ PIOS/ PIOS/

PIO3

PIO2 PIO2 PIO2 PIO2 GND

TMS

P

SPI_SI SPI_SCK SPI_SS_B

CBSEL1

1

2

3

4

5

6

7

8

9 10 11 12 13 14

I/O Bank 2

(2.42, 30-MAR-2012)

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Lattice Semiconductor Corporation

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Figure 42: iCE65L04 CB132 Chip-Scale BGA Footprint (Top View)

I/O Bank 0

1

2

3

4

5

6

7

8

9 10 11 12 13 14

VPP_ VPP_

GND PIO0 PIO0 PIO0

FAST 2V5

GBIN0/ GBIN1/

VCCIO_0

PIO0 PIO0 PIO0 PIO0 PIO0

A

B

C

D

E

PIO0 PIO0

PIO3/

PIO1

B _DP00A

PIO3/

DP01A

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0

PIO1

C _DP00B

PIO3/

PIO3/ PIO3/

DP01B DP02A

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1

PIO1 PIO1

D _DP03A

PIO3/

VCCIO_3

E _DP03B

DP02B

PIO3/ PIO3/

DP04B DP04A

VCCIO_0

VCCIO_1

GND

GND VCC

PIO1 PIO1

F

^GBIN3/F

PIO1

GBIN7/

PIO3

PIO3/ PIO3/

DP05A DP05B

VCC GND GND GND

GND GND GND VCC

G

^GBIN2/G

PIO1

GBIN6/

PIO3

PIO3/ PIO3/

DP06A DP06B

VCCIO_1

H

PIO3/

DP07B

PIO3/

VCC

VCCIO_3

VCCIO_2

VCC GND

GND

J

DP07A

PIO3/ PIO3/

DP08A DP08B

VCCIO_3

PIO1

K

PIO3/

SPI_

TCK

VCC

PIO2/ _{CRESET_B}

CBSEL0

GND PIO2 PIO2 PIO2 PIO2 PIO2

PIO1

L _DP09A

L

PIO3/

DP09B

PIOS/

TDI

VCCIO_2

CDONE

TRST_B

PIO2 PIO2

PIO2 PIO2 PIO2 PIO2

M

SPI_SO

PIO3/

TDO

N _DP10A

N

SPI Bank

GBIN5/ GBIN4/

PIO2 PIO2

PIO3/

PIO2/

PIO2

PIOS/ PIOS/ PIOS/

PIO2 PIO2 PIO2 PIO2 GND

TMS

P _DP10B

P

SPI_SI SPI_SCK SPI_SS_B

CBSEL1

1

2

3

4

5

6

7

8

9 10 11 12 13 14

I/O Bank 2

Lattice Semiconductor Corporation

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iCE65 Ultra Low-Power mobileFPGA^™Family

Figure 43: iCE65L08 CB132 Chip-Scale BGA Footprint (Top View)

I/O Bank 0

1

2

3

4

5

6

7

8

9 10 11 12 13 14

VPP_ VPP_

GND PIO0 PIO0 PIO0

FAST 2V5

GBIN0/ GBIN1/

VCCIO_0

PIO0 PIO0 PIO0 PIO0 PIO0

A

B

C

D

E

PIO0 PIO0

PIO3/

PIO1

B _DP00A

PIO3/

DP01A

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0

PIO1

C _DP00B

PIO3/

PIO3/ PIO3/

DP01B DP02A

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1

PIO1 PIO1

D _DP03A

PIO3/

VCCIO_3

E _DP03B

DP02B

PIO3/ PIO3/

DP04B DP04A

VCCIO_0

VCCIO_1

GND

GND VCC

PIO1 PIO1

F

^GBIN3/F

PIO1

GBIN7/

DP05B

PIO3/ PIO3/

DP05A DP11B

VCC GND GND GND

GND GND GND VCC

G

^GBIN2/G

PIO1

GBIN6/

DP06A

PIO3/ PIO3/

DP06B DP11A

VCCIO_1

H

PIO3/

DP07B

PIO3/

VCC

VCCIO_3

VCCIO_2

VCC GND

GND

J

DP07A

PIO3/ PIO3/

DP08A DP08B

VCCIO_3

PIO1

K

PIO3/

SPI_

TCK

VCC

PIO2/ _{CRESET_B}

CBSEL0

GND PIO2 PIO2 PIO2 PIO2 PIO2

PIO1

L _DP09A

L

PIO3/

DP09B

PIOS/

TDI

VCCIO_2

CDONE

TRST_B

PIO2 PIO2

PIO2 PIO2 PIO2 PIO2

M

SPI_SO

PIO3/

TDO

N _DP10A

N

SPI Bank

GBIN5/ GBIN4/

PIO2 PIO2

PIO3/

PIO2/

PIO2

PIOS/ PIOS/ PIOS/

PIO2 PIO2 PIO2 PIO2 GND

TMS

P _DP10B

P

SPI_SI SPI_SCK SPI_SS_B

CBSEL1

1

2

3

4

5

6

7

8

9 10 11 12 13 14

I/O Bank 2

(2.42, 30-MAR-2012)

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Pinout Table

Table 41 provides a detailed pinout table for the CB132 package. Pins are generally arranged by I/O bank, then by

ball function. The table also highlights the differential I/O pairs in I/O Bank 3.

Table 41: iCE65 CB132 Chip-scale BGA Pinout Table

Ball Function

Ball Number

iCE65L01: A7

iCE65L04/L08: A6

iCE65L01: A6

iCE65L04/08: A7

A1

Pin Type

GBIN

Bank

0

GBIN0/PIO0

GBIN

0

GBIN1/PIO0

PIO0

PIO

0

A2

A3

iCE65L01: (NC)

iCE65L04/L08: PIO0

PIO0

iCE65L01: (NC)

iCE65L04: PIO0

A4

A5

A10

A11

PIO

0

PIO0

iCE65L01: (NC)

iCE65L04/L08: PIO0

PIO0

iCE65L01: (NC)

iCE65L04: PIO0

A12

C10

C11

C12

C4

C5

C6

C7

C8

PIO

0

PIO0

C9

D5

D6

D7

D8

D9

D10

D11

A8

PIO

VCCIO

VCCIO_0

F6

GBIN2/PIO1

GBIN3/PIO1

PIO1

G14

F14

B14

C14

D12

D14

E11

E12

E14

F11

F12

G11

G12

H11

GBIN

PIO

1

PIO1

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63

iCE65 Ultra Low-Power mobileFPGA^™Family

Ball Function

PIO1

Ball Number

H12

J11

Pin Type

PIO

Bank

1

PIO1

PIO

PIO1

J12

PIO

1

PIO1

K11

PIO

1

PIO1

K12

PIO

1

PIO1

K14

PIO

1

PIO1

L14

PIO

1

TCK

TDI

TDO

TMS

L12

JTAG

VCCIO

1

M12

N14

P14

M14

F9

TRST_B

VCCIO_1

H14

CDONE

CRESET_B

GBIN4/PIO2

GBIN5/PIO2

PIO2

M10

L10

P8

P7

L4

L5

L6

L7

L8

M3

M4

M6

M7

M8

M9

P2

P3

P4

P5

P9

CONFIG

GBIN

PIO

2

PIO2

PIO2/CBSEL0

PIO2/CBSEL1

VCCIO_2

L9

P10

J9

M5

PIO3/DP00A

PIO3/DP00B

B1

C1

DPIO

3

PIO3/DP01A

PIO3/DP01B

C3

D3

DPIO

3

PIO3/DP02A

PIO3/DP02B

D4

E4

DPIO

3

PIO3/DP03A

PIO3/DP03B

D1

E1

DPIO

3

PIO3/DP04A

PIO3/DP04B

F4

F3

DPIO

3

L01/L04: GBIN6/PIO3

L08: GBIN6/DP06A

H1

GBIN

3

(2.42, 30-MAR-2012)

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Ball Function

L01/L04: GBIN7/PIO3

L08: GBIN7/DP05B

Ball Number

G1

Pin Type

GBIN

Bank

3

L01/L04: PIO3/DP05A

L08: PIO3/DP05A

L01/L04: PIO3/DP05B

L08: PIO3/DP11B

G3

G4

DPIO

3

L01/L04: PIO3/DP06A

L08: PIO3/DP06B

L01/L04: PIO3/DP06B

L08: PIO3/DP11A

H3

H4

DPIO

3

PIO3/DP07A

PIO3/DP07B

J3

J1

DPIO

3

PIO3/DP08A

PIO3/DP08B

K3

K4

DPIO

3

PIO3/DP09A

PIO3/DP09B

L1

M1

DPIO

3

PIO3/DP10A

PIO3/DP10B

N1

P1

DPIO

3

VCCIO_3

E3

J6

K1

VCCIO

3

PIOS/SPI_SO

PIOS/SPI_SI

PIOS/SPI_SCK

PIOS/SPI_SS_B

SPI_VCC

M11

P11

P12

P13

L11

SPI

GND

VCC

A9

F1

F7

G7

G8

G9

H6

H7

H8

J8

GND

VCC

GND

VCC

J14

L3

P6

F8

G6

H9

J4

J7

VPP_2V5

VPP_FAST

A14

A13

VPP

Lattice Semiconductor Corporation

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iCE65 Ultra Low-Power mobileFPGA^™Family

Package Mechanical Drawing

Figure 44: CB132 Package Mechanical Drawing

CB132: 8 x 8 mm, 132-ball, 0.5 mm ball-pitch, chip-scale ball grid array

Top View

Bottom View

Mark pin 1 dot

A

B

C

D

E

F

A

B

C

D

E

F

iCE65L04F-T

CB132C ENG

NXXXXXXX

YYWW

G

H

J

G

H

J

K

L

K

L

M

N

P

M

N

P

b

e

E1

Side View

E

Top Marking Format

Description

Symbol

Min.

Nominal

Max.

Units

Line Content

Description

Logo

Number of Ball Columns

Number of Ball Rows

Number of Signal Balls

X

Y

14

Columns

Rows

1

Logo

iCE65L04F Part number

n

E

132

8.00

0.50

—

Balls

2

-T

Power/Speed

Package type

Engineering

X

Y

7.90

—

8.10

—

CB132C

ENG

Body Size

3

D

Ball Pitch

e

4

5

6

NXXXXXXX Lot Number

YYWW Date Code

Ball Diameter

b

0.27

—

0.37

—

mm

X

Y

E1

D1

A

6.50

—

Edge Ball Center to

Center

—

Package Height

Stand Off

—

1.00

0.26

Thermal Resistance

A1

0.16

—

Junction-to-Ambient

θ

0 LFM

42

(⁰C/W)

200 LFM

34

(2.42, 30-MAR-2012)

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66

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CB196 Chip-Scale Ball-Grid Array

The CB196 package is a chip-scale, fully-populated, ball-grid array with 0.5 mm ball pitch.

Footprint Diagram

Figure 45 shows the iCE65L04 chip-scale BGA footprint for the 8 x 8 mm CB196 package. The footprint for the

iCE65L08 is different than the iCE64L04 footprint, as shown in Figure 46. The pinout differences are highlighted by

warning diamonds () in the footprint diagrams and summarized in Table 43.

Although both the iCE65L04 and iCE65L08 are both available in the CB196 package and almost

completely pin compatible, there are differences as shown in Table 43.

!

Figure 31 shows the conventions used in the diagram. Also see Table 42 for a complete, detailed pinout for the 196-

ball chip-scale BGA packages. The signal pins are also grouped into the four I/O Banks and the SPI interface.

Figure 45: iCE65L04 CB196 Chip-Scale BGA Footprint (Top View)

I/O Bank 0

1

2

3

4

5

6

7

GBIN0/

PIO0

8

9 10 11 12 13 14

VPP_ VPP_

GND PIO0 PIO0 PIO0

FAST 2V5

VCCIO_0

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0

A

B

C

D

E

F

A

B

C

D

E

F

PIO3/

DP00B

PIO0 PIO0 PIO0 PIO0 PIO0 VCC PIO0 PIO0 PIO0 PIO0 GND PIO1 PIO1

PIO3/

DP00A

PIO1/

DP01B

GND

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1

PIO3/ PIO3/ PIO1/ PIO3/

DP02A DP02B DP01A DP04A

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 PIO1

GBIN1/

PIO0

PIO3/ PIO3/

DP03A DP03B

PIO3/ PIO3/

DP04B DP06B

VCCIO_3

PIO0

PIO0 PIO0 PIO1 PIO1 PIO1 PIO1 PIO1



GBIN2/

PIO1

PIO3/ PIO3/ PIO3/

DP05A DP05B DP06A

VCCIO_0

VCCIO_1

GND VCC

PIO1 PIO1 PIO1 PIO1



GBIN7/

PIO3/

GBIN3/

PIO1

PIO3/ PIO3/ PIO3/ PIO3/

VCC GND GND GND PIO1 PIO1

PIO1 PIO1

G

H

J

G

H

J

DP07A DP09A DP09B DP13B

DP07B



GBIN6/

PIO3/

DP08A

PIO3/ PIO3/ PIO3/ PIO3/

DP08B DP11B DP11A DP13A

VCCIO_1

GND GND GND VCC PIO1 PIO1 PIO1 PIO1



PIO3/ PIO3/ PIO3/

DP10A DP10B DP12B

VCCIO_3

VCCIO_2

VCC GND

PIO1 PIO1 PIO1 PIO1 GND

PIO3/ PIO3/ PIO3/

VCCIO_3

PIO2 PIO2 PIO2 PIO2 PIO2 GND PIO1 PIO1 VCC PIO1

K

L

K

L

DP12A DP16A DP16B



GBIN4/

PIO3/ PIO3/

DP14A DP14B

SPI_

VCC

PIO2/ _{CRESET_B}

GND PIO2 PIO2 PIO2

PIO2

TCK PIO1 PIO1

PIO2

CBSEL0



PIO3/ PIO3/

PIOS/

VCCIO_2

CDONE

TRST_B

PIO2 PIO2

PIO2 PIO2 PIO2 PIO2

TDI PIO1

M _{DP15A DP15B}

M

N

P

SPI_SO



PIO3/ PIO3/

DP17A DP17B

VCCIO_2

PIO2 PIO2 PIO2 PIO2 VCC PIO2 PIO2

PIO2 PIO2 PIO2 TDO

N



GBIN5/

PIO2/ PIOS/ PIOS/ PIOS/

PIO2 PIO2 PIO2 PIO2

GND PIO2 PIO2 PIO2

TMS

CBSEL1 SPI_SI SPI_SCKSPI_SS_B

P

PIO2

1

2

3

4

5^

6

7

8

9 10 11 12 13 14

SPI Bank

I/O Bank 2

Lattice Semiconductor Corporation

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67

iCE65 Ultra Low-Power mobileFPGA^™Family

Figure 46: iCE65L08 CB196 Chip-Scale BGA Footprint (Top View)

I/O Bank 0

1

2

3

4

5

6

7

GBIN0/

PIO0

8

9 10 11 12 13 14

VPP_ VPP_

GND PIO0 PIO0 PIO0

FAST 2V5

VCCIO_0

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0

A

B

C

D

E

F

A

B

C

D

E

F

PIO3/

DP00B

PIO0 PIO0 PIO0 PIO0 PIO0 VCC PIO0 PIO0 PIO0 PIO0 GND PIO1 PIO1

PIO3/

DP00A

PIO1/

DP01B

GND

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1

PIO3/ PIO3/ PIO1/ PIO3/

DP02A DP02B DP01A DP04A

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1 PIO1 PIO1 PIO1

GBIN1/

PIO0

PIO3/ PIO3/

DP03B DP03A

PIO3/ PIO3/

DP04B DP06B

VCCIO_3

PIO0

PIO0 PIO0 PIO1 PIO1 PIO1 PIO1 PIO1



GBIN2/

PIO1

PIO3/ PIO3/ PIO3/

DP05B DP05A DP06A

VCCIO_0

VCCIO_1

GND VCC

PIO1 PIO1 PIO1 PIO1



GBIN3/

PIO1

PIO3/ PIO3/ PIO3/ PIO3/ PIO3/

DP11A DP11B DP09A DP09B DP13B

VCC GND GND GND PIO1 PIO1

PIO1 PIO1

G

H

J

G

H

J



GBIN6/

PIO3/

DP08A

GBIN7/

PIO3/

DP07B

PIO3/

DP08B

PIO3/ PIO3/

VCCIO_1

GND GND GND VCC PIO1 PIO1 PIO1 PIO1

_DP07A DP13A



PIO3/ PIO3/ PIO3/

DP10A DP10B DP12B

VCCIO_3

VCCIO_2

VCC GND

PIO1 PIO1 PIO1 PIO1 GND

PIO3/ PIO3/ PIO3/

VCCIO_3

PIO2 PIO2 PIO2 PIO2 PIO2 GND PIO1 PIO1 VCC PIO1

K

L

K

L

DP12A DP16B DP16A



PIO3/ PIO3/

DP14A DP14B

SPI_

VCC

PIO2/ _{CRESET_B}

CBSEL0

GND PIO2 PIO2 PIO2 PIO2 PIO2

TCK PIO1 PIO1



GBIN5/

PIO3/ PIO3/

PIOS/

VCCIO_2

CDONE

TRST_B

PIO2 PIO2

PIO2

PIO2 PIO2

TDI PIO1

M _{DP15A DP15B}

M

N

P

PIO2

SPI_SO



GBIN4/

PIO3/ PIO3/

DP17A DP17B

VCCIO_2

PIO2 PIO2 PIO2 PIO2 VCC

PIO2

PIO2 PIO2 PIO2 TDO

N

PIO2



PIO2/ PIOS/ PIOS/ PIOS/

CBSEL1 SPI_SI SPI_SCKSPI_SS_B

PIO2 PIO2 PIO2 PIO2 PIO2 GND PIO2 PIO2 PIO2

TMS

P

1

2

3

4

5 ^

6

7

8

9 10 11 12 13 14

SPI Bank

I/O Bank 2

Pinout Table

Table 42 provides a detailed pinout table for the iCE65L04 in the CB196 chip-scale BGA package. Pins are generally

arranged by I/O bank, then by ball function. The pinout for the iCE65L08 is different than the iCE64L04 pinout.

Although both the iCE65L04 and iCE65L08 are both available in the CB196 package and almost

completely pin compatible, there are differences as shown in Table 43.

!

Table 42: iCE65L04 CB196 Chip-scale BGA Pinout Table

Ball Function

GBIN0/PIO0

GBIN1/PIO0

PIO0

Ball Number

Pin Type

GBIN

PIO

Bank

A7

E7

A1

A2

A3

A4

0

PIO0

PIO

(2.42, 30-MAR-2012)

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Ball Function

PIO0

VCCIO_0

Ball Number

A5

Pin Type

PIO

VCCIO

Bank

0

A6

A10

A11

A12

B2

B3

B4

B5

B6

B8

B9

B10

B11

C4

C5

C6

C7

C8

C9

C10

C11

D5

D6

D7

D8

D9

D10

E6

E8

E9

A8

F6

GBIN2/PIO1

GBIN3/PIO1

PIO1

F10

G12

B13

B14

C12

C13

C14

D11

D12

D13

D14

E10

E11

E12

E13

E14

F11

F12

F13

GBIN

PIO

1

PIO1

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iCE65 Ultra Low-Power mobileFPGA^™Family

Ball Function

PIO1

TCK

Ball Number

F14

Pin Type

PIO

Bank

1

G10

G11

G13

G14

H10

H11

H12

H13

J10

J11

J12

J13

K11

K12

K14

L13

L14

M13

L12

PIO

JTAG

VCCIO

TDI

TDO

TMS

M12

N14

P14

M14

F9

TRST_B

VCCIO_1

1

H14

CDONE

CRESET_B

GBIN4/PIO2 ()

M10

L10

iCE65L04: L7

CONFIG

GBIN

2

iCE65L08: N8

GBIN5/PIO2 ()

iCE65L04: P5

GBIN

2

iCE65L08: M7

PIO2

PIO2 ()

K5

K6

K7

K8

K9

L4

L5

L6

L8

M3

M4

M6

PIO

2

iCE65L04: M7

iCE65L08: P5

PIO2

M8

M9

N3

N4

N5

N6

PIO

2

(2.42, 30-MAR-2012)

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Ball Function

PIO2 ()

Ball Number

iCE65L04: N8

Pin Type

PIO

Bank

2

iCE65L08: L7

PIO2

N9

N11

N12

N13

P1

P2

P3

P4

P7

P8

P9

L9

P10

J9

PIO

VCCIO

2

PIO2

PIO2/CBSEL0

PIO2/CBSEL1

VCCIO_2

M5

N10

PIO3/DP00A

PIO3/DP00B

C1

B1

DPIO

3

PIO3/DP01A

PIO3/DP01B

D3

C3

DPIO

3

PIO3/DP02A

PIO3/DP02B

D1

D2

DPIO

3

PIO3/DP03A ()

iCE65L04: E1

iCE65L08: E2

iCE65L04: E2

iCE65L04: E1

DPIO

3

PIO3/DP03B ()

DPIO

3

PIO3/DP04A

PIO3/DP04B

D4

E4

DPIO

3

PIO3/DP05A ()

iCE65L04: F3

iCE65L08: F4

iCE65L04: F4

iCE65L08: F3

DPIO

3

PIO3/DP05B ()

DPIO

3

PIO3/DP06A

PIO3/DP06B

F5

E5

DPIO

3

PIO3/DP07A ()

iCE65L04: G2

iCE65L08: H4

iCE65L04: G1

iCE65L08: H3

DPIO

3

GBIN7/PIO3/DP07B ()

GBIN

3

GBIN6/PIO3/DP08A

PIO3/DP08B

H1

H2

GBIN

DPIO

3

PIO3/DP09A

PIO3/DP09B

G3

G4

DPIO

3

PIO3/DP10A

PIO3/DP10B

J1

J2

DPIO

3

iCE65L04: H4

iCE65L08: G1

iCE65L04: H3

iCE65L08: G2

PIO3/DP11A ()

DPIO

3

PIO3/DP11B ()

DPIO

3

PIO3/DP12A

PIO3/DP12B

K2

J3

DPIO

3

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

www.latticesemi.com

71

iCE65 Ultra Low-Power mobileFPGA^™Family

Ball Function

Ball Number

Pin Type

Bank

PIO3/DP13A

PIO3/DP13B

H5

G5

DPIO

3

PIO3/DP14A

PIO3/DP14B

L1

L2

DPIO

3

PIO3/DP15A

PIO3/DP15B

M1

M2

DPIO

3

PIO3/DP16A ()

iCE65L04: K3

iCE65L08: K4

iCE65L08: K3

DPIO

3

PIO3/DP16B ()

DPIO

3

PIO3/DP17A

PIO3/DP17B

N1

N2

DPIO

3

VCCIO_3

E3

J6

K1

VCCIO

3

PIOS/SPI_SO

PIOS/SPI_SI

PIOS/SPI_SCK

PIOS/SPI_SS_B

SPI_VCC

M11

P11

P12

P13

L11

SPI

GND

A9

B12

C2

F1

GND

F7

G7

G8

G9

H6

H7

H8

J5

J8

J14

K10

L3

P6

VCC

B7

F2

F8

G6

H9

J4

J7

K13

N7

VCC

VPP_2V5

VPP_FAST

A14

A13

VPP

(2.42, 30-MAR-2012)

72

Lattice Semiconductor Corporation

www.latticesemi.com

Pinout Differences between iCE65L04 and iCE65L08 in CB196 Package

Table 43 lists the package balls that are different between the pinouts for iCE65L04 and the iCE65L08 in the CB196

package. The table also describes the functional differences between these pins, which is critical when designing a

CB196 footprint that supports both the iCE65L04 and the iCE65L08 devices. In some cases, only the differential

inputs are swapped; single-ended I/Os are not affected. A swapped differential pair can be inverted internally for

functional equivalence. In other cases, a global buffer input is swapped with another PIO pin in the same bank.

Table 43: Pinout Differences between iCE65L04 and iCE65L08 in CB196 Package

Ball Number

iCE65L04

PIO3/DP03A

PIO3/DP03B

PIO3/DP05A

PIO3/DP05B

GBIN7/PIO3/DP07B

PIO3/DP07A

PIO3/DP11B

PIO3/DP11A

PIO3/DP16A

PIO3/DP16B

GBIN4/PIO2

PIO2

iCE65L08

PIO3/DP03B

PIO3/DP03A

PIO3/DP05B

PIO3/DP05A

PIO3/DP11A

PIO3/DP11B

GBIN7/PIO3/DP07B

PIO3/DP07A

PIO3/DP16B

PIO3/DP16A

PIO2

Functional Difference

Differential inputs swapped, single-ended

I/Os not affected

Differential inputs swapped, single-ended

I/Os not affected

Global buffer input GBIN7 and its

associated differential input is swapped

with another differential pair in I/O

Bank 3

E1

E2

F3

F4

G1

G2

H3

H4

K3

K4

L7

N8

M7

P5

Differential inputs swapped, single-ended

I/Os not affected

Global buffer input GBIN4 swapped with

another PIO pin in I/O Bank 2

Global buffer input GBIN5 swapped with

another PIO pin in I/O Bank 2

GBIN4/PIO2

GBIN5/PIO2

PIO2

GBIN5/PIO2

Lattice Semiconductor Corporation

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73

iCE65 Ultra Low-Power mobileFPGA^™Family

Package Mechanical Drawing

Figure 47:

(a) iCE65L04 CB196 Package Mechanical Drawing

CB196: 8 x8 mm, 196-ball, 0.5 mm ball-pitch, fully-populated, chip-scale

ball grid array

Top View

Bottom View

Mark pin 1 dot

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

iCE65L04F-T

CB196I

G

H

J

K

L

K

L

NXXXXXXX

YYWW

M

N

P

M

N

P

b

e

E1

Side View

E

Top Marking Format

Line Content

Description

Logo

Description

Symbol

Min.

Nominal

Max.

Units

1

Logo

Number of Ball Columns

Number of Ball Rows

Number of Signal Balls

X

Y

14

Columns

Rows

iCE65L04F Part number

2

-T

Power/Speed

Package type

Engineering

n

E

196

8.00

0.50

—

Balls

CB196I

ENG

X

Y

7.90

—

8.10

—

3

Body Size

D

4

5

6

NXXXXXXX Lot Number

YYWW Date Code

Ball Pitch

e

Ball Diameter

b

0.27

—

0.37

—

mm

X

Y

E1

D1

A

6.50

—

Edge Ball Center to

Center

—

Thermal Resistance

Package Height

Stand Off

—

1.00

0.26

Junction-to-Ambient

A1

0.16

—

θ

0 LFM

42

(⁰C/W)

200 LFM

34

(2.42, 30-MAR-2012)

Lattice Semiconductor Corporation

74

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(b) iCE65L08 CB196 Package Mechanical Drawing

CB196: 8 x8 mm, 196-ball, 0.5 mm ball-pitch, fully-populated, chip-scale

ball grid array

Top View

Bottom View

Mark pin 1 dot

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

iCE65L08F-T

CB196C ENG

NXXXXXXX

YYWW

G

H

J

K

L

K

L

M

N

P

M

N

P

b

e

E1

Side View

E

Top Marking Format

Line Content

Description

Logo

Description

Symbol

Min.

Nominal

Max.

Units

1

Logo

Number of Ball Columns

Number of Ball Rows

Number of Signal Balls

X

Y

14

Columns

Rows

iCE65L08F Part number

2

-T

Power/Speed

Package type

Engineering

n

E

196

8.00

0.50

—

Balls

CB196C

ENG

X

Y

7.90

—

8.10

—

3

Body Size

D

4

5

6

NXXXXXXX Lot Number

YYWW Date Code

Ball Pitch

e

Ball Diameter

b

0.27

—

0.37

—

mm

X

Y

E1

D1

A

6.50

—

Edge Ball Center to

Center

—

Thermal Resistance

Package Height

Stand Off

—

1.00

0.26

Junction-to-Ambient

A1

0.16

—

θ

0 LFM

42

(⁰C/W)

200 LFM

34

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

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75

iCE65 Ultra Low-Power mobileFPGA^™Family

CB284 Chip-Scale Ball-Grid Array

The CB284 package, partially-populated 0.5 mm pitch, ball grid array simplifies PCB layout with empty ball rings.

Footprint Diagram

Figure 48 shows the CB284 chip-scale BGA footprint. The 8 x 8 mm CB132 package fits within the same ball

pattern as the 12 x 12 mm CB284 package. In other words, the central 8 x 8 section of the CB284 footprint matches

the CB132 footprint.

Figure 31 shows the conventions used in the diagram.

Also see Table 44 for a complete, detailed pinout for the 132-ball and 284-ball chip-scale BGA packages.

The signal pins are also grouped into the four I/O Banks and the SPI interface.

Figure 48: iCE65 CB284 Chip-Scale BGA Footprint (Top View)

I/O Bank 0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

VCCIO_0

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0

PIO1

VCCIO_1

A

B

C

D

E

PIO3/

B _DP07A

PIO3/

PIO0 PIO0 PIO0 PIO0 PIO0 VCC PIO0 PIO0 PIO0 GND PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1

C _DP07B

PIO3/

VCC

PIO1

VCCIO_1

D _DP08A

GBIN0/ GBIN1/

PIO0 PIO0

PIO3/

DP05A

VPP_ VPP_

GND PIO0 PIO0 PIO0

FAST 2V5

VCCIO_0

PIO0 PIO0 PIO0 PIO0 PIO0

E _DP08B

PIO3/

DP05B

PIO3/

DP00A

VCCIO_3

PIO1

F

PIO3/

DP06A

PIO3/

DP00B

PIO3/

DP01A

GND

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0

G

H

J

PIO3/

DP06B

PIO3/

DP03A

PIO3/ PIO3/

DP01B DP02A

PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO1

PIO1 PIO1

H _DP09A

PIO3/

DP09B

PIO3/

DP03B

PIO3/

VCCIO_3

GND

PIO1

J

DP02B

GBIN3/

PIO1

PIO3/

PIO3/ PIO3/

DP04B DP04A

VCCIO_3

VCCIO_0

VCCIO_1

GND

GND VCC

PIO1 PIO1

PIO1

VCC

PIO1

GND

PIO1

K _DP10A

K

L

GBIN7/

PIO3/

DP11B

GBIN6/

PIO3/

GBIN2/

PIO1

PIO3/

DP11A

PIO3/ PIO3/

DP19A DP19B

VCC GND GND GND

GND GND GND VCC

L _DP10B

PIO3/

DP15A

PIO3/ PIO3/

DP20A DP20B

VCCIO_1

VREF

M

N

P

DP15A

PIO3/

DP16A

PIO3/

DP21B

PIO3/

VCC

VCCIO_3

VCCIO_2

GND

VCC GND

GND

PIO1

TRST_B

N

DP21A

PIO3/

DP16B

PIO3/ PIO3/

DP22A DP22B

VCCIO_3

P

PIO3/

DP23A

SPI_

TCK

VCC

PIO2/ _{CRESET_B}

CBSEL0

VCCIO_3

GND

GND PIO2 PIO2 PIO2 PIO2 PIO2

R

T

PIO3/

DP23B

PIOS/

TDI

VCCIO_2

CDONE

GND

PIO2 PIO2

PIO2 PIO2 PIO2 PIO2

T _DP12A

SPI_SO

PIO3/

DP17A

PIO3/

DP24A

TDO

U _DP12B

U

V

SPI Bank

PIO2/ PIOS/ PIOS/ PIOS/

GBIN5/ GBIN4/

PIO2 PIO2

PIO3/

DP17B

PIO3/

DP24B

GND

PIO2 PIO2 PIO2 PIO2 GND

PIO2

TMS

CBSEL1 SPI_SI SPI_SCKSPI_SS_B

V

PIO3/

DP13A

PIO3/

DP18A

W

Y

PIO3/

DP18B

VCCIO_2

PIO2 PIO2 PIO2 PIO2 VCC PIO2 PIO2

GND PIO2 PIO2 PIO2 GND PIO2 PIO2 PIO2 PIO2

Y _DP13B

PIO3/

DP14A

AA

AB

PIO3/

DP14B

PIO2 PIO2 PIO2 GND PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2

AB

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

I/O Bank 2

(2.42, 30-MAR-2012)

Lattice Semiconductor Corporation

76

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Pinout Table

Table 44 provides a detailed pinout table for the two chip-scale BGA packages. Pins are generally arranged by I/O

bank, then by ball function. The balls with a black circle () are unconnected balls (N.C.) for the iCE65L04 in the

CB284 package. The CB132 package fits within the CB284 package footprint as shown in Figure 48. The right-most

column shows which CB132 ball corresponds to the CB284.

The table also highlights the differential I/O pairs in I/O Bank 3.

Table 44: iCE65 CB284 Chip-scale BGA Pinout Table (with CB132 cross reference)

Ball Number

iCE65L04

iCE65L08

E10

E11

A1

Pin Type by Device

CB132 Ball

Ball Function

GBIN0/PIO0

GBIN1/PIO0

PIO0 ()

PIO0

iCE65L04 iCE65L08

Bank

0

Equivalent

A6

A7

—

GBIN

N.C.

PIO

N.C.

PIO

N.C.

PIO

GBIN

PIO

A2

A3

A4

A5

A6

A7

A9

A10

A11

A12

A13

A15

A16

A17

A18

A14

A19

A20

C3

—

PIO0

PIO0 ()

PIO0

PIO0 ()

PIO0

C4

C5

C6

C7

C9

C10

C11

C13

C14

C15

C16

C17

C18

C19

E5

—

A1

A2

A3

A4

A5

A10

E6

E7

E8

E9

E14

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

www.latticesemi.com

77

iCE65 Ultra Low-Power mobileFPGA^™Family

Ball Number

iCE65L04

iCE65L08

E15

Pin Type by Device

CB132 Ball

Equivalent

A11

A12

C4

Ball Function

PIO0

iCE65L04

PIO

iCE65L08

PIO

Bank

0

PIO0

E16

G8

PIO

0

PIO0

G9

PIO

0

C5

PIO0

G10

PIO

0

C6

PIO0

G11

PIO

0

C7

PIO0

G12

PIO

0

C8

PIO0

G13

PIO

0

C9

PIO0

G14

G15

G16

H9

PIO

0

C10

C11

C12

D5

PIO0

H10

PIO

0

D6

PIO0

H11

PIO

0

D7

PIO0

H12

PIO

0

D8

PIO0

H13

PIO

0

D9

PIO0

VCCIO_0

H14

H15

A8

A21

E12

K10

PIO

VCCIO

PIO

VCCIO

0

D10

D11

—

A8

F6

GBIN2/PIO1

GBIN3/PIO1

PIO1 ()

PIO1

PIO1 ()

PIO1

PIO1 ()

PIO1

PIO1 ()

PIO1

PIO1 ()

PIO1

PIO1 ()

PIO1

L18

K18

A22

AA22

B22

C20

C22

D20

D22

E20

E22

F18

F20

F22

G18

G20

G22

H16

H18

H20

J15

GBIN

N.C.

PIO

N.C.

PIO

N.C.

PIO

N.C.

PIO

N.C.

PIO

N.C.

PIO

N.C.

GBIN

PIO

1

G14

F14

—

B14

—

C14

—

D12

D14

—

E11

E12

E14

—

J16

J18

J22

K15

K16

K20

K22

F11

F12

—

PIO1

PIO1 ()

—

(2.42, 30-MAR-2012)

Lattice Semiconductor Corporation

78

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Ball Number

iCE65L04

iCE65L08

L15

Pin Type by Device

iCE65L04 iCE65L08

CB132 Ball

Equivalent

G11

G12

—

Ball Function

PIO1

PIO1 ()

PIO1

PIO1 ()

PIO1

PIO1 ()

PIO1

PIO1 ()

PIO1

PIO1 ()

TCK

Bank

1

PIO

L16

L22

N.C.

PIO

M15

M16

M20

M22

N15

N16

N22

P15

P16

P18

P20

P22

R18

R20

R22

T20

T22

U20

U22

V20

V22

W20

W22

Y22

R16

T16

U18

V18

T18

H22

J20

H11

H12

—

PIO

N.C.

PIO

—

J11

J12

—

K11

K12

K14

—

L14

—

PIO

N.C.

PIO

N.C.

PIO

N.C.

JTAG

VCCIO

PIO

—

JTAG

VCCIO

L12

M12

N14

P14

M14

—

F9

H14

TDI

TDO

TMS

TRST_B

VCCIO_1

K13

M18

CDONE

CRESET_B

GBIN4/PIO2

GBIN5/PIO2

PIO2

T14

R14

V12

V11

R8

CONFIG

GBIN

PIO

CONFIG

GBIN

PIO

2

M10

L10

P7

P8

L4

L5

L6

L7

L8

M3

M4

M6

M7

M8

PIO2

R9

R10

R11

R12

T7

T8

T10

T11

T12

PIO2

PIO

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

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79

iCE65 Ultra Low-Power mobileFPGA^™Family

Ball Number

iCE65L04

iCE65L08

T13

Pin Type by Device

CB132 Ball

Ball Function

PIO2

iCE65L04

PIO

iCE65L08

PIO

VCCIO

Bank

2

Equivalent

M9

P2

P3

P4

P5

P9

—

PIO2

PIO2 ()

PIO2

V6

V7

V8

V9

V13

Y4

Y5

Y6

Y7

Y9

Y10

Y13

Y14

Y15

Y17

Y18

Y19

Y20

AB2

AB3

AB4

AB6

AB7

AB8

PIO

—

PIO

N.C.

PIO

AB9

PIO

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

R13

PIO2 ()

PIO2/CBSEL0

PIO2/CBSEL1

VCCIO_2

N.C.

PIO

L9

P10

J9

M5

—

V14

N13

T9

PIO

VCCIO

Y11

PIO3/DP00A

PIO3/DP00B

F5

G5

DPIO

3

B1

C1

PIO3/DP01A

PIO3/DP01B

G7

H7

DPIO

3

C3

D3

PIO3/DP02A

PIO3/DP02B

H8

J8

DPIO

3

D4

E4

(2.42, 30-MAR-2012)

Lattice Semiconductor Corporation

80

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Ball Number

iCE65L04

iCE65L08

Pin Type by Device

iCE65L04 iCE65L08

CB132 Ball

Equivalent

Ball Function

Bank

PIO3/DP03A

PIO3/DP03B

H5

J5

DPIO

3

D1

E1

PIO3/DP04A

PIO3/DP04B

K8

K7

DPIO

3

F4

F3

PIO3/DP05A

PIO3/DP05B

E3

F3

DPIO

3

—

PIO3/DP06A

PIO3/DP06B

G3

H3

DPIO

3

—

PIO3/DP07A ()

PIO3/DP07B ()

B1

C1

N.C.

DPIO

3

—

PIO3/DP08A ()

PIO3/DP08B ()

D1

E1

N.C.

DPIO

3

—

PIO3/DP09A

PIO3/DP09B

H1

J1

DPIO

3

—

PIO3/DP10A

PIO3/DP10B

K1

L1

DPIO

3

—

PIO3/DP11A

GBIN7/PIO3/DP11B

L3

L5

DPIO

GBIN

DPIO

GBIN

3

—

G1

PIO3/DP12A ()

PIO3/DP12B ()

T1

U1

N.C.

DPIO

3

—

PIO3/DP13A ()

PIO3/DP13B ()

W1

Y1

N.C.

DPIO

3

—

PIO3/DP14A ()

PIO3/DP14B ()

AA1

AB1

N.C.

DPIO

3

—

GBIN6/PIO3/DP15A

PIO3/DP15B

M5

M3

GBIN

DPIO

GBIN

DPIO

3

H1

—

PIO3/DP16A

PIO3/DP16B

N3

P3

DPIO

3

—

PIO3/DP17A

PIO3/DP17B

U3

V3

DPIO

3

—

PIO3/DP18A

PIO3/DP18B

W3

Y3

DPIO

3

—

PIO3/DP19A

PIO3/DP19B

L7

L8

DPIO

3

G3

G4

PIO3/DP20A

PIO3/DP20B

M7

M8

DPIO

3

H3

H4

PIO3/DP21A

PIO3/DP21B

N7

N5

DPIO

3

J3

J1

PIO3/DP22A

PIO3/DP22B

P7

P8

DPIO

3

K3

K4

PIO3/DP23A

PIO3/DP23B

R5

T5

DPIO

3

L1

M1

PIO3/DP24A

PIO3/DP24B

U5

V5

DPIO

3

N1

P1

VCCIO_3

F1

P1

VCCIO

3

—

Lattice Semiconductor Corporation

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81

iCE65 Ultra Low-Power mobileFPGA^™Family

Ball Number

Pin Type by Device

iCE65L04

iCE65L08

J7

CB132 Ball

Equivalent

Ball Function

VCCIO_3

VREF

iCE65L04

VCCIO

VREF

iCE65L08

VCCIO

VREF

Bank

3

E3

—

J6

K1

—

K3

N10

P5

R3

M1

PIOS/SPI_SO

PIOS/SPI_SI

PIOS/SPI_SCK

PIOS/SPI_SS_B

SPI_VCC

T15

V15

V16

V17

R15

SPI

M11

P11

P12

P13

L11

GND

C12

E13

J3

GND

—

A9

—

K5

F1

F7

G7

G8

G9

H6

H7

H8

—

J8

J14

—

L3

—

K11

L11

L12

L13

M10

M11

M12

N1

N12

N18

N20

R7

T3

V1

V10

Y12

Y16

AB5

G1

P6

—

R1

—

VCC

C8

D3

VCC

—

F8

G6

—

H9

J4

J7

—

K12

L10

L20

M13

N8

N11

Y8

VPP_2V5

VPP_FAST

E18

E17

VPP

A14

A13

(2.42, 30-MAR-2012)

Lattice Semiconductor Corporation

82

www.latticesemi.com

Package Mechanical Drawing

Figure 49: CB284 Package Mechanical Drawing

CB284: 12 x 12 mm, 284-ball, 0.5 mm ball-pitch, chip-scale ball grid array

Mark pin 1 dot

Top View

Bottom View

A

B

A

B

C

D

E

C

D

E

F

G

H

J

G

H

J

K

L

iCE65L08F-T ENG

CB284C NXXXXXXX

YYWW

M

N

P

M

N

P

R

T

R

T

U

V

U

V

W

Y

W

Y

AA

AB

AA

AB

b

e

E1

E

Side View

Top Marking Format

Description

Symbol

Min.

Nominal

Max.

Units

Line Content

Description

Logo

Number of Ball Columns

Number of Ball Rows

Number of Signal Balls

X

Y

22

Columns

Rows

1

2

3

Logo

iCE65L08F Part number

n

E

284

12.00

0.50

—

Balls

-T

ENG

Power/Speed

Engineering

X

Y

11.90

—

12.10

—

Body Size

D

CB284C

Package type and

Ball Pitch

e

NXXXXXXX Lot number

Ball Diameter

b

0.27

—

0.37

—

mm

4

5

6

YYWW

N/A

Date Code

Blank

X

Y

E1

D1

A

10.50

—

Edge Ball Center to

Center

—

Package Height

Stand Off

—

1.00

0.26

A1

0.16

—

Thermal Resistance

Junction-to-Ambient

θ (⁰C/W)

0 LFM

35

200 LFM

28

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83

iCE65 Ultra Low-Power mobileFPGA^™Family

Die Cross Reference

The tables in this section list all the pads on a specific die type and provide a cross reference on how a specific pad

connects to a ball or pin in each of the available package offerings. Similarly, the tables provide the pad coordinates

for the die-based version of the product (DiePlus). These tables also provide a way to prototype with one package

option and then later move to a different package or die.

As described in “Input and Output Register Control per PIO Pair” on page 16, PIO pairs share register control inputs.

Similarly, as described in “Differential Inputs and Outputs” on page 12, a PIO pair can form a differential input or

output. PIO pairs in I/O Bank 3 are optionally differential inputs or differential outputs. PIO pairs in all other I/O

Banks are optionally differential outputs. In the tables, differential pairs are surrounded by a heavy blue box.

iCE65L04

Table 45 lists all the pads on the iCE65L04 die and how these pads connect to the balls or pins in the supported

package styles. Most VCC, VCCIO, and GND pads are double-bonded inside the package although the table shows

only a single connection.

For additional information on the iCE65L04 DiePlus product, please refer to the following data sheet.

DiePlus Advantage FPGA Known Good Die

Table 45: iCE65L04 Die Cross Reference

iCE65L04

Pad Name

DiePlus

CB132

VQ100

CB196

CB284

Pad

X (µm)

Y (µm)

PIO3_00/DP00A

PIO3_01/DP00B

1

2

B1

C1

B1

F5

G5

1

2

129.40

231.40

2,687.75

2,642.74

PIO3_02/DP01A

PIO3_03/DP01B

3

4

C3

D3

C3

G7

H7

3

4

129.40

231.40

2,597.75

2,552.74

GND

VCCIO_3

5

—

6

F1

—

E3

—

F1

—

E3

—

K5

—

J7

—

5

6

7

8

129.40

231.40

129.40

231.40

2,507.75

2,462.74

2,417.75

2,372.74

—

PIO3_04/DP02A

PIO3_05/DP02B

7

8

D4

E4

D1

D2

H8

J8

9

10

129.40

231.40

2,327.75

2,292.74

PIO3_06/DP03A

PIO3_07/DP03B

—

D1

E1

E2

H5

J5

11

12

129.40

231.40

2,257.75

2,222.74

VCC

—

H9

D3

13

129.40

2,187.75

PIO3_08/DP04A

PIO3_09/DP04B

9

10

F4

F3

D4

E4

K8

K7

14

15

231.40

129.40

2,152.74

2,117.75

PIO3_10/DP05A

PIO3_11/DP05B

—

F3

F4

E3

F3

16

17

231.40

129.40

2,082.74

2,047.75

GND

—

H6

A9

M10

18

231.40

2,012.74

PIO3_12/DP06A

PIO3_13/DP06B

—

F5

E5

G3

H3

19

20

129.40

231.40

1,977.75

1,942.74

GND

—

A9

—

J3

—

21

22

129.40

231.40

1,907.75

1,872.74

PIO3_14/DP07A

PIO3_15/DP07B

—

H1

J1

23

24

129.40

231.40

1,837.75

1,802.74

VCCIO_3

VCC

—

11

—

G6

K1

G6

K3

L10

25

26

129.40

231.40

1,767.75

1,732.74

PIO3_16/DP08A

PIO3_17/DP08B

—

K1

L1

27

28

129.40

231.40

1,697.75

1,662.74

(2.42, 30-MAR-2012)

84

Lattice Semiconductor Corporation

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iCE65L04

Pad Name

DiePlus

CB132

VQ100

CB196

CB284

Pad

X (µm)

Y (µm)

PIO3_18/DP09A

GBIN7/PIO3_19/DP09B

12

13

—

G1

G2

G1

L3

L5

29

30

129.40

231.40

1,627.75

1,592.74

VCCIO_3

VREF

14

N/A

—

J6

N/A

—

J6

N/A

A9

N10

M1

N1

31

32

33

129.40

231.40

129.40

1,557.75

1,522.74

1,487.75

GND

GBIN6/PIO3_20/DP10A

PIO3_21/DP10B

15

16

H1

—

H1

H2

M5

M3

34

35

231.40

129.40

1,452.74

1,417.75

GND

17

H7

A9

M11

36

231.40

1,382.74

PIO3_22/DP11A

PIO3_23/DP11B

—

G3

G4

N3

P3

37

38

129.40

231.40

1,347.75

1,312.74

VCCIO_3

GND

—

K1

—

A9

—

R3

—

T3

—

39

40

41

42

129.40

231.40

129.40

231.40

1,277.75

1,242.74

1,207.75

1,172.74

GND

PIO3_24/DP12A

PIO3_25/DP12B

—

J1

J2

U3

V3

43

44

129.40

231.40

1,137.75

1,102.74

GND

—

A9

V1

45

129.40

1,067.75

PIO3_26/DP13A

PIO3_27/DP13B

—

H4

H3

W3

Y3

46

47

231.40

129.40

1,032.74

997.75

PIO3_28/DP14A

PIO3_29/DP14B

18

19

G3

G4

K2

J3

L7

L8

48

49

231.40

129.40

962.74

927.75

PIO3_30/DP15A

PIO3_31/DP15B

—

H3

H4

H5

G5

M7

M8

50

51

231.40

129.40

892.74

857.75

VCC

—

J4

F2

N8

52

231.40

822.74

PIO3_32/DP16A

PIO3_33/DP16B

20

21

J3

J1

L1

L2

N7

N5

53

54

129.40

231.40

787.75

752.74

VCCIO_3

GND

22

—

23

—

K1

—

L3

—

K1

—

L3

—

P5

—

R7

—

55

56

57

58

129.40

231.40

129.40

231.40

717.75

682.74

637.75

592.74

GND

PIO3_34/DP17A

PIO3_35/DP17B

—

K3

K4

M1

M2

P7

P8

59

60

129.40

231.40

547.75

502.74

PIO3_36/DP18A

PIO3_37/DP18B

24

25

L1

M1

K3

K4

R5

T5

61

62

129.40

231.40

457.75

412.74

PIO3_38/DP19A

PIO3_39/DP19B

—

N1

P1

N1

N2

U5

V5

63

64

129.40

231.40

367.75

322.74

PIO2_00

PIO2_01

—

P2

—

L4

AB2

V6

65

66

545.00

595.00

139.20

37.20

PIO2_02

GND

PIO2_03

—

26

M3

—

L4

M3

C2

P1

T7

AB5

R8

67

68

69

645.00

695.00

745.00

139.20

37.20

139.20

PIO2_04

PIO2_05

27

28

P3

M4

N3

P2

V7

T8

70

71

795.00

845.00

37.20

139.20

PIO2_06

PIO2_07

29

30

L5

P4

L5

M4

R9

V8

72

73

895.00

930.00

37.20

139.20

Lattice Semiconductor Corporation

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85

iCE65 Ultra Low-Power mobileFPGA^™Family

iCE65L04

Pad Name

DiePlus

CB132

VQ100

CB196

CB284

Pad

X (µm)

Y (µm)

PIO2_08

VCCIO_2

PIO2_09

—

31

—

L6

M5

P5

P3

M5

K5

R10

T9

V9

74

75

76

965.00

1,000.00

1,035.00

37.20

139.20

37.20

PIO2_10

GND

PIO2_11

—

32

—

M6

P6

—

N4

H7

P4

T10

V10

Y4

77

78

79

1,070.00

1,105.00

1,140.00

139.20

37.20

139.20

PIO2_12

PIO2_13

—

L6

—

Y5

AB6

80

81

1,175.00

1,210.00

37.20

139.20

PIO2_14

PIO2_15

—

AB7

AB8

82

83

1,245.00

1,280.00

37.20

139.20

PIO2_16

PIO2_17

—

AB9

AB10

84

85

1,315.00

1,350.00

37.20

139.20

PIO2_18

GND

PIO2_19

—

J8

—

H8

K6

AB11

N12

Y6

86

87

88

1,385.00

1,420.00

1,455.00

37.20

139.20

37.20

PIO2_20

VCC

PIO2_21

—

N5

J4

M6

Y7

Y8

Y9

89

90

91

1,490.00

1,525.00

1,560.00

139.20

37.20

139.20

PIO2_22

GBIN5/PIO2_23

—

33

—

P7

N6

P5

Y10

V11

92

93

1,595.00

1,630.00

37.20

139.20

GBIN4/PIO2_24

PIO2_25

34

—

P8

—

L7

—

V12

AB12

94

95

1,665.00

1,700.00

37.20

139.20

VCCIO_2

—

J9

Y11

96

1,735.00

37.20

PIO2_26

PIO2_27

—

K7

AB13

AB14

97

98

1,770.00

1,805.00

139.20

37.20

GND

—

J5

Y12

99

1,840.00

139.20

PIO2_28

PIO2_29

—

K9

M7

AB15

Y13

100

101

1,875.00

1,910.00

37.20

139.20

PIO2_30

PIO2_31

—

K8

P7

Y14

Y15

102

103

1,945.00

1,980.00

37.20

139.20

PIO2_32

PIO2_33

—

L8

P8

Y17

Y18

104

105

2,015.00

2,050.00

37.20

139.20

PIO2_34

PIO2_35

—

N8

M8

Y19

Y20

106

107

2,085.00

2,120.00

37.20

139.20

VCC

35

—

J7

—

J7

—

N11

—

108

109

2,155.00

2,190.00

37.20

139.20

PIO2_36

PIO2_37

36

37

P9

M7

P9

N9

V13

T11

110

111

2,225.00

2,260.00

37.20

139.20

VCCIO_2

38

J9

N10

N13

112

2,295.00

37.20

PIO2_38

GND

PIO2_39

—

39

—

L7

H8

M8

M9

J8

N12

R11

M12

T12

113

114

115

2,330.00

2,365.00

2,400.00

139.20

37.20

139.20

PIO2_40

PIO2_41

—

40

L8

M9

N11

N13

R12

T13

116

117

2,435.00

2,470.00

37.20

139.20

PIO2_42/CBSEL0

PIO2_43/CBSEL1

41

42

L9

P10

L9

P10

R13

V14

118

119

2,505.00

2,540.00

37.20

139.20

CDONE

43

M10

T14

120

2,575.00

37.20

(2.42, 30-MAR-2012)

86

Lattice Semiconductor Corporation

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iCE65L04

Pad Name

CRESET_B

DiePlus

CB132

L10

VQ100

44

CB196

L10

CB284

R14

Pad

121

X (µm)

2,625.00

Y (µm)

139.20

PIOS_00/SPI_SO

PIOS_01/SPI_SI

45

46

M11

P11

M11

P11

T15

V15

122

123

2,690.00

2,740.00

37.20

139.20

GND

47

—

P6

Y16

124

2,790.00

37.20

PIOS_02/SPI_SCK

PIOS_03/SPI_SS_B

48

49

P12

P13

P12

P13

V16

V17

125

126

2,840.00

2,890.00

139.20

37.20

SPI_VCC

50

L11

R15

127

2,990.00

37.20

TDI

TMS

TCK

TDO

TRST_B

N/A

M12

P14

L12

N14

M14

M12

P14

L12

N14

M14

T16

V18

R16

U18

T18

128

129

130

131

132

3,610.80

3,712.80

3,610.80

3,712.80

3,610.80

342.00

392.00

442.00

492.00

542.00

PIO1_00

PIO1_01

51

52

L14

K12

K11

L13

R18

P16

133

134

3,712.80

3,610.80

592.00

642.00

PIO1_02

PIO1_03

53

54

K11

K14

K12

M13

P15

P18

135

136

3,712.80

3,610.80

692.00

727.00

GND

55

J14

N18

137

138

3,712.80

3,610.80

762.00

797.00

PIO1_04

PIO1_05

56

57

J12

J11

J10

L14

N16

N15

139

140

3,712.80

3,610.80

832.00

867.00

VCCIO_1

58

—

H14

—

H14

—

M18

—

141

142

3,712.80

3,610.80

902.00

937.00

PIO1_06

PIO1_07

59

60

H12

H11

J11

K14

M16

M15

143

144

3,712.80

3,610.80

972.00

1,007.00

PIO1_08

PIO1_09

—

H10

J13

W20

V20

145

146

3,712.80

3,610.80

1,042.00

1,077.00

PIO1_10

VCC

PIO1_11

—

61

—

H9

—

J12

N7

—

U20

M13

—

147

148

149

150

3,712.80

3,610.80

3,712.80

3,610.80

1,112.00

1,147.00

1,182.00

1,217.00

—

H13

T22

PIO1_12

PIO1_13

—

H12

—

R22

P22

151

152

3,712.80

3,610.80

1,252.00

1,287.00

PIO1_14

PIO1_15

—

G13

N22

T20

153

154

3,712.80

3,610.80

1,322.00

1,357.00

PIO1_16

PIO1_17

—

H11

G14

R20

P20

155

156

3,712.80

3,610.80

1,392.00

1,427.00

GND

—

K10

—

N20

—

157

158

3,712.80

3,610.80

1,462.00

1,497.00

PIO1_18

GBIN3/PIO1_19

—

62

—

F14

G10

G12

M20

K18

159

160

3,712.80

3,610.80

1,532.00

1,567.00

GBIN2/PIO1_20

PIO1_21

63

—

G14

—

F10

F14

L18

K20

161

162

3,712.80

3,610.80

1,602.00

1,637.00

VCCIO_1

—

H14

—

J20

—

163

164

3,712.80

3,610.80

1,672.00

1,707.00

PIO1_22

PIO1_23

—

F13

D13

H20

G20

165

166

3,712.80

3,610.80

1,742.00

1,777.00

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

www.latticesemi.com

87

iCE65 Ultra Low-Power mobileFPGA^™Family

iCE65L04

Pad Name

DiePlus

CB132

VQ100

CB196

CB284

Pad

X (µm)

Y (µm)

PIO1_24

PIO1_25

—

G11

F11

F20

E20

167

168

3,712.80

3,610.80

1,812.00

1,847.00

PIO1_26

PIO1_27

—

E10

E14

D20

C20

169

170

3,712.80

3,610.80

1,882.00

1,917.00

GND

—

G8

—

G8

—

L12

—

171

172

3,712.80

3,610.80

1,952.00

1,987.00

PIO1_28

PIO1_29

—

G12

F12

D14

G22

L16

173

174

3,712.80

3,610.80

2,022.00

2,057.00

PIO1_30

PIO1_31

64

65

G11

F12

E13

C14

L15

K16

175

176

3,712.80

3,610.80

2,092.00

2,127.00

VCC

—

K13

—

L20

—

177

178

3,712.80

3,610.80

2,162.00

2,197.00

PIO1_32

PIO1_33

66

—

E14

F11

E11

C13

J18

K15

179

180

3,712.80

3,610.80

2,232.00

2,267.00

VCCIO_1

67

—

F9

—

F9

—

K13

—

181

182

3,712.80

3,610.80

2,302.00

2,337.00

PIO1_34

PIO1_35

68

69

E12

D14

E12

B14

J16

H18

183

184

3,712.80

3,610.80

2,377.00

2,427.00

GND

70

G9

L13

185

3,712.80

2,477.00

PIO1_36

PIO1_37

71

72

E11

D12

B13

D12

J15

H16

186

187

3,610.80

3,712.80

2,527.00

2,577.00

PIO1_38

PIO1_39

73

74

C14

B14

C12

D11

G18

F18

188

189

3,610.80

3,712.80

2,627.00

2,677.00

VPP_2V5

75

A14

E18

190

3,610.80

2,739.68

VPP_FAST

VCC

76

77

A13

F8

A13

F8

E17

K12

191

192

193

3,097.00

2,997.00

2,947.00

2,962.80

2,860.80

2,962.80

VCC

PIO0_00

PIO0_01

78

—

A12

C12

C11

—

E16

G16

194

195

2,897.00

2,847.00

2,860.80

2,962.80

PIO0_02

PIO0_03

79

80

A11

C11

A12

B11

E15

G15

196

197

2,797.00

2,747.00

2,860.80

2,962.80

PIO0_04

PIO0_05

—

81

D11

A10

—

D10

H15

E14

198

199

2,697.00

2,647.00

2,860.80

2,962.80

PIO0_06

PIO0_07

82

83

C10

D10

A11

D9

G14

H14

200

201

2,612.00

2,577.00

2,860.80

2,962.80

GND

84

—

A9

—

H6

—

E13

—

202

203

2,542.00

2,507.00

2,860.80

2,962.80

PIO0_08

PIO0_09

85

86

C9

D9

C10

A10

G13

H13

204

205

2,472.00

2,437.00

2,860.80

2,962.80

PIO0_10

PIO0_11

87

—

C8

D8

B10

E9

G12

H12

206

207

2,402.00

2,367.00

2,860.80

2,962.80

PIO0_12

PIO0_13

—

A18

A17

208

209

2,332.00

2,297.00

2,860.80

2,962.80

PIO0_14

PIO0_15

—

A16

A15

210

211

2,262.00

2,227.00

2,860.80

2,962.80

VCCIO_0

88

—

A8

—

A8

—

E12

—

212

213

2,192.00

2,157.00

2,860.80

2,962.80

(2.42, 30-MAR-2012)

88

Lattice Semiconductor Corporation

www.latticesemi.com

iCE65L04

Pad Name

DiePlus

CB132

VQ100

CB196

CB284

Pad

X (µm)

Y (µm)

PIO0_16

PIO0_17

—

C9

C19

C18

214

215

2,122.00

2,087.00

2,860.80

2,962.80

PIO0_18

PIO0_19

—

B9

D8

C17

C16

216

217

2,052.00

2,017.00

2,860.80

2,962.80

PIO0_20

PIO0_21

—

C8

E8

C15

C14

218

219

1,982.00

1,947.00

2,860.80

2,962.80

PIO0_22

GBIN1/PIO0_23

—

89

—

A7

B8

E7

C13

E11

220

221

1,912.00

1,877.00

2,860.80

2,962.80

GND

—

B12

—

C12

—

222

223

1,842.00

1,807.00

2,860.80

2,962.80

GBIN0/PIO0_24

PIO0_25

90

—

A6

—

A7

D7

E10

C11

224

225

1,772.00

1,737.00

2,860.80

2,962.80

PIO0_26

PIO0_27

—

C7

E6

C10

C9

226

227

1,702.00

1,667.00

2,860.80

2,962.80

VCC

—

B7

—

C8

—

228

229

1,632.00

1,597.00

2,860.80

2,962.80

PIO0_28

PIO0_29

—

A6

B6

C7

C6

230

231

1,562.00

1,527.00

2,860.80

2,962.80

PIO0_30

PIO0_31

—

A5

D6

C5

C4

232

233

1,492.00

1,457.00

2,860.80

2,962.80

GND

—

F7

—

F7

—

K11

—

234

235

1,422.00

1,387.00

2,860.80

2,962.80

PIO0_32

PIO0_33

—

C3

A7

236

237

1,352.00

1,317.00

2,860.80

2,962.80

PIO0_34

PIO0_35

—

A6

A5

238

239

1,282.00

1,247.00

2,860.80

2,962.80

PIO0_36

VCCIO_0

PIO0_37

91

92

93

C7

F6

D7

C6

F6

C5

G11

K10

H11

240

241

242

243

1,212.00

1,177.00

1,142.00

1,107.00

2,860.80

2,962.80

2,860.80

2,962.80

PIO0_38

PIO0_39

94

95

C6

A5

B5

A4

G10

E9

244

245

1,072.00

1,037.00

2,860.80

2,962.80

PIO0_40

PIO0_41

96

97

D6

C5

B4

D5

H10

G9

246

247

1,002.00

967.00

2,860.80

2,962.80

PIO0_42

GND

PIO0_43

—

98

99

A4

G7

D5

A3

G7

B3

E8

L11

H9

248

249

250

917.00

867.00

817.00

2,860.80

2,962.80

2,860.80

PIO0_44

PIO0_45

—

100

C4

A3

C4

A2

G8

E7

251

252

767.00

717.00

2,962.80

2,860.80

PIO0_46

PIO0_47

—

A2

A1

B2

E6

E5

253

254

667.00

617.00

2,962.80

2,860.80

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

www.latticesemi.com

89

iCE65 Ultra Low-Power mobileFPGA^™Family

iCE65L08

Table 46 lists all the pads on the iCE65L08 die and how these pads connect to the balls or pins in the supported

package styles. Most VCC, VCCIO, and GND pads are double-bonded inside the package although the table shows

only a single connection.

For additional information on the iCE65L08 DiePlus product, please refer to the following data sheet.

 DiePlusAdvantage FPGA Known Good Die

Table 46: iCE65L08 Die Cross Reference

Available Packages

CB196 CB284

B1

DiePlus

X (µm)

129.735

231.735

iCE65L08

Pad Name

PIO3_00/DP00A

PIO3_01/DP00B

Pad

1

2

Y (µm)

3,882.665

3,837.665

—

C1

PIO3_02/DP01A

PIO3_03/DP01B

C1

B1

F5

G5

3

4

129.735

231.735

3,792.665

3,747.665

GND

VCCIO_3

C2

—

E3

—

K5

—

J7

—

5

6

7

8

129.735

231.735

129.735

231.735

3,702.665

3,657.665

3,612.665

3,567.665

PIO3_04/DP02A

PIO3_05/DP02B

D3

C3

E3

F3

9

10

129.735

231.735

3,512.665

3,477.665

PIO3_06/DP03A

PIO3_07/DP03B

D1

D2

G3

H3

11

12

129.735

231.735

3,442.665

3,407.665

VCC

F2

—

D3

—

13

14

129.735

231.735

3,372.665

3,337.665

PIO3_08/DP04A

PIO3_09/DP04B

D4

E4

D1

E1

15

16

129.735

231.735

3,302.665

3,267.665

PIO3_10/DP05A

PIO3_11/DP05B

—

H1

J1

17

18

129.735

231.735

3,232.665

3,197.665

GND

F1

—

M10

—

19

20

129.735

231.735

3,162.665

3,127.665

PIO3_12/DP06A

PIO3_13/DP06B

E2

E1

H5

J5

21

22

129.735

231.735

3,092.665

3,057.665

GND

L3

—

J3

—

23

24

129.735

231.735

3,022.665

2,987.665

PIO3_14/DP07A

PIO3_15/DP07B

F5

E5

K1

L1

25

26

129.735

231.735

2,952.665

2,917.665

VCCIO_3

VCC

E3

—

G6

—

K3

—

L10

—

27

28

29

30

129.735

231.735

129.735

231.735

2,882.665

2,847.665

2,812.665

2,777.665

VCC

PIO3_16/DP08A

PIO3_17/DP08B

F4

F3

G7

H7

31

32

129.735

231.735

2,742.665

2,707.665

VCCIO_3

GND

K1

—

F1

—

G1

—

33

34

35

36

129.735

231.735

129.735

231.735

2,672.665

2,637.665

2,602.665

2,567.665

GND

PIO3_18/DP09A

PIO3_19/DP09B

G3

G4

K8

K7

37

38

129.735

231.735

2,532.665

2,497.665

(2.42, 30-MAR-2012)

90

Lattice Semiconductor Corporation

www.latticesemi.com

Available Packages

CB196 CB284

DiePlus

X (µm)

iCE65L08

Pad Name

Pad

Y (µm)

PIO3_20/DP10A

PIO3_21/DP10B

—

39

40

129.735

231.735

2,462.665

2,427.665

H8

J8

PIO3_22/DP11A

PIO3_23/DP11B

41

42

129.735

231.735

2,392.665

2,357.665

G1

G2

T1

U1

VCCIO_3

VREF

GND

N10

—

M1

—

N1

—

P1

—

43

44

45

46

47

48

49

50

51

52

129.735

231.735

129.735

231.735

129.735

231.735

129.735

231.735

129.735

231.735

2,322.665

2,287.665

2,252.665

2,217.665

2,182.665

2,147.665

2,112.665

2,077.665

2,042.665

2,007.665

K1

—

N/A

J5

—

J6

—

H6

—

GND

VCCIO_3

GND

R1

—

GND

PIO3_24/DP12A

GBIN7/PIO3_25/DP12B

53

54

129.735

231.735

1,972.665

1,937.665

H4

H3

L3

L5

GND

55

129.735

1,902.665

H7

V1

GBIN6/PIO3_26/DP13A

PIO3_27/DP13B

56

57

231.735

129.735

1,867.665

1,832.665

H1

H2

M5

M3

PIO3_28/DP14A

PIO3_29/DP14B

—

58

59

231.735

129.735

1,798.665

1,762.665

N7

N5

PIO3_30/DP15A

PIO3_31/DP15B

60

61

231.735

129.735

1,727.665

1,692.665

J1

J2

N3

P3

GND

M11

—

62

63

231.735

129.735

1,657.665

1,622.665

J5

—

PIO3_32/DP16A

PIO3_33/DP16B

64

65

231.735

129.735

1,587.665

1,552.665

H5

G5

W1

Y1

VCCIO_3

GND

R3

—

T3

—

66

67

68

69

231.735

129.735

231.735

129.735

1,517.665

1,482.665

1,447.665

1,412.665

J6

—

J5

—

GND

PIO3_34/DP17A

PIO3_35/DP17B

70

71

231.735

129.735

1,377.665

1,342.665

K2

J3

AA1

AB1

PIO3_36/DP18A

PIO3_37/DP18B

—

72

73

231.735

129.735

1,307.665

1,272.665

L7

L8

PIO3_38/DP19A

PIO3_39/DP19B

—

74

75

231.735

129.735

1,237.665

1,202.665

M7

M8

PIO3_40/DP20A

PIO3_41/DP20B

76

77

231.735

129.735

1,167.665

1,132.665

L1

L2

P7

P8

VCC

N8

—

78

79

231.735

129.735

1,097.665

1,062.665

J4

—

PIO3_42/DP21A

PIO3_43/DP21B

80

81

231.735

129.735

1,027.665

992.665

K4

K3

R5

T5

VCCIO_3

GND

P5

—

R7

—

82

83

84

85

231.735

129.735

231.735

129.735

957.665

912.665

867.665

822.67

K1

—

L3

—

GND

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

www.latticesemi.com

91

iCE65 Ultra Low-Power mobileFPGA^™Family

Available Packages

CB196 CB284

M1 U3

DiePlus

X (µm)

231.735

129.735

iCE65L08

Pad Name

PIO3_44/DP22A

PIO3_45/DP22B

Pad

86

87

Y (µm)

777.67

732.67

M2

V3

PIO3_46/DP23A

PIO3_47/DP23B

N1

N2

U5

V5

88

89

231.735

129.735

687.67

642.67

PIO3_48/DP24A

PIO3_49/DP24B

—

W3

Y3

90

91

231.735

129.735

597.67

552.665

PIO2_00

PIO2_01

P1

M3

AB2

R8

92

93

510.0

560.0

139.5

37.5

PIO2_02

GND

PIO2_03

P2

P6

—

Y4

AB5

—

94

95

96

97

610.0

660.0

710.0

760.0

139.5

37.5

139.5

37.5

M4

T7

PIO2_04

PIO2_05

N3

—

AB3

R9

98

99

810.0

859.3

139.5

37.5

PIO2_06

PIO2_07

—

L4

Y5

T8

100

101

910.0

960.0

139.5

37.5

PIO2_08

VCCIO_2

PIO2_09

P3

M5

—

V6

T9

—

102

103

104

105

1,012.5

139.5

37.5

139.5

37.5

1,047.5

1,082.5

1,117.5

P4

R10

PIO2_10

GND

PIO2_11

N4

H8

—

AB4

V10

—

106

107

108

109

1,152.5

1,187.5

1,222.5

1,257.5

139.5

37.5

139.5

37.5

K5

V7

PIO2_12

PIO2_13

P5

—

Y7

V9

110

111

1,292.5

1,327.5

139.5

37.5

PIO2_14

PIO2_15

—

Y6

AB7

112

113

1,362.5

1,397.5

139.5

37.5

PIO2_16

PIO2_17

—

L5

AB6

Y9

114

115

1,432.5

1,467.5

139.5

37.5

PIO2_18

GND

PIO2_19

N5

P6

—

V8

N12

—

116

117

118

119

1,502.3

1,537.3

1,572.5

1,607.5

139.5

37.5

139.5

37.5

N6

AB8

PIO2_20

VCC

PIO2_21

K6

J7

—

AB9

Y8

—

120

121

122

123

1,642.5

1,677.5

1,712.5

1,747.5

139.5

37.5

139.5

37.5

L6

T10

PIO2_22

PIO2_23

M6

—

AB10

AB11

124

125

1,782.5

1,817.5

139.5

37.5

PIO2_24

PIO2_25

—

L7

AB12

Y10

126

127

1,852.5

1,887.5

139.5

37.5

PIO2_26

PIO2_27

P7

K7

AB13

AB14

128

129

1,922.5

1,957.5

139.5

37.5

VCCIO_2

N10

—

Y11

—

130

131

1,992.5

2,027.5

139.5

37.5

(2.42, 30-MAR-2012)

92

Lattice Semiconductor Corporation

www.latticesemi.com

Available Packages

CB196 CB284

Y13

DiePlus

X (µm)

2,062.5

2,097.5

iCE65L08

Pad Name

PIO2_28

Pad

132

133

Y (µm)

139.5

37.5

—

GBIN5/PIO2_29

M7

V11

GBIN4/PIO2_30

GND

N8

J8

—

V12

Y12

—

134

135

136

137

2,132.5

2,167.5

2,202.5

2,237.5

139.5

37.5

139.5

37.5

GND

PIO2_31

P8

Y14

PIO2_32

PIO2_33

—

M8

AB15

V13

138

139

2,272.5

2,307.5

139.5

37.5

PIO2_34

PIO2_35

—

L8

AB16

Y15

140

141

2,342.5

2,377.5

139.5

37.5

PIO2_36

PIO2_37

—

N9

AB17

AB18

142

143

2,412.5

2,447.5

139.5

37.5

PIO2_38

PIO2_39

—

AB19

AB20

144

145

2,482.5

2,517.5

139.5

37.5

PIO2_40

PIO2_41

—

AB21

Y17

146

147

2,552.5

2,587.5

139.5

37.5

PIO2_42

PIO2_43

—

AB22

Y18

148

149

2,622.5

2,657.5

139.5

37.5

PIO2_44

VCC

PIO2_45

P9

N7

—

Y19

N11

—

150

151

152

153

2,692.5

2,727.5

2,762.5

2,797.5

139.5

37.5

139.5

37.5

M9

Y20

PIO2_46

VCCIO_2

PIO2_47

K8

J9

—

T11

N13

—

154

155

156

157

2,832.5

2,867.5

2,902.5

2,937.5

139.5

37.5

139.5

37.5

N11

R11

GND

J8

—

M12

—

158

159

2,972.5

3,007.5

139.5

37.5

PIO2_48

PIO2_49

N12

K9

T12

R12

160

161

3,042.5

3,077.5

139.5

37.5

PIO2_50

N13

T13

162

3,112.5

139.5

PIO2_51/CBSEL0

PIO2_52/CBSEL1

L9

P10

R13

V14

163

164

3,147.5

3,182.5

37.5

139.5

CDONE

CRESET_B

M10

L10

T14

R14

165

166

3,217.5

3,260.0

37.5

139.5

PIOS_00/SPI_SO

PIOS_01/SPI_SI

M11

P11

T15

V15

167

168

3,320.0

3,370.0

37.5

139.5

GND

J8

—

Y16

—

169

170

3,420.0

3,470.0

37.5

139.5

PIOS_02/SPI_SCK

PIOS_03/SPI_SS_B

P12

P13

V16

V17

171

172

3,520.0

3,570.0

37.5

139.5

VCC

SPI_VCC

—

L11

—

R15

—

173

174

175

176

3,620.0

3,670.0

3,720.0

3,770.0

37.5

139.5

37.5

139.5

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

www.latticesemi.com

93

iCE65 Ultra Low-Power mobileFPGA^™Family

Available Packages

CB196 CB284

M12 T16

DiePlus

X (µm)

iCE65L08

Pad Name

Pad

Y (µm)

TDI

TMS

TCK

TDO

TRST_B

177

178

179

180

181

4,470.5

4,572.5

4,470.5

4,572.5

4,470.5

634.615

684.615

734.615

784.615

834.615

P14

L12

N14

M14

V18

R16

U18

T18

PIO1_00

PIO1_01

M13

K11

R18

P16

182

183

4,572.5

4,470.5

884.615

934.615

PIO1_02

PIO1_03

L13

L14

P15

P18

184

185

4,572.5

4,470.5

984.615

1,034.615

GND

G9

—

N18

—

186

187

4,572.5

4,470.5

1,084.615

1,134.615

PIO1_04

PIO1_05

J11

K12

N16

N15

188

189

4,572.5

4,470.5

1,184.615

1,234.62

VCCIO_1

F9

—

M18

—

190

191

4,572.5

4,470.5

1,287.115

1,322.115

PIO1_06

PIO1_07

J12

K14

M15

M16

192

193

4,572.5

4,470.5

1,357.115

1,392.115

PIO1_08

PIO1_09

—

T20

W20

194

195

4,572.5

4,470.5

1,427.115

1,462.115

PIO1_10

VCC

PIO1_11

—

H9

—

V20

M13

—

196

197

198

199

4,572.5

4,470.5

4,572.5

4,470.5

1,497.115

1,532.115

1,567.115

1,602.115

—

R20

PIO1_12

PIO1_13

—

Y22

AA22

200

201

4,572.5

4,470.5

1,637.115

1,672.115

PIO1_14

PIO1_15

—

J13

U20

W22

202

203

4,572.5

4,470.5

1,707.115

1,742.115

PIO1_16

PIO1_17

H11

J10

P20

V22

204

205

4,572.5

4,470.5

1,777.115

1,812.115

PIO1_18

GND

PIO1_19

H12

K10

—

U22

N20

—

206

207

208

209

4,572.5

4,470.5

4,572.5

4,470.5

1,847.115

1,882.115

1,917.110

1,952.115

H13

T22

PIO1_20

PIO1_21

—

H10

M20

R22

210

211

4,572.5

4,470.5

1,987.115

2,022.115

PIO1_22

VCCIO_1

PIO1_23

—

F9

—

P22

J20

—

212

213

214

215

4,572.5

4,470.5

4,572.5

4,470.5

2,057.115

2,092.115

2,127.115

2,162.115

G10

M22

PIO1_24

PIO1_25

G11

—

N22

K22

216

217

4,572.5

4,470.5

2,197.115

2,232.115

PIO1_26

GBIN3/PIO1_27

—

G12

L22

K18

218

219

4,572.5

4,470.5

2,267.115

2,302.11

GBIN2/PIO1_28

PIO1_29

F10

—

L18

J22

220

221

4,572.5

4,470.5

2,337.115

2,372.115

(2.42, 30-MAR-2012)

94

Lattice Semiconductor Corporation

www.latticesemi.com

Available Packages

CB196 CB284

K20

DiePlus

X (µm)

4,572.5

4,470.5

iCE65L08

Pad Name

PIO1_30

PIO1_31

Pad

222

223

Y (µm)

2,407.115

2,442.115

—

G14

F22

PIO1_32

PIO1_33

—

F11

G22

E22

224

225

4,572.5

4,470.5

2,477.115

2,512.115

PIO1_34

PIO1_35

F12

G13

L16

D22

226

227

4,572.5

4,470.5

2,547.115

2,582.115

GND

G8

—

L12

—

228

229

4,572.5

4,470.5

2,617.115

2,652.115

PIO1_36

VCCIO_1

PIO1_37

E10

H14

—

K16

H22

—

230

231

232

233

4,572.5

4,470.5

4,572.5

4,470.5

2,687.12

2,722.12

2,757.12

2,792.12

F14

H20

PIO1_38

PIO1_39

E11

D12

J18

C22

234

235

4,572.5

4,470.5

2,827.12

2,862.12

PIO1_40

PIO1_41

F13

E13

J16

B22

236

237

4,572.5

4,470.5

2,897.12

2,932.12

PIO1_42

PIO1_43

E12

E14

H18

G20

238

239

4,572.5

4,470.5

2,967.12

3,002.12

PIO1_44

PIO1_45

—

L15

A22

240

241

4,572.5

4,470.5

3,037.12

3,072.12

PIO1_46

VCC

PIO1_47

—

K13

—

H16

L20

—

242

243

244

245

4,572.5

4,470.5

4,572.5

4,470.5

3,107.12

3,142.12

3,177.12

3,229.615

D14

F20

PIO1_48

VCCIO_1

PIO1_49

D11

H14

—

K15

K13

—

246

247

248

249

4,572.5

4,470.5

4,572.5

4,470.5

3,279.615

3,329.615

3,379.615

3,429.62

C14

E20

PIO1_50

GND

PIO1_51

D13

J14

—

J15

L13

—

250

251

252

253

4,572.5

4,470.5

4,572.5

4,470.5

3,479.615

3,529.615

3,579.615

3,629.615

B14

D20

PIO1_52

PIO1_53

C13

B13

G18

C20

254

255

4,572.5

4,470.5

3,679.595

3,729.595

PIO1_54

VPP_2V5

C12

A14

F18

E18

256

257

4,572.5

4,470.5

3,779.595

3,879.575

VPP_FAST

VCC

A13

F8

—

E17

K12

—

258

259

260

3,866.975

3,766.98

3,716.98

4,054.5

4,156.5

4,054.5

VCC

PIO0_00

PIO0_01

—

G16

C19

261

262

3,666.98

3,616.98

4,156.5

4,054.5

PIO0_02

PIO0_03

C11

—

H15

C18

263

264

3,566.98

3,516.98

4,156.5

4,054.5

PIO0_04

VCCIO_0

PIO0_05

A12

F6

B11

H14

A21

C17

265

266

267

3,466.98

3,416.98

3,366.98

4,156.5

4,054.5

4,156.5

PIO0_06

PIO0_07

D10

A11

E16

G15

268

269

3,316.98

3,266.98

4,054.5

4,156.5

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

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95

iCE65 Ultra Low-Power mobileFPGA^™Family

Available Packages

CB196 CB284

F7 E13

DiePlus

X (µm)

3,216.98

iCE65L08

Pad Name

GND

Pad

270

271

Y (µm)

4,054.5

4,156.5

GND

—

3,166.98

PIO0_08

PIO0_09

D9

C10

E15

G14

272

273

3,116.98

3,064.48

4,054.5

4,156.5

PIO0_10

PIO0_11

A10

B10

A20

H13

274

275

3,029.48

2,994.48

4,054.5

4,156.5

PIO0_12

PIO0_13

—

E9

A19

G13

276

277

2,959.48

2,924.48

4,054.5

4,156.5

PIO0_14

PIO0_15

—

C16

E14

278

279

2,889.48

2,854.48

4,054.5

4,156.5

VCCIO_0

F6

—

E12

—

280

281

2,819.48

2,784.48

4,054.5

4,156.5

PIO0_16

PIO0_17

—

A18

A17

282

283

2,749.48

2,714.48

4,054.5

4,156.5

PIO0_18

PIO0_19

C9

—

C15

A16

284

285

2,679.48

2,644.48

4,054.5

4,156.5

PIO0_20

PIO0_21

B9

—

C14

H12

286

287

2,609.48

2,574.48

4,054.5

4,156.5

PIO0_22

PIO0_23

D8

C8

A15

H11

288

289

2,539.48

2,504.48

4,054.5

4,156.5

PIO0_24

PIO0_25

E8

—

C13

A14

290

291

2,469.48

2,434.48

4,054.5

4,156.5

GND

B12

—

C12

—

292

293

2,399.48

2,364.48

4,054.5

4,156.5

PIO0_26

PIO0_27

B8

D7

A13

A12

294

295

2,329.48

2,294.48

4,054.5

4,156.5

PIO0_28

GBIN1/PIO0_29

—

E7

C11

E11

296

297

2,259.48

2,224.48

4,054.5

4,156.5

GBIN0/PIO0_30

PIO0_31

A7

—

E10

G12

298

299

2,189.48

2,154.48

4,054.5

4,156.5

VCCIO_0

A8

—

A8

—

300

301

2,119.48

2,084.48

4,054.5

4,156.5

PIO0_32

PIO0_33

C7

—

A11

G11

302

303

2,049.48

2,014.48

4,054.5

4,156.5

PIO0_34

PIO0_35

E6

—

A10

C10

304

305

1,979.48

1,944.48

4,054.5

4,156.5

VCC

B7

—

C8

—

306

307

1,909.48

1,874.48

4,054.5

4,156.5

PIO0_36

PIO0_37

—

A6

A9

A7

308

309

1,839.48

1,804.48

4,054.5

4,156.5

PIO0_38

PIO0_39

B6

A5

C9

A6

310

311

1,769.48

1,734.48

4,054.5

4,156.5

GND

G7

K11

312

313

1,699.48

1,664.48

4,054.5

4,156.5

—

PIO0_40

PIO0_41

D6

C6

E9

G10

314

315

1,629.48

1,594.48

4,054.5

4,156.5

(2.42, 30-MAR-2012)

96

Lattice Semiconductor Corporation

www.latticesemi.com

Available Packages

CB196 CB284

C5 A5

DiePlus

X (µm)

1,559.48

1,524.48

iCE65L08

Pad Name

PIO0_42

PIO0_43

Pad

316

317

Y (µm)

4,054.5

4,156.5

B5

G9

PIO0_44

PIO0_45

A4

—

A3

A4

318

319

1,489.48

1,454.48

4,054.5

4,156.5

PIO0_46

PIO0_47

—

A2

C7

320

321

1,419.48

1,384.48

4,054.5

4,156.5

PIO0_48

VCCIO_0

PIO0_49

—

A8

—

C6

K10

—

322

323

324

325

1,331.98

1,281.98

1,231.98

1,181.98

4,054.5

4,156.5

4,054.5

4,156.5

E8

PIO0_50

PIO0_51

B4

C4

A1

E7

326

327

1,131.98

1,081.98

4,054.5

4,156.5

PIO0_52

PIO0_53

A3

B3

C5

E6

328

329

1,031.98

981.98

4,054.5

4,156.5

PIO0_54

GND

PIO0_55

D5

A9

—

C3

L11

—

330

331

332

333

931.98

881.98

831.98

781.98

4,054.5

4,156.5

4,054.5

4,156.5

B2

G8

PIO0_56

PIO0_57

A2

A1

C4

H10

334

335

731.98

681.98

4,054.5

4,156.5

PIO0_58

PIO0_59

—

E5

H9

336

337

631.98

581.98

4,054.5

4,156.5

Lattice Semiconductor Corporation

(2.42, 30-MAR-2011)

www.latticesemi.com

97

iCE65 Ultra Low-Power mobileFPGA^™Family

Electrical Characteristics

All parameter limits are specified under worst-case supply voltage, temperature, and processing conditions.

Absolute Maximum Ratings

Stresses beyond those listed under Table 47 may cause permanent damage to the device. These are stress ratings

only; functional operation of the device at these or any other conditions beyond those listed under the

Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended

periods of time adversely affects device reliability.

Table 47: Absolute Maximum Ratings

Symbol

Description

Min

Max

Units

VCC

Core supply Voltage

–0.5

1.42

V

VPP_2V5

VPP_FAST

VCCIO_0

VCCIO_1

VCCIO_2

SPI_VCC

VCCIO_3

VPP_2V5 NVCM programming and operating supply

Optional fast NVCM programming supply

I/O bank supply voltage (I/O Banks 0, 1, and 2 plus SPI

interface)

–0.5

4.00

I/O Bank 3 supply voltage

–0.5

–1.0

iCE65L01: 4.00

iCE65L04/08: 3.6

V

VIN_0

VIN_1

VIN_2

VIN_SPI

VIN_3

VIN_VREF

IOUT

Voltage applied to PIO pin within a specific I/O bank (I/O

Banks 0, 1, and 2 plus SPI interface)

5.5

Voltage applied to PIO pin within I/O Bank 3

–0.5

iCE65L01: 4.00

iCE65L04/08: 3.6

V

DC output current per pin

Junction temperature

Storage temperature, no bias

—

–55

–65

20

125

150

mA

°C

T_J

T_STG

Recommended Operating Conditions

Table 48: Recommended Operating Conditions

Minimum

0.95

Nominal

1.00

1.20

Maximum Units

Symbol

VCC

Description

Core supply voltage

–L: Ultra-Low Power mode

1.05

1.26

V

–L: Low Power

1.14

–T: High Performance

Release from Power-on Reset

Configure from NVCM

NVCM programming

VPP_2V5

VPP_2V5 NVCM

programming and operating

supply

1.30

2.30

—

3.47

3.00

V

VPP_FAST

SPI_VCC

VCCIO_0

VCCIO_1

VCCIO_2

VCCIO_3

SPI_VCC

Optional fast NVCM programming supply

SPI interface supply voltage

Leave unconnected in application

1.71

3.14

—

3.30

3.47

V

I/O standards, all banks*

LVCMOS33

Non-standard voltage:

in between 2.5V and 3.3V

use LVCMOS25 in iCEcube2

LVCMOS25, LVDS

LVCMOS18, SubLVDS

LVCMOS15

Nominal

-5%

2.5< Nominal Nominal

V

<3.3

+5%

2.38

1.71

1.43

2.38

1.71

0

2.50

1.80

1.50

2.50

1.80

—

2.63

1.89

1.58

2.63

1.89

70

V

VCCIO_3

T_A

I/O standards only available

in iCE65L04/08 I/O Bank 3*

SSTL2

SSTL18

MDDR

V

Ambient temperature

Commercial (C)

Industrial (I)

°C

–40

10

—

85

T_PROG

NVCM programming temperature

25

30

NOTE:

VPP_FAST is only used for fast production programming. Leave floating or unconnected in application. When the iCE65

device is active, VPP_2V5 must be connected to a valid voltage.

(2.42, 30-MAR-2012)

Lattice Semiconductor Corporation

98

www.latticesemi.com

I/O Characteristics

Table 49: PIO Pin Electrical Characteristics

Symbol

Description

Conditions

Minimum

Nominal

Maximum Units

I_l

Input pin

leakage current

I/O Bank 0, 1, 2

I/O Bank 3

V_IN= VCCIO_maxto 0 V

V_IN= VCCIO_max

±10

µA

I_OZ

Three-state I/O pin (Hi-Z) leakage

current

V_O= VCCIO_maxto 0 V

±10

µA

C_PIO

C_GBIN

PIO pin input capacitance

GBIN global buffer pin input

capacitance

6

pF

R_PULLUInternal PIO pull-up resistance

VCCIO = 3.3V

VCCIO = 2.5V

VCCIO = 1.8V

VCCIO = 1.5V

VCCIO = 1.2V

40

50

90

kΩ

mV

during configuration

P

V_HYST

Input hysteresis

VCCIO = 1.5V to 3.3V

50

NOTE: All characteristics are characterized and may or may not be tested on each pin on each device.

Single-ended I/O Characteristics

Table 50: I/O Characteristics (I/O Banks 0, 1, 2 and SPI only) (I/O Bank 3 iCE65L01 only)

Nominal I/O

Bank Supply

Voltage

3.3V

Output Current at

Voltage (mA)

Input Voltage (V)

Output Voltage (V)

I/O Standard

LVCMOS33

LVCMOS25

LVCMOS18

I_OH

V_IL

V_IH

V_OL

0.4

V_OH

2.40

2.00

1.40

I_OL

0.80

0.70

2.00

1.70

8

6

4

8

6

4

2.5V

1.8V

35% VCCIO 65% VCCIO

Not supported

LVCMOS15

1.5V

0.4

1.20

2

Use I/O Bank 3

Table 51: I/O Characteristics (I/O Bank 3 and iCE65L04/08 only)

mA at

Voltage

I_OL.I_OH

I/O Attribute

Name

Input Voltage (V)

Output Voltage (V)

Supply

Voltage

I/O Standard

LVCMOS33

Max. V_IL

Min. V_IH

Max. V_OL

Min. V_OH

SL_LVCMOS33_8

SB_LVCMOS25_16

SB_LVCMOS25_12

SB_LVCMOS25_8 *

SB_LVCMOS25_4

SB_LVCMOS18_10

SB_LVCMOS18_8

SB_LVCMOS18_4 *

SB_LVCMOS18_2

SB_LVCMOS15_4

SB_LVCMOS15_2 *

SB_MDDR10

SB_MDDR8

SB_MDDR4 *

SB_MDDR2

SB_SSTL2_CLASS_2

SB_SSTL2_CLASS_1

SB_SSTL18_FULL

SB_SSTL18_HALF

3.3V

0.80

2.20

0.4

2.40

±8

±16

±12

±8

±4

±10

±8

±4

±2

±4

±2

LVCMOS25

2.5V

0.70

1.70

0.4

2.00

LVCMOS18

LVCMOS15

MDDR

35% VCCIO

65% VCCIO

VCCIO–0.45

75% VCCIO

VCCIO–0.45

VTT+0.430

1.8V

1.5V

1.8V

0.4

25% VCCIO

0.4

±10

±8

±4

±2

SSTL2 (Class 2)

SSTL2 (Class 1)

SSTL18 (Full)

SSTL18 (Half)

NOTES:

0.35

0.54

0.28

±16.2

±8.1

±13.4

±6.7

VREF–0.180

VREF–0.125

VREF+0.180

VREF+0.125

2.5V

1.8V

VTT+0.280

VTT+0.475

VTT–0.475

SSTL2 and SSTL18 I/O standards require the VREF input pin, which is only available on the CB284 package and die-based products.

Lattice Semiconductor Corporation

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99

iCE65 Ultra Low-Power mobileFPGA^™Family

Differential Inputs

Figure 50: Differential Input Specifications

VCCIO_3

DPxxB

Differential

Input common mode voltage

input voltage

V_{IN_B}

50%

V_ID

V_{IN_A}

DPxxA

V_ICM

iC65 Differential

Input

GND

Input common mode voltage:

VCCIO_ꢁ

2

V_ICꢀ

=

ꢀꢁ

ꢂꢃꢄ

Differential input voltage:

V_ID=|V_{IN_B}ꢂV_{IN_A}

|

Table 52: Recommended Operating Conditions for Differential Inputs

VCCIO_3 (V)

V_ID(mV)

V_ICM(V)

I/O

Standard

Min

Nom

Max

Min

Nom

Max

Min

Nom

Max

VCCIOꢅꢆ

LVDS

2.38

2.50

1.80

2.63

250

350

150

450

ꢇ ꢈꢉꢆꢈ

ꢊ ꢈꢉꢆꢈ

2

VCCIOꢅꢆ

SubLVDS

1.71

1.89

100

200

ꢇ ꢈꢉꢋꢌ

ꢊ ꢈꢉꢋꢌ

2

Differential Outputs

Figure 51: Differential Output Specifications

VCCIO_x

Differential

1%

R_P

Output common mode voltage

output voltage

R_S

V_{OUT_B}

50%

V_OD

V_{OUT_A}

V_OCM

iC65 Differential

Output Pair

GND

Output common mode voltage:

Differential output voltage:

VCCIO_x

2

V_OCꢀ

=

ꢀꢁ_ꢍꢃꢄ

V_OD=|V_{OUT_B}ꢂV_{OUT_A}

|

Table 53: Recommended Operating Conditions for Differential Outputs

Ω

VCCIO_x (V)

V_OD(mV)

V_OCM(V)

Nom

I/O

Standard

Min

Nom

Max

Min

Nom

Max

Min

Max

R_S

R_P

VCCIO

2

VCCIO

LVDS

2.38

1.71

2.50

2.63

1.89

150

140

300

350

150

400

ꢇ ꢈꢉꢎꢌ

ꢇ ꢈꢉꢎꢈ

ꢊ ꢈꢉꢎꢌ

ꢊ ꢈꢉꢎꢈ

2

VCCIO

2

VCCIO

2

VCCIO

2

SubLVDS

1.80

270

120

100

200

(2.42, 30-MAR-2012)

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I/O Banks 0, 1, 2 and SPI Bank Characteristic Curves

Figure 52: Typical LVCMOS Output Low Characteristics (I/O Banks 0, 1, 2, and SPI)

50

40

30

20

10

0

VCCIO= 3.3V

VCCIO= 2.5V

VCCIO= 1.8V

VCCIO= 1.5V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

V_OL( V )

Figure 53: Typical LVCMOS Output High Characteristics (I/O Banks 0, 1, 2, and SPI)

0

VCCIO= 1.5V

-10

-20

1.8V

VCCIO= 2.5V

-30

-40

-50

-60

-70

2.5V

VCCIO= 1.8V

VCCIO= 3.3V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

V_OH( V )

Figure 54: Input with Internal Pull-Up Resistor Enabled (I/O Banks 0, 1, 2, and SPI)

0

-10

VCCIO= 1.8V

-20

-30

-40

VCCIO= 2.5V

-50

-60

-70

-80

-90

VCCIO= 3.3V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

V_IN(Volts)

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101

iCE65 Ultra Low-Power mobileFPGA^™Family

AC Timing Guidelines

The following examples provide some guidelines of device performance. The actual performance depends on the

specific application and how it is physically implemented in the iCE65 FPGA using the Lattice iCEcube software.

The following guidelines assume typical conditions (VCC = 1.0 V or 1.2 V as specified, temperature = 25 ˚C). Apply

derating factors using the iCEcube timing analyzer to adjust to other operating regimes.

Programmable Logic Block (PLB) Timing

Table 54 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths

shown in Figure 55 and Figure 56.

Figure 55 PLB Sequential Timing Circuit

PAD

PIO

DFF

PAD

PIO

D

Q

LUT4

Logic Cell

GBIN

GBUF

Figure 56 PLB Combinational Timing Circuit

PAD

PIO

LUT4

Logic Cell

Table 54: Typical Programmable Logic Block (PLB) Timing

Device: iCE65

Power/Speed Grade

L01

–T

L04, L08

–L

–T

Nominal VCC 1.2 V 1.0 V 1.2 V 1.2 V

Typ.

Description

Symbol

F_TOGGLE

t_CKO

From

To

Units

MHz

ns

Sequential Logic Paths

Flip-flop toggle frequency. DFF flip-flop output fed back to

LUT4 input with 4-input XOR, clocked on same clock edge.

GBIN

input

DFF

clock

input

GBIN

input

GBIN

input

PIO

256

5.4

224

256

8.7

256

7.1

Logic cell flip-flop (DFF) clock-to-output time, measured

from the DFF CLK input to PIO output, including

interconnect delay.

16.5

output

Global Buffer Input (GBIN) delay, though Global Buffer

(GBUF) clock network to clock input on the logic cell DFF

flip-flop.

t_GBCKLC

DFF

clock

input

GBIN

input

2.2

7.3

3.8

2.7

ns

Minimum setup time on PIO input, through LUT4, to DFF

flip-flop D-input before active clock edge on the GBIN

input, including interconnect delay.

Minimum hold time on PIO input, through LUT4, to DFF

flip-flop D-input after active clock edge on the GBIN input,

including interconnect delay.

t_SULI

t_HDLI

PIO

input

1.0

0

4.0

0

2.1

0

1.2

0

ns

GBIN

input

PIO

input

Combinational Logic Paths

Asynchronous delay from PIO input pad to adjacent PLB

interconnect.

t_LUT4IN

t_ILO

PIO

input

LUT4

input output

LUT4 PIO

output output

LUT4

input

LUT4

2.6

0.6

4.9

9.8

1.9

5.2

1.0

8.4

3.3

0.6

6.6

ns

Logic cell LUT4 combinational logic propagation delay,

regardless of logic complexity from input to output.

Asynchronous delay from adjacent PLB interconnect

to PIO output pad.

t_LUT4IN

16.0

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Programmable Input/Output (PIO) Block

Table 55 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths

shown in Figure 57 and Figure 58. The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The

iCEcube development software reports timing adjustments for other I/O standards.

Figure 57: Programmable I/O (PIO) Pad-to-Pad Timing Circuit

PAD

PIO

Figure 58: Programmable I/O (PIO) Sequential Timing Circuit

PAD

PIO

INFF

OUTFF

D

Q

D

Q

GBIN

GBUF

Table 55: Typical Programmable Input/Output (PIO) Timing (LVCMOS25)

Device: iCE65

Power/Speed Grad

L01

–T

L04, L08

–L

–T

Nominal VCC 1.2 V

1.0 V

Typ.

1.2 V

Typ.

1.2 V

Typ.

Description

Synchronous Output Paths

Units

Symbol

t_OCKO

From

To

Typ.

OUTFF

clock

input

Delay from clock input on OUTFF output flip-

flop to PIO output pad.

PIO

output

4.7

2.1

13.8

7.3

3.8

5.6

2.6

ns

OUTFF

clock

input

Global Buffer Input (GBIN) delay, though

Global Buffer (GBUF) clock network to clock

input on the PIO OUTFF output flip-flop.

t_GBCKIO

GBIN

input

ns

Synchronous Input Paths

Setup time on PIO input pin to INFF input flip-

flop before active clock edge on GBIN input,

including interconnect delay.

t_SUPDIN

PIO

input

GBIN

input

0

ns

Hold time on PIO input to INFF input flip-flop

after active clock edge on the GBIN input,

including interconnect delay.

t_HDPDIN

GBIN

input

PIO

input

2.7

7.1

3.6

2.8

Pad to Pad

Inter-

Asynchronous delay from PIO input pad to

t_PADIN

t_PADO

PIO

input

Inter-

connect

2.5

4.5

9.5

5.0

7.7

3.2

6.2

ns

connect adjacent interconnect.

Asynchronous delay from adjacent

interconnect to PIO output pad including

interconnect delay.

PIO

output

14.6

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103

iCE65 Ultra Low-Power mobileFPGA^™Family

RAM4K Block

Table 56 provides timing information for the logic in a RAM4K block, which includes the paths shown in Figure 59.

Figure 59: RAM4K Timing Circuit

PAD

PIO

WDATA

RDATA

RAM4K

RAM Block

(256x16)

GBIN

GBUF

WCLK

RCLK

Table 56: Typical RAM4K Block Timing

Device: iCE65

Power/Speed Grade

Nominal VCC

L01

–T

1.2 V

Typ.

L04, L08

–L

1.2 V

Typ.

–L

1.0 V

Typ.

–T

1.2 V

Typ.

Symbol From

To

Description

Units

Write Setup/Hold Time

Minimum write data setup time on PIO

inputs before active clock edge on GBIN

input, include interconnect delay.

Minimum write data hold time on PIO

inputs after active clock edge on GBIN

input, including interconnect delay.

t_SUWD

PIO

input

GBIN

input

0.6

0

3.1

1.7

0

0.8

0

ns

t_HDWD

GBIN

input

PIO

input

0

ns

Read Clock-Output-Time

Clock-to-output delay from RCLK input

pin, through RAM4K RDATA output flip-

flop to PIO output pad, including

interconnect delay.

Global Buffer Input (GBIN) delay, though

Global Buffer (GBUF) clock network to

the RCLK clock input.

t_CKORD

RCLK

clock

input

PIO

output

5.6

2.1

17.1

7.3

9.1

3.8

7.3

2.6

ns

t_GBCKRM

GBIN

input

RCLK

clock

input

Write and Read Clock Characteristics

WCLK

RCLK

WCLK

RCLK

Write clock High time

t_RMWCKH

t_RMWCKL

t_RMWCYC

F_WMAX

0.54

0.63

1.27

256

1.14

1.32

2.64

256

0.54

0.63

1.27

256

0.54

0.63

1.27

256

ns

Write clock Low time

Write clock cycle time

Sustained write clock frequency

MHz

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Internal Configuration Oscillator Frequency

Table 57 shows the operating frequency for the iCE65’s internal configuration oscillator.

Table 57: Internal Oscillator Frequency

Frequency (MHz)

Oscillator

Mode

Symbol

f_OSCD

Min.

Max.

Description

Default

4.0

6.8

Default oscillator frequency. Slow enough to safely operate

with any SPI serial PROM.

f_OSCL

f_OSCH

Low

Frequency

High

Frequency

Off

14

21

0

21

31

0

Supported by most SPI serial Flash PROMs

Supported by some high-speed SPI serial Flash PROMs

Oscillator turned off by default after configuration to save

power.

Configuration Timing

Table 58 shows the maximum time to configure an iCE65 device, by oscillator mode. The calculations use the

slowest frequency for a given oscillator mode from Table 57 and the maximum configuration bitstream size from

Table 1 which includes full RAM4K block initialization. The configuration bitstream selects the desired oscillator

mode based on the performance of the configuration data source.

Table 58: Maximum SPI Master or NVCM Configuration Timing by Oscillator Mode

Symbol

Description

Device

Default

Low Freq.

High Freq.

Units

t_CONFIGL

Time from when

iCE65L01

iCE65L04

iCE65L08

53

25

55

11

25

50

ms

minimum Power-on

Reset (POR) threshold is

reached until user

application starts.

115

230

110

Table 59 provides timing for the CRESET_B and CDONE pins.

Table 59: General Configuration Timing

All Grades

Symbol

t_{CRESET_B}

From

CREST_B

To

CREST_B

Description

Minimum CRESET_B Low pulse width required to restart

configuration, from falling edge to rising edge

Min.

200

Max.

—

Units

ns

CDONE

High

PIO pins Number of configuration clock cycles after CDONE goes

Clock

cycles

t_{DONE_IO}

—

49

active

High before the PIO pins are activated.

SPI Peripheral Mode (Clock = SPI_SCK, cycles measured

rising-edge to rising-edge)

Depends on

SPI_SCK frequency

NVCM or SPI Master Mode by internal

oscillator frequency setting (Clock =

internal oscillator)

Default

Low

High

µs

7.20

2.34

1.59

12.25

3.50

2.33

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iCE65 Ultra Low-Power mobileFPGA^™Family

Table 60 provides various timing specifications for the SPI peripheral mode interface.

Table 60: SPI Peripheral Mode Timing

All Grades

Min. Max.

Symbol

t_{CR_SCK}

From

To

Description

Units

µs

CRESET_B

SPI_SCK Minimum time from a rising edge on CRESET_B until

the first SPI write operation, first SPI_SCK. During

this time, the iCE65 FPGA is clearing its internal

configuration memory

SPI_SCK Setup time on SPI_SI before the rising SPI_SCK clock edge

SPI_SI Hold time on SPI_SI after the rising SPI_SCK clock edge

—

iC65L01

iC65L04

iC65L08

800

1200

12

20

40

1

SPI_SI

SPI_SCK

t_SUSPISI

t_HDSPISI

t_SPISCKH

t_SPISCKL

t_SPISCKCYC

F_{SPI_SCK}

—

1,000

25

ns

SPI_SCK SPI_SCK SPI_SCK clock High time

SPI_SCK SPI_SCK SPI_SCK clock Low time

SPI_SCK SPI_SCK SPI_SCK clock period*

SPI_SCK SPI_SCK Sustained SPI_SCK clock frequency*

MHz

* = Applies after sending the synchronization pattern.

Power Consumption Characteristics

Core Power

Table 61 shows the power consumed on the internal VCC supply rail when the device is filled with 16-bit binary

counters, measured with a 32.768 kHz and at 32.0 MHz. Low power (-L) at 1.0 V operation and high-performance

(-T) version at 1.2V operation is provided.

Table 61: VCC Power Consumption for Device Filled with 16-Bit Binary Counters

iCE65L01

iCE65L04

iCE65L08

Units

Symbol Description

VCC

1.0V

1.2V

1.0V

1.2V

1.0V

1.2V

Max.

Grade

–L

–T

–L

–T

Typical

12

19

15

23

3

26

43

31

50

7

54

90

62

100

14

17

I_CC0K

I_CC32K

I_CC32M

f =0,

µA

f ≤ ꢁ2.768

kHz

f = 32.0

MHz

–L

–T

mA

4

8

I/O Power

Table 62 provides the static current by I/O bank. The typical current for I/O Banks 0, 1, 2 and the SPI bank is not

measurable within the accuracy of the test environment. The PIOs in I/O Bank 3 use different circuitry and dissipate

a small amount of static current.

Table 62: I/O Bank Static Current (f = 0 MHz)

Symbol

I_{CCO_0}

I_{CCO_1}

I_{CCO_2}

I_{CCO_3}

Description

Typical

« 1

Max

Units

µA

I/O Bank 0

I/O Bank 1

I/O Bank 2

I/O Bank 3

Static current consumption per I/O bank.

f = 0 MHz. No PIO pull-up resistors

enabled. All inputs grounded. All

outputs driving Low.

iCE65L01: « 1

iCE65L04/08: 1.2

« 1

I_{CCO_SPI}

SPI Bank

µA

NOTE: The typical static current for I/O Banks 0, 1, 2, and the SPI bank is less than the accuracy of the device tester.

Power Estimator

To estimate the power consumption for a specific application, please download and use the iCE65 Power Estimator

Spreadsheet our use the power estimator built into the iCEcube software.

 iCE65 Power Estimator Spreadsheet

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Notes

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iCE65 Ultra Low-Power mobileFPGA^™Family

Revision History

Version

2.42

2.41

2.4

Date

Description

Changed company name. Updated Table 1

Added VQ100 marking for NVCM programming.

Added L01 CB121 package Figure 39. Added note “else VCCIO_1 draws current” to JTAG

inputs TCK, TDI and TMS do not have the input pull-up resistor and must be tied off to

GND when unused, Table 32. Input pin leakage current Table 49 split by bank. QN84

package drawing, Figure 35, added note “underside metal is at ground potential”,

increased thermal resistance. Added Marking Format and Thermal resistance to CB81

Packag Mechanical Drawing Figure 33. Added coplanarity specification to VQ100 Package

Mechanical Drawing Figure 37

30-MAR-2012

1-AUG-2011

13-MAY-2011

18-OCT-2010

12-OCT-2010

2.3

2.2.3

Added L01 CB81 and L08 CB132 packages.

Changed Figure 29: Application Processor Waveforms for SPI Peripheral Mode

Configuration Process and Table 60 from 300 µs CRESET_B to 800 µs for iCE65L01/04

and 1200 µs for iCE65L08.

8-OCT-2010

5-OCT-2010

2.2.2

2.2.1

Added iCE65L04 marking specification to Figure 47 CB196 Package Mechanical Drawing.

Changed FSPI_SCK from 0.125 MHz to 1 MHz in SPI Peripheral Configuration Interface

and in Table 60.

6-AUG-2010

26-MAY-2010

15-MAR-2010

2.2

2.1.1

2.1

Programmable Interconnect section removed.

Switched labels on Figure 53 LVCMOS Output High, VCCIO = 1.8V with VCCIO = 2.5V.

Added JTAG unused input tie off guideline. Added marking specification and thermal

characteristics to package drawings. Added production datasheet for iCE65L01 with

timing update, including QN84, VQ100 and CB132. Added NVCM shut-off on SPI

configuration. Added non-standard VCCIO operating conditions. Increased the minimum

voltage supply specification for LVCMOS33 to 3.14V in Table 48.

12-NOV-2009

2.0.1

2.0

Recommended Operation Conditions, Table 47, replaced junction with ambient.

14-SEPT-2009 Finalized production data sheet for iCE65L04 and iCE65L08. Improved SubLVDS input specification

V_ICMin Table 52. CS63 and CC72 packages removed and placed in iCE DiCE KGD, Known Good Die

datasheet. Added “IBIS Models for I/O Banks 0, 1, 2 and the SPI Bank”. Added “Printed Circuit

Board Layout Information”.

1.5.1

1.5

13-JUL-2009

20-JUN-2009

Updated the text in “SPI PROM Requirements” section. ꢀinor label change in Figure 48.

Updated timing information and added –T high-speed device option (affected Figure 2, Table 48,

Table 54, Table 55, Table 56, and Table 61). Added support for 3.3V LVCMOS I/Os in I/O Bank 3

(affected Figure 7, Table 5, Table 7, Table 8, Table 47, Table 48, and Table 51). Added a section

about the SPI Peripheral Configuration Interface and timing in Table 60. Added a warning that a

Warm Boot operation can only jump to another configuration image that has Warm Boot disabled.

Updated configuration image size and configuration time for the iCE65L02 in Table 27 and Table 58.

Reduced the minimum voltage supply specification for LVCMOS33 to 2.7V in Table 48. Added

information about which power rails can be disconnected without effecting the Power-On Reset

(POR) circuit and clarified description of VPP_2V5 pin in Table 36. Added I/O characterization

curves (Figure 52, Figure 53, and Figure 54). Minor changes to Figure 20 and Figure 21. Changed

timing per Figures 54-58 and Tables 55-57.

1.4.4

1.4.3

25-MAR-2009

9-MAR-2009

Clarified the voltage requirements for the VPP_2V5 pin in Table 36 and notes under Table 48.

Removed volatile-only (-V) product offering from Figure 2. Corrected NC on ball V22, removed it

for ball T22 on CB284 package (Figure 48).

1.4.2

1.4.1

27-FEB-2009

24-FEB-2009

Updated Table 14, Table 23, Table 26, Table 30, Table 33, Table 35, and Table 46. Updated I/O

Bank 3 information in Table 7 and Table 48.

Based on characterization data, reduced 32KHz operating current by 40% in Table 1, Table 61, and

Figure 1. Corrected that SSTL18 standards require VREF pin in Table 7. Correct ball numbers for

GBIN4/GBIN5 for CS110 package.

1.4

9-FEB-2009

Added footprint and pinout information for the VQ100 Very-thin Quad Flat Package. Added footprint for

iCE65L08 in CB196 (Figure 46) and added Table 43 showing the differences between the ‘L04 and ‘L08 in the

CB196 package. Unified the package footprint nomenclature in the Package and Pinout Information section.

Added note to Global Buffer Inputs that the differential clock direct input is not available on the CB132 package.

Added tables showing the ball/pin number for various control functions, by package (Table 14, Table 23, Table

26, Table 30, and Table 33). Corrected the GBIN/GBUF designations. GBIN4 and GBIN5 were swapped as were

GBIN6 and GBIN7. This change affected all pinout tables and footprint diagrams. Updated and corrected

“Differential Global Buffer Input.” Tested and corrected the clock-enable and reset connections between global

buffers and various resources (Table 11, Table 12, and Table 13). Added “Automatic Global Buffer Insertion,

Manual Insertion.” Added “Die Cross Reference” section. Improved industrial temperature range by lowering

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minimum temperature to –40°C in Figure 2 and Table 48. Added NVCM programming temperature to Table 48.

Added footprint and pinout information for the CS110 Wafer-Level Chip-Scale Ball Grid Array. Clarified that the

CB196 footprint shown is for the iCE65L04; the iCE65L08 footprint for the CB196 package is similar but

different. Added updated information on Differential Inputs and Outputs, including support for SubLVDS.

Updated Electrical Characteristics and AC Timing Guidelines sections. Added support for the LVCMOS15 I/O

standard. Corrected the diagram showing the direct differential clock input, Figure 16. Updated the number of

I/Os by package in Table 34. Updated company address. Other minor updates throughout.

Updated I/O Bank 3 characteristics in Table 7 and Table 51. Corrected label in Figure 14. Added JTAG

configuration to Table 20. Added pull-up resistor information in Table 22 and Figure 21. Added “Internal Device

Reset” section. Updated internal oscillator performance in and Table 57. Updated configuration timing in Table

58 based on new oscillator timing. Completely reorganized the “Package and Pinout Information” section.

Added information on CS63 and CB196 packages. Updated information on VPP_2V5 signal in Table 36.

Reduced package height for CB1ꢁ2 and CB284 packages to 1.0 mm. Added “Differential Inputs” and

“Differential Outputs” sections.

1.3

1.2

17-DEC-2008

11-OCT-2008

1.1

1.0

4-SEPT-2008

31-MAY-2008

Updated package roadmap (Table 2) and updated ordering codes (Figure 2). Updated Figure 7. Updated Figure

24. Added CS63 package footprint (Figure 36), pinout (Table 39) and Package.

Initial public release.

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iCE65 Ultra Low-Power mobileFPGA^™Family

www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective

holders. The specifications and information herein are subject to change without notice.

Lattice Semiconductor Corporation

5555 N.E. Moore Court

Hillsboro, Oregon 97124-6421

United States of America

Tel: +1 503 268 8000

Fax: +1 503 268 8347

cumentation services by Prevailing Technology, Inc. (www.prevailing-technology.com)

)

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型号：	ICE65L01F-LCB81C
厂家：	LATTICE SEMICONDUCTOR
描述：	Field Programmable Gate Array, 1280-Cell, CMOS, PBGA81 栅可编程逻辑
文件：	总110页 (文件大小：2299K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICE65L01F-LCB81C [LATTICE]

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