ICE65L08F-LCC72C [LATTICE]
Field Programmable Gate Array, 7680-Cell, CMOS, PBGA72,;
| 型号： | ICE65L08F-LCC72C |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | Field Programmable Gate Array, 7680-Cell, CMOS, PBGA72, 栅 可编程逻辑 |
| 文件： | 总32页 (文件大小：1731K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R
DiePlus™ Advantage
SiliconBlue
January 25, 2011 (2.0.6)
Data Sheet
DiePlus Advantage is SiliconBlue’s focused program to
provide designers with an optimal device mounting
solution for mobile handheld applications. This data
sheet provides detailed information regarding DiePlus
Advantage devices. For general family information,
please refer to the iCE65 mobileFPGA Device Family
Data Sheet.
Figure 1: iCE65L04 Known Good Die
Smallest possible board footprint
Mechanical package structures such as lead frames and
heat slugs are eliminated, as well plastic encapsulation
Available as known-good die (KGD) or bumped die
using wafer-level chip scale (WLCSP) packaging
technology
Lowest cost solution, eliminating costs
associated with encapsulated packages
Up to 90% less weight than equivalent
pin-count packaged devices
Very flexible delivery options for KGD
Whole wafer uncut, with wafer map
Cut wafer mounted on blue tape, with wafer map
KGD on tape and reel
WLCSP technology eliminates need for KGD
manufacturing flow
Selectable die thickness: 4.0, 10.0, or 31.0 mil
Devices use standard PCB reflow mounting methods
Eliminates need for wire bonding and lead frames
Available in 0.4mm pitch (CS) or 0.5mm pitch (CC)
WLCSP redistribution layer technology exhibits
excellent electrical characteristics
No signal integrity issues often associated with mounting
substrates
Laser etched custom marking available for
WLCSP devices
Robust electrical connections minimize resistance and
inductance
Full wafer custom programming of Non-Volatile
Configuration Memory (NVCM) available
Table 1: iCE65 Ultra Low-Power Programmable Logic DiePlus Family Summary
iCE65L01
iCE65L04
iCE65P04
iCE65L08
Logic Cells (LUT + Flip-Flop)
RAM4K Memory Blocks
Maximum Programmable I/O Pins
Maximum Differential Input Pairs
Size
1,280
3,520
3,520
7,680
16
20
20
32
95
176
20
174
20
222
25
0
2.5mm x 2.5mm
3.9mm x 3.2mm
3.8mm x 3.1mm
4.8mm x 4.4mm
Wafer Level Chip Scale
Package, WLCSP
Package
I/O Pins
I/O Pads
CS36
25(0)
95(0)
CS63
48(4)
CC72
55(8)
Known Good Die, KGD
176(20)
174(20)
222(25)
© 2007-2011 by SiliconBlue Technologies Corporation. All rights reserved.
www.SiliconBlueTech.com
(2.0.6, 25-JAN-2011)
1
iCE65 Ultra Low-Power DiePlus™ Family
Industry’s most advanced packages
These devices can then be mounted to printed circuit
boards just like standard ball grid array devices. By
using WLCSP, iCE65 mobileFPGAs offer very small
footprints and eliminate standard plastic package costs.
The iCE65 mobileFPGA family uses the most
advanced packaging technology available,
including Wafer Level Chip Scale Packaging
(WLCSP).
WLCSP
technology
adds
a
redistribution layer to a bare die, allowing standard
mounting balls to be added.
s
by Prevailing Technology, Inc. ( www.pre vailing-technology.com)
(2.0.6, 25-JAN-2011)
2
SiliconBlue Technologies Corporation
www.SiliconBlueTech.com
SiliconBlue
Ordering Information: WLCSP
Figure 2 describes the iCE65 ordering codes for all packaged components. See the separate iCE DiCE data sheets
when ordering die-based products.
Figure 2: iCE65 Ordering Codes (WLCSP)
iCE65 L04 F -L CB 132 C
Logic Cells (x1,000)
Temperature Range
C= Commercial
L01, L04, P04, L08
(TA = 0° to 70° Celsius)
I= Industrial
Configuration Memory
(TA = –40° to 85° Celsius)
F= NVCM + reprogrammable
Package Leads
Package Style
Power Consumption/
Speed
-L= Low power
-T= High speed
CC= wafer level chip-scale package (0.5 mm pitch)
CS= wafer level chip-scale package (0.4 mm pitch)
iCE65 devices offer two power consumption, speed options. Standard products (“-L” ordering code) have low
standby and dynamic power consumption. The “-T” provides higher-speed logic.
Similarly, iCE65 devices are available in two operating temperature ranges, one for typical commercial applications,
the other with an extended temperature range for industrial and telecommunications applications. The ordering
code also specifies the device package option.
iCE65 Footprint Diagram Conventions
Figure 3 illustrates the naming conventions used in the following footprint diagrams. Each PIO pin is associated
with an I/O Bank. PIO pins in I/O Bank 3 that support differential inputs are also numbered by differential input
pair.
Figure 3: CS and CC Package Footprint Diagram Conventions
Ball column number
1
Ball row number
Single-ended PIO Numbering
PIO0
A PIO0
Ball number A1
I/O bank number
PIO3/
DP07A
Differential Input Pair Numbering
DifferentialB
PIO0/
DP07A
Input Pair
Indicators
Pair pin polarity
Pair number
PIO3/
DP07B
C
Differential Pair
Dot indicates unconnected pin
for iCE65L04 in CB284 package
SiliconBlue Technologies Corporation
www.SiliconBlueTech.com
(2.0.6, 25-JAN-2011)
3
iCE65 Ultra Low-Power DiePlus™ Family
CS36 Wafer-Level Chip-Scale Ball Grid Array
The CS36 package is a wafer-level chip-scale package with 0.4 mm ball pitch. The iCE65L01 is the only device
available in this package.
Footprint Diagram
Figure 4 shows the footprint diagram for the 36-ball wafer-level chip-scale package (CS36). Figure 3 shows the
conventions used in the diagram. Compared to other packages, the footprint may appear left-right flipped because
the balls on the CS36 package are mounted on the same side as the active circuitry. In other packages, the balls are
mounted on the opposite side from the active circuitry.
See Table 2 for a complete, detailed pinout for the 36-ball wafer-level chip-scale BGA packages.
The signal pins are also grouped into the four I/O Banks and the SPI interface.
Figure 4: iC65L01 CS36 Wafer-Level Chip-Scale BGA Footprint (Top View)
I/O Bank 0
1
VPP_
2V5
2
3
GBIN0/
PIO0
4
VCCIO_0
5
6
A
B
C
D
E
A
B
C
PIO0
VCC PIO0
GBIN3/GBIN2/GBIN1/
PIO1 PIO1 PIO0
PIO0 PIO0 PIO3
VCCIO_1
VCCIO_3
PIO1 GND PIO0 PIO3
GBIN6/GBIN7/ D
SPI_VCC
PIO1 PIO1 GND
PIO3 PIO3
GBIN4/
PIO2
PIOS/ PIOS/ CRESET_B
E
F
PIO3 PIO3
SPI_SCK
SI
GBIN5/
PIO2
PIOS/ PIOS/ CDONE
VCCIO_2
F
PIO3
SPI_SS_B
SO
1
2
3
4
5
6
SPI Bank
I/O Bank 2
Pinout Table
Table 2 provides a detailed pinout table for the CS36 package. Pins are generally arranged by I/O bank, then by ball
function. The CS36 package has no JTAG pins. The CS36 has no Cold Boot, CBSEL0 and CBSEL1 pins.
Table 2: iCE65L01 CS36 Wafer-level Chip-scale BGA Pinout Table
Ball Function
GBIN0/PIO0
GBIN1/PIO0
PIO0
Ball Number
Type
GBIN
GBIN
PIO
PIO
PIO
PIO
PIO
VCCIO
Bank
A3
B3
A2
A6
B4
B5
C4
A4
0
0
0
0
0
0
0
0
PIO0
PIO0
PIO0
PIO0
VCCIO_0
GBIN2/PIO1
GBIN3/PIO1
PIO1
PIO1
PIO1
VCCIO_1
B2
B1
C2
D2
D3
C1
GBIN
GBIN
PIO
PIO
PIO
1
1
1
1
1
1
VCCIO
(2.0.6, 25-JAN-2011)
4
SiliconBlue Technologies Corporation
www.SiliconBlueTech.com
SiliconBlue
Ball Function
Ball Number
Type
Bank
CDONE
F3
E3
E4
F4
F5
CONFIG
CONFIG
GBIN
GBIN
VCCIO
2
2
2
2
2
CRESET_B
GBIN4/PIO2
GBIN5/PIO2
VCCIO_2
GBIN7/PIO3
D6
GBIN
3
GBIN6/PIO3
PIO3
D5
B6
GBIN
PIO
3
3
PIO3
PIO3
C5
E5
PIO
PIO
3
3
PIO3
PIO3
E6
F6
C6
PIO
PIO
3
3
3
VCCIO_3
VCCIO
PIOS/SPI_SO
PIOS/SPI_SI
PIOS/SPI_SCK
PIOS/SPI_SS_B
SPI_VCC
F2
E2
E1
F1
D1
PIO/SPI
PIO/SPI
PIO/SPI
PIO/SPI
SPI
SPI
SPI
SPI
SPI
SPI
GND
GND
C3
D4
GND
GND
GND
GND
VCC
A5
A1
VCC
VPP
VCC
VPP
VPP_2V5
SiliconBlue Technologies Corporation
(2.0.6, 25-JAN-2011)
www.SiliconBlueTech.com
5
iCE65 Ultra Low-Power DiePlus™ Family
Package Mechanical Drawing
Figure 5: CS36 Package Mechanical Drawing
Mark
pin 1
dot
SBT
iCE65L01F-T
CS36C
NXXXXXX
YYWW
Top Side
Coating
Top Marking Format
Line Content
Description
Logo
1
Logo
iCE65L01F Part number
2
-T
Power/Speed
Package type
Engineering
CS36C
ENG
3
4
5
NXXXXXXX Lot Number
YYWW Date Code
Thermal Resistance
Junction-to-Ambient
θ
0 LFM
42
(⁰C/W)
200 LFM
34
0.801
0.840
0.879
(2.0.6, 25-JAN-2011)
6
SiliconBlue Technologies Corporation
www.SiliconBlueTech.com
SiliconBlue
CS63 Wafer-Level Chip-Scale Ball Grid Array
The CS63 package is a wafer-level chip-scale package with 0.4 mm ball pitch. The iCE65L04 is the only device
available in this package.
Footprint Diagram
Figure 6 shows the footprint diagram for the 63-ball wafer-level chip-scale package (CS63). Figure 3 shows the
conventions used in the diagram. Compared to other packages, the footprint may appear left-right flipped because
the balls on the CS63 package are mounted on the same side as the active circuitry. In other packages, the balls are
mounted on the opposite side from the active circuitry.
See Table 3 for a complete, detailed pinout for the 63-ball wafer-level chip-scale BGA packages.
The signal pins are also grouped into the four I/O Banks and the SPI interface.
Figure 6: iC65L04 CS63 Wafer-Level Chip-Scale BGA Footprint (Top View)
I/O Bank 0
1
2
3
4
5
6
7
8
9
GBIN1/
PIO0
VPP_
FAST
VCCIO_0
A PIO1
GND
PIO0 PIO0 PIO0 PIO0 A
GBIN0/
PIO0
VPP_
2V5
VCCIO_3
B PIO1
PIO0 PIO0
PIO0 PIO0
VCC B
GBIN2/ GBIN3/
PIO1 PIO1
PIO3/ PIO3/
DP00A DP00B
C
PIO1 PIO1 PIO0 PIO0 PIO0
PIO2/
C
D
E
F
GBIN7/
PIO3/
DP01B
PIO3/
DP01A
D PIO1 GND PIO1 PIO1
PIO2 GND
CBSEL0
GBIN6/
PIO3/
DP02A
PIO3/
DP03B
PIO2/
VCCIO_1
E
VCC PIO1
PIO2 PIO2 PIO2
CBSEL1
PIO3/ PIO3/
DP03A DP02B
PIOS/ PIOS/ CRESET_B
F PIO1
GND PIO2 PIO2
SPI_SCK SPI_SI
GBIN4/ GBIN5/
VCCIO_2
PIO2 PIO2
PIOS/ PIOS/
SPI_VCC
CDONE
G
PIO2 PIO2 G
SPI_SS_B SPI_SO
1
2
3
4
5
6
7
8
9
SPI Bank
I/O Bank 2
Pinout Table
Table 3 provides a detailed pinout table for the CS63 package. Pins are generally arranged by I/O bank, then by ball
function. The table also highlights the differential I/O pairs in I/O Bank 3. The CS63 package has no JTAG pins.
Table 3: iCE65L04 CS63 Wafer-level Chip-scale BGA Pinout Table
Ball Function
GBIN0/PIO0
GBIN1/PIO0
PIO0
Ball Number
Type
GBIN
GBIN
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
Bank
0
0
0
0
0
0
0
0
0
0
0
0
B5
A5
A6
A7
A8
A9
B3
B4
B6
B7
C5
C6
C7
PIO0
PIO0
PIO0
PIO0
PIO0
PIO0
PIO0
PIO0
PIO0
PIO0
0
SiliconBlue Technologies Corporation
(2.0.6, 25-JAN-2011)
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7
iCE65 Ultra Low-Power DiePlus™ Family
Ball Function
VCCIO_0
Ball Number
A4
Type
VCCIO
Bank
0
GBIN2/PIO1
GBIN3/PIO1
PIO1
C1
C2
A1
B1
C3
C4
D1
D3
D4
E3
F1
E1
GBIN
GBIN
PIO
PIO
PIO
PIO
PIO
PIO
PIO
1
1
1
1
1
1
1
1
1
1
1
1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO
PIO
VCCIO
VCCIO_1
CDONE
CRESET_B
GBIN4/PIO2
GBIN5/PIO2
PIO2
G4
F4
G5
G6
D6
E5
E6
E7
F6
F7
G8
G9
D5
E4
G7
CONFIG
CONFIG
GBIN
GBIN
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
VCCIO
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PIO2
PIO2
PIO2
PIO2
PIO2
PIO2
PIO2
PIO2/CBSEL0
PIO2/CBSEL1
VCCIO_2
PIO3/DP00A
PIO3/DP00B
C8
C9
DPIO
DPIO
3
3
PIO3/DP01A
GBIN7/PIO3/DP01B
D8
D9
DPIO
DPIO/GBIN
3
3
GBIN6/PIO3/DP02A
PIO3/DP02B
E9
F9
DPIO/GBIN
DPIO
3
3
PIO3/DP03B
PIO3/DP03A
E8
F8
DPIO
DPIO
3
3
VCCIO_3
B8
VCCIO
3
PIOS/SPI_SO
PIOS/SPI_SI
PIOS/SPI_SCK
PIOS/SPI_SS_B
SPI_VCC
G3
F3
F2
G2
G1
PIO/SPI
PIO/SPI
PIO/SPI
PIO/SPI
SPI
SPI
SPI
SPI
SPI
SPI
GND
GND
GND
GND
A3
D2
D7
F5
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
B9
E2
VCC
VCC
VCC
VCC
VPP_2V5
VPP_FAST
B2
A2
VPP
VPP
VPP
VPP
(2.0.6, 25-JAN-2011)
8
SiliconBlue Technologies Corporation
www.SiliconBlueTech.com
SiliconBlue
Package Mechanical Drawing
Figure 7: CS63 Package Mechanical Drawing
CS63: 3.83 x 3.16 mm, 63-ball, 0.4 mm ball-pitch, wafer-level chip-scale
ball grid array
Top View
Bottom View
Mark pin 1 dot
A
B
C
D
E
F
A
B
C
D
E
F
SILICONBLUE
iCE65L04F-T
CS63C
NXXXXXXX
YYWW
G
G
b
e
E1
E
Side View
Description
Symbol
Min.
Nominal
Max.
Units
Number of Ball Columns
Number of Ball Rows
Number of Signal Balls
X
Y
9
Columns
Rows
7
n
E
63
Balls
X
Y
3.81
3.14
—
3.83
3.16
0.40
0.25
3.20
2.40
0.840
0.20
3.85
3.18
—
Body Size
D
Ball Pitch
e
Ball Diameter
b
0.23
—
0.29
—
mm
X
Y
E1
D1
A
Edge Ball Center to
Center
—
—
Package Height
Stand Off
0.801
0.17
0.879
0.23
A1
SiliconBlue Technologies Corporation
(2.0.6, 25-JAN-2011)
www.SiliconBlueTech.com
9
iCE65 Ultra Low-Power DiePlus™ Family
CC72 Wafer-Level Chip-Scale Ball Grid Array
The CC72 package is wafer-level chip-scale ball grid array with 0.5 mm ball pitch. The iCE65L08 is the only device
available in this package.
Footprint Diagram
Figure 8 shows the footprint diagram for the 72-ball wafer-level chip-scale package (CC72). Figure 3 shows the
conventions used in the diagram. Compared to other packages, the footprint may appear left-right flipped because
the balls on the CC72 package are mounted on the same side as the active circuitry. In other packages, the balls are
mounted on the opposite side from the active circuitry.
See Table 4 for a complete, detailed pinout for the 72-ball wafer-level chip-scale BGA packages.
The signal pins are also grouped into the four I/O Banks and the SPI interface.
Figure 8: iC65L08 CC72 Wafer-Level Chip-Scale BGA Footprint (Top View)
I/O Bank 0
1
2
3
4
5
6
7
8
9
GBIN1/
PIO0
VPP_ VPP_
2V5 FAST
VCCIO_0
A
PIO0 GND
VCC
PIO0 PIO0 A
GBIN0/
PIO0
PIO3/ PIO3/
PIO0 PIO0 B
B PIO1 PIO1 PIO0 PIO0
DP00B DP00A
PIO3/ PIO3/
DP01A DP01B
VCCIO_3
C PIO1 PIO1 PIO1 PIO1 PIO0 PIO0
C
GBIN3/ GBIN2/
PIO1 PIO1
PIO3/ PIO3/
DP02A DP02B
PIO3/
DP03B
D
PIO1 PIO1 PIO1
GND D
VCC E
GND F
GBIN7/
PIO3/
PIO3/
PIO3/
DP03A
VCCIO_1
E GND
PIO1 PIO1 PIO2
PIO2/ PIO2/
DP04A
DP04B
GBIN6/
PIO3/
DP05A
PIO3/
DP05B
F VCC PIO1 PIO1
PIO2
PIO2
CBSEL1 CBSEL0
GBIN5/
PIO2
PIO3/ PIO3/ PIO3/
DP06B DP06A DP07A
PIOS/ PIOS/ CRESET_B
G PIO1
G
H
SPI_SCK SPI_SI
GBIN4/
PIO2
PIO3/
GND PIO2
DP07B
PIOS/ PIOS/
SPI_VCC
VCCIO_2
CDONE
H
SPI_SS_B SPI_SO
1
2
3
4
5
6
7
8
9
SPI Bank
I/O Bank 2
Pinout Table
Table 4 provides a detailed pinout table for the CC72 package. Pins are generally arranged by I/O bank, then by ball
function. The table also highlights the differential I/O pairs in I/O Bank 3. The CC72 package has no JTAG pins.
Table 4: iCE65L08 CC72 Wafer-level Chip-scale BGA Pinout Table
Ball Function
GBIN0/PIO0
GBIN1/PIO0
PIO0
Ball Number
Type
GBIN
GBIN
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
Bank
B5
A5
A3
A8
A9
B3
B4
B6
B7
C5
C6
0
0
0
0
0
0
0
0
0
0
0
PIO0
PIO0
PIO0
PIO0
PIO0
PIO0
PIO0
PIO0
(2.0.6, 25-JAN-2011)
10
SiliconBlue Technologies Corporation
www.SiliconBlueTech.com
SiliconBlue
Ball Function
VCCIO_0
Ball Number
A7
Type
VCCIO
Bank
0
GBIN2/PIO1
GBIN3/PIO1
PIO1
D2
D1
B1
B2
C1
C2
C3
C4
D3
D4
D5
E3
E4
F2
F3
G1
E2
GBIN
GBIN
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
VCCIO
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
PIO1
VCCIO_1
CDONE
CRESET_B
GBIN4/PIO2
GBIN5/PIO2
PIO2
H4
G4
H5
G5
E5
F6
G6
H8
F5
F4
H6
CONFIG
CONFIG
GBIN
GBIN
PIO
PIO
PIO
PIO
PIO
2
2
2
2
2
2
2
2
2
2
2
PIO2
PIO2
PIO2
PIO2/CBSEL0
PIO2/CBSEL1
VCCIO_2
PIO
VCCIO
PIO3/DP00A
PIO3/DP00B
PIO3/DP01A
PIO3/DP01B
B9
B8
C7
C8
DPIO
DPIO
DPIO
DPIO
3
3
3
3
PIO3/DP02A
PIO3/DP02B
D7
D8
DPIO
DPIO
3
3
PIO3/DP03A
PIO3/DP03B
D6
E6
DPIO
DPIO
3
3
PIO3/DP04A
GBIN7/PIO3/DP04B
E8
E7
DPIO
DPIO/GBIN
3
3
GBIN6/PIO3/DP05A
PIO3/DP05B
F8
F7
DPIO/GBIN
DPIO
3
3
PIO3/DP06A
PIO3/DP06B
G8
G7
DPIO
DPIO
3
3
PIO3/DP07A
PIO3/DP07B
G9
H9
DPIO
DPIO
3
3
VCCIO_3
C9
VCCIO
3
PIOS/SPI_SO
PIOS/SPI_SI
PIOS/SPI_SCK
H3
G3
G2
PIO/SPI
PIO/SPI
PIO/SPI
SPI
SPI
SPI
SiliconBlue Technologies Corporation
(2.0.6, 25-JAN-2011)
www.SiliconBlueTech.com
11
iCE65 Ultra Low-Power DiePlus™ Family
Ball Function
PIOS/SPI_SS_B
SPI_VCC
Ball Number
Type
PIO/SPI
SPI
Bank
SPI
SPI
H2
H1
GND
GND
GND
GND
GND
A4
D9
E1
F9
H7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
A6
E9
F1
VCC
VCC
VCC
VCC
VCC
VCC
VPP_2V5
VPP_FAST
A1
A2
VPP
VPP
VPP
VPP
Package Mechanical Drawing
Figure 9: iCE65L08 CC72 Package Mechanical Drawing
CC72: 4.3 x 4.7 mm, 72-ball, 0.5 mm ball-pitch, wafer-level chip-scale
ball grid array
Top View
Bottom View
A
B
C
D
E
F
A
B
C
D
E
F
Mark
pin 1
dot
SILICONBLUE
iCE65L08F-T
CC72C
NXXXXXXX
YYWW
G
H
G
H
Top Side
Coating
b
e
E1
E
Side View
Top Marking Format
Description
Symbol
Min.
Nominal
Max.
Units
Line Content
Description
Logo
1
Logo
Number of Ball Columns
Number of Ball Rows
Number of Signal Balls
X
Y
9
8
Columns
Rows
iCE65L08F Part number
2
n
E
72
Balls
-T
Power/Speed
Package type
Engineering
X
Y
—
—
—
4.69
4.274
0.50
4.71
4.29
—
CC72C
ENG
Body Size
3
D
Ball Pitch
e
4
5
NXXXXXXX Lot Number
YYWW Date Code
Ball Diameter
b
0.29
—
0.30
4.00
0.35
—
mm
X
Y
E1
D1
A
Edge Ball Center to
Center
—
3.50
—
Thermal Resistance
Package Height
Stand Off
0.841
—
0.880
0.25
0.919
—
Junction-to-Ambient
A1
θ (⁰C/W)
0 LFM
37
200 LFM
30
(2.0.6, 25-JAN-2011)
12
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Ordering Information: KGD
Figure 10 describes the iCE65 Known Good Die product ordering codes.
Figure 10: iCE65 Ordering Codes (KGD)
iCE65L 08 F -L DI 310 C W
Logic Cells (x1,000)
Delivery Option
02, 04, 08
W= Whole wafer, uncut, with wafer map
B= Whole wafer, sawed, with wafer map,
mounted on blue tape
Configuration Memory
T= Tape and reel, good die only
F= Nonvolatile Configuration Memory
(NVCM) + Reprogrammable
Temperature Range
C= Commercial
I= Industrial
Power Consumption
-L= Low power (1.2V or 1.0V operation)
-T= High speed (1.2V operation)
Wafer/Die Thickness
040 = 4.0 mil
Die-based Product
100 = 10.0 mil
310 = 31.0 mil
Delivery Option
Thick
- ness
W
B
T
4.0
10.0
31.0
No
No
Yes
Yes
Yes
No
Yes
Yes
No
iCE65 FPGA devices are available with two power consumption options. Standard products (“-L” ordering code)
have low standby and dynamic power consumption. The “-T” option provides higher-speed logic.
Please consult the die distributor or SiliconBlue Technologies Corporation before ordering to verify long-term
availability of these die products.
Specifications discussed herein are subject to change without notice. This product is sold “as is” and is delivered
with no guarantees or warranties, expressed or implied.
Die Samples
Die samples are available through an authorized SiliconBlue sales representative. Samples are provided untested,
but with expected high yield (about 90%).
Functional Specifications
Please refer to the packaged product data sheet found on the SiliconBlue Technologies web site
(www.siliconbluetech.com) for functional and parametric specifications. The specifications are provided for
reference only.
Physical Specifications
Table 5 lists key physical characteristics of each iCE65 die.
Table 5: KDG Physical Specifications
Feature
Dimension
Wafer Diameter
Wafer Thickness
300 mm (12 inches)
31 mil, 10 mil, or 4 mil, specified in order code, Figure 10
iCE65L01
iCE65L04
iCE65P04
iCE65L08
2,490 μm x 2,520 µm
3,870 μm x 3,200 µm
3,830 μm x 3,080 µm
4,810 µm x 4,394 µm
160 µm
Die Size (stepping interval)
Scribe Width Along X-Axis (dsw_X)
Scribe Width Along Y-Axis (dsw_Y)
Bond Pad Size (min)
160 µm
61 µm x 75 µm
58 µm x 72 µm
35 µm
Passivation Openings (min)
Minimum Bond Pad Pitch (staggered)
SiliconBlue Technologies Corporation
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13
iCE65 Ultra Low-Power DiePlus™ Family
Die Attach Guidelines
Bond Wires: Connect die pads using gold wire. The preferred bond wire diameter is 0.7 mil, not to exceed 0.9
mil.
Preferred Attachments: If possible within the application, attach all pads. If not possible, follow the following
connection guidelines.
VCC Connections: A minimum of four VCC attachments are required. The four VCC attachments must use two
sets of adjacent VCC pads. Pads 259 and 260 in Table 9 are an example of an adjacent pad set.
VCCIO Connections: A minimum of two VCCIO pads must be attached in every I/O bank used.
A minimum of two VCCIO_2 pads in I/O Bank 2 must be attached. The VCCIO_2 connection is required to trigger the
Power-On Reset (POR) circuit.
A minimum of two VCCIO_1 pads in I/O Bank 1 must be attached unless the TRST_B pad is attached to ground, disabling
the JTAG interface.
If the JTAG interface is disabled, then ground the JTAG input pins,
attached to pads TDI, TMS, TCK and TRST_B to ground.
If the JTAG interface is disabled, then leave the JTAG output pin unconnected, pad TDO.
If I/O Bank 3 is used in the application, connect the following pads as directed.
Attach a minimum of two VCC (Post) pads.
Attach a minimum of two GND (Post) pads.
Attach a minimum of one VCCIO_3 (Level) pads and electrically connect to other attached VCCIO_3 pads.
Attach at least one VCC (Pre) pad.
Attach at least one GND (Pre) pad
The VCC (Core) and GND (Core) pads may be left unconnected if the required numbers of VCC and GND
pads are attached elsewhere.
If using an SSTL I/O standard, attach VREF to a valid reference voltage as described in the iCE65 family
data sheet and attach GND (Shield) pad to ground.
If not using an STTL I/O standard, attach VREF to ground.
If unused in the application, the VCCIO connections to I/O Bank 0 and I/O Bank 3 can be left disconnected or attached to
ground.
VPP_2V5 Connection: The VPP_2V5 pad must attach to a valid voltage, as described in the iCE65 family data
sheet, to trigger the Power-On Reset (POR) circuit.
VCC_SPI Connection: At least one VCC_SPI pad must attach to a valid voltage, as described in the iCE65
family data sheet, to trigger the Power-On Reset (POR) circuit.
GND Connections: A minimum of two GND connections must be attached in every I/O bank used.
(2.0.6, 25-JAN-2011)
14
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Physical Specifications: iCE65L01
Figure 11 shows the physical outlines of iCE65L01 die on a wafer, including pad orientation and physical origin. The
bond pad identification and coordinates are provided in Table 6. Table 5 lists key physical characteristics of each
iCE65 die.
Figure 11: iCE65L01 Die Outline
dsw_X
dsw_Y
130
I/O
Bank
0
1
3
5
7
129
127
2
4
128
126
124
125
123
121
119
117
115
113
111
109
107
105
103
101
99
97
95
93
91
89
87
6
8
10
122
120
118
116
114
112
110
108
106
104
102
100
98
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
SiliconBlue
Technologies
iCE65L01 Die
96
94
92
90
88
I/O Bank 2 /
SPI Bank
+y
+X
Coordinates listed relative to this origin
NOTE: Not to scale.
SiliconBlue Technologies Corporation
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15
iCE65 Ultra Low-Power DiePlus™ Family
Bond Pad Listing and Coordinates: iCE68L01
Table 6 lists each of the 166 bonding pads on an iCE65L01 device. The pad number begins in the upper left corner of
the die, as shown in Figure 11, and increments in a counter-clockwise direction around the perimeter of the die. .
Each bonding pad is identified. Signal names are color-coded by function. I/O pairs are grouped together with a
thick surrounding box. These pairs in I/O Bank 3 represent an optional differential input or output. In all other
banks, these pairs represent an optional differential output. The pad coordinates are measured relative to the
origin, in the lower left corner of the die.
Table 6: iCE65L01 Bond Pad Listing and Coordinates (Relative to Origin)
From Origin
X (µm) Y (µm)
From Origin
Pad
1
2
Signal Name
Pad
40
Signal Name
PIO3_21
X (µm)
139.5
Y (µm)
515.13
PIO3_00
PIO3_01
37.5
139.5
2060.13
2010.13
41
42
PIO3_22
PIO3_23
37.5
139.5
465.13
415.13
3
4
PIO3_02
PIO3_03
37.5
139.5
1960.13
1910.13
43
44
PIO3_24
PIO3_25
37.5
139.5
365.13
315.13
5
6
7
8
GND
GND
VCCIO_3
VCCIO_3
37.5
139.5
37.5
1860.13
1810.13
1760.13
1710.13
45
46
PIO2_00
PIO2_01
139.5
37.5
307
357
139.5
47
48
PIO2_02
PIO2_03
139.5
37.5
407
457
9
10
PIO3_04
PIO3_05
37.5
139.5
1660.13
1610.13
49
50
PIO2_04
PIO2_05
139.5
37.5
507
557
11
12
PIO3_06
PIO3_07
37.5
139.5
1575.13
1540.13
51
52
PIO2_06
PIO2_07
139.5
37.5
607
657
13
14
PIO3_08
PIO3_09
37.5
139.5
1505.13
1470.13
53
54
VCCIO_2
VCCIO_2
139.5
37.5
692
727
15
16
GND
GND
37.5
139.5
1435.13
1400.13
55
56
PIO2_08
PIO2_09
139.5
37.5
762
797
17
18
VCC
VCC
37.5
139.5
1365.13
1330.13
57
58
GND
GND
139.5
37.5
832
867
19
20
PIO3_10
GBIN7/PIO3_11
37.5
139.5
1295.13
1260.13
59
60
GBIN4/PIO2_10
PIO2_11
139.5
37.5
902
937
21
22
23
VCCIO_3
VCCIO_3
VCCIO_3
37.5
139.5
37.5
1225.13
1190.13
1155.13
61
62
VCC
VCC
139.5
37.5
972
1007
GBIN6/PIO3_12
PIO3_13
24
25
139.5
37.5
1120.13
1085.13
63
64
GBIN5/PIO2_12
PIO2_13
139.5
37.5
1042
1077
26
27
GND
GND
139.5
37.5
1050.13
1015.13
65
66
VCCIO_2
VCCIO_2
139.5
37.5
1112
1147
28
29
PIO3_14
PIO3_15
139.5
37.5
980.13
945.13
67
68
VCCIO_2
PIO2_14
139.5
37.5
1182
1217
30
31
PIO3_16
PIO3_17
139.5
37.5
910.13
875.13
69
70
GND
GND
139.5
37.5
1252
1287
32
VCC
139.5
840.13
71
72
GND
NC
139.5
37.5
1322
1357
33
34
PIO3_18
PIO3_19
37.5
139.5
805.13
770.13
73
74
PIO2_15
PIO2_16
139.5
37.5
1392
1427
35
36
37
38
VCCIO_3
VCCIO_3
GND
37.5
139.5
37.5
735.13
700.13
665.13
615.13
75
76
77
PIO2_17
PIO2_18/CBSEL0
PIO2_19/CBSEL1
139.5
37.5
139.5
1462
1497
1532
GND
139.5
39
PIO3_20
37.5
565.13
(2.0.6, 25-JAN-2011)
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From Origin
X (µm) Y (µm)
From Origin
Pad
Signal Name
Pad
Signal Name
X (µm)
Y (µm)
78
79
CDONE
CRESET_B
37.5
139.5
1602
1652
124
125
PIO1_19
PIO1_20
2270.5
2372.5
1849.8
1899.8
126
127
128
129
130
VCCIO_1
VCCIO_1
GND
2270.5
2372.5
2270.5
2372.5
2270.5
1949.8
1999.8
2049.8
2099.8
2199.8
80
81
PIOS_00/SPI_SO
PIOS_01/SPI_SI
37.5
139.5
1702
1752
82
GND
37.5
1802
GND
83
84
PIOS_02/SPI_SCK
PIOS_03/SPI_SS_B
139.5
37.5
1852
1902
VPP_2V5
85
86
SPI_VCC
SPI_VCC_OP
139.5
37.5
1952
2002
131
132
133
VPP_FAST
VCC
1992
1884
1834
2300.5
2402.5
2300.5
87
88
89
90
91
TDI
TMS
TCK
TDO
TRST_B
2155
139.5
244.4
294.4
344.4
394.4
VCC
2372.5
2270.5
2372.5
2270.5
134
PIO0_00
1784
2402.5
135
136
PIO0_01
PIO0_02
1734
1684
2300.5
2402.5
137
138
PIO0_03
PIO0_04
1634
1584
2300.5
2402.5
92
93
PIO1_00
PIO1_01
2372.5
2270.5
444.4
494.4
139
140
PIO0_05
PIO0_06
1534
1499
2300.5
2402.5
94
95
PIO1_02
PIO1_03
2372.5
2270.5
544.4
594.4
141
142
GND
GND
1464
1429
2300.5
2402.5
96
97
GND
GND
2270.5
2372.5
679.4
714.4
143
144
PIO0_07
PIO0_08
1394
1359
2300.5
2402.5
98
99
PIO1_04
PIO1_05
2270.5
2372.5
749.4
784.4
145
146
PIO0_09
PIO0_10
1324
1289
2300.5
2402.5
100
101
VCCIO_1
VCCIO_1
2270.5
2372.5
819.4
854.4
147
148
VCCIO_0
VCCIO_0
1254
1219
2300.5
2402.5
102
103
PIO1_06
PIO1_07
2270.5
2372.5
889.4
924.4
149
150
GBIN1/PIO0_11
GBIN0/PIO0_12
1184
1149
2300.5
2402.5
104
105
106
VCC
VCC
GBIN3/PIO1_08
2270.5
2372.5
2270.5
959.4
994.4
1029.4
151
152
GND
GND
865
830
2300.5
2402.5
107
108
109
GBIN2/PIO1_09
GND
2372.5
2270.5
2372.5
1064.4
1259.4
1294.4
153
154
155
156
PIO0_13
VCCIO_0
VCCIO_0
PIO0_14
795
760
725
690
2300.5
2402.5
2300.5
2402.5
GND
110
111
PIO1_10
PIO1_11
2270.5
2372.5
1329.4
1364.4
157
158
PIO0_15
PIO0_16
655
620
2300.5
2402.5
112
113
PIO1_12
PIO1_13
2270.5
2372.5
1399.4
1434.4
159
160
PIO0_17
PIO0_18
585
535
2300.5
2402.5
114
PIO1_14
2270.5
1469.4
115
116
VCCIO_1
VCCIO_1
2372.5
2270.5
1504.4
1539.4
161
162
VCCIO_0
GND
760
435
2402.5
2402.5
117
118
PIO1_15
PIO1_16
2372.5
2270.5
1574.4
1609.4
163
164
PIO0_19
PIO0_20
385
335
2300.5
2402.5
119
120
121
GND
GND
GND
2372.5
2270.5
2372.5
1644.4
1679.4
1714.4
165
166
PIO0_21
PIO0_22
285
235
2300.5
2402.5
122
123
PIO1_17
PIO1_18
2270.5
2372.5
1749.4
1799.4
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17
iCE65 Ultra Low-Power DiePlus™ Family
Physical Specifications: iCE65L04
Figure 12 shows the physical outlines of iCE65L04 die on a wafer, including pad orientation and physical origin. The
bond pad identification and coordinates are provided in Table 7. Table 5 lists key physical characteristics of each
iCE65 die.
Figure 12: iCE65L04 Die Outline
dsw_X
dsw_Y
190
1
3
5
7
189
187
2
4
188
186
184
I/O Bank 0
185
183
181
179
177
175
6
8
10
182
180
178
176
174
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
173
171
169
167
165
163
161
159
157
155
153
151
149
147
145
143
141
139
137
135
172
170
168
166
164
162
160
158
156
154
152
150
148
146
144
142
140
138
136
SiliconBlue Technologies
iCE65L04 Die
134
132
130
57
59
61
58
60
62
133
131
129
I/O Bank 2 / SPI Bank
63
+y
128
64
+X
Coordinates listed relative to this origin
NOTE: Not to scale.
(2.0.6, 25-JAN-2011)
18
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Bond Pad Listing and Coordinates: iCE68L04
Table 7 lists each of the 254 bonding pads on an iCE65L04 device. The pad number begins in the upper left corner of
the die, as shown in Figure 12, and increments in a counter-clockwise direction around the perimeter of the die. .
Each bonding pad is identified. Signal names are color-coded by function. I/O pairs are grouped together with a
thick surrounding box. These pairs in I/O Bank 3 represent an optional differential input or output. In all other
banks, these pairs represent an optional differential output. The pad coordinates are measured relative to the
origin, in the lower left corner of the die.
Table 7: iCE65L04 Bond Pad Listing and Coordinates (Relative to Origin)
From Origin
From Origin
Pad
1
2
Signal Name
PIO3_00/DP00A
PIO3_01/DP00B
X (µm)
129.40
231.40
Y (µm)
2,687.75
2,642.74
Pad
39
40
41
42
Signal Name
VCCIO_3
VCCIO_3
GND
X (µm)
Y (µm)
1,277.75
1,242.74
1,207.75
1,172.74
129.40
231.40
129.40
231.40
3
4
PIO3_02/DP01A
PIO3_03/DP01B
129.40
231.40
2,597.75
2,552.74
GND
43
44
PIO3_24/DP12A
PIO3_25/DP12B
129.40
231.40
1,137.75
1,102.74
5
6
7
8
GND
GND
VCCIO_3
VCCIO_3
129.40
231.40
129.40
231.40
2,507.75
2,462.74
2,417.75
2,372.74
45
GND
129.40
1,067.75
46
47
PIO3_26/DP13A
PIO3_27/DP13B
231.40
129.40
1,032.74
997.75
9
10
PIO3_04/DP02A
PIO3_05/DP02B
129.40
231.40
2,327.75
2,292.74
48
49
PIO3_28/DP14A
PIO3_29/DP14B
231.40
129.40
962.74
927.75
11
12
PIO3_06/DP03A
PIO3_07/DP03B
129.40
231.40
2,257.75
2,222.74
50
51
PIO3_30/DP15A
PIO3_31/DP15B
231.40
129.40
892.74
857.75
13
VCC
129.40
2,187.75
52
VCC
231.40
822.74
14
15
PIO3_08/DP04A
PIO3_09/DP04B
231.40
129.40
2,152.74
2,117.75
53
54
PIO3_32/DP16A
PIO3_33/DP16B
129.40
231.40
787.75
752.74
16
17
PIO3_10/DP05A
PIO3_11/DP05B
231.40
129.40
2,082.74
2,047.75
55
56
57
58
VCCIO_3
VCCIO_3
GND
129.40
231.40
129.40
231.40
717.75
682.74
637.75
592.74
18
GND
231.40
2,012.74
19
20
PIO3_12/DP06A
PIO3_13/DP06B
129.40
231.40
1,977.75
1,942.74
GND
59
60
PIO3_34/DP17A
PIO3_35/DP17B
129.40
231.40
547.75
502.74
21
22
GND
GND
129.40
231.40
1,907.75
1,872.74
61
62
PIO3_36/DP18A
PIO3_37/DP18B
129.40
231.40
457.75
412.74
23
24
PIO3_14/DP07A
PIO3_15/DP07B
129.40
231.40
1,837.75
1,802.74
63
64
PIO3_38/DP19A
PIO3_39/DP19B
129.40
231.40
367.75
322.74
25
26
VCCIO_3
VCC
129.40
231.40
1,767.75
1,732.74
65
66
PIO2_00
PIO2_01
545.00
595.00
139.20
37.20
27
28
PIO3_16/DP08A
PIO3_17/DP08B
129.40
231.40
1,697.75
1,662.74
67
68
69
PIO2_02
GND
PIO2_03
645.00
695.00
745.00
139.20
37.20
139.20
29
30
PIO3_18/DP09A
GBIN7/PIO3_19/DP09B
129.40
231.40
1,627.75
1,592.74
31
32
33
VCCIO_3
VREF
GND
129.40
231.40
129.40
1,557.75
1,522.74
1,487.75
70
71
PIO2_04
PIO2_05
795.00
845.00
37.20
139.20
GBIN6/PIO3_20/DP10A
PIO3_21/DP10B
72
73
PIO2_06
PIO2_07
895.00
930.00
37.20
139.20
34
35
231.40
129.40
1,452.74
1,417.75
74
75
76
PIO2_08
VCCIO_2
PIO2_09
965.00
1,000.00
1,035.00
37.20
139.20
37.20
36
GND
231.40
1,382.74
37
38
PIO3_22/DP11A
PIO3_23/DP11B
129.40
231.40
1,347.75
1,312.74
77
PIO2_10
1,070.00
139.20
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19
iCE65 Ultra Low-Power DiePlus™ Family
From Origin
From Origin
Pad
78
79
Signal Name
GND
X (µm)
1,105.00
1,140.00
Y (µm)
37.20
139.20
Pad
125
126
Signal Name
PIOS_02/SPI_SCK
PIOS_03/SPI_SS_B
X (µm)
2,840.00
2,890.00
Y (µm)
139.20
37.20
PIO2_11
80
81
PIO2_12
PIO2_13
1,175.00
1,210.00
37.20
139.20
127
SPI_VCC
2,990.00
37.20
128
129
130
131
132
TDI
TMS
TCK
TDO
TRST_B
3,610.80
3,712.80
3,610.80
3,712.80
3,610.80
342.00
392.00
442.00
492.00
542.00
82
83
PIO2_14
PIO2_15
1,245.00
1,280.00
37.20
139.20
84
85
PIO2_16
PIO2_17
1,315.00
1,350.00
37.20
139.20
86
87
88
PIO2_18
GND
PIO2_19
1,385.00
1,420.00
1,455.00
37.20
139.20
37.20
133
134
PIO1_00
PIO1_01
3,712.80
3,610.80
592.00
642.00
135
136
PIO1_02
PIO1_03
3,712.80
3,610.80
692.00
727.00
89
90
91
PIO2_20
VCC
PIO2_21
1,490.00
1,525.00
1,560.00
139.20
37.20
139.20
137
138
GND
GND
3,712.80
3,610.80
762.00
797.00
92
93
PIO2_22
GBIN5/PIO2_23
1,595.00
1,630.00
37.20
139.20
139
140
PIO1_04
PIO1_05
3,712.80
3,610.80
832.00
867.00
94
95
GBIN4/PIO2_24
PIO2_25
1,665.00
1,700.00
37.20
139.20
141
142
VCCIO_1
VCCIO_1
3,712.80
3,610.80
902.00
937.00
96
VCCIO_2
1,735.00
37.20
143
144
PIO1_06
PIO1_07
3,712.80
3,610.80
972.00
1,007.00
97
98
PIO2_26
PIO2_27
1,770.00
1,805.00
139.20
37.20
145
146
PIO1_08
PIO1_09
3,712.80
3,610.80
1,042.00
1,077.00
99
GND
1,840.00
139.20
100
101
PIO2_28
PIO2_29
1,875.00
1,910.00
37.20
139.20
147
148
149
150
PIO1_10
VCC
VCC
PIO1_11
3,712.80
3,610.80
3,712.80
3,610.80
1,112.00
1,147.00
1,182.00
1,217.00
102
103
PIO2_30
PIO2_31
1,945.00
1,980.00
37.20
139.20
104
105
PIO2_32
PIO2_33
2,015.00
2,050.00
37.20
139.20
151
152
PIO1_12
PIO1_13
3,712.80
3,610.80
1,252.00
1,287.00
106
107
PIO2_34
PIO2_35
2,085.00
2,120.00
37.20
139.20
153
154
PIO1_14
PIO1_15
3,712.80
3,610.80
1,322.00
1,357.00
108
109
VCC
VCC
2,155.00
2,190.00
37.20
139.20
155
156
PIO1_16
PIO1_17
3,712.80
3,610.80
1,392.00
1,427.00
110
111
PIO2_36
PIO2_37
2,225.00
2,260.00
37.20
139.20
157
158
GND
GND
3,712.80
3,610.80
1,462.00
1,497.00
112
VCCIO_2
2,295.00
37.20
159
160
PIO1_18
GBIN3/PIO1_19
3,712.80
3,610.80
1,532.00
1,567.00
113
114
115
PIO2_38
GND
PIO2_39
2,330.00
2,365.00
2,400.00
139.20
37.20
139.20
161
162
GBIN2/PIO1_20
PIO1_21
3,712.80
3,610.80
1,602.00
1,637.00
116
117
PIO2_40
PIO2_41
2,435.00
2,470.00
37.20
139.20
163
164
VCCIO_1
VCCIO_1
3,712.80
3,610.80
1,672.00
1,707.00
118
119
PIO2_42/CBSEL0
PIO2_43/CBSEL1
2,505.00
2,540.00
37.20
139.20
165
166
PIO1_22
PIO1_23
3,712.80
3,610.80
1,742.00
1,777.00
120
121
CDONE
CRESET_B
2,575.00
2,625.00
37.20
139.20
167
168
PIO1_24
PIO1_25
3,712.80
3,610.80
1,812.00
1,847.00
169
170
PIO1_26
PIO1_27
3,712.80
3,610.80
1,882.00
1,917.00
122
123
PIOS_00/SPI_SO
PIOS_01/SPI_SI
2,690.00
2,740.00
37.20
139.20
171
GND
3,712.80
1,952.00
124
GND
2,790.00
37.20
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From Origin
From Origin
Pad
172
Signal Name
GND
X (µm)
3,610.80
Y (µm)
1,987.00
Pad
218
219
Signal Name
X (µm)
1,982.00
1,947.00
Y (µm)
2,860.80
2,962.80
PIO0_20
PIO0_21
173
174
PIO1_28
PIO1_29
3,712.80
3,610.80
2,022.00
2,057.00
220
221
PIO0_22
GBIN1/PIO0_23
1,912.00
1,877.00
2,860.80
2,962.80
175
176
PIO1_30
PIO1_31
3,712.80
3,610.80
2,092.00
2,127.00
222
223
GND
GND
1,842.00
1,807.00
2,860.80
2,962.80
177
178
VCC
VCC
3,712.80
3,610.80
2,162.00
2,197.00
224
225
GBIN0/PIO0_24
PIO0_25
1,772.00
1,737.00
2,860.80
2,962.80
179
180
PIO1_32
PIO1_33
3,712.80
3,610.80
2,232.00
2,267.00
226
227
PIO0_26
PIO0_27
1,702.00
1,667.00
2,860.80
2,962.80
181
182
VCCIO_1
VCCIO_1
3,712.80
3,610.80
2,302.00
2,337.00
228
229
VCC
VCC
1,632.00
1,597.00
2,860.80
2,962.80
183
184
PIO1_34
PIO1_35
3,712.80
3,610.80
2,377.00
2,427.00
230
231
PIO0_28
PIO0_29
1,562.00
1,527.00
2,860.80
2,962.80
185
GND
3,712.80
2,477.00
232
233
PIO0_30
PIO0_31
1,492.00
1,457.00
2,860.80
2,962.80
186
187
PIO1_36
PIO1_37
3,610.80
3,712.80
2,527.00
2,577.00
234
235
GND
GND
1,422.00
1,387.00
2,860.80
2,962.80
188
189
PIO1_38
PIO1_39
3,610.80
3,712.80
2,627.00
2,677.00
236
237
PIO0_32
PIO0_33
1,352.00
1,317.00
2,860.80
2,962.80
190
VPP_2V5
3,610.80
2,739.68
191
192
193
VPP_FAST
VCC
3,047.00
2,997.00
2,947.00
2,962.80
2,860.80
2,962.80
238
239
PIO0_34
PIO0_35
1,282.00
1,247.00
2,860.80
2,962.80
VCC
240
241
242
243
PIO0_36
VCCIO_0
VCCIO_0
PIO0_37
1,212.00
1,177.00
1,142.00
1,107.00
2,860.80
2,962.80
2,860.80
2,962.80
194
195
PIO0_00
PIO0_01
2,897.00
2,847.00
2,860.80
2,962.80
196
197
PIO0_02
PIO0_03
2,797.00
2,747.00
2,860.80
2,962.80
244
245
PIO0_38
PIO0_39
1,072.00
1,037.00
2,860.80
2,962.80
198
199
PIO0_04
PIO0_05
2,697.00
2,647.00
2,860.80
2,962.80
246
247
PIO0_40
PIO0_41
1,002.00
967.00
2,860.80
2,962.80
200
201
PIO0_06
PIO0_07
2,612.00
2,577.00
2,860.80
2,962.80
248
249
250
PIO0_42
GND
PIO0_43
917.00
867.00
817.00
2,860.80
2,962.80
2,860.80
202
203
GND
GND
2,542.00
2,507.00
2,860.80
2,962.80
251
252
PIO0_44
PIO0_45
767.00
717.00
2,962.80
2,860.80
204
205
PIO0_08
PIO0_09
2,472.00
2,437.00
2,860.80
2,962.80
253
254
PIO0_46
PIO0_47
667.00
617.00
2,962.80
2,860.80
206
207
PIO0_10
PIO0_11
2,402.00
2,367.00
2,860.80
2,962.80
208
209
PIO0_12
PIO0_13
2,332.00
2,297.00
2,860.80
2,962.80
210
211
PIO0_14
PIO0_15
2,262.00
2,227.00
2,860.80
2,962.80
212
213
VCCIO_0
VCCIO_0
2,192.00
2,157.00
2,860.80
2,962.80
214
215
PIO0_16
PIO0_17
2,122.00
2,087.00
2,860.80
2,962.80
216
217
PIO0_18
PIO0_19
2,052.00
2,017.00
2,860.80
2,962.80
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21
iCE65 Ultra Low-Power DiePlus™ Family
Physical Specifications: iCE65P04
Figure 13 shows the physical outlines of iCE65P04 die on a wafer, including pad orientation and physical origin. The
bond pad identification and coordinates are provided Table 8. Table 5 lists key physical characteristics of each
iCE65 die.
Figure 13: iCE65P04 Die Outline
dsw_X
dsw_Y
192
1
3
5
7
191
189
2
4
190
188
186
I/O Bank 0
187
185
183
181
179
177
6
8
10
184
182
180
178
176
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
175
173
171
169
167
165
163
161
159
157
155
153
151
149
147
145
143
141
139
137
174
172
170
168
166
164
162
160
158
156
154
152
150
148
146
144
142
140
138
SiliconBlue Technologies
iCE65P04 Die
136
134
132
57
59
61
58
60
62
135
133
131
I/O Bank 2 / SPI Bank
63
+y
130
64
+X
Coordinates listed relative to this origin
NOTE: Not to scale.
(2.0.6, 25-JAN-2011)
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SiliconBlue
Bond Pad Listing and Coordinates: iCE65P04
Table 8 lists each of the 256 bonding pads on an iCE65P04 device. The pad number begins in the upper left corner of
the die, as shown in Figure 13, and increments in a counter-clockwise direction around the perimeter of the die. .
Each bonding pad is identified. Signal names are color-coded by function. I/O pairs are grouped together with a
thick surrounding box. These pairs in I/O Bank 3 represent an optional differential input or output. In all other
banks, these pairs represent an optional differential output. The pad coordinates are measured relative to the
origin, in the lower left corner of the die.
Table 8: iCE65P04 Bond Pad Listing and Coordinates (Relative to Origin)
From Origin
From Origin
Pad
1
2
Signal Name
PIO3_00/DP00A
PIO3_01/DP00B
X (µm)
129.4
231.4
Y (µm)
2687.75
2642.74
Pad
39
40
41
42
Signal Name
VCCIO_3
VCCIO_3
GND
X (µm)
Y (µm)
1277.75
1242.74
1207.75
1172.74
129.4
231.4
129.4
231.4
3
4
PIO3_02/DP01A
PIO3_03/DP01B
129.4
231.4
2597.75
2552.74
GND
43
44
PIO3_24/DP12A
PIO3_25/DP12B
129.4
231.4
1137.75
1102.74
5
6
7
8
GND
GND
VCCIO_3
VCCIO_3
129.4
231.4
129.4
231.4
2507.75
2462.74
2417.75
2372.74
45
GND
129.4
1067.75
46
47
PIO3_26/DP13A
PIO3_27/DP13B
231.4
129.4
1032.74
997.75
9
10
PIO3_04/DP02A
PIO3_05/DP02B
129.4
231.4
2327.75
2292.74
48
49
PIO3_28/DP14A
PIO3_29/DP14B
231.4
129.4
962.74
927.75
11
12
PIO3_06/DP03A
PIO3_07/DP03B
129.4
231.4
2257.75
2222.74
50
51
PIO3_30/DP15A
PIO3_31/DP15B
231.4
129.4
892.74
857.75
13
VCC
129.4
2187.75
52
VCC
231.4
822.74
14
15
PIO3_08/DP04A
PIO3_09/DP04B
231.4
129.4
2152.74
2117.75
53
54
PIO3_32/DP16A
PIO3_33/DP16B
129.4
231.4
787.75
752.74
16
17
PIO3_10/DP05A
PIO3_11/DP05B
231.4
129.4
2082.74
2047.75
55
56
57
58
VCCIO_3
VCCIO_3
GND
129.4
231.4
129.4
231.4
717.75
682.74
637.75
592.74
18
GND
231.4
2012.74
19
20
PIO3_12/DP06A
PIO3_13/DP06B
129.4
231.4
1977.75
1942.74
GND
59
60
PIO3_34/DP17A
PIO3_35/DP17B
129.4
231.4
547.75
502.74
21
22
GND
GND
129.4
231.4
1907.75
1872.74
61
62
PIO3_36/DP18A
PIO3_37/DP18B
129.4
231.4
457.75
412.74
23
24
PIO3_14/DP07A
PIO3_15/DP07B
129.4
231.4
1837.75
1802.74
63
64
PIO3_38/DP19A
PIO3_39/DP19B
129.4
231.4
367.75
322.74
25
26
VCCIO_3
VCC
129.4
231.4
1767.75
1732.74
65
66
PIO2_00
PIO2_01
440
490
139.2
37.2
27
28
PIO3_16/DP08A
PIO3_17/DP08B
129.4
231.4
1697.75
1662.74
67
68
69
PIO2_02
GND
PIO2_03
540
590
640
139.2
37.2
139.2
29
30
PIO3_18/DP09A
GBIN7/PIO3_19/DP09B
129.4
231.4
1627.75
1592.74
31
32
33
VCCIO_3
VREF
GND
129.4
231.4
129.4
1557.75
1522.74
1487.75
70
71
PIO2_04
PIO2_05
690
740
37.2
139.2
GBIN6/PIO3_20/DP10A
PIO3_21/DP10B
72
73
PIO2_06
PIO2_07
790
825
37.2
139.2
34
35
231.4
129.4
1452.74
1417.75
74
75
76
PIO2_08
VCCIO_2
PIO2_09
860
895
930
37.2
139.2
37.2
36
GND
231.4
1382.74
37
38
PIO3_22/DP11A
PIO3_23/DP11B
129.4
231.4
1347.75
1312.74
77
PIO2_10
965
139.2
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iCE65 Ultra Low-Power DiePlus™ Family
From Origin
From Origin
Pad
78
Signal Name
GND
X (µm)
1000
Y (µm)
37.2
Pad
125
Signal Name
PIOS_01/SPI_SI
X (µm)
2740
Y (µm)
139.2
79
PIO2_11
1035
139.2
126
GND
2790
37.2
80
81
PIO2_12
PIO2_13
1070
1105
37.2
139.2
127
128
PIOS_02/SPI_SCK
PIOS_03/SPI_SS_B
2840
2890
139.2
37.2
82
83
PIO2_14
PIO2_15
1140
1175
37.2
139.2
129
SPI_VCC
2990
37.2
130
131
132
133
134
TDI
TMS
TCK
TDO
TRST_B
3,610.80
3,712.80
3,610.80
3,712.80
3,610.80
342.00
392.00
442.00
492.00
542.00
84
85
PIO2_16
PIO2_17
1210
1245
37.2
139.2
86
87
88
PIO2_18
GND
PIO2_19
1280
1315
1350
37.2
139.2
37.2
135
136
PIO1_00
PIO1_01
3,712.80
3,610.80
592.00
642.00
89
90
91
PIO2_20
VCC
PIO2_21
1385
1420
1455
139.2
37.2
139.2
137
138
PIO1_02
PIO1_03
3,712.80
3,610.80
692.00
727.00
92
93
PIO2_22
PLLGND
1490
1525
37.2
139
140
GND
GND
3,712.80
3,610.80
762.00
797.00
139.2
94
95
PLLVCC
GBIN5/PIO2_23
1595
1630
37.2
139.2
141
142
PIO1_04
PIO1_05
3,712.80
3,610.80
832.00
867.00
96
97
GBIN4/PIO2_24
PIO2_25
1665
1700
37.2
139.2
143
144
VCCIO_1
VCCIO_1
3,712.80
3,610.80
902.00
937.00
98
VCCIO_2
1735
37.2
145
146
PIO1_06
PIO1_07
3,712.80
3,610.80
972.00
1,007.00
99
100
PIO2_26
PIO2_27
1770
1805
139.2
37.2
147
148
PIO1_08
PIO1_09
3,712.80
3,610.80
1,042.00
1,077.00
101
GND
1840
139.2
102
103
PIO2_28
PIO2_29
1875
1910
37.2
139.2
149
150
151
152
PIO1_10
VCC
VCC
PIO1_11
3,712.80
3,610.80
3,712.80
3,610.80
1,112.00
1,147.00
1,182.00
1,217.00
104
105
PIO2_30
PIO2_31
1945
1980
37.2
139.2
153
154
PIO1_12
PIO1_13
3,712.80
3,610.80
1,252.00
1,287.00
106
107
PIO2_32
PIO2_33
2015
2050
37.2
139.2
155
156
PIO1_14
PIO1_15
3,712.80
3,610.80
1,322.00
1,357.00
108
109
PIO2_34
PIO2_35
2085
2120
37.2
139.2
157
158
PIO1_16
PIO1_17
3,712.80
3,610.80
1,392.00
1,427.00
110
111
VCC
VCC
2155
2190
37.2
139.2
159
160
GND
GND
3,712.80
3,610.80
1,462.00
1,497.00
112
113
PIO2_36
PIO2_37
2225
2260
37.2
139.2
161
162
PIO1_18
GBIN3/PIO1_19
3,712.80
3,610.80
1,532.00
1,567.00
114
VCCIO_2
2295
37.2
115
116
117
PIO2_38
GND
PIO2_39
2330
2365
2400
139.2
37.2
139.2
163
164
GBIN2/PIO1_20
PIO1_21
3,712.80
3,610.80
1,602.00
1,637.00
165
166
VCCIO_1
VCCIO_1
3,712.80
3,610.80
1,672.00
1,707.00
118
119
PIO2_40
PIO2_41
2435
2470
37.2
139.2
167
168
PIO1_22
PIO1_23
3,712.80
3,610.80
1,742.00
1,777.00
120
121
PIO2_42/CBSEL0
PIO2_43/CBSEL1
2505
2540
37.2
139.2
169
170
PIO1_24
PIO1_25
3,712.80
3,610.80
1,812.00
1,847.00
122
123
CDONE
CRESET_B
2575
2625
37.2
139.2
171
PIO1_26
3,712.80
1,882.00
124
PIOS_00/SPI_SO
2690
37.2
(2.0.6, 25-JAN-2011)
24
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From Origin
From Origin
Pad
172
Signal Name
PIO1_27
X (µm)
3,610.80
Y (µm)
1,917.00
Pad
218
219
Signal Name
X (µm)
2,052.00
2,017.00
Y (µm)
2,860.80
2,962.80
PIO0_18
PIO0_19
173
174
GND
GND
3,712.80
3,610.80
1,952.00
1,987.00
220
221
PIO0_20
PIO0_21
1,982.00
1,947.00
2,860.80
2,962.80
175
176
PIO1_28
PIO1_29
3,712.80
3,610.80
2,022.00
2,057.00
222
223
PIO0_22
GBIN1/PIO0_23
1,912.00
1,877.00
2,860.80
2,962.80
177
178
PIO1_30
PIO1_31
3,712.80
3,610.80
2,092.00
2,127.00
224
225
GND
GND
1,842.00
1,807.00
2,860.80
2,962.80
179
180
VCC
VCC
3,712.80
3,610.80
2,162.00
2,197.00
226
227
GBIN0/PIO0_24
PIO0_25
1,772.00
1,737.00
2,860.80
2,962.80
181
182
PIO1_32
PIO1_33
3,712.80
3,610.80
2,232.00
2,267.00
228
229
PIO0_26
PIO0_27
1,702.00
1,667.00
2,860.80
2,962.80
183
184
VCCIO_1
VCCIO_1
3,712.80
3,610.80
2,302.00
2,337.00
230
231
VCC
VCC
1,632.00
1,597.00
2,860.80
2,962.80
185
186
PIO1_34
PIO1_35
3,712.80
3,610.80
2,377.00
2,427.00
232
233
PIO0_28
PIO0_29
1,562.00
1,527.00
2,860.80
2,962.80
187
GND
3,712.80
2,477.00
234
235
PIO0_30
PIO0_31
1,492.00
1,457.00
2,860.80
2,962.80
188
189
PIO1_36
PIO1_37
3,610.80
3,712.80
2,527.00
2,577.00
236
237
GND
GND
1,422.00
1,387.00
2,860.80
2,962.80
190
191
PIO1_38
PIO1_39
3,610.80
3,712.80
2,627.00
2,677.00
238
239
PIO0_32
PIO0_33
1,352.00
1,317.00
2,860.80
2,962.80
192
VPP_2V5
3,610.80
2,739.68
193
194
195
VPP_FAST
VCC
3,096.90
2,997.00
2,947.00
2,962.80
2,860.80
2,962.80
240
241
PIO0_34
PIO0_35
1,282.00
1,247.00
2,860.80
2,962.80
VCC
242
243
244
245
PIO0_36
VCCIO_0
VCCIO_0
PIO0_37
1,212.00
1,177.00
1,142.00
1,107.00
2,860.80
2,962.80
2,860.80
2,962.80
196
197
PIO0_00
PIO0_01
2,897.00
2,847.00
2,860.80
2,962.80
198
199
PIO0_02
PIO0_03
2,797.00
2,747.00
2,860.80
2,962.80
246
247
PIO0_38
PIO0_39
1,072.00
1,037.00
2,860.80
2,962.80
200
201
PIO0_04
PIO0_05
2,697.00
2,647.00
2,860.80
2,962.80
248
249
PIO0_40
PIO0_41
1,002.00 2, 860.80
967.00
2,962.80
202
203
PIO0_06
PIO0_07
2,612.00
2,577.00
2,860.80
2,962.80
250
251
252
PIO0_42
GND
PIO0_43
917.00
867.00
817.00
2,860.80
2,962.80
2,860.80
204
205
GND
GND
2,542.00
2,507.00
2,860.80
2,962.80
253
254
PIO0_44
PIO0_45
767.00
717.00
2,962.80
2,860.80
206
207
PIO0_08
PIO0_09
2,472.00
2,437.00
2,860.80
2,962.80
255
256
PIO0_46
PIO0_47
667.00
617.00
2,962.80
2,860.80
208
209
PIO0_10
PIO0_11
2,402.00
2,367.00
2,860.80
2,962.80
210
211
PIO0_12
PIO0_13
2,332.00
2,297.00
2,860.80
2,962.80
212
213
PIO0_14
PIO0_15
2,262.00
2,227.00
2,860.80
2,962.80
214
215
VCCIO_0
VCCIO_0
2,192.00
2,157.00
2,860.80
2,962.80
216
217
PIO0_16
PIO0_17
2,122.00
2,087.00
2,860.80
2,962.80
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25
iCE65 Ultra Low-Power DiePlus™ Family
Physical Specifications: iCE65L08
Figure 14 shows the physical outlines of iCE65L08 die on a wafer, including pad orientation and physical origin. The
bond pad identification and coordinates are provided in Table 9. Table 5 lists key physical characteristics of each
iCE65 die.
Figure 14: iCE65L08 Die Outline
dsw_X
1
2
4
6
257
3
5
7
256
254
252
250
248
246
I/O Bank 0
255
253
251
249
247
245
8
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
244
242
240
238
236
234
232
230
228
226
224
222
220
218
216
214
212
210
208
206
204
202
200
198
196
194
192
190
243
241
239
237
235
233
231
229
227
225
223
221
219
217
215
213
211
209
207
205
203
201
199
197
195
193
191
SiliconBlue Technologies
iCE65L08 Die
189
187
185
183
181
179
177
188
186
184
182
84
86
88
90
180
178
91
SPI
I/O Bank 2
+y
+X
Coordinates listed relative to this origin
NOTE: Not to scale.
(2.0.6, 25-JAN-2011)
26
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Bond Pad Listing and Coordinates
Table 9 lists each of the 337 bonding pads on an iCE65L08 device. The pad number begins in the upper left corner of
the die, as shown in Figure 14 and increments in a counter-clockwise direction around the perimeter of the die. Each
bonding pad is identified. Signal names are color-coded by function. I/O pairs are grouped together with a thick
surrounding box. These pairs in I/O Bank 3 represent an optional differential input or output. In all other banks,
these pairs represent an optional differential output. The pad coordinates are measured relative to the origin, in the
lower left corner of the die.
Table 9: iCE65L08 Bond Pad Listing and Coordinates (Relative to Origin)
From Origin
X (µm) Y (µm)
From Origin
X (µm) Y (µm)
Pad
Signal Name
Pad
Signal Name
40 PIO3_21/DP10B
231.735 2,427.665
1
2
PIO3_00/DP00A
PIO3_01/DP00B
129.735 3,882.665
231.735 3,837.665
41 PIO3_22/DP11A
42 PIO3_23/DP11B
129.735 2,392.665
231.735 2,357.665
3
4
PIO3_02/DP01A
PIO3_03/DP01B
129.735 3,792.665
231.735 3,747.665
43 VCCIO_3 (Level)
44 VCCIO_3 (Level)
45 VREF
46 VREF
47 GND (Shield)
48 GND (Pre)
49 VCCIO_3 (Post)
50 VCCIO_3 (Post)
51 GND (Post)
52 GND (Post)
129.735 2,322.665
231.735 2,287.665
129.735 2,252.665
231.735 2,217.665
129.735 2,182.665
231.735 2,147.665
129.735 2,112.665
231.735 2,077.665
129.735 2,042.665
231.735 2,007.665
5
6
7
8
GND (Post)
GND (Post)
VCCIO_3 (Post)
VCCIO_3 (Post)
129.735 3,702.665
231.735 3,657.665
129.735 3,612.665
231.735 3,567.665
9
PIO3_04/DP02A
129.735 3,512.665
231.735 3,477.665
10 PIO3_05/DP02B
11 PIO3_06/DP03A
12 PIO3_07/DP03B
129.735 3,442.665
231.735 3,407.665
13 VCC (Core)
14 VCC (Pre)
129.735 3,372.665
231.735 3,337.665
53 PIO3_24/DP12A
129.735 1,972.665
GBIN7/
PIO3_25/DP12B
15 PIO3_08/DP04A
16 PIO3_09/DP04B
129.735 3,302.665
231.735 3,267.665
54
231.735 1,937.665
55 GND (Core)
129.735 1,902.665
17 PIO3_10/DP05A
18 PIO3_11/DP05B
129.735 3,232.665
231.735 3,197.665
GBIN6/
56
231.735 1,867.665
129.735 1,832.665
PIO3_26/DP13A
19 GND (Pre)
20 GND (Core)
129.735 3,162.665
231.735 3,127.665
57 PIO3_27/DP13B
58 PIO3_28/DP14A
59 PIO3_29/DP14B
231.735 1,798.665
129.735 1,762.665
21 PIO3_12/DP06A
22 PIO3_13/DP06B
129.735 3,092.665
231.735 3,057.665
60 PIO3_30/DP15A
61 PIO3_31/DP15B
231.735 1,727.665
129.735 1,692.665
23 GND (Post)
24 GND (Post)
129.735 3,022.665
231.735 2,987.665
62 GND (Pre)
63 GND (Pre)
231.735 1,657.665
129.735 1,622.665
25 PIO3_14/DP07A
26 PIO3_15/DP07B
129.735 2,952.665
231.735 2,917.665
64 PIO3_32/DP16A
65 PIO3_33/DP16B
231.735 1,587.665
129.735 1,552.665
27 VCCIO_3 (Post)
28 VCCIO_3 (Post)
29 VCC (Pre)
129.735 2,882.665
231.735 2,847.665
129.735 2,812.665
231.735 2,777.665
66 VCCIO_3 (Post)
67 VCCIO_3 (Post)
68 GND (Post)
231.735 1,517.665
129.735 1,482.665
231.735 1,447.665
129.735 1,412.665
30 VCC (Pre)
31 PIO3_16/DP08A
32 PIO3_17/DP08B
129.735 2,742.665
231.735 2,707.665
69 GND (Post)
70 PIO3_34/DP17A
71 PIO3_35/DP17B
231.735 1,377.665
129.735 1,342.665
33 VCCIO_3 (Level)
34 VCCIO_3 (Level)
35 GND (Pre)
129.735 2,672.665
231.735 2,637.665
129.735 2,602.665
231.735 2,567.665
72 PIO3_36/DP18A
73 PIO3_37/DP18B
231.735 1,307.665
129.735 1,272.665
36 GND (Pre)
74 PIO3_38/DP19A
75 PIO3_39/DP19B
231.735 1,237.665
129.735 1,202.665
37 PIO3_18/DP09A
38 PIO3_19/DP09B
129.735 2,532.665
231.735 2,497.665
76 PIO3_40/DP20A
231.735 1,167.665
39 PIO3_20/DP10A
129.735 2,462.665
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iCE65 Ultra Low-Power DiePlus™ Family
From Origin
From Origin
Pad
Signal Name
X (µm)
Y (µm)
Pad
Signal Name
X (µm)
Y (µm)
77 PIO3_41/DP20B
129.735 1,132.665
124 PIO2_22
125 PIO2_23
1,782.5
1,817.5
139.5
37.5
78 VCC (Pre)
79 VCC (Core)
231.735 1,097.665
129.735 1,062.665
126 PIO2_24
127 PIO2_25
1,852.5
1,887.5
139.5
37.5
80 PIO3_42/DP21A
81 PIO3_43/DP21B
231.735 1,027.665
129.735
992.665
128 PIO2_26
129 PIO2_27
1,922.5
1,957.5
139.5
37.5
82 VCCIO_3 (Post)
83 VCCIO_3 (Post)
84 GND (Post)
231.735
129.735
231.735
129.735
957.665
912.665
867.665
822.67
130 VCCIO_2
131 VCCIO_2
1,992.5
2,027.5
139.5
37.5
85 GND (Post)
132 PIO2_28
133 GBIN5/PIO2_29
2,062.5
2,097.5
139.5
37.5
86 PIO3_44/DP22A
87 PIO3_45/DP22B
231.735
129.735
777.67
732.67
134 GBIN4/PIO2_30
135 GND
136 GND
2,132.5
2,167.5
2,202.5
2,237.5
139.5
37.5
139.5
37.5
88 PIO3_46/DP23A
89 PIO3_47/DP23B
231.735
129.735
687.67
642.67
90 PIO3_48/DP24A
91 PIO3_49/DP24B
231.735
129.735
597.67
552.665
137 PIO2_31
138 PIO2_32
139 PIO2_33
2,272.5
2,307.5
139.5
37.5
92 PIO2_00
93 PIO2_01
510.0
560.0
139.5
37.5
140 PIO2_34
141 PIO2_35
2,342.5
2,377.5
139.5
37.5
94 PIO2_02
95 GND
96 GND
610.0
660.0
710.0
760.0
139.5
37.5
139.5
37.5
142 PIO2_36
143 PIO2_37
2,412.5
2,447.5
139.5
37.5
97 PIO2_03
144 PIO2_38
145 PIO2_39
2,482.5
2,517.5
139.5
37.5
98 PIO2_04
99 PIO2_05
810.0
859.3
139.5
37.5
146 PIO2_40
147 PIO2_41
2,552.5
2,587.5
139.5
37.5
100 PIO2_06
101 PIO2_07
910.0
960.0
139.5
37.5
148 PIO2_42
149 PIO2_43
2,622.5
2,657.5
139.5
37.5
102 PIO2_08
103 VCCIO_2
104 VCCIO_2
105 PIO2_09
1,012.5
139.5
37.5
139.5
37.5
1,047.5
1,082.5
1,117.5
150 PIO2_44
151 VCC
152 VCC
2,692.5
2,727.5
2,762.5
2,797.5
139.5
37.5
139.5
37.5
153 PIO2_45
106 PIO2_10
107 GND
108 GND
1,152.5
1,187.5
1,222.5
1,257.5
139.5
37.5
139.5
37.5
154 PIO2_46
155 VCCIO_2
156 VCCIO_2
157 PIO2_47
2,832.5
2,867.5
2,902.5
2,937.5
139.5
37.5
139.5
37.5
109 PIO2_11
110 PIO2_12
111 PIO2_13
1,292.5
1,327.5
139.5
37.5
158 GND
159 GND
2,972.5
3,007.5
139.5
37.5
112 PIO2_14
113 PIO2_15
1,362.5
1,397.5
139.5
37.5
160 PIO2_48
161 PIO2_49
3,042.5
3,077.5
139.5
37.5
114 PIO2_16
115 PIO2_17
1,432.5
1,467.5
139.5
37.5
162 PIO2_50
3,112.5
139.5
116 PIO2_18
117 GND
118 GND
1,502.3
1,537.3
1,572.5
1,607.5
139.5
37.5
139.5
37.5
163 PIO2_51/CBSEL0
164 PIO2_52/CBSEL1
3,147.5
3,182.5
37.5
139.5
165 CDONE
166 CRESET_B
3,217.5
3,260.0
37.5
139.5
119 PIO2_19
120 PIO2_20
121 VCC
122 VCC
1,642.5
1,677.5
1,712.5
1,747.5
139.5
37.5
139.5
37.5
167 PIOS_00/SPI_SO
168 PIOS_01/SPI_SI
3,320.0
3,370.0
37.5
139.5
169 GND
170 GND
3,420.0
3,470.0
37.5
139.5
123 PIO2_21
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From Origin
From Origin
Pad
Signal Name
X (µm)
Y (µm)
Pad
Signal Name
X (µm)
Y (µm)
171 PIOS_02/SPI_SCK
172 PIOS_03/SPI_SS_B
3,520.0
3,570.0
37.5
139.5
220 GBIN2/PIO1_28
221 PIO1_29
4,572.5
4,470.5
2,337.115
2,372.115
173 VCC
174 VCC
175 SPI_VCC
176 SPI_VCC
3,620.0
3,670.0
3,720.0
3,770.0
37.5
139.5
37.5
222 PIO1_30
223 PIO1_31
4,572.5
4,470.5
2,407.115
2,442.115
224 PIO1_32
225 PIO1_33
4,572.5
4,470.5
2,477.115
2,512.115
139.5
177 TDI
4,470.5
4,572.5
4,470.5
4,572.5
4,470.5
634.615
684.615
734.615
784.615
834.615
226 PIO1_34
227 PIO1_35
4,572.5
4,470.5
2,547.115
2,582.115
178 TMS
179 TCK
180 TDO
181 TRST_B
228 GND
229 GND
4,572.5
4,470.5
2,617.115
2,652.115
230 PIO1_36
231 VCCIO_1
232 VCCIO_1
233 PIO1_37
4,572.5
4,470.5
4,572.5
4,470.5
2,687.12
2,722.12
2,757.12
2,792.12
182 PIO1_00
183 PIO1_01
4,572.5
4,470.5
884.615
934.615
184 PIO1_02
185 PIO1_03
4,572.5
4,470.5
984.615
1,034.615
234 PIO1_38
235 PIO1_39
4,572.5
4,470.5
2,827.12
2,862.12
186 GND
187 GND
4,572.5
4,470.5
1,084.615
1,134.615
236 PIO1_40
237 PIO1_41
4,572.5
4,470.5
2,897.12
2,932.12
188 PIO1_04
189 PIO1_05
4,572.5
4,470.5
1,184.615
1,234.62
238 PIO1_42
239 PIO1_43
4,572.5
4,470.5
2,967.12
3,002.12
190 VCCIO_1
191 VCCIO_1
4,572.5
4,470.5
1,287.115
1,322.115
240 PIO1_44
241 PIO1_45
4,572.5
4,470.5
3,037.12
3,072.12
192 PIO1_06
193 PIO1_07
4,572.5
4,470.5
1,357.115
1,392.115
242 PIO1_46
243 VCC
244 VCC
4,572.5
4,470.5
4,572.5
4,470.5
3,107.12
3,142.12
3,177.12
3,229.615
194 PIO1_08
195 PIO1_09
4,572.5
4,470.5
1,427.115
1,462.115
196 PIO1_10
197 VCC
198 VCC
4,572.5
4,470.5
4,572.5
4,470.5
1,497.115
1,532.115
1,567.115
1,602.115
245 PIO1_47
246 PIO1_48
247 VCCIO_1
248 VCCIO_1
249 PIO1_49
4,572.5
4,470.5
4,572.5
4,470.5
3,279.615
3,329.615
3,379.615
3,429.62
199 PIO1_11
200 PIO1_12
201 PIO1_13
4,572.5
4,470.5
1,637.115
1,672.115
250 PIO1_50
251 GND
252 GND
4,572.5
4,470.5
4,572.5
4,470.5
3,479.615
3,529.615
3,579.615
3,629.615
202 PIO1_14
203 PIO1_15
4,572.5
4,470.5
1,707.115
1,742.115
204 PIO1_16
205 PIO1_17
4,572.5
4,470.5
1,777.115
1,812.115
253 PIO1_51
254 PIO1_52
255 PIO1_53
4,572.5
4,470.5
3,679.595
3,729.595
206 PIO1_18
207 GND
208 GND
4,572.5
4,470.5
4,572.5
4,470.5
1,847.115
1,882.115
1,917.110
1,952.115
256 PIO1_54
257 VPP_2V5
4,572.5
4,470.5
3,779.595
3,879.575
209 PIO1_19
210 PIO1_20
211 PIO1_21
4,572.5
4,470.5
1,987.115
2,022.115
258 VPP_FAST
259 VCC
260 VCC
3,866.975 4,054.5
3,766.98
3,716.98
4,156.5
4,054.5
212 PIO1_22
213 VCCIO_1
214 VCCIO_1
215 PIO1_23
4,572.5
4,470.5
4,572.5
4,470.5
2,057.115
2,092.115
2,127.115
2,162.115
261 PIO0_00
262 PIO0_01
3,666.98
3,616.98
4,156.5
4,054.5
263 PIO0_02
264 PIO0_03
3,566.98
3,516.98
4,156.5
4,054.5
216 PIO1_24
217 PIO1_25
4,572.5
4,470.5
2,197.115
2,232.115
265 PIO0_04
266 VCCIO_0
3,466.98
3,416.98
4,156.5
4,054.5
218 PIO1_26
219 GBIN3/PIO1_27
4,572.5
4,470.5
2,267.115
2,302.11
SiliconBlue Technologies Corporation
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29
iCE65 Ultra Low-Power DiePlus™ Family
From Origin
From Origin
X (µm) Y (µm)
Pad
Signal Name
X (µm)
Y (µm)
Pad
Signal Name
267 PIO0_05
3,366.98
4,156.5
306 VCC
307 VCC
1,909.48
1,874.48
4,054.5
4,156.5
268 PIO0_06
269 PIO0_07
3,316.98
3,266.98
4,054.5
4,156.5
308 PIO0_36
309 PIO0_37
1,839.48
1,804.48
4,054.5
4,156.5
270 GND
271 GND
3,216.98
3,166.98
4,054.5
4,156.5
310 PIO0_38
311 PIO0_39
1,769.48
1,734.48
4,054.5
4,156.5
272 PIO0_08
273 PIO0_09
3,116.98
3,064.48
4,054.5
4,156.5
312 GND
313 GND
1,699.48
1,664.48
4,054.5
4,156.5
274 PIO0_10
275 PIO0_11
3,029.48
2,994.48
4,054.5
4,156.5
314 PIO0_40
315 PIO0_41
1,629.48
1,594.48
4,054.5
4,156.5
276 PIO0_12
277 PIO0_13
2,959.48
2,924.48
4,054.5
4,156.5
316 PIO0_42
317 PIO0_43
1,559.48
1,524.48
4,054.5
4,156.5
278 PIO0_14
279 PIO0_15
2,889.48
2,854.48
4,054.5
4,156.5
318 PIO0_44
319 PIO0_45
1,489.48
1,454.48
4,054.5
4,156.5
280 VCCIO_0
281 VCCIO_0
2,819.48
2,784.48
4,054.5
4,156.5
320 PIO0_46
321 PIO0_47
1,419.48
1,384.48
4,054.5
4,156.5
282 PIO0_16
283 PIO0_17
2,749.48
2,714.48
4,054.5
4,156.5
322 PIO0_48
323 VCCIO_0
324 VCCIO_0
325 PIO0_49
1,331.98
1,281.98
1,231.98
1,181.98
4,054.5
4,156.5
4,054.5
4,156.5
284 PIO0_18
285 PIO0_19
2,679.48
2,644.48
4,054.5
4,156.5
286 PIO0_20
287 PIO0_21
2,609.48
2,574.48
4,054.5
4,156.5
326 PIO0_50
327 PIO0_51
1,131.98
1,081.98
4,054.5
4,156.5
288 PIO0_22
289 PIO0_23
2,539.48
2,504.48
4,054.5
4,156.5
328 PIO0_52
329 PIO0_53
1,031.98
981.98
4,054.5
4,156.5
330 PIO0_54
331 GND
332 GND
931.98
881.98
831.98
781.98
4,054.5
4,156.5
4,054.5
4,156.5
290 PIO0_24
291 PIO0_25
2,469.48
2,434.48
4,054.5
4,156.5
292 GND
293 GND
2,399.48
2,364.48
4,054.5
4,156.5
333 PIO0_55
334 PIO0_56
335 PIO0_57
731.98
681.98
4,054.5
4,156.5
294 PIO0_26
295 PIO0_27
2,329.48
2,294.48
4,054.5
4,156.5
336 PIO0_58
337 PIO0_59
631.98
581.98
4,054.5
4,156.5
296 PIO0_28
297 GBIN1/PIO0_29
2,259.48
2,224.48
4,054.5
4,156.5
298 GBIN0/PIO0_30
299 PIO0_31
2,189.48
2,154.48
4,054.5
4,156.5
300 VCCIO_0
301 VCCIO_0
2,119.48
2,084.48
4,054.5
4,156.5
302 PIO0_32
303 PIO0_33
2,049.48
2,014.48
4,054.5
4,156.5
304 PIO0_34
305 PIO0_35
1,979.48
1,944.48
4,054.5
4,156.5
(2.0.6, 25-JAN-2011)
30
SiliconBlue Technologies Corporation
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SiliconBlue
Die Testing Procedures
SiliconBlue Technologies die products are tested to ensure product functionality in our standard package. Each die
has gone through wafer probe test of various functional and parametric conditions.
SiliconBlue Technologies retains a wafer map of each wafer as part of the probe records, along with a lot summary of
wafer yields for each lot probed. SiliconBlue Technologies reserves the right to change the probe program at any time
for continuous product improvement.
Die users may experience differences in performance relative to SiliconBlue Technologies’ data sheets. This is due to
differences in package capacitance, inductance, resistance, and trace length.
Product Reliability Monitors
Reliability of all packaged products is monitored by ongoing QRA reliability evaluations. From these evaluations,
samples are subjected to a battery of tests known as “Accelerated Life and Environmental Stress Tests.” During these
tests, devices are stressed for many hours under conditions designed to simulate years of normal field use. A
summary of these product family evaluations is published on a regular basis.
Storage Requirements
SiliconBlue Technologies’ die products are packaged in a cleanroom environment for shipping. Upon receipt,
transfer the die or wafers to a similar environment for storage. SiliconBlue Technologies recommends that the die or
wafers be maintained in a filtered nitrogen atmosphere until removed for assembly. The moisture content of the
storage facility should be maintained at 30% ±10% relative humidity. ESD damage precautions are necessary during
handling. The die must be in an ESD-protected environment at all times for inspection and assembly.
SiliconBlue Technologies Corporation
(2.0.6, 25-JAN-2011)
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iCE65 Ultra Low-Power DiePlus™ Family
Revision History
Version
2.0.6
Date
Description
25-JAN-2011 Removed P, Waffle Pack option from Ordering Codes Figure 10.
Updated CC72 Ball Diameter Figure 9
2.0.5
2.0.4
2.0.3
7-JAN-2011
Made minor correction to Figure 13.
23-AUG-2010 Updated Figure 7 CS63 Package Mechanical Drawing
1-JUL-2010
Removed *Production Qualification scheduled to complete in June 2010. Table 1
Increased WLCSP thickness with Top-side coating, Figures 5, 7, & 9
Changed iCE65P04 Known Good Die, KGD I/O Pads from 174 to 176 in Table 1.
Changed Wafer Thickness in Table 5 to 31 mil, 10 mil, or 4 mil.
2.0.2
2.0.1
2.0
1-JUN-2010
1-JUN-2010
13-MAY-2010 Removed PRELIMINARY. Added devices: iCE65L01 die and WLCSP CS36, iCE65P04 die.
28-JAN-2010 Initial DiePlus Release combines WLCSP from May 7, 2009 (1.5) iCE65 Family Data Sheet,
February 24, 2009 (1.5.1) iCE DiCE iCE65L04 Data Sheet and July 27, 2009 (1.1) iCE DiCE
iCE65L08 Data Sheet.
1.0
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Technologies LTD in the United States. Specific device designations, and all other words and logos that are identified as
trademarks are, unless noted otherwise, the trademarks of SiliconBlue Technologies LTD. All other product or service names are
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