JANSR2N7294 [INTERSIL]
23A, 200V, 0.115 Ohm, Rad Hard, N-Channel Power MOSFET; 23A ， 200V ， 0.115欧姆，抗辐射， N沟道功率MOSFET
| 型号： | JANSR2N7294 |
| 厂家： | 
Intersil |
| 描述： | 23A, 200V, 0.115 Ohm, Rad Hard, N-Channel Power MOSFET |
| 文件： | 总7页 (文件大小：51K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JANSR2N7294
Formerly FRF250R4
June 1998
23A, 200V, 0.115 Ohm, Rad Hard,
N-Channel Power MOSFET
Features
Description
• 23A, 200V, r
= 0.115Ω
The Intersil Corporation has designed a series of SECOND
GENERATION hardened power MOSFETs of both N-Chan-
nel and P-Channel enhancement types with ratings from
100V to 500V, 1A to 60A, and on resistance as low as
25mΩ. Total dose hardness is offered at 100K RAD (Si) and
1000K RAD (Si) with neutron hardness ranging from 1E13
for 500V product to 1E14 for 100V product. Dose rate hard-
DS(ON)
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
- Typically Survives 2E12 if Current Limited to I
DSS
DM
ness (GAMMA DOT) exists for rates to 1E9 without current
limiting and 2E12 with current limiting.
• Photo Current
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to exhibit mini-
mal characteristic changes to total dose (GAMMA) and
neutron (n ) exposures. Design and processing efforts are
also directed to enhance survival to dose rate (GAMMA
DOT) exposure.
- 12nA Per-RAD(Si)/s Typically
• Neutron
o
- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm
2
2
- Usable to 1E14 Neutrons/cm
Also available at other radiation and screening levels. See us
on the web, Intersil’ home page: http://www.intersil.com.
Contact your local Intersil Sales Office for additional informa-
tion.
Ordering Information
PART NUMBER
PACKAGE
TO-254AA
BRAND
JANSR2N7294
JANSR2N7294
Symbol
D
Die family TA17652.
MIL-PRF-19500/605.
G
S
Package
TO-254AA
G
S
D
CAUTION: Beryllia Warning per MIL-S-19500
refer to package specifications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 4292.1
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000.
2-23
JANSR2N7294
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
JANSR2N7294
UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
200
200
V
V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
o
T
T
= 25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
23
15
A
A
A
V
C
D
D
o
= 100 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
69
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
±20
GS
Maximum Power Dissipation
o
T
T
= 25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
125
50
W
W
C
T
o
= 100 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
C
T
o
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . I
1.00
69
W/ C
A
A
A
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
23
S
SM
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
69
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T , T
-55 to 150
300
C
J
STG
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
(Distance >0.063in (1.6mm) from Case, 10s Max)
C
L
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
C
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
SYMBOL
BV
TEST CONDITIONS
= 1mA, V = 0V
MIN
TYP
MAX
-
UNITS
V
I
200
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DSS
D
GS
o
V
V
= V
= 1mA
,
T
T
T
T
T
T
T
= -55 C
-
5.0
V
GS(TH)
GS
DS
C
C
C
C
C
C
C
I
o
D
= 25 C
2.0
4.0
V
o
= 125 C
1.0
-
-
V
o
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
V
V
= 160V,
= 0V
= 25 C
25
µA
µA
nA
nA
V
DSS
DS
GS
o
= 125 C
-
250
100
200
2.78
0.115
0.253
156
510
574
280
558
298
20
o
I
V
= ±20V
= 25 C
-
GSS
GS
o
= 125 C
-
Drain to Source On-State Voltage
Drain to Source On Resistance
V
V
= 10V, I = 23A
-
DS(ON)
GS
D
o
r
I
= 15A,
T
T
= 25 C
-
Ω
DS(ON)
D
C
C
V
= 10V
o
GS
= 125 C
-
Ω
Turn-On Delay Time
t
V
R
R
= 100V, I = 23A,
-
ns
ns
ns
ns
nC
nC
nC
nC
nC
d(ON)
DD
D
= 4.35Ω, V = 10V,
L
GS
Rise Time
t
-
r
= 25Ω
GS
Turn-Off Delay Time
t
-
d(OFF)
Fall Time
t
-
f
Total Gate Charge (Not on slash sheet)
Gate Charge at 10V
Q
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
= 100V,
-
g(TOT)
GS
DD
= 23A
I
D
Q
V
-
g(10)
GS
Threshold Gate Charge (Not on slash sheet)
Gate Charge Source
Q
V
-
g(TH)
GS
Q
Q
-
66
gs
Gate Charge Drain
-
144
1.0
gd
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
-
C/W
JC
JA
θ
o
R
-
48
C/W
θ
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
= 25A
MIN
TYP
MAX
UNITS
V
I
0.6
-
-
-
1.8
V
SD
SD
t
I
= 25A, dI /dt = 100A/µs
1700
ns
rr
SD
SD
2-24
JANSR2N7294
o
Electrical Specifications up to 100K RAD T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
= 0, I = 1mA
MIN
MAX
-
UNITS
Drain to Source Breakdown Volts (Note 3)
Gate to Source Threshold Volts (Note 3)
BV
DSS
V
200
V
V
GS
D
V
V
= V , I = 1mA
DS
2.0
4.0
GS(TH)
GS
D
Gate to Body Leakage
(Notes 2, 3)
I
V
= ±20V, V
= 0V
-
-
-
-
100
25
nA
µA
V
GSS
GS DS
Zero Gate Leakage
(Note 3)
I
V
= 0, V = 160V
DS
DSS
GS
Drain to Source On-State Volts
Drain to Source On Resistance
(Notes 1, 3)
(Notes 1, 3)
V
V
= 10V, I = 23A
2.78
0.115
DS(ON)
GS
D
r
V
= 10V, I = 15A
Ω
DS(ON)
GS
D
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 10V, V
DS
= 0V and V
= 0V, V
= 80% BV
.
GS
DS
DSS
Typical Performance Curves Unless Otherwise Specified
28
24
o
100
10
T
= 25 C
C
20
16
12
100µs
1ms
10ms
1
8
100ms
OPERATION IN THIS
AREA MAY BE
4
0
LIMITED BY r
DS(ON)
0.1
-50
0
T
50
100
o
150
1
10
100
V
, DRAIN TO SOURCE VOLTAGE (V)
, CASE TEMPERATURE ( C)
DS
C
FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 2. FORWARD BIAS SAFE OPERATING AREA
2-25
JANSR2N7294
Typical Performance Curves Unless Otherwise Specified (Continued)
10
1
0.5
0.2
0.1
0.05
0.1
P
DM
0.02
0.01
t
t
1
2
SINGLE PULSE
0.01
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
+ T
J
DM
JC C
θ
0.001
-5
-4
-3
-2
10
-1
0
1
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I IS REACHED
AS
V
DS
L
BV
DSS
+
I
-
CURRENT
TRANSFORMER
AS
t
P
V
DS
I
AS
V
VARY t TO OBTAIN
DD
P
+
50Ω
REQUIRED PEAK I
AS
V
DD
V
≤ 20V
GS
-
50V-150V
DUT
50Ω
t
P
0V
t
AV
FIGURE 4. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 5. UNCLAMPED ENERGY WAVEFORMS
2-26
JANSR2N7294
Test Circuits and Waveforms
t
t
ON
OFF
t
d(OFF)
V
DD
t
d(ON)
t
t
f
r
R
L
V
DS
90%
90%
V
DS
V
= 10V
GS
10%
10%
DUT
0V
90%
50%
R
GS
50%
V
GS
PULSE WIDTH
10%
FIGURE 6. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 7. RESISTIVE SWITCHING WAVEFORMS
Q
Q
10V
G
Q
GD
GS
V
G
CHARGE
FIGURE 8. BASIC GATE CHARGE WAVEFORM
2-27
JANSR2N7294
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
o
Delta Tests and Limits (JANS) T = 25 C, Unless Otherwise Specified
C
PARAMETER
Gate to Source Leakage Current
Zero Gate Voltage Drain Current
Drain to Source On Resistance
Gate Threshold Voltage
NOTES:
SYMBOL
TEST CONDITIONS
= ±20V
GS
MAX
UNITS
nA
I
V
±20 (Note 4)
±25 (Note 4)
±20% (Note 5)
±20% (Note 5)
GSS
I
V
= 80% Rated Value
o
µA
DSS
DS
r
T
= 25 C at Rated I
D
Ω
DS(ON)
C
V
I
= 1.0mA
V
GS(TH)
D
4. Or 100% of Initial Reading (whichever is greater).
5. Of Initial Reading.
Screening Information
TEST
JANS
Gate Stress
V
= 30V, t = 250µs
GS
Pind
Required
o
Pre Burn-In Tests (Note 6)
Steady State Gate Bias (Gate Stress)
MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25 C)
MIL-STD-750, Method 1042, Condition B
o
V
= 80% of Rated Value, T = 150 C, Time = 48 hours
A
GS
Interim Electrical Tests (Note 6)
All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
o
V
= 80% of Rated Value, T = 150 C, Time = 240 hours
A
DS
PDA
5%
Final Electrical Tests (Note 6)
MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
6. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area
SYMBOL
TEST CONDITIONS
= 160V, t = 10ms
MAX
1.6
UNITS
A
SOA
V
DS
Unclamped Inductive Switching
Thermal Response
I
V
= 15V, L = 0.1mH
69
A
AS
GS(PEAK)
∆V
∆V
t
t
= 100ms; V = 25V; I = 4A
136
187
mV
mV
SD
SD
H
H
H
Thermal Impedance
= 500ms; V = 25V; I = 4A
H H
H
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
2-28
JANSR2N7294
TO-254AA
3 LEAD JEDEC TO-254AA HERMETIC METAL PACKAGE
A
INCHES
MIN
MILLIMETERS
ØP
E
A
SYMBOL
MAX
0.260
0.050
0.045
0.800
0.545
MIN
6.33
MAX
6.60
NOTES
1
A
0.249
0.040
0.035
0.790
0.535
-
Q
A
1.02
1.27
-
1
H
1
Øb
D
0.89
1.14
2, 3
20.07
13.59
20.32
13.84
-
-
E
D
e
0.150 TYP
0.300 BSC
3.81 TYP
7.62 BSC
4
4
-
e
1
H
0.245
0.265
0.160
0.560
0.149
0.130
6.23
6.73
4.06
1
1
J
0.140
0.520
0.139
0.110
3.56
13.21
3.54
4
-
L
14.22
3.78
0.065 R MAX.
TYP.
ØP
Q
-
L
Øb
2.80
3.30
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. A of
JEDEC outline TO-254AA dated 11-86.
1
2
3
J
e
1
2. Add typically 0.002 inches (0.05mm) for solder coating.
3. Lead dimension (without solder).
e
1
4. Position of lead to be measured 0.250 inches (6.35mm) from bot-
tom of dimension D.
5. Die to base BeO isolated, terminals to case ceramic isolated.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
WARNING!
BERYLLIA WARNING PER MIL-S-19500
Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical
operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound
shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’
compounds.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
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Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
2-29
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