JANSR2N7396 [INTERSIL]
5A, 200V, 0.460 Ohm, Rad Hard, N-Channel Power MOSFET; 5A ， 200V ， 0.460欧姆，抗辐射， N沟道功率MOSFET
| 型号： | JANSR2N7396 |
| 厂家： | 
Intersil |
| 描述： | 5A, 200V, 0.460 Ohm, Rad Hard, N-Channel Power MOSFET |
| 文件： | 总8页 (文件大小：48K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JANSR2N7396
Formerly FSL230R4
June 1998
5A, 200V, 0.460 Ohm, Rad Hard,
N-Channel Power MOSFET
Features
Description
• 5A, 200V, r
= 0.460Ω
The Discrete Products Operation of Intersil Corporation has
developed a series of Radiation Hardened MOSFETs specif-
ically designed for commercial and military space applica-
tions. Enhanced Power MOSFET immunity to Single Event
Effects (SEE), Single Event Gate Rupture (SEGR) in particu-
lar, is combined with 100K RADS of total dose hardness to
provide devices which are ideally suited to harsh space envi-
ronments. The dose rate and neutron tolerance necessary
for military applications have not been sacrificed.
DS(ON)
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
2
- SEE Immunity for LET of 36MeV/mg/cm with
V
up to 80% of Rated Breakdown and
of 10V Off-Bias
DS
V
GS
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications
exposed to radiation environments such as switching regula-
tion, switching converters, motor drives, relay drivers and
drivers for high-power bipolar switching transistors requiring
high speed and low gate drive power. This type can be
operated directly from integrated circuits.
- 3.0nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm
2
2
- Usable to 1E14 Neutrons/cm
Ordering Information
Also available at other radiation and screening levels. See us
on the web, Intersil’ home page:http://www.intersil.com.
Contact your local Intersil Sales Office for additional
information.
PART NUMBER
PACKAGE
TO-205AF
BRAND
JANSR2N7396
JANSR2N7396
Die Family TA17637.
MIL-PRF-19500/631.
Symbol
Package
TO-205AF
G
D
S
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 4452.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
2-34
JANSR2N7396
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
JANSR2N7396
UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
200
200
V
V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
o
T
T
= 25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
5
3
A
A
A
V
C
D
D
o
= 100 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
15
±20
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation
o
T
T
= 25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
25
10
W
W
C
T
o
= 100 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
C
T
o
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . I
0.20
15
W/ C
A
A
A
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
5
S
SM
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
15
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T , T
-55 to 150
300
C
J
STG
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
(Distance >0.063in (1.6mm) from Case, 10s Max)
C
L
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.0
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
C
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
BV
DSS
I
= 1mA, V
GS
= 0V
200
-
-
5.0
4.0
-
V
V
D
o
V
V
= V
= 1mA
,
T
= -55 C
-
-
GS(TH)
GS
DS
C
C
C
C
C
C
C
I
D
o
T
T
T
T
T
T
= 25 C
1.5
-
V
o
= 125 C
0.5
-
-
V
o
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
V
V
= 160V,
= 0V
= 25 C
-
25
µA
µA
nA
nA
V
DSS
DS
GS
o
= 125 C
-
-
250
100
200
2.42
0.460
0.805
65
o
I
V
= ±20V
= 25 C
-
-
GSS
GS
o
= 125 C
-
-
Drain to Source On-State Voltage
Drain to Source On Resistance
V
V
= 12V, I = 5A
-
-
DS(ON)
GS
D
o
r
I
= 3A,
= 12V
T
T
= 25 C
-
0.340
Ω
DS(ON)12
D
C
C
V
GS
o
= 125 C
-
-
-
Ω
Turn-On Delay Time
t
V
R
R
= 100V, I = 5A,
-
ns
ns
ns
ns
nC
nC
nC
nC
nC
C/W
C/W
d(ON)
DD
D
= 20Ω, V = 12V,
L
GS
Rise Time
t
-
-
150
120
85
r
= 7.5Ω
GS
Turn-Off Delay Time
t
-
-
d(OFF)
Fall Time
t
-
-
f
Total Gate Charge (Not on slash sheet)
Gate Charge at 12V
Q
V
= 0V to 20V
= 0V to 12V
= 0V to 2V
V
= 100V,
-
-
58
g(TOT)
GS
DD
= 5A
I
D
Q
V
-
31
-
38
g(12)
g(TH)
GS
Threshold Gate Charge (Not on slash sheet)
Gate Charge Source
Q
V
-
2.6
8.4
20
GS
Q
-
6.1
15
-
gs
gd
Gate Charge Drain
Q
-
o
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
-
5.0
175
JC
JA
θ
R
-
-
θ
2-35
JANSR2N7396
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
0.6
-
TYP
MAX
1.8
UNITS
V
V
I
I
= 5A
-
-
SD
SD
t
= 5A, dI /dt = 100A/µs
360
ns
rr
SD
SD
o
Electrical Specifications up to 100K RAD T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 0, I = 1mA
MIN
MAX
-
UNITS
Drain to Source Breakdown Volts (Note 3)
V
200
V
V
DSS
GS
D
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
(Note 3)
V
V
= V , I = 1mA
DS
1.5
4.0
GS(TH)
GS
D
(Notes 2, 3)
(Note 3)
I
V
= ±20V, V
= 0V
-
-
-
-
100
25
nA
µA
V
GSS
GS
DS
I
V
= 0, V
= 160V
DSS
GS DS
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
(Notes 1, 3)
(Notes 1, 3)
V
V
= 12V, I = 5A
2.42
0.460
DS(ON)
GS
D
r
V
= 12V, I = 3A
Ω
DS(ON)12
GS
D
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 12V, V
DS
= 0V and V
GS
= 0V, V
= 80% BV
.
DS
DSS
Single Event Effects (SEB, SEGR) (Note 4)
ENVIRONMENT (NOTE 5)
(NOTE 6)
APPLIED
MAXIMUM
ION
SPECIES
TYPICAL LET
(MeV/mg/cm)
TYPICAL
RANGE (µ)
V
BIAS
V
BIAS
GS
(V)
DS
(V)
TEST
SYMBOL
Single Event Effects Safe Operating
Area
SEESOA
Ni
Br
Br
Br
Br
26
37
37
37
37
43
36
36
36
36
-20
-5
200
200
160
100
40
-10
-15
-20
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
2
o
5. Fluence = 1E5 ions/cm (typical), T = 25 C.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
Typical Performance Curves Unless Otherwise Specified
2
LET = 26MeV/mg/cm , RANGE = 43µ
2
LET = 37MeV/mg/cm , RANGE = 36µ
1E-3
1E-4
240
2
FLUENCE = 1E5 IONS/cm (TYPICAL)
200
160
120
ILM = 10A
30A
1E-5
1E-6
1E-7
100A
300A
80
40
0
o
TEMP = 25 C
10
30
100
300
1000
0
-5
-10
-15
-20
-25
V
(V)
DRAIN SUPPLY (V)
GS
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO I
AS
2-36
JANSR2N7396
Typical Performance Curves Unless Otherwise Specified (Continued)
7
6
5
4
3
2
50
o
T
= 25 C
C
10
100µs
1ms
1
10ms
OPERATION IN THIS
AREA MAY BE
1
0
100ms
LIMITED BY r
DS(ON)
0.1
-50
0
T
50
100
o
150
1
10
100
600
, CASE TEMPERATURE ( C)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
C
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5
PULSE DURATION = 250ms, V
GS
= 12V, I = 3A
D
2.0
1.5
1.0
0.5
0.0
Q
Q
12V
G
Q
GS
GD
V
G
-80
-40
0
40
80
120
160
CHARGE
o
T , JUNCTION TEMPERATURE ( C)
J
FIGURE 5. BASIC GATE CHARGE WAVEFORM
FIGURE 6. NORMALIZED r vs JUNCTION TEMPERATURE
DS(ON)
1
10
0
10
0.5
0.2
0.1
-1
-2
-3
10
10
10
0.05
0.02
0.01
SINGLE PULSE
P
DM
NOTES:
DUTY FACTOR: D = t /t
t
1
1
2
+ T
t
2
PEAK T = P
J
x Z
DM
JC
C
θ
-5
10
-4
10
-3
10
-2
10
-1
0
10
1
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
2-37
JANSR2N7396
Typical Performance Curves Unless Otherwise Specified (Continued)
30
10
o
STARTING T = 25 C
J
o
STARTING T = 150 C
J
IF R = 0
t
= (L) (I ) / (1.3 RATED BV
AS
- V )
DD
AV
IF R ≠ 0
AV
DSS
t
= (L/R) ln [(I *R) / (1.3 RATED BV
AS
- V ) + 1]
DD
DSS
1
0.01
0.1
1
10
t
, TIME IN AVALANCHE (ms)
AV
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I IS REACHED
AS
V
DS
L
BV
DSS
+
I
-
CURRENT
TRANSFORMER
t
P
AS
V
DS
I
AS
V
DD
VARY t TO OBTAIN
P
+
50Ω
REQUIRED PEAK I
AS
V
DD
V
≤ 20V
GS
-
50V-150V
DUT
50Ω
t
P
0V
t
AV
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
V
DD
t
d(ON)
t
t
f
r
R
L
V
DS
90%
90%
V
DS
V
= 12V
GS
10%
10%
DUT
0V
90%
50%
R
GS
50%
V
GS
PULSE WIDTH
10%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
2-38
JANSR2N7396
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
o
Delta Tests and Limits (JANS) T = 25 C, Unless Otherwise Specified
C
PARAMETER
Gate to Source Leakage Current
Zero Gate Voltage Drain Current
Drain to Source On Resistance
Gate Threshold Voltage
NOTES:
SYMBOL
TEST CONDITIONS
= ±20V
GS
MAX
UNITS
nA
I
V
±20 (Note 7)
±25 (Note 7)
±20% (Note 8)
±20% (Note 8)
GSS
I
V
= 80% Rated Value
o
µA
DSS
DS
r
T
= 25 C at Rated I
D
Ω
DS(ON)
C
V
I
= 1.0mA
V
GS(TH)
D
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
Screening Information
TEST
JANS
Gate Stress
V
= 30V, t = 250µs
GS
Pind
Required
Pre Burn-In Tests (Note 9)
MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25 C)
o
Steady State Gate
Bias (Gate Stress)
MIL-STD-750, Method 1042, Condition B
= 80% of Rated Value,
V
GS
T = 150 C, Time = 48 hours
o
A
Interim Electrical Tests (Note 9)
All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse
Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
V
= 80% of Rated Value,
DS
o
T = 150 C, Time = 240 hours
A
PDA
5%
Final Electrical Tests (Note 9)
MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area
SYMBOL
TEST CONDITIONS
MAX
0.65
15
UNITS
A
SOA
V
= 160V, t = 10ms
DS
Unclamped Inductive Switching
Thermal Response
I
V
= 15V, L = 0.1mH
A
AS
GS(PEAK)
∆V
∆V
t
t
= 10ms; V = 25V; I = 2A
125
250
mV
mV
SD
SD
H
H
H
Thermal Impedance
= 500ms; V = 25V; I = 1A
H H
H
2-39
JANSR2N7396
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning
Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi Temp Drain Stress Post Reverse
Bias Delta Data
F. Group A
G. Group B
H. Group C
I. Group D
- Attributes Data Sheet
- Attributes Data Sheet
- Attributes Data Sheet
- Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A
G. Group B
H. Group C
I. Group D
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
2-40
JANSR2N7396
TO-205AF
3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE
ØD
INCHES
MIN
MILLIMETERS
ØD
1
SYMBOL
MAX
0.180
0.021
0.370
0.335
0.105
0.210
0.105
0.020
0.034
0.045
0.560
-
MIN
4.07
0.41
8.89
8.01
2.42
4.83
2.42
0.26
0.72
0.74
12.70
1.91
MAX
4.57
0.53
9.39
8.50
2.66
5.33
2.66
0.50
0.86
1.14
14.22
-
NOTES
P
A
0.160
0.016
0.350
0.315
0.095
0.190
0.095
0.010
0.028
0.029
0.500
0.075
-
2, 3
-
A
Øb
ØD
SEATING
PLANE
h
ØD
e
-
1
L
Øb
4
4
4
-
e
e
1
e
2
e1
h
j
-
o
90
2
k
-
e2
1
3
L
P
3
5
o
45
j
k
NOTES:
1. These dimensions are within allowable dimensions of Rev. E of
JEDEC TO-205AF outline dated 11-82.
2. Lead dimension (without solder).
3. Solder coating may vary along lead length, add typically 0.002
inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.100 inches (2.54mm) from bottom
of seating plane.
5. This zone controlled for automatic handling. The variation in
actual diameter within this zone shall not exceed 0.010 inches
(0.254mm).
6. Lead no. 3 butt welded to stem base.
7. Controlling dimension: Inch.
8. Revision 3 dated 6-94.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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TEL: (32) 2.724.2111
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Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
2-41
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