JANSR2N7402 [INFINEON]
Power Field-Effect Transistor, 3A I(D), 500V, 2.7ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA;
| 型号： | JANSR2N7402 |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 3A I(D), 500V, 2.7ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA 局域网 开关 脉冲 晶体管 |
| 文件： | 总9页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JANSR2N7402
Formerly FSS430R4
January 2002
3A, 500V, 2.70 Ohm, Rad Hard,
N-Channel Power MOSFET
Features
Description
• 3A, 500V, r
= 2.70Ω
The Discrete Products Operation of Fairchild Corporation
has developed a series of Radiation Hardened MOSFETs
specifically designed for commercial and military space
applications. Enhanced Power MOSFET immunity to Single
Event Effects (SEE), Single Event Gate Rupture (SEGR) in
particular, is combined with 100K RADS of total dose hard-
ness to provide devices which are ideally suited to harsh
space environments. The dose rate and neutron tolerance
necessary for military applications have not been sacrificed.
DS(ON)
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
2
- SEE Immunity for LET of 36MeV/mg/cm with
V
up to 80% of Rated Breakdown and
of 10V Off-Bias
DS
V
GS
The Fairchild portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications
exposed to radiation environments such as switching regula-
tion, switching converters, motor drives, relay drivers and
drivers for high-power bipolar switching transistors requiring
high speed and low gate drive power. This type can be
operated directly from integrated circuits.
- 8.0nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E12 Neutrons/cm
2
2
- Usable to 3E13 Neutrons/cm
Ordering Information
Also available at other radiation and screening levels. See us
PART NUMBER
PACKAGE
TO-257AA
BRAND
JANSR2N7402
on
the
web,
Fairchild’s
home
page:
http://www.fairchildsemi.com. Contact your local Fairchild
Sales Office for additional information.
JANSR2N7402
Die Family TA17639.
MIL-PRF-19500/632.
Symbol
Package
TO-257AA
S
D
G
CAUTION: Beryllia Warning per MIL-S-19500
refer to package specifications.
©2002 Fairchild Semiconductor Corporation
JANSR2N7402 Rev. B
JANSR2N7402
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
JANSR2N7402
UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
500
500
V
V
DS
Drain to Gate Voltage (R
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Continuous Drain Current
o
T
T
= 25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
o
I
3
2
A
A
A
V
C
D
D
= 100 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
9
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±20
GS
Maximum Power Dissipation
o
T
T
= 25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
50
W
W
C
T
T
o
= 100 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
20
C
o
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.40
W/ C
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . I
9
A
A
A
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
3
9
S
SM
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
-55 to 150
300
C
o
J
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
(Distance >0.063in (1.6mm) from Case, 10s Max)
C
L
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
C
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
SYMBOL
BV
TEST CONDITIONS
MIN
TYP
MAX UNITS
I
= 1mA, V
D GS
= 0V
500
-
-
V
V
DSS
o
V
V
I
= V
,
T
= -55 C
-
-
5.0
4.0
-
GS(TH)
GS
= 1mA
DS
C
C
C
C
C
C
C
D
o
T
T
T
T
T
T
= 25 C
1.5
-
V
o
= 125 C
0.5
-
-
V
o
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
V
V
= 400V,
= 0V
= 25 C
-
25
µA
µA
nA
nA
V
DSS
DS
GS
o
= 125 C
-
-
250
100
200
8.51
2.70
5.37
85
o
I
V
= ±20V
= 25 C
-
-
GSS
GS
o
= 125 C
-
-
Drain to Source On-State Voltage
Drain to Source On Resistance
V
V
= 12V, I = 3A
-
-
DS(ON)
GS
D
o
r
I
V
= 2A,
= 12V
T
T
= 25 C
-
1.70
Ω
DS(ON)12
D
C
C
GS
o
= 125 C
-
-
-
Ω
Turn-On Delay Time
t
V
R
R
= 250V, I = 3A,
-
ns
ns
ns
ns
nC
nC
nC
nC
nC
C/W
C/W
d(ON)
DD
D
= 83.3Ω, V = 12V,
L
GS
Rise Time
t
-
-
120
150
85
r
= 7.5Ω
GS
Turn-Off Delay Time
t
-
-
d(OFF)
Fall Time
t
-
-
f
Total Gate Charge (Not on slash sheet)
Gate Charge at 12V
Q
V
V
V
= 0V to 20V
= 0V to 12V
= 0V to 2V
V
= 250V,
-
-
55
g(TOT)
GS
GS
GS
DD
= 3A
I
D
Q
-
28
-
36
g(12)
Threshold Gate Charge (Not on slash sheet)
Gate Charge Source
Q
-
2.0
8.4
15
g(TH)
Q
Q
-
6.1
11
-
gs
gd
Gate Charge Drain
-
o
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
-
2.5
60
JC
JA
θ
θ
R
-
-
©2001 Fairchild Semiconductor Corporation
JANSR2N7402 Rev. B
JANSR2N7402
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
0.6
-
TYP
MAX
1.8
UNITS
V
V
I
I
= 3A
-
-
SD
SD
SD
t
= 3A, dI /dt = 100A/µs
400
ns
rr
SD
o
Electrical Specifications up to 100K R A DT = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 0, I = 1mA
MIN
MAX
-
UNITS
Drain to Source Breakdown Volts (Note 3)
V
V
V
V
V
V
500
V
V
DSS
GS
GS
GS
GS
GS
GS
D
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
(Note 3)
V
= V , I = 1mA
DS
1.5
4.0
100
25
GS(TH)
D
(Notes 2, 3)
(Note 3)
I
= ±20V, V
= 0V
= 400V
-
-
-
-
nA
µA
V
GSS
DS
I
= 0, V
DS
DSS
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
(Notes 1, 3)
(Notes 1, 3)
V
= 12V, I = 3A
8.51
2.70
DS(ON)
D
r
= 12V, I = 2A
Ω
DS(ON)12
D
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
= 12V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
.
DSS
GS
Single Event Effects (SEB, SEGR) (Note 4)
ENVIRONMENT (NOTE 5)
(NOTE 6)
APPLIED
MAXIMUM
ION
SPECIES
TYPICAL LET
(MeV/mg/cm)
TYPICAL
RANGE (µ)
V
BIAS
V
BIAS
GS
(V)
DS
(V)
TEST
SYMBOL
Single Event Effects Safe Operating
Area
SEESOA
Ni
Ni
Br
Br
Br
26
26
37
37
37
43
43
36
36
36
-15
-20
-5
500
450
500
400
100
-10
-15
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
2
o
5. Fluence = 1E5 ions/cm (typical), T = 25 C.
C
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
©2001 Fairchild Semiconductor Corporation
JANSR2N7402 Rev. B
JANSR2N7402
Typical Performance Curves Unless Otherwise Specified
2
LET = 26MeV/mg/cm , RANGE = 43µ
2
1E-3
LET = 37MeV/mg/cm , RANGE = 36µ
600
500
400
300
200
2
FLUENCE = 1E5 IONS/cm (TYPICAL)
1E-4
ILM = 10A
30A
1E-5
1E-6
1E-7
100A
300A
100
0
o
TEMP = 25 C
10
30
100
300
1000
0
-5
-10
-15
(V)
-20
-25
V
GS
DRAIN SUPPLY (V)
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
4.0
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO I
AS
30
10
o
T
= 25 C
C
3.0
2.0
1.0
0
100µs
1
1ms
10ms
0.1
100ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
0.01
-50
0
50
100
150
1
10
100
1000
o
T
, CASE TEMPERATURE ( C)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
C
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2001 Fairchild Semiconductor Corporation
JANSR2N7402 Rev. B
JANSR2N7402
Typical Performance Curves Unless Otherwise Specified (Continued)
2.5
PULSE DURATION = 250ms, V = 12V, I = 2A
GS
D
2.0
Q
Q
12V
G
1.5
1.0
Q
GS
GD
V
G
0.5
0.0
-80
-40
0
40
80
120
160
CHARGE
o
T , JUNCTION TEMPERATURE ( C)
J
FIGURE 5. BASIC GATE CHARGE WAVEFORM
FIGURE 6. NORMALIZED r vs JUNCTION TEMPERATURE
DS(ON)
10
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
P
DM
0.01
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
1
2
t
1
t
PEAK T = P
J
x Z
+ T
C
2
DM
JC
θ
0.001
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
10
o
STARTING T = 25 C
J
o
STARTING T = 150 C
J
1
IF R = 0
= (L) (I ) / (1.3 RATED BV
DSS
t
- V )
DD
AV
IF R ≠ 0
= (L/R) ln [(I *R) /
AS
t
AV
(1.3 RATED BV
AS
- V ) + 1]
DD
DSS
0.1
, TIME IN AVALANCHE (ms)
0.1
0.01
1
10
t
AV
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
©2001 Fairchild Semiconductor Corporation
JANSR2N7402 Rev. B
JANSR2N7402
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I IS REACHED
AS
V
DS
L
BV
DSS
+
I
-
CURRENT
TRANSFORMER
t
P
AS
V
DS
I
AS
V
DD
VARY t TO OBTAIN
P
+
50Ω
REQUIRED PEAK I
AS
V
DD
V
≤ 20V
GS
-
50V-150V
DUT
50Ω
t
P
0V
t
AV
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
t
ON
t
OFF
t
d(OFF)
V
DD
t
d(ON)
t
t
f
r
R
L
V
DS
90%
90%
V
DS
V
= 12V
GS
10%
10%
DUT
0V
90%
50%
R
GS
50%
V
GS
PULSE WIDTH
10%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
JANSR2N7402 Rev. B
JANSR2N7402
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
o
Delta Tests and Limits (JANS) T = 25 C, Unless Otherwise Specified
C
PARAMETER
Gate to Source Leakage Current
Zero Gate Voltage Drain Current
Drain to Source On Resistance
Gate Threshold Voltage
NOTES:
SYMBOL
TEST CONDITIONS
= ±20V
MAX
UNITS
nA
I
V
V
±20 (Note 7)
±25 (Note 7)
±20% (Note 8)
±20% (Note 8)
GSS
GS
I
= 80% Rated Value
o
µA
DSS
DS
r
T
= 25 C at Rated I
D
Ω
DS(ON)
C
V
I
= 1.0mA
D
V
GS(TH)
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
Screening Information
TEST
JANS
Gate Stress
V
= 30V, t = 250µs
GS
Pind
Required
Pre Burn-In Tests (Note 9)
MIL-S-19500 Group A,
Subgroup 2 (All StaticTests at 25 C)
o
Steady State Gate
Bias (Gate Stress)
MIL-STD-750, Method 1042, Condition B
= 80% of Rated Value,
V
GS
= 150 C, Time = 48 hours
o
T
A
Interim Electrical Tests (Note 9)
All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse
Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
V
= 80% of Rated Value,
DS
= 150 C, Time = 240 hours
o
T
A
PDA
5%
Final Electrical Tests (Note 9)
MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area
SYMBOL
TEST CONDITIONS
= 200V, t = 10ms
MAX
0.63
9
UNITS
A
SOA
V
V
DS
Unclamped Inductive Switching
Thermal Response
I
= 15V, L = 0.1mH
A
AS
GS(PEAK)
∆V
t
t
= 100ms; V = 25V; I = 1A
90
mV
mV
SD
SD
H
H
H
H
Thermal Impedance
∆V
= 500ms; V = 25V; I = 1A
125
H
H
©2001 Fairchild Semiconductor Corporation
JANSR2N7402 Rev. B
JANSR2N7402
Rad Hard Data Packages - Fairchild Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning
Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi Temp Drain Stress Post Reverse
Bias Delta Data
F. Group A
G. Group B
H. Group C
I. Group D
- Attributes Data Sheet
- Attributes Data Sheet
- Attributes Data Sheet
- Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A
G. Group B
H. Group C
I. Group D
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
©2001 Fairchild Semiconductor Corporation
JANSR2N7402 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
â
SMART START™
STAR*POWER™
Stealth™
VCX™
FAST
ACEx™
Bottomless™
CoolFET™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
FASTr™
FRFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOLT™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenchâ
QFET™
EcoSPARK™
E2CMOSTM
TinyLogic™
QS™
EnSignaTM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILENTSWITCHERâ
FACT™
FACT Quiet Series™
UltraFETâ
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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