JANSR2N7401 [INTERSIL]
6A, 250V, 0.600 Ohm, Rad Hard, N-Channel Power MOSFET; 6A ， 250V ， 0.600欧姆，抗辐射， N沟道功率MOSFET
| 型号： | JANSR2N7401 |
| 厂家： | 
Intersil |
| 描述： | 6A, 250V, 0.600 Ohm, Rad Hard, N-Channel Power MOSFET |
| 文件： | 总8页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JANSR2N7401
August 1998
File Number 4571
Formerly FSS234R4
6A, 250V, 0.600 Ohm, Rad Hard,
N-Channel Power MOSFET
Features
• 6A, 250V, r
• Total Dose
= 0.600Ω
DS(ON)
The Discrete Products Operation of Intersil has developed a
series of Radiation Hardened MOSFETs specifically
designed for commercial and military space applications.
Enhanced Power MOSFET immunity to Single Event Effects
(SEE), Single Event Gate Rupture (SEGR) in particular, is
combined with 100K RADS of total dose hardness to provide
devices which are ideally suited to harsh space environ-
ments. The dose rate and neutron tolerance necessary for
military applications have not been sacrificed.
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
2
- SEE Immunity for LET of 36MeV/mg/cm with V
up
DS
of 10V Off-Bias
to 80% of Rated Breakdown and V
GS
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings. Numer-
ous packaging options are also available.
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
- 4.0nA Per-RAD(Si)/s Typically
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications
exposed to radiation environments such as switching regula-
tion, switching converters, motor drives, relay drivers and
drivers for high-power bipolar switching transistors requiring
high speed and low gate drive power. This type can be oper-
ated directly from integrated circuits.
• Neutron
2
- Maintain Pre-RAD Specifications for 1E13 Neutrons/cm
2
- Usable to 1E14 Neutrons/cm
Symbol
Also available at other radiation and screening levels. See us
on the web, Intersil’ home page: http://www.semi.inter-
sil.com. Contact your local Intersil Sales Office for additional
information.
Ordering Information
PART NUMBER
PACKAGE
BRAND
JANSR2N7401
TO-257AA
JANSR2N7401
Die Family TA17638.
MIL-PRF-19500/632.
Package
TO-257AA
S
D
G
CAUTION: Beryllia Warning per MIL-S-19500
refer to package specifications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-1
JANSR2N7401
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
JANSR2N7401
UNITS
Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
250
250
V
V
DS
Drain to Gate Voltage (R
GS
= 20kΩ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
o
T
T
= 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
6
4
A
A
A
V
C
D
o
= 100 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
18
±20
DM
Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation
o
T
T
= 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
50
20
W
W
C
T
o
= 100 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
C
T
o
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . I
0.40
18
W/ C
A
A
A
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
6
S
SM
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
18
o
Operating and Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
-55 to 150
300
C
J
STG
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
(Distance >0.063in (1.6mm) from Case, 10s Max)
C
L
Weight (Typical)
__
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
C
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
SYMBOL
BV
TEST CONDITIONS
= 1mA, V = 0V
MIN
TYP
MAX
-
UNITS
V
I
250
-
DSS
D
GS
o
V
V
= V
= 1mA
,
T
T
T
T
T
T
T
= -55 C
-
-
5.0
4.0
-
V
GS(TH)
GS
DS
C
C
C
C
C
C
C
I
D
o
= 25 C
1.5
-
V
o
= 125 C
0.5
-
-
V
o
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
V
V
= 200V,
= 0V
= 25 C
-
25
µA
µA
nA
nA
V
DSS
DS
GS
o
= 125 C
-
-
250
100
200
3.78
0.600
1.08
70
o
I
V
= ±20V
= 25 C
-
-
GSS
GS
o
= 125 C
-
-
Drain to Source On-State Voltage
Drain to Source On Resistance
V
V
= 12V, I = 6A
-
-
DS(ON)
GS
D
o
r
I
= 4A,
T
T
= 25 C
-
0.450
Ω
DS(ON)12
D
C
C
V
= 12V
GS
o
= 125 C
-
-
-
Ω
Turn-On Delay Time
t
V
R
R
= 125V, I = 6A,
-
ns
ns
ns
ns
nC
nC
nC
nC
nC
d(ON)
DD
D
= 20.8Ω, V = 12V,
L
GS
Rise Time
t
-
-
140
120
95
r
= 7.5Ω
GS
Turn-Off Delay Time
t
-
-
d(OFF)
Fall Time
t
-
-
f
Total Gate Charge (Not on slash sheet)
Gate Charge at 12V
Q
V
= 0V to 20V
= 0V to 12V
= 0V to 2V
V
= 125V,
-
-
62
g(TOT)
GS
DD
= 6A
I
D
Q
V
-
32
-
41
g(12)
g(TH)
GS
Threshold Gate Charge (Not on slash sheet)
Gate Charge Source
Q
V
-
3.0
11
GS
Q
-
7.3
16
-
gs
gd
Gate Charge Drain
Q
-
21
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
-
2.5
60
C/W
JC
JA
θ
o
R
-
-
C/W
θ
4-2
JANSR2N7401
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
0.6
-
TYP
MAX
1.8
UNITS
V
V
I
I
= 6A
-
-
SD
SD
t
= 6A,dI /dt = 100A/µs
420
ns
rr
SD
SD
o
Electrical Specifications up to 100K RAD T = 25 C, Unless Otherwise Specified
C
PARAMETER
Drain to Source Breakdown Volts
Gate to Source Threshold Volts
Gate to Body Leakage
SYMBOL
BV
TEST CONDITIONS
= 0, I = 1mA
MIN
MAX
-
UNITS
(Note 3)
V
250
V
V
DSS
GS
D
(Note 3)
V
V
= V , I = 1mA
DS
1.5
4.0
GS(TH)
GS
D
(Notes 2, 3)
(Note 3)
I
V
= ±20V, V
= 0V
= 200V
-
-
-
-
100
25
nA
µA
V
GSS
GS DS
Zero Gate Leakage
I
V
= 0, V
DSS
GS
DS
= 12V, I = 6A
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
(Notes 1, 3)
(Notes 1, 3)
V
V
3.78
0.600
DS(ON)
GS
D
r
V
= 12V, I = 4A
Ω
DS(ON)12
GS
D
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 12V, V
= 0V and V
GS
= 0V, V
= 80% BV .
DSS
DS
DS
Single Event Effects (SEB, SEGR) Note 4
ENVIRONMENT (NOTE 5)
APPLIED
(NOTE 6)
ION
SPECIES
TYPICAL LET
(MeV/mg/cm)
TYPICAL
RANGE (µ)
V
BIAS
MAXIMUM
GS
(V)
TEST
SYMBOL
SEESOA
V
BIAS (V)
DS
Single Event Effects Safe Operating Area
Ni
Br
Br
Br
Br
26
37
37
37
37
43
36
36
36
36
-20
-5
250
250
-10
-15
-20
200
125
50
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
2
o
5. Fluence = 1E5 ions/cm (typical), T = 25 C.
C
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
Typical Performance Curves Unless Otherwise Specified
2
LET = 26MeV/mg/cm , RANGE = 43µ
2
1E-3
1E-4
LET = 37MeV/mg/cm , RANGE = 36µ
300
200
100
0
2
FLUENCE = 1E5 IONS/cm (TYPICAL)
ILM = 10A
30A
1E-5
1E-6
1E-7
100A
300A
o
TEMP = 25 C
10
30
100
DRAIN SUPPLY (V)
300
1000
0
-5
-10
-15
-20
-25
V
(V)
GS
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO I
AS
4-3
JANSR2N7401
Typical Performance Curves Unless Otherwise Specified (Continued)
8
50
o
T
= 25 C
C
6
10
100µs
4
1
1ms
2
OPERATION IN THIS
AREA MAY BE
10ms
LIMITED BY r
DS(ON)
100ms
0
0.1
1
-50
0
50
100
o
150
10
100
700
T
, CASE TEMPERATURE ( C)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
C
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5
PULSE DURATION = 250ms,V
GS
= 12V, I = 4A
D
2.0
1.5
1.0
0.5
0.0
Q
Q
12V
G
Q
GS
GD
V
G
-80
-40
0
40
80
120
o
160
T , JUNCTION TEMPERATURE ( C)
CHARGE
J
FIGURE 5. BASIC GATE CHARGE WAVEFORM
10
FIGURE 6. NORMALIZED r
vs JUNCTION TEMPERATURE
DS(ON)
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
P
DM
0.01
NOTES:
t
t
DUTY FACTOR: D = t /t
SINGLE PULSE
10
1
2
1
2
PEAK T = P
x Z
+ T
θJC C
J
DM
0.001
10
-5
-4
-3
-2
-1
0
1
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
4-4
JANSR2N7401
Typical Performance Curves Unless Otherwise Specified (Continued)
30
o
STARTING T = 25 C
J
10
o
STARTING T = 150 C
J
IF R = 0
t
= (L) (I ) / (1.3 RATED BV
- V )
DD
AV
IF R ≠ 0
= (L/R) ln [(I *R) / (1.3 RATED BV
AS DSS
t
- V ) + 1]
AV
AS
0.01
DSS DD
1
0.001
0.1
1
10
t
, TIME IN AVALANCHE (ms)
AV
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I IS REACHED
AS
V
DS
L
BV
DSS
+
I
-
CURRENT
TRANSFORMER
t
P
AS
V
DS
I
AS
V
DD
VARY t TO OBTAIN
P
+
50Ω
REQUIRED PEAK I
AS
V
DD
V
≤ 20V
GS
-
50V-150V
DUT
50Ω
t
P
0V
t
AV
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
V
DD
t
d(ON)
t
t
f
r
R
L
V
DS
90%
90%
V
DS
V
= 12V
GS
10%
10%
DUT
0V
90%
50%
R
GS
50%
V
GS
PULSE WIDTH
10%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
Screening Information
4-5
JANSR2N7401
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
o
Delta Tests and Limits (JANS) T = 25 C, Unless Otherwise Specified
C
PARAMETER
Gate to Source Leakage Current
Zero Gate Voltage Drain Current
Drain to Source On Resistance
Gate Threshold Voltage
NOTES:
SYMBOL
TEST CONDITIONS
= ±20V
GS
MAX
UNITS
nA
I
V
±20 (Note 7)
±25 (Note 7)
±20% (Note 8)
±20% (Note 8)
GSS
I
V
= 80% Rated Value
o
µA
DSS
DS
r
T
= 25 C at Rated I
D
Ω
DS(ON)
C
V
I
= 1.0mA
V
GS(TH)
D
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
Screening Information
TEST
JANS
Gate Stress
V
= 30V, t = 250µs
GS
Pind
Required
Pre Burn-In Tests (Note 9)
MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25 C)
o
Steady State Gate
Bias (Gate Stress)
MIL-STD-750, Method 1042, Condition B
V
= 80% of Rated Value,
GS
T = 150 C, Time = 48 hours
o
A
Interim Electrical Tests (Note 9)
All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse
Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
V
= 80% of Rated Value,
DS
o
T = 150 C, Time = 240 hours
A
PDA
5%
Final Electrical Tests (Note 9)
MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area
SYMBOL
SOA
TEST CONDITIONS
MAX
0.33
18
UNITS
A
V
= 200V, t = 10ms
DS
Unclamped Inductive Switching
Thermal Response
I
V
= 15V, L = 0.1mH
A
AS
GS(PEAK)
∆V
t
t
= 100ms; V = 25V; I = 1A
90
mV
mV
SD
SD
H
H
H
Thermal Impedance
∆V
= 500ms; V = 25V; I = 1A
125
H
H
H
4-6
JANSR2N7401
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning
Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi Temp Drain Stress Post Reverse
Bias Delta Data
F. Group A
G. Group B
H. Group C
I. Group D
- Attributes Data Sheet
- Attributes Data Sheet
- Attributes Data Sheet
- Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A
G. Group B
H. Group C
I. Group D
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
4-7
JANSR2N7401
TO-257AA
3 LEAD JEDEC TO-257AA HERMETIC METAL PACKAGE
A
INCHES
MIN
MILLIMETERS
ØP
E
A
1
SYMBOL
MAX
0.200
0.045
0.035
0.090
0.665
0.420
MIN
4.83
MAX
5.08
NOTES
A
0.190
0.035
0.025
0.060
0.645
0.410
-
Q
H
1
A
0.89
1.14
-
1
Øb
0.64
0.88
2, 3
D
Øb
D
E
1.53
2.28
-
-
1
16.39
10.42
16.89
10.66
-
e
0.100 TYP
0.200 BSC
0.230
2.54 TYP
5.08 BSC
4
4
-
e
0.065 R TYP.
1
Øb1
L
1
H
0.250
0.130
0.650
0.035
0.150
0.133
5.85
6.35
3.30
16.51
0.88
3.81
3.37
1
1
J
0.110
0.600
-
2.80
15.24
-
4
-
L
Øb
L
L
-
1
ØP
Q
0.140
0.113
3.56
2.88
-
1
2
e
3
J
-
1
e1
NOTES:
1. These dimensions are within allowable dimensions of Rev. B of
JEDEC TO-257AA dated 9-88.
2. Add typically 0.002 inches (0.05mm) for solder coating.
3. Lead dimension (without solder).
4. Position of lead to be measured 0.150 inches (3.81mm) from bottom
of dimension D.
5. Die to base BeO isolated, terminals to case ceramic isolated.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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TEL: (407) 724-7000
FAX: (407) 724-7240
4-8
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